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Merge branch 'drm-sti-next-add-dvo' of git://git.linaro.org/people/benjamin.gaignard...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
139 } while (0)
140
141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
143 /* For display hotplug interrupt */
144 void
145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
146 {
147 assert_spin_locked(&dev_priv->irq_lock);
148
149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
150 return;
151
152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
155 POSTING_READ(DEIMR);
156 }
157 }
158
159 void
160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
161 {
162 assert_spin_locked(&dev_priv->irq_lock);
163
164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
165 return;
166
167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
170 POSTING_READ(DEIMR);
171 }
172 }
173
174 /**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183 {
184 assert_spin_locked(&dev_priv->irq_lock);
185
186 WARN_ON(enabled_irq_mask & ~interrupt_mask);
187
188 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
189 return;
190
191 dev_priv->gt_irq_mask &= ~interrupt_mask;
192 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
193 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
194 POSTING_READ(GTIMR);
195 }
196
197 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
198 {
199 ilk_update_gt_irq(dev_priv, mask, mask);
200 }
201
202 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
203 {
204 ilk_update_gt_irq(dev_priv, mask, 0);
205 }
206
207 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
208 {
209 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
210 }
211
212 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
213 {
214 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
215 }
216
217 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
218 {
219 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
220 }
221
222 /**
223 * snb_update_pm_irq - update GEN6_PMIMR
224 * @dev_priv: driver private
225 * @interrupt_mask: mask of interrupt bits to update
226 * @enabled_irq_mask: mask of interrupt bits to enable
227 */
228 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
229 uint32_t interrupt_mask,
230 uint32_t enabled_irq_mask)
231 {
232 uint32_t new_val;
233
234 WARN_ON(enabled_irq_mask & ~interrupt_mask);
235
236 assert_spin_locked(&dev_priv->irq_lock);
237
238 new_val = dev_priv->pm_irq_mask;
239 new_val &= ~interrupt_mask;
240 new_val |= (~enabled_irq_mask & interrupt_mask);
241
242 if (new_val != dev_priv->pm_irq_mask) {
243 dev_priv->pm_irq_mask = new_val;
244 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
245 POSTING_READ(gen6_pm_imr(dev_priv));
246 }
247 }
248
249 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
250 {
251 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
252 return;
253
254 snb_update_pm_irq(dev_priv, mask, mask);
255 }
256
257 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
258 uint32_t mask)
259 {
260 snb_update_pm_irq(dev_priv, mask, 0);
261 }
262
263 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
264 {
265 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
266 return;
267
268 __gen6_disable_pm_irq(dev_priv, mask);
269 }
270
271 void gen6_reset_rps_interrupts(struct drm_device *dev)
272 {
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 uint32_t reg = gen6_pm_iir(dev_priv);
275
276 spin_lock_irq(&dev_priv->irq_lock);
277 I915_WRITE(reg, dev_priv->pm_rps_events);
278 I915_WRITE(reg, dev_priv->pm_rps_events);
279 POSTING_READ(reg);
280 spin_unlock_irq(&dev_priv->irq_lock);
281 }
282
283 void gen6_enable_rps_interrupts(struct drm_device *dev)
284 {
285 struct drm_i915_private *dev_priv = dev->dev_private;
286
287 spin_lock_irq(&dev_priv->irq_lock);
288
289 WARN_ON(dev_priv->rps.pm_iir);
290 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
291 dev_priv->rps.interrupts_enabled = true;
292 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
293 dev_priv->pm_rps_events);
294 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
295
296 spin_unlock_irq(&dev_priv->irq_lock);
297 }
298
299 void gen6_disable_rps_interrupts(struct drm_device *dev)
300 {
301 struct drm_i915_private *dev_priv = dev->dev_private;
302
303 spin_lock_irq(&dev_priv->irq_lock);
304 dev_priv->rps.interrupts_enabled = false;
305 spin_unlock_irq(&dev_priv->irq_lock);
306
307 cancel_work_sync(&dev_priv->rps.work);
308
309 spin_lock_irq(&dev_priv->irq_lock);
310
311 I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
312 ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
313
314 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
315 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
316 ~dev_priv->pm_rps_events);
317 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
318 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
319
320 dev_priv->rps.pm_iir = 0;
321
322 spin_unlock_irq(&dev_priv->irq_lock);
323 }
324
325 /**
326 * ibx_display_interrupt_update - update SDEIMR
327 * @dev_priv: driver private
328 * @interrupt_mask: mask of interrupt bits to update
329 * @enabled_irq_mask: mask of interrupt bits to enable
330 */
331 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
332 uint32_t interrupt_mask,
333 uint32_t enabled_irq_mask)
334 {
335 uint32_t sdeimr = I915_READ(SDEIMR);
336 sdeimr &= ~interrupt_mask;
337 sdeimr |= (~enabled_irq_mask & interrupt_mask);
338
339 WARN_ON(enabled_irq_mask & ~interrupt_mask);
340
341 assert_spin_locked(&dev_priv->irq_lock);
342
343 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
344 return;
345
346 I915_WRITE(SDEIMR, sdeimr);
347 POSTING_READ(SDEIMR);
348 }
349
350 static void
351 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
352 u32 enable_mask, u32 status_mask)
353 {
354 u32 reg = PIPESTAT(pipe);
355 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
356
357 assert_spin_locked(&dev_priv->irq_lock);
358 WARN_ON(!intel_irqs_enabled(dev_priv));
359
360 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
361 status_mask & ~PIPESTAT_INT_STATUS_MASK,
362 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
363 pipe_name(pipe), enable_mask, status_mask))
364 return;
365
366 if ((pipestat & enable_mask) == enable_mask)
367 return;
368
369 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
370
371 /* Enable the interrupt, clear any pending status */
372 pipestat |= enable_mask | status_mask;
373 I915_WRITE(reg, pipestat);
374 POSTING_READ(reg);
375 }
376
377 static void
378 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
379 u32 enable_mask, u32 status_mask)
380 {
381 u32 reg = PIPESTAT(pipe);
382 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
383
384 assert_spin_locked(&dev_priv->irq_lock);
385 WARN_ON(!intel_irqs_enabled(dev_priv));
386
387 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
388 status_mask & ~PIPESTAT_INT_STATUS_MASK,
389 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
390 pipe_name(pipe), enable_mask, status_mask))
391 return;
392
393 if ((pipestat & enable_mask) == 0)
394 return;
395
396 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
397
398 pipestat &= ~enable_mask;
399 I915_WRITE(reg, pipestat);
400 POSTING_READ(reg);
401 }
402
403 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
404 {
405 u32 enable_mask = status_mask << 16;
406
407 /*
408 * On pipe A we don't support the PSR interrupt yet,
409 * on pipe B and C the same bit MBZ.
410 */
411 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
412 return 0;
413 /*
414 * On pipe B and C we don't support the PSR interrupt yet, on pipe
415 * A the same bit is for perf counters which we don't use either.
416 */
417 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
418 return 0;
419
420 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
421 SPRITE0_FLIP_DONE_INT_EN_VLV |
422 SPRITE1_FLIP_DONE_INT_EN_VLV);
423 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
424 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
425 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
426 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
427
428 return enable_mask;
429 }
430
431 void
432 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
433 u32 status_mask)
434 {
435 u32 enable_mask;
436
437 if (IS_VALLEYVIEW(dev_priv->dev))
438 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
439 status_mask);
440 else
441 enable_mask = status_mask << 16;
442 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
443 }
444
445 void
446 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
447 u32 status_mask)
448 {
449 u32 enable_mask;
450
451 if (IS_VALLEYVIEW(dev_priv->dev))
452 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
453 status_mask);
454 else
455 enable_mask = status_mask << 16;
456 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
457 }
458
459 /**
460 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
461 */
462 static void i915_enable_asle_pipestat(struct drm_device *dev)
463 {
464 struct drm_i915_private *dev_priv = dev->dev_private;
465
466 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
467 return;
468
469 spin_lock_irq(&dev_priv->irq_lock);
470
471 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
472 if (INTEL_INFO(dev)->gen >= 4)
473 i915_enable_pipestat(dev_priv, PIPE_A,
474 PIPE_LEGACY_BLC_EVENT_STATUS);
475
476 spin_unlock_irq(&dev_priv->irq_lock);
477 }
478
479 /**
480 * i915_pipe_enabled - check if a pipe is enabled
481 * @dev: DRM device
482 * @pipe: pipe to check
483 *
484 * Reading certain registers when the pipe is disabled can hang the chip.
485 * Use this routine to make sure the PLL is running and the pipe is active
486 * before reading such registers if unsure.
487 */
488 static int
489 i915_pipe_enabled(struct drm_device *dev, int pipe)
490 {
491 struct drm_i915_private *dev_priv = dev->dev_private;
492
493 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
494 /* Locking is horribly broken here, but whatever. */
495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
497
498 return intel_crtc->active;
499 } else {
500 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
501 }
502 }
503
504 /*
505 * This timing diagram depicts the video signal in and
506 * around the vertical blanking period.
507 *
508 * Assumptions about the fictitious mode used in this example:
509 * vblank_start >= 3
510 * vsync_start = vblank_start + 1
511 * vsync_end = vblank_start + 2
512 * vtotal = vblank_start + 3
513 *
514 * start of vblank:
515 * latch double buffered registers
516 * increment frame counter (ctg+)
517 * generate start of vblank interrupt (gen4+)
518 * |
519 * | frame start:
520 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
521 * | may be shifted forward 1-3 extra lines via PIPECONF
522 * | |
523 * | | start of vsync:
524 * | | generate vsync interrupt
525 * | | |
526 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
527 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
528 * ----va---> <-----------------vb--------------------> <--------va-------------
529 * | | <----vs-----> |
530 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
531 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
532 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
533 * | | |
534 * last visible pixel first visible pixel
535 * | increment frame counter (gen3/4)
536 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
537 *
538 * x = horizontal active
539 * _ = horizontal blanking
540 * hs = horizontal sync
541 * va = vertical active
542 * vb = vertical blanking
543 * vs = vertical sync
544 * vbs = vblank_start (number)
545 *
546 * Summary:
547 * - most events happen at the start of horizontal sync
548 * - frame start happens at the start of horizontal blank, 1-4 lines
549 * (depending on PIPECONF settings) after the start of vblank
550 * - gen3/4 pixel and frame counter are synchronized with the start
551 * of horizontal active on the first line of vertical active
552 */
553
554 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
555 {
556 /* Gen2 doesn't have a hardware frame counter */
557 return 0;
558 }
559
560 /* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
562 */
563 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
564 {
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 unsigned long high_frame;
567 unsigned long low_frame;
568 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
569
570 if (!i915_pipe_enabled(dev, pipe)) {
571 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
572 "pipe %c\n", pipe_name(pipe));
573 return 0;
574 }
575
576 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
577 struct intel_crtc *intel_crtc =
578 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
579 const struct drm_display_mode *mode =
580 &intel_crtc->config.adjusted_mode;
581
582 htotal = mode->crtc_htotal;
583 hsync_start = mode->crtc_hsync_start;
584 vbl_start = mode->crtc_vblank_start;
585 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
586 vbl_start = DIV_ROUND_UP(vbl_start, 2);
587 } else {
588 enum transcoder cpu_transcoder = (enum transcoder) pipe;
589
590 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
591 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
592 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
593 if ((I915_READ(PIPECONF(cpu_transcoder)) &
594 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
595 vbl_start = DIV_ROUND_UP(vbl_start, 2);
596 }
597
598 /* Convert to pixel count */
599 vbl_start *= htotal;
600
601 /* Start of vblank event occurs at start of hsync */
602 vbl_start -= htotal - hsync_start;
603
604 high_frame = PIPEFRAME(pipe);
605 low_frame = PIPEFRAMEPIXEL(pipe);
606
607 /*
608 * High & low register fields aren't synchronized, so make sure
609 * we get a low value that's stable across two reads of the high
610 * register.
611 */
612 do {
613 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
614 low = I915_READ(low_frame);
615 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
616 } while (high1 != high2);
617
618 high1 >>= PIPE_FRAME_HIGH_SHIFT;
619 pixel = low & PIPE_PIXEL_MASK;
620 low >>= PIPE_FRAME_LOW_SHIFT;
621
622 /*
623 * The frame counter increments at beginning of active.
624 * Cook up a vblank counter by also checking the pixel
625 * counter against vblank start.
626 */
627 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
628 }
629
630 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
631 {
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 int reg = PIPE_FRMCOUNT_GM45(pipe);
634
635 if (!i915_pipe_enabled(dev, pipe)) {
636 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
637 "pipe %c\n", pipe_name(pipe));
638 return 0;
639 }
640
641 return I915_READ(reg);
642 }
643
644 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
645 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
646
647 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
648 {
649 struct drm_device *dev = crtc->base.dev;
650 struct drm_i915_private *dev_priv = dev->dev_private;
651 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
652 enum pipe pipe = crtc->pipe;
653 int position, vtotal;
654
655 vtotal = mode->crtc_vtotal;
656 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
657 vtotal /= 2;
658
659 if (IS_GEN2(dev))
660 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
661 else
662 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
663
664 /*
665 * See update_scanline_offset() for the details on the
666 * scanline_offset adjustment.
667 */
668 return (position + crtc->scanline_offset) % vtotal;
669 }
670
671 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
672 unsigned int flags, int *vpos, int *hpos,
673 ktime_t *stime, ktime_t *etime)
674 {
675 struct drm_i915_private *dev_priv = dev->dev_private;
676 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
678 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
679 int position;
680 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
681 bool in_vbl = true;
682 int ret = 0;
683 unsigned long irqflags;
684
685 if (!intel_crtc->active) {
686 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
687 "pipe %c\n", pipe_name(pipe));
688 return 0;
689 }
690
691 htotal = mode->crtc_htotal;
692 hsync_start = mode->crtc_hsync_start;
693 vtotal = mode->crtc_vtotal;
694 vbl_start = mode->crtc_vblank_start;
695 vbl_end = mode->crtc_vblank_end;
696
697 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
698 vbl_start = DIV_ROUND_UP(vbl_start, 2);
699 vbl_end /= 2;
700 vtotal /= 2;
701 }
702
703 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
704
705 /*
706 * Lock uncore.lock, as we will do multiple timing critical raw
707 * register reads, potentially with preemption disabled, so the
708 * following code must not block on uncore.lock.
709 */
710 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
711
712 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
713
714 /* Get optional system timestamp before query. */
715 if (stime)
716 *stime = ktime_get();
717
718 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
719 /* No obvious pixelcount register. Only query vertical
720 * scanout position from Display scan line register.
721 */
722 position = __intel_get_crtc_scanline(intel_crtc);
723 } else {
724 /* Have access to pixelcount since start of frame.
725 * We can split this into vertical and horizontal
726 * scanout position.
727 */
728 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
729
730 /* convert to pixel counts */
731 vbl_start *= htotal;
732 vbl_end *= htotal;
733 vtotal *= htotal;
734
735 /*
736 * In interlaced modes, the pixel counter counts all pixels,
737 * so one field will have htotal more pixels. In order to avoid
738 * the reported position from jumping backwards when the pixel
739 * counter is beyond the length of the shorter field, just
740 * clamp the position the length of the shorter field. This
741 * matches how the scanline counter based position works since
742 * the scanline counter doesn't count the two half lines.
743 */
744 if (position >= vtotal)
745 position = vtotal - 1;
746
747 /*
748 * Start of vblank interrupt is triggered at start of hsync,
749 * just prior to the first active line of vblank. However we
750 * consider lines to start at the leading edge of horizontal
751 * active. So, should we get here before we've crossed into
752 * the horizontal active of the first line in vblank, we would
753 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
754 * always add htotal-hsync_start to the current pixel position.
755 */
756 position = (position + htotal - hsync_start) % vtotal;
757 }
758
759 /* Get optional system timestamp after query. */
760 if (etime)
761 *etime = ktime_get();
762
763 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
764
765 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
766
767 in_vbl = position >= vbl_start && position < vbl_end;
768
769 /*
770 * While in vblank, position will be negative
771 * counting up towards 0 at vbl_end. And outside
772 * vblank, position will be positive counting
773 * up since vbl_end.
774 */
775 if (position >= vbl_start)
776 position -= vbl_end;
777 else
778 position += vtotal - vbl_end;
779
780 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
781 *vpos = position;
782 *hpos = 0;
783 } else {
784 *vpos = position / htotal;
785 *hpos = position - (*vpos * htotal);
786 }
787
788 /* In vblank? */
789 if (in_vbl)
790 ret |= DRM_SCANOUTPOS_IN_VBLANK;
791
792 return ret;
793 }
794
795 int intel_get_crtc_scanline(struct intel_crtc *crtc)
796 {
797 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
798 unsigned long irqflags;
799 int position;
800
801 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
802 position = __intel_get_crtc_scanline(crtc);
803 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
804
805 return position;
806 }
807
808 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
809 int *max_error,
810 struct timeval *vblank_time,
811 unsigned flags)
812 {
813 struct drm_crtc *crtc;
814
815 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
816 DRM_ERROR("Invalid crtc %d\n", pipe);
817 return -EINVAL;
818 }
819
820 /* Get drm_crtc to timestamp: */
821 crtc = intel_get_crtc_for_pipe(dev, pipe);
822 if (crtc == NULL) {
823 DRM_ERROR("Invalid crtc %d\n", pipe);
824 return -EINVAL;
825 }
826
827 if (!crtc->enabled) {
828 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
829 return -EBUSY;
830 }
831
832 /* Helper routine in DRM core does all the work: */
833 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
834 vblank_time, flags,
835 crtc,
836 &to_intel_crtc(crtc)->config.adjusted_mode);
837 }
838
839 static bool intel_hpd_irq_event(struct drm_device *dev,
840 struct drm_connector *connector)
841 {
842 enum drm_connector_status old_status;
843
844 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
845 old_status = connector->status;
846
847 connector->status = connector->funcs->detect(connector, false);
848 if (old_status == connector->status)
849 return false;
850
851 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
852 connector->base.id,
853 connector->name,
854 drm_get_connector_status_name(old_status),
855 drm_get_connector_status_name(connector->status));
856
857 return true;
858 }
859
860 static void i915_digport_work_func(struct work_struct *work)
861 {
862 struct drm_i915_private *dev_priv =
863 container_of(work, struct drm_i915_private, dig_port_work);
864 u32 long_port_mask, short_port_mask;
865 struct intel_digital_port *intel_dig_port;
866 int i, ret;
867 u32 old_bits = 0;
868
869 spin_lock_irq(&dev_priv->irq_lock);
870 long_port_mask = dev_priv->long_hpd_port_mask;
871 dev_priv->long_hpd_port_mask = 0;
872 short_port_mask = dev_priv->short_hpd_port_mask;
873 dev_priv->short_hpd_port_mask = 0;
874 spin_unlock_irq(&dev_priv->irq_lock);
875
876 for (i = 0; i < I915_MAX_PORTS; i++) {
877 bool valid = false;
878 bool long_hpd = false;
879 intel_dig_port = dev_priv->hpd_irq_port[i];
880 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
881 continue;
882
883 if (long_port_mask & (1 << i)) {
884 valid = true;
885 long_hpd = true;
886 } else if (short_port_mask & (1 << i))
887 valid = true;
888
889 if (valid) {
890 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
891 if (ret == true) {
892 /* if we get true fallback to old school hpd */
893 old_bits |= (1 << intel_dig_port->base.hpd_pin);
894 }
895 }
896 }
897
898 if (old_bits) {
899 spin_lock_irq(&dev_priv->irq_lock);
900 dev_priv->hpd_event_bits |= old_bits;
901 spin_unlock_irq(&dev_priv->irq_lock);
902 schedule_work(&dev_priv->hotplug_work);
903 }
904 }
905
906 /*
907 * Handle hotplug events outside the interrupt handler proper.
908 */
909 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
910
911 static void i915_hotplug_work_func(struct work_struct *work)
912 {
913 struct drm_i915_private *dev_priv =
914 container_of(work, struct drm_i915_private, hotplug_work);
915 struct drm_device *dev = dev_priv->dev;
916 struct drm_mode_config *mode_config = &dev->mode_config;
917 struct intel_connector *intel_connector;
918 struct intel_encoder *intel_encoder;
919 struct drm_connector *connector;
920 bool hpd_disabled = false;
921 bool changed = false;
922 u32 hpd_event_bits;
923
924 mutex_lock(&mode_config->mutex);
925 DRM_DEBUG_KMS("running encoder hotplug functions\n");
926
927 spin_lock_irq(&dev_priv->irq_lock);
928
929 hpd_event_bits = dev_priv->hpd_event_bits;
930 dev_priv->hpd_event_bits = 0;
931 list_for_each_entry(connector, &mode_config->connector_list, head) {
932 intel_connector = to_intel_connector(connector);
933 if (!intel_connector->encoder)
934 continue;
935 intel_encoder = intel_connector->encoder;
936 if (intel_encoder->hpd_pin > HPD_NONE &&
937 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
938 connector->polled == DRM_CONNECTOR_POLL_HPD) {
939 DRM_INFO("HPD interrupt storm detected on connector %s: "
940 "switching from hotplug detection to polling\n",
941 connector->name);
942 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
943 connector->polled = DRM_CONNECTOR_POLL_CONNECT
944 | DRM_CONNECTOR_POLL_DISCONNECT;
945 hpd_disabled = true;
946 }
947 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
948 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
949 connector->name, intel_encoder->hpd_pin);
950 }
951 }
952 /* if there were no outputs to poll, poll was disabled,
953 * therefore make sure it's enabled when disabling HPD on
954 * some connectors */
955 if (hpd_disabled) {
956 drm_kms_helper_poll_enable(dev);
957 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
958 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
959 }
960
961 spin_unlock_irq(&dev_priv->irq_lock);
962
963 list_for_each_entry(connector, &mode_config->connector_list, head) {
964 intel_connector = to_intel_connector(connector);
965 if (!intel_connector->encoder)
966 continue;
967 intel_encoder = intel_connector->encoder;
968 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
969 if (intel_encoder->hot_plug)
970 intel_encoder->hot_plug(intel_encoder);
971 if (intel_hpd_irq_event(dev, connector))
972 changed = true;
973 }
974 }
975 mutex_unlock(&mode_config->mutex);
976
977 if (changed)
978 drm_kms_helper_hotplug_event(dev);
979 }
980
981 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
982 {
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 u32 busy_up, busy_down, max_avg, min_avg;
985 u8 new_delay;
986
987 spin_lock(&mchdev_lock);
988
989 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
990
991 new_delay = dev_priv->ips.cur_delay;
992
993 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
994 busy_up = I915_READ(RCPREVBSYTUPAVG);
995 busy_down = I915_READ(RCPREVBSYTDNAVG);
996 max_avg = I915_READ(RCBMAXAVG);
997 min_avg = I915_READ(RCBMINAVG);
998
999 /* Handle RCS change request from hw */
1000 if (busy_up > max_avg) {
1001 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1002 new_delay = dev_priv->ips.cur_delay - 1;
1003 if (new_delay < dev_priv->ips.max_delay)
1004 new_delay = dev_priv->ips.max_delay;
1005 } else if (busy_down < min_avg) {
1006 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1007 new_delay = dev_priv->ips.cur_delay + 1;
1008 if (new_delay > dev_priv->ips.min_delay)
1009 new_delay = dev_priv->ips.min_delay;
1010 }
1011
1012 if (ironlake_set_drps(dev, new_delay))
1013 dev_priv->ips.cur_delay = new_delay;
1014
1015 spin_unlock(&mchdev_lock);
1016
1017 return;
1018 }
1019
1020 static void notify_ring(struct drm_device *dev,
1021 struct intel_engine_cs *ring)
1022 {
1023 if (!intel_ring_initialized(ring))
1024 return;
1025
1026 trace_i915_gem_request_notify(ring);
1027
1028 wake_up_all(&ring->irq_queue);
1029 }
1030
1031 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1032 struct intel_rps_ei *rps_ei)
1033 {
1034 u32 cz_ts, cz_freq_khz;
1035 u32 render_count, media_count;
1036 u32 elapsed_render, elapsed_media, elapsed_time;
1037 u32 residency = 0;
1038
1039 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1040 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1041
1042 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1043 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1044
1045 if (rps_ei->cz_clock == 0) {
1046 rps_ei->cz_clock = cz_ts;
1047 rps_ei->render_c0 = render_count;
1048 rps_ei->media_c0 = media_count;
1049
1050 return dev_priv->rps.cur_freq;
1051 }
1052
1053 elapsed_time = cz_ts - rps_ei->cz_clock;
1054 rps_ei->cz_clock = cz_ts;
1055
1056 elapsed_render = render_count - rps_ei->render_c0;
1057 rps_ei->render_c0 = render_count;
1058
1059 elapsed_media = media_count - rps_ei->media_c0;
1060 rps_ei->media_c0 = media_count;
1061
1062 /* Convert all the counters into common unit of milli sec */
1063 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1064 elapsed_render /= cz_freq_khz;
1065 elapsed_media /= cz_freq_khz;
1066
1067 /*
1068 * Calculate overall C0 residency percentage
1069 * only if elapsed time is non zero
1070 */
1071 if (elapsed_time) {
1072 residency =
1073 ((max(elapsed_render, elapsed_media) * 100)
1074 / elapsed_time);
1075 }
1076
1077 return residency;
1078 }
1079
1080 /**
1081 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1082 * busy-ness calculated from C0 counters of render & media power wells
1083 * @dev_priv: DRM device private
1084 *
1085 */
1086 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1087 {
1088 u32 residency_C0_up = 0, residency_C0_down = 0;
1089 int new_delay, adj;
1090
1091 dev_priv->rps.ei_interrupt_count++;
1092
1093 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1094
1095
1096 if (dev_priv->rps.up_ei.cz_clock == 0) {
1097 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1098 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1099 return dev_priv->rps.cur_freq;
1100 }
1101
1102
1103 /*
1104 * To down throttle, C0 residency should be less than down threshold
1105 * for continous EI intervals. So calculate down EI counters
1106 * once in VLV_INT_COUNT_FOR_DOWN_EI
1107 */
1108 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1109
1110 dev_priv->rps.ei_interrupt_count = 0;
1111
1112 residency_C0_down = vlv_c0_residency(dev_priv,
1113 &dev_priv->rps.down_ei);
1114 } else {
1115 residency_C0_up = vlv_c0_residency(dev_priv,
1116 &dev_priv->rps.up_ei);
1117 }
1118
1119 new_delay = dev_priv->rps.cur_freq;
1120
1121 adj = dev_priv->rps.last_adj;
1122 /* C0 residency is greater than UP threshold. Increase Frequency */
1123 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1124 if (adj > 0)
1125 adj *= 2;
1126 else
1127 adj = 1;
1128
1129 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1130 new_delay = dev_priv->rps.cur_freq + adj;
1131
1132 /*
1133 * For better performance, jump directly
1134 * to RPe if we're below it.
1135 */
1136 if (new_delay < dev_priv->rps.efficient_freq)
1137 new_delay = dev_priv->rps.efficient_freq;
1138
1139 } else if (!dev_priv->rps.ei_interrupt_count &&
1140 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1141 if (adj < 0)
1142 adj *= 2;
1143 else
1144 adj = -1;
1145 /*
1146 * This means, C0 residency is less than down threshold over
1147 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1148 */
1149 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1150 new_delay = dev_priv->rps.cur_freq + adj;
1151 }
1152
1153 return new_delay;
1154 }
1155
1156 static void gen6_pm_rps_work(struct work_struct *work)
1157 {
1158 struct drm_i915_private *dev_priv =
1159 container_of(work, struct drm_i915_private, rps.work);
1160 u32 pm_iir;
1161 int new_delay, adj;
1162
1163 spin_lock_irq(&dev_priv->irq_lock);
1164 /* Speed up work cancelation during disabling rps interrupts. */
1165 if (!dev_priv->rps.interrupts_enabled) {
1166 spin_unlock_irq(&dev_priv->irq_lock);
1167 return;
1168 }
1169 pm_iir = dev_priv->rps.pm_iir;
1170 dev_priv->rps.pm_iir = 0;
1171 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1172 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1173 spin_unlock_irq(&dev_priv->irq_lock);
1174
1175 /* Make sure we didn't queue anything we're not going to process. */
1176 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1177
1178 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1179 return;
1180
1181 mutex_lock(&dev_priv->rps.hw_lock);
1182
1183 adj = dev_priv->rps.last_adj;
1184 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1185 if (adj > 0)
1186 adj *= 2;
1187 else {
1188 /* CHV needs even encode values */
1189 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1190 }
1191 new_delay = dev_priv->rps.cur_freq + adj;
1192
1193 /*
1194 * For better performance, jump directly
1195 * to RPe if we're below it.
1196 */
1197 if (new_delay < dev_priv->rps.efficient_freq)
1198 new_delay = dev_priv->rps.efficient_freq;
1199 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1200 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1201 new_delay = dev_priv->rps.efficient_freq;
1202 else
1203 new_delay = dev_priv->rps.min_freq_softlimit;
1204 adj = 0;
1205 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1206 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1207 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1208 if (adj < 0)
1209 adj *= 2;
1210 else {
1211 /* CHV needs even encode values */
1212 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1213 }
1214 new_delay = dev_priv->rps.cur_freq + adj;
1215 } else { /* unknown event */
1216 new_delay = dev_priv->rps.cur_freq;
1217 }
1218
1219 /* sysfs frequency interfaces may have snuck in while servicing the
1220 * interrupt
1221 */
1222 new_delay = clamp_t(int, new_delay,
1223 dev_priv->rps.min_freq_softlimit,
1224 dev_priv->rps.max_freq_softlimit);
1225
1226 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1227
1228 if (IS_VALLEYVIEW(dev_priv->dev))
1229 valleyview_set_rps(dev_priv->dev, new_delay);
1230 else
1231 gen6_set_rps(dev_priv->dev, new_delay);
1232
1233 mutex_unlock(&dev_priv->rps.hw_lock);
1234 }
1235
1236
1237 /**
1238 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1239 * occurred.
1240 * @work: workqueue struct
1241 *
1242 * Doesn't actually do anything except notify userspace. As a consequence of
1243 * this event, userspace should try to remap the bad rows since statistically
1244 * it is likely the same row is more likely to go bad again.
1245 */
1246 static void ivybridge_parity_work(struct work_struct *work)
1247 {
1248 struct drm_i915_private *dev_priv =
1249 container_of(work, struct drm_i915_private, l3_parity.error_work);
1250 u32 error_status, row, bank, subbank;
1251 char *parity_event[6];
1252 uint32_t misccpctl;
1253 uint8_t slice = 0;
1254
1255 /* We must turn off DOP level clock gating to access the L3 registers.
1256 * In order to prevent a get/put style interface, acquire struct mutex
1257 * any time we access those registers.
1258 */
1259 mutex_lock(&dev_priv->dev->struct_mutex);
1260
1261 /* If we've screwed up tracking, just let the interrupt fire again */
1262 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1263 goto out;
1264
1265 misccpctl = I915_READ(GEN7_MISCCPCTL);
1266 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1267 POSTING_READ(GEN7_MISCCPCTL);
1268
1269 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1270 u32 reg;
1271
1272 slice--;
1273 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1274 break;
1275
1276 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1277
1278 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1279
1280 error_status = I915_READ(reg);
1281 row = GEN7_PARITY_ERROR_ROW(error_status);
1282 bank = GEN7_PARITY_ERROR_BANK(error_status);
1283 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1284
1285 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1286 POSTING_READ(reg);
1287
1288 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1289 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1290 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1291 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1292 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1293 parity_event[5] = NULL;
1294
1295 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1296 KOBJ_CHANGE, parity_event);
1297
1298 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1299 slice, row, bank, subbank);
1300
1301 kfree(parity_event[4]);
1302 kfree(parity_event[3]);
1303 kfree(parity_event[2]);
1304 kfree(parity_event[1]);
1305 }
1306
1307 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1308
1309 out:
1310 WARN_ON(dev_priv->l3_parity.which_slice);
1311 spin_lock_irq(&dev_priv->irq_lock);
1312 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1313 spin_unlock_irq(&dev_priv->irq_lock);
1314
1315 mutex_unlock(&dev_priv->dev->struct_mutex);
1316 }
1317
1318 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1319 {
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321
1322 if (!HAS_L3_DPF(dev))
1323 return;
1324
1325 spin_lock(&dev_priv->irq_lock);
1326 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1327 spin_unlock(&dev_priv->irq_lock);
1328
1329 iir &= GT_PARITY_ERROR(dev);
1330 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1331 dev_priv->l3_parity.which_slice |= 1 << 1;
1332
1333 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1334 dev_priv->l3_parity.which_slice |= 1 << 0;
1335
1336 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1337 }
1338
1339 static void ilk_gt_irq_handler(struct drm_device *dev,
1340 struct drm_i915_private *dev_priv,
1341 u32 gt_iir)
1342 {
1343 if (gt_iir &
1344 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1345 notify_ring(dev, &dev_priv->ring[RCS]);
1346 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1347 notify_ring(dev, &dev_priv->ring[VCS]);
1348 }
1349
1350 static void snb_gt_irq_handler(struct drm_device *dev,
1351 struct drm_i915_private *dev_priv,
1352 u32 gt_iir)
1353 {
1354
1355 if (gt_iir &
1356 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1357 notify_ring(dev, &dev_priv->ring[RCS]);
1358 if (gt_iir & GT_BSD_USER_INTERRUPT)
1359 notify_ring(dev, &dev_priv->ring[VCS]);
1360 if (gt_iir & GT_BLT_USER_INTERRUPT)
1361 notify_ring(dev, &dev_priv->ring[BCS]);
1362
1363 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1364 GT_BSD_CS_ERROR_INTERRUPT |
1365 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1366 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1367
1368 if (gt_iir & GT_PARITY_ERROR(dev))
1369 ivybridge_parity_error_irq_handler(dev, gt_iir);
1370 }
1371
1372 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1373 struct drm_i915_private *dev_priv,
1374 u32 master_ctl)
1375 {
1376 struct intel_engine_cs *ring;
1377 u32 rcs, bcs, vcs;
1378 uint32_t tmp = 0;
1379 irqreturn_t ret = IRQ_NONE;
1380
1381 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1382 tmp = I915_READ(GEN8_GT_IIR(0));
1383 if (tmp) {
1384 I915_WRITE(GEN8_GT_IIR(0), tmp);
1385 ret = IRQ_HANDLED;
1386
1387 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1388 ring = &dev_priv->ring[RCS];
1389 if (rcs & GT_RENDER_USER_INTERRUPT)
1390 notify_ring(dev, ring);
1391 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1392 intel_lrc_irq_handler(ring);
1393
1394 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1395 ring = &dev_priv->ring[BCS];
1396 if (bcs & GT_RENDER_USER_INTERRUPT)
1397 notify_ring(dev, ring);
1398 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1399 intel_lrc_irq_handler(ring);
1400 } else
1401 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1402 }
1403
1404 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1405 tmp = I915_READ(GEN8_GT_IIR(1));
1406 if (tmp) {
1407 I915_WRITE(GEN8_GT_IIR(1), tmp);
1408 ret = IRQ_HANDLED;
1409
1410 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1411 ring = &dev_priv->ring[VCS];
1412 if (vcs & GT_RENDER_USER_INTERRUPT)
1413 notify_ring(dev, ring);
1414 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1415 intel_lrc_irq_handler(ring);
1416
1417 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1418 ring = &dev_priv->ring[VCS2];
1419 if (vcs & GT_RENDER_USER_INTERRUPT)
1420 notify_ring(dev, ring);
1421 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1422 intel_lrc_irq_handler(ring);
1423 } else
1424 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1425 }
1426
1427 if (master_ctl & GEN8_GT_PM_IRQ) {
1428 tmp = I915_READ(GEN8_GT_IIR(2));
1429 if (tmp & dev_priv->pm_rps_events) {
1430 I915_WRITE(GEN8_GT_IIR(2),
1431 tmp & dev_priv->pm_rps_events);
1432 ret = IRQ_HANDLED;
1433 gen6_rps_irq_handler(dev_priv, tmp);
1434 } else
1435 DRM_ERROR("The master control interrupt lied (PM)!\n");
1436 }
1437
1438 if (master_ctl & GEN8_GT_VECS_IRQ) {
1439 tmp = I915_READ(GEN8_GT_IIR(3));
1440 if (tmp) {
1441 I915_WRITE(GEN8_GT_IIR(3), tmp);
1442 ret = IRQ_HANDLED;
1443
1444 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1445 ring = &dev_priv->ring[VECS];
1446 if (vcs & GT_RENDER_USER_INTERRUPT)
1447 notify_ring(dev, ring);
1448 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1449 intel_lrc_irq_handler(ring);
1450 } else
1451 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1452 }
1453
1454 return ret;
1455 }
1456
1457 #define HPD_STORM_DETECT_PERIOD 1000
1458 #define HPD_STORM_THRESHOLD 5
1459
1460 static int pch_port_to_hotplug_shift(enum port port)
1461 {
1462 switch (port) {
1463 case PORT_A:
1464 case PORT_E:
1465 default:
1466 return -1;
1467 case PORT_B:
1468 return 0;
1469 case PORT_C:
1470 return 8;
1471 case PORT_D:
1472 return 16;
1473 }
1474 }
1475
1476 static int i915_port_to_hotplug_shift(enum port port)
1477 {
1478 switch (port) {
1479 case PORT_A:
1480 case PORT_E:
1481 default:
1482 return -1;
1483 case PORT_B:
1484 return 17;
1485 case PORT_C:
1486 return 19;
1487 case PORT_D:
1488 return 21;
1489 }
1490 }
1491
1492 static inline enum port get_port_from_pin(enum hpd_pin pin)
1493 {
1494 switch (pin) {
1495 case HPD_PORT_B:
1496 return PORT_B;
1497 case HPD_PORT_C:
1498 return PORT_C;
1499 case HPD_PORT_D:
1500 return PORT_D;
1501 default:
1502 return PORT_A; /* no hpd */
1503 }
1504 }
1505
1506 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1507 u32 hotplug_trigger,
1508 u32 dig_hotplug_reg,
1509 const u32 *hpd)
1510 {
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int i;
1513 enum port port;
1514 bool storm_detected = false;
1515 bool queue_dig = false, queue_hp = false;
1516 u32 dig_shift;
1517 u32 dig_port_mask = 0;
1518
1519 if (!hotplug_trigger)
1520 return;
1521
1522 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1523 hotplug_trigger, dig_hotplug_reg);
1524
1525 spin_lock(&dev_priv->irq_lock);
1526 for (i = 1; i < HPD_NUM_PINS; i++) {
1527 if (!(hpd[i] & hotplug_trigger))
1528 continue;
1529
1530 port = get_port_from_pin(i);
1531 if (port && dev_priv->hpd_irq_port[port]) {
1532 bool long_hpd;
1533
1534 if (HAS_PCH_SPLIT(dev)) {
1535 dig_shift = pch_port_to_hotplug_shift(port);
1536 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1537 } else {
1538 dig_shift = i915_port_to_hotplug_shift(port);
1539 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1540 }
1541
1542 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1543 port_name(port),
1544 long_hpd ? "long" : "short");
1545 /* for long HPD pulses we want to have the digital queue happen,
1546 but we still want HPD storm detection to function. */
1547 if (long_hpd) {
1548 dev_priv->long_hpd_port_mask |= (1 << port);
1549 dig_port_mask |= hpd[i];
1550 } else {
1551 /* for short HPD just trigger the digital queue */
1552 dev_priv->short_hpd_port_mask |= (1 << port);
1553 hotplug_trigger &= ~hpd[i];
1554 }
1555 queue_dig = true;
1556 }
1557 }
1558
1559 for (i = 1; i < HPD_NUM_PINS; i++) {
1560 if (hpd[i] & hotplug_trigger &&
1561 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1562 /*
1563 * On GMCH platforms the interrupt mask bits only
1564 * prevent irq generation, not the setting of the
1565 * hotplug bits itself. So only WARN about unexpected
1566 * interrupts on saner platforms.
1567 */
1568 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1569 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1570 hotplug_trigger, i, hpd[i]);
1571
1572 continue;
1573 }
1574
1575 if (!(hpd[i] & hotplug_trigger) ||
1576 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1577 continue;
1578
1579 if (!(dig_port_mask & hpd[i])) {
1580 dev_priv->hpd_event_bits |= (1 << i);
1581 queue_hp = true;
1582 }
1583
1584 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1585 dev_priv->hpd_stats[i].hpd_last_jiffies
1586 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1587 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1588 dev_priv->hpd_stats[i].hpd_cnt = 0;
1589 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1590 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1591 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1592 dev_priv->hpd_event_bits &= ~(1 << i);
1593 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1594 storm_detected = true;
1595 } else {
1596 dev_priv->hpd_stats[i].hpd_cnt++;
1597 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1598 dev_priv->hpd_stats[i].hpd_cnt);
1599 }
1600 }
1601
1602 if (storm_detected)
1603 dev_priv->display.hpd_irq_setup(dev);
1604 spin_unlock(&dev_priv->irq_lock);
1605
1606 /*
1607 * Our hotplug handler can grab modeset locks (by calling down into the
1608 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1609 * queue for otherwise the flush_work in the pageflip code will
1610 * deadlock.
1611 */
1612 if (queue_dig)
1613 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1614 if (queue_hp)
1615 schedule_work(&dev_priv->hotplug_work);
1616 }
1617
1618 static void gmbus_irq_handler(struct drm_device *dev)
1619 {
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621
1622 wake_up_all(&dev_priv->gmbus_wait_queue);
1623 }
1624
1625 static void dp_aux_irq_handler(struct drm_device *dev)
1626 {
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628
1629 wake_up_all(&dev_priv->gmbus_wait_queue);
1630 }
1631
1632 #if defined(CONFIG_DEBUG_FS)
1633 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1634 uint32_t crc0, uint32_t crc1,
1635 uint32_t crc2, uint32_t crc3,
1636 uint32_t crc4)
1637 {
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1640 struct intel_pipe_crc_entry *entry;
1641 int head, tail;
1642
1643 spin_lock(&pipe_crc->lock);
1644
1645 if (!pipe_crc->entries) {
1646 spin_unlock(&pipe_crc->lock);
1647 DRM_DEBUG_KMS("spurious interrupt\n");
1648 return;
1649 }
1650
1651 head = pipe_crc->head;
1652 tail = pipe_crc->tail;
1653
1654 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1655 spin_unlock(&pipe_crc->lock);
1656 DRM_ERROR("CRC buffer overflowing\n");
1657 return;
1658 }
1659
1660 entry = &pipe_crc->entries[head];
1661
1662 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1663 entry->crc[0] = crc0;
1664 entry->crc[1] = crc1;
1665 entry->crc[2] = crc2;
1666 entry->crc[3] = crc3;
1667 entry->crc[4] = crc4;
1668
1669 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1670 pipe_crc->head = head;
1671
1672 spin_unlock(&pipe_crc->lock);
1673
1674 wake_up_interruptible(&pipe_crc->wq);
1675 }
1676 #else
1677 static inline void
1678 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1679 uint32_t crc0, uint32_t crc1,
1680 uint32_t crc2, uint32_t crc3,
1681 uint32_t crc4) {}
1682 #endif
1683
1684
1685 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1686 {
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688
1689 display_pipe_crc_irq_handler(dev, pipe,
1690 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1691 0, 0, 0, 0);
1692 }
1693
1694 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1695 {
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698 display_pipe_crc_irq_handler(dev, pipe,
1699 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1700 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1701 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1702 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1703 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1704 }
1705
1706 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1707 {
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 uint32_t res1, res2;
1710
1711 if (INTEL_INFO(dev)->gen >= 3)
1712 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1713 else
1714 res1 = 0;
1715
1716 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1717 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1718 else
1719 res2 = 0;
1720
1721 display_pipe_crc_irq_handler(dev, pipe,
1722 I915_READ(PIPE_CRC_RES_RED(pipe)),
1723 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1724 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1725 res1, res2);
1726 }
1727
1728 /* The RPS events need forcewake, so we add them to a work queue and mask their
1729 * IMR bits until the work is done. Other interrupts can be processed without
1730 * the work queue. */
1731 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1732 {
1733 /* TODO: RPS on GEN9+ is not supported yet. */
1734 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1735 "GEN9+: unexpected RPS IRQ\n"))
1736 return;
1737
1738 if (pm_iir & dev_priv->pm_rps_events) {
1739 spin_lock(&dev_priv->irq_lock);
1740 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1741 if (dev_priv->rps.interrupts_enabled) {
1742 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1743 queue_work(dev_priv->wq, &dev_priv->rps.work);
1744 }
1745 spin_unlock(&dev_priv->irq_lock);
1746 }
1747
1748 if (INTEL_INFO(dev_priv)->gen >= 8)
1749 return;
1750
1751 if (HAS_VEBOX(dev_priv->dev)) {
1752 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1753 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1754
1755 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1756 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1757 }
1758 }
1759
1760 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1761 {
1762 if (!drm_handle_vblank(dev, pipe))
1763 return false;
1764
1765 return true;
1766 }
1767
1768 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1769 {
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 u32 pipe_stats[I915_MAX_PIPES] = { };
1772 int pipe;
1773
1774 spin_lock(&dev_priv->irq_lock);
1775 for_each_pipe(dev_priv, pipe) {
1776 int reg;
1777 u32 mask, iir_bit = 0;
1778
1779 /*
1780 * PIPESTAT bits get signalled even when the interrupt is
1781 * disabled with the mask bits, and some of the status bits do
1782 * not generate interrupts at all (like the underrun bit). Hence
1783 * we need to be careful that we only handle what we want to
1784 * handle.
1785 */
1786
1787 /* fifo underruns are filterered in the underrun handler. */
1788 mask = PIPE_FIFO_UNDERRUN_STATUS;
1789
1790 switch (pipe) {
1791 case PIPE_A:
1792 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1793 break;
1794 case PIPE_B:
1795 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1796 break;
1797 case PIPE_C:
1798 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1799 break;
1800 }
1801 if (iir & iir_bit)
1802 mask |= dev_priv->pipestat_irq_mask[pipe];
1803
1804 if (!mask)
1805 continue;
1806
1807 reg = PIPESTAT(pipe);
1808 mask |= PIPESTAT_INT_ENABLE_MASK;
1809 pipe_stats[pipe] = I915_READ(reg) & mask;
1810
1811 /*
1812 * Clear the PIPE*STAT regs before the IIR
1813 */
1814 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1815 PIPESTAT_INT_STATUS_MASK))
1816 I915_WRITE(reg, pipe_stats[pipe]);
1817 }
1818 spin_unlock(&dev_priv->irq_lock);
1819
1820 for_each_pipe(dev_priv, pipe) {
1821 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1822 intel_pipe_handle_vblank(dev, pipe))
1823 intel_check_page_flip(dev, pipe);
1824
1825 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1826 intel_prepare_page_flip(dev, pipe);
1827 intel_finish_page_flip(dev, pipe);
1828 }
1829
1830 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1831 i9xx_pipe_crc_irq_handler(dev, pipe);
1832
1833 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1834 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1835 }
1836
1837 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1838 gmbus_irq_handler(dev);
1839 }
1840
1841 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1842 {
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1845
1846 if (hotplug_status) {
1847 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1848 /*
1849 * Make sure hotplug status is cleared before we clear IIR, or else we
1850 * may miss hotplug events.
1851 */
1852 POSTING_READ(PORT_HOTPLUG_STAT);
1853
1854 if (IS_G4X(dev)) {
1855 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1856
1857 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1858 } else {
1859 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1860
1861 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1862 }
1863
1864 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1865 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1866 dp_aux_irq_handler(dev);
1867 }
1868 }
1869
1870 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1871 {
1872 struct drm_device *dev = arg;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 u32 iir, gt_iir, pm_iir;
1875 irqreturn_t ret = IRQ_NONE;
1876
1877 while (true) {
1878 /* Find, clear, then process each source of interrupt */
1879
1880 gt_iir = I915_READ(GTIIR);
1881 if (gt_iir)
1882 I915_WRITE(GTIIR, gt_iir);
1883
1884 pm_iir = I915_READ(GEN6_PMIIR);
1885 if (pm_iir)
1886 I915_WRITE(GEN6_PMIIR, pm_iir);
1887
1888 iir = I915_READ(VLV_IIR);
1889 if (iir) {
1890 /* Consume port before clearing IIR or we'll miss events */
1891 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1892 i9xx_hpd_irq_handler(dev);
1893 I915_WRITE(VLV_IIR, iir);
1894 }
1895
1896 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1897 goto out;
1898
1899 ret = IRQ_HANDLED;
1900
1901 if (gt_iir)
1902 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1903 if (pm_iir)
1904 gen6_rps_irq_handler(dev_priv, pm_iir);
1905 /* Call regardless, as some status bits might not be
1906 * signalled in iir */
1907 valleyview_pipestat_irq_handler(dev, iir);
1908 }
1909
1910 out:
1911 return ret;
1912 }
1913
1914 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1915 {
1916 struct drm_device *dev = arg;
1917 struct drm_i915_private *dev_priv = dev->dev_private;
1918 u32 master_ctl, iir;
1919 irqreturn_t ret = IRQ_NONE;
1920
1921 for (;;) {
1922 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1923 iir = I915_READ(VLV_IIR);
1924
1925 if (master_ctl == 0 && iir == 0)
1926 break;
1927
1928 ret = IRQ_HANDLED;
1929
1930 I915_WRITE(GEN8_MASTER_IRQ, 0);
1931
1932 /* Find, clear, then process each source of interrupt */
1933
1934 if (iir) {
1935 /* Consume port before clearing IIR or we'll miss events */
1936 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1937 i9xx_hpd_irq_handler(dev);
1938 I915_WRITE(VLV_IIR, iir);
1939 }
1940
1941 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1942
1943 /* Call regardless, as some status bits might not be
1944 * signalled in iir */
1945 valleyview_pipestat_irq_handler(dev, iir);
1946
1947 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1948 POSTING_READ(GEN8_MASTER_IRQ);
1949 }
1950
1951 return ret;
1952 }
1953
1954 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1955 {
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 int pipe;
1958 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1959 u32 dig_hotplug_reg;
1960
1961 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1962 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1963
1964 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1965
1966 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1967 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1968 SDE_AUDIO_POWER_SHIFT);
1969 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1970 port_name(port));
1971 }
1972
1973 if (pch_iir & SDE_AUX_MASK)
1974 dp_aux_irq_handler(dev);
1975
1976 if (pch_iir & SDE_GMBUS)
1977 gmbus_irq_handler(dev);
1978
1979 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1980 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1981
1982 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1983 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1984
1985 if (pch_iir & SDE_POISON)
1986 DRM_ERROR("PCH poison interrupt\n");
1987
1988 if (pch_iir & SDE_FDI_MASK)
1989 for_each_pipe(dev_priv, pipe)
1990 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1991 pipe_name(pipe),
1992 I915_READ(FDI_RX_IIR(pipe)));
1993
1994 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1995 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1996
1997 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1998 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1999
2000 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2001 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2002
2003 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2004 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2005 }
2006
2007 static void ivb_err_int_handler(struct drm_device *dev)
2008 {
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 err_int = I915_READ(GEN7_ERR_INT);
2011 enum pipe pipe;
2012
2013 if (err_int & ERR_INT_POISON)
2014 DRM_ERROR("Poison interrupt\n");
2015
2016 for_each_pipe(dev_priv, pipe) {
2017 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2018 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2019
2020 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2021 if (IS_IVYBRIDGE(dev))
2022 ivb_pipe_crc_irq_handler(dev, pipe);
2023 else
2024 hsw_pipe_crc_irq_handler(dev, pipe);
2025 }
2026 }
2027
2028 I915_WRITE(GEN7_ERR_INT, err_int);
2029 }
2030
2031 static void cpt_serr_int_handler(struct drm_device *dev)
2032 {
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2034 u32 serr_int = I915_READ(SERR_INT);
2035
2036 if (serr_int & SERR_INT_POISON)
2037 DRM_ERROR("PCH poison interrupt\n");
2038
2039 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2040 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2041
2042 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2043 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2044
2045 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2046 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2047
2048 I915_WRITE(SERR_INT, serr_int);
2049 }
2050
2051 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2052 {
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 int pipe;
2055 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2056 u32 dig_hotplug_reg;
2057
2058 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2059 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2060
2061 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2062
2063 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2064 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2065 SDE_AUDIO_POWER_SHIFT_CPT);
2066 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2067 port_name(port));
2068 }
2069
2070 if (pch_iir & SDE_AUX_MASK_CPT)
2071 dp_aux_irq_handler(dev);
2072
2073 if (pch_iir & SDE_GMBUS_CPT)
2074 gmbus_irq_handler(dev);
2075
2076 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2077 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2078
2079 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2080 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2081
2082 if (pch_iir & SDE_FDI_MASK_CPT)
2083 for_each_pipe(dev_priv, pipe)
2084 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2085 pipe_name(pipe),
2086 I915_READ(FDI_RX_IIR(pipe)));
2087
2088 if (pch_iir & SDE_ERROR_CPT)
2089 cpt_serr_int_handler(dev);
2090 }
2091
2092 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2093 {
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 enum pipe pipe;
2096
2097 if (de_iir & DE_AUX_CHANNEL_A)
2098 dp_aux_irq_handler(dev);
2099
2100 if (de_iir & DE_GSE)
2101 intel_opregion_asle_intr(dev);
2102
2103 if (de_iir & DE_POISON)
2104 DRM_ERROR("Poison interrupt\n");
2105
2106 for_each_pipe(dev_priv, pipe) {
2107 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2108 intel_pipe_handle_vblank(dev, pipe))
2109 intel_check_page_flip(dev, pipe);
2110
2111 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2112 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2113
2114 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2115 i9xx_pipe_crc_irq_handler(dev, pipe);
2116
2117 /* plane/pipes map 1:1 on ilk+ */
2118 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2119 intel_prepare_page_flip(dev, pipe);
2120 intel_finish_page_flip_plane(dev, pipe);
2121 }
2122 }
2123
2124 /* check event from PCH */
2125 if (de_iir & DE_PCH_EVENT) {
2126 u32 pch_iir = I915_READ(SDEIIR);
2127
2128 if (HAS_PCH_CPT(dev))
2129 cpt_irq_handler(dev, pch_iir);
2130 else
2131 ibx_irq_handler(dev, pch_iir);
2132
2133 /* should clear PCH hotplug event before clear CPU irq */
2134 I915_WRITE(SDEIIR, pch_iir);
2135 }
2136
2137 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2138 ironlake_rps_change_irq_handler(dev);
2139 }
2140
2141 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2142 {
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 enum pipe pipe;
2145
2146 if (de_iir & DE_ERR_INT_IVB)
2147 ivb_err_int_handler(dev);
2148
2149 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2150 dp_aux_irq_handler(dev);
2151
2152 if (de_iir & DE_GSE_IVB)
2153 intel_opregion_asle_intr(dev);
2154
2155 for_each_pipe(dev_priv, pipe) {
2156 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2157 intel_pipe_handle_vblank(dev, pipe))
2158 intel_check_page_flip(dev, pipe);
2159
2160 /* plane/pipes map 1:1 on ilk+ */
2161 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2162 intel_prepare_page_flip(dev, pipe);
2163 intel_finish_page_flip_plane(dev, pipe);
2164 }
2165 }
2166
2167 /* check event from PCH */
2168 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2169 u32 pch_iir = I915_READ(SDEIIR);
2170
2171 cpt_irq_handler(dev, pch_iir);
2172
2173 /* clear PCH hotplug event before clear CPU irq */
2174 I915_WRITE(SDEIIR, pch_iir);
2175 }
2176 }
2177
2178 /*
2179 * To handle irqs with the minimum potential races with fresh interrupts, we:
2180 * 1 - Disable Master Interrupt Control.
2181 * 2 - Find the source(s) of the interrupt.
2182 * 3 - Clear the Interrupt Identity bits (IIR).
2183 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2184 * 5 - Re-enable Master Interrupt Control.
2185 */
2186 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2187 {
2188 struct drm_device *dev = arg;
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2191 irqreturn_t ret = IRQ_NONE;
2192
2193 /* We get interrupts on unclaimed registers, so check for this before we
2194 * do any I915_{READ,WRITE}. */
2195 intel_uncore_check_errors(dev);
2196
2197 /* disable master interrupt before clearing iir */
2198 de_ier = I915_READ(DEIER);
2199 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2200 POSTING_READ(DEIER);
2201
2202 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2203 * interrupts will will be stored on its back queue, and then we'll be
2204 * able to process them after we restore SDEIER (as soon as we restore
2205 * it, we'll get an interrupt if SDEIIR still has something to process
2206 * due to its back queue). */
2207 if (!HAS_PCH_NOP(dev)) {
2208 sde_ier = I915_READ(SDEIER);
2209 I915_WRITE(SDEIER, 0);
2210 POSTING_READ(SDEIER);
2211 }
2212
2213 /* Find, clear, then process each source of interrupt */
2214
2215 gt_iir = I915_READ(GTIIR);
2216 if (gt_iir) {
2217 I915_WRITE(GTIIR, gt_iir);
2218 ret = IRQ_HANDLED;
2219 if (INTEL_INFO(dev)->gen >= 6)
2220 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2221 else
2222 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2223 }
2224
2225 de_iir = I915_READ(DEIIR);
2226 if (de_iir) {
2227 I915_WRITE(DEIIR, de_iir);
2228 ret = IRQ_HANDLED;
2229 if (INTEL_INFO(dev)->gen >= 7)
2230 ivb_display_irq_handler(dev, de_iir);
2231 else
2232 ilk_display_irq_handler(dev, de_iir);
2233 }
2234
2235 if (INTEL_INFO(dev)->gen >= 6) {
2236 u32 pm_iir = I915_READ(GEN6_PMIIR);
2237 if (pm_iir) {
2238 I915_WRITE(GEN6_PMIIR, pm_iir);
2239 ret = IRQ_HANDLED;
2240 gen6_rps_irq_handler(dev_priv, pm_iir);
2241 }
2242 }
2243
2244 I915_WRITE(DEIER, de_ier);
2245 POSTING_READ(DEIER);
2246 if (!HAS_PCH_NOP(dev)) {
2247 I915_WRITE(SDEIER, sde_ier);
2248 POSTING_READ(SDEIER);
2249 }
2250
2251 return ret;
2252 }
2253
2254 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2255 {
2256 struct drm_device *dev = arg;
2257 struct drm_i915_private *dev_priv = dev->dev_private;
2258 u32 master_ctl;
2259 irqreturn_t ret = IRQ_NONE;
2260 uint32_t tmp = 0;
2261 enum pipe pipe;
2262 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2263
2264 if (IS_GEN9(dev))
2265 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2266 GEN9_AUX_CHANNEL_D;
2267
2268 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2269 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2270 if (!master_ctl)
2271 return IRQ_NONE;
2272
2273 I915_WRITE(GEN8_MASTER_IRQ, 0);
2274 POSTING_READ(GEN8_MASTER_IRQ);
2275
2276 /* Find, clear, then process each source of interrupt */
2277
2278 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2279
2280 if (master_ctl & GEN8_DE_MISC_IRQ) {
2281 tmp = I915_READ(GEN8_DE_MISC_IIR);
2282 if (tmp) {
2283 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2284 ret = IRQ_HANDLED;
2285 if (tmp & GEN8_DE_MISC_GSE)
2286 intel_opregion_asle_intr(dev);
2287 else
2288 DRM_ERROR("Unexpected DE Misc interrupt\n");
2289 }
2290 else
2291 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2292 }
2293
2294 if (master_ctl & GEN8_DE_PORT_IRQ) {
2295 tmp = I915_READ(GEN8_DE_PORT_IIR);
2296 if (tmp) {
2297 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2298 ret = IRQ_HANDLED;
2299
2300 if (tmp & aux_mask)
2301 dp_aux_irq_handler(dev);
2302 else
2303 DRM_ERROR("Unexpected DE Port interrupt\n");
2304 }
2305 else
2306 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2307 }
2308
2309 for_each_pipe(dev_priv, pipe) {
2310 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2311
2312 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2313 continue;
2314
2315 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2316 if (pipe_iir) {
2317 ret = IRQ_HANDLED;
2318 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2319
2320 if (pipe_iir & GEN8_PIPE_VBLANK &&
2321 intel_pipe_handle_vblank(dev, pipe))
2322 intel_check_page_flip(dev, pipe);
2323
2324 if (IS_GEN9(dev))
2325 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2326 else
2327 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2328
2329 if (flip_done) {
2330 intel_prepare_page_flip(dev, pipe);
2331 intel_finish_page_flip_plane(dev, pipe);
2332 }
2333
2334 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2335 hsw_pipe_crc_irq_handler(dev, pipe);
2336
2337 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2338 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2339 pipe);
2340
2341
2342 if (IS_GEN9(dev))
2343 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2344 else
2345 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2346
2347 if (fault_errors)
2348 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2349 pipe_name(pipe),
2350 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2351 } else
2352 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2353 }
2354
2355 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2356 /*
2357 * FIXME(BDW): Assume for now that the new interrupt handling
2358 * scheme also closed the SDE interrupt handling race we've seen
2359 * on older pch-split platforms. But this needs testing.
2360 */
2361 u32 pch_iir = I915_READ(SDEIIR);
2362 if (pch_iir) {
2363 I915_WRITE(SDEIIR, pch_iir);
2364 ret = IRQ_HANDLED;
2365 cpt_irq_handler(dev, pch_iir);
2366 } else
2367 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2368
2369 }
2370
2371 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2372 POSTING_READ(GEN8_MASTER_IRQ);
2373
2374 return ret;
2375 }
2376
2377 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2378 bool reset_completed)
2379 {
2380 struct intel_engine_cs *ring;
2381 int i;
2382
2383 /*
2384 * Notify all waiters for GPU completion events that reset state has
2385 * been changed, and that they need to restart their wait after
2386 * checking for potential errors (and bail out to drop locks if there is
2387 * a gpu reset pending so that i915_error_work_func can acquire them).
2388 */
2389
2390 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2391 for_each_ring(ring, dev_priv, i)
2392 wake_up_all(&ring->irq_queue);
2393
2394 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2395 wake_up_all(&dev_priv->pending_flip_queue);
2396
2397 /*
2398 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2399 * reset state is cleared.
2400 */
2401 if (reset_completed)
2402 wake_up_all(&dev_priv->gpu_error.reset_queue);
2403 }
2404
2405 /**
2406 * i915_error_work_func - do process context error handling work
2407 * @work: work struct
2408 *
2409 * Fire an error uevent so userspace can see that a hang or error
2410 * was detected.
2411 */
2412 static void i915_error_work_func(struct work_struct *work)
2413 {
2414 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2415 work);
2416 struct drm_i915_private *dev_priv =
2417 container_of(error, struct drm_i915_private, gpu_error);
2418 struct drm_device *dev = dev_priv->dev;
2419 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2420 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2421 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2422 int ret;
2423
2424 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2425
2426 /*
2427 * Note that there's only one work item which does gpu resets, so we
2428 * need not worry about concurrent gpu resets potentially incrementing
2429 * error->reset_counter twice. We only need to take care of another
2430 * racing irq/hangcheck declaring the gpu dead for a second time. A
2431 * quick check for that is good enough: schedule_work ensures the
2432 * correct ordering between hang detection and this work item, and since
2433 * the reset in-progress bit is only ever set by code outside of this
2434 * work we don't need to worry about any other races.
2435 */
2436 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2437 DRM_DEBUG_DRIVER("resetting chip\n");
2438 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2439 reset_event);
2440
2441 /*
2442 * In most cases it's guaranteed that we get here with an RPM
2443 * reference held, for example because there is a pending GPU
2444 * request that won't finish until the reset is done. This
2445 * isn't the case at least when we get here by doing a
2446 * simulated reset via debugs, so get an RPM reference.
2447 */
2448 intel_runtime_pm_get(dev_priv);
2449
2450 intel_prepare_reset(dev);
2451
2452 /*
2453 * All state reset _must_ be completed before we update the
2454 * reset counter, for otherwise waiters might miss the reset
2455 * pending state and not properly drop locks, resulting in
2456 * deadlocks with the reset work.
2457 */
2458 ret = i915_reset(dev);
2459
2460 intel_finish_reset(dev);
2461
2462 intel_runtime_pm_put(dev_priv);
2463
2464 if (ret == 0) {
2465 /*
2466 * After all the gem state is reset, increment the reset
2467 * counter and wake up everyone waiting for the reset to
2468 * complete.
2469 *
2470 * Since unlock operations are a one-sided barrier only,
2471 * we need to insert a barrier here to order any seqno
2472 * updates before
2473 * the counter increment.
2474 */
2475 smp_mb__before_atomic();
2476 atomic_inc(&dev_priv->gpu_error.reset_counter);
2477
2478 kobject_uevent_env(&dev->primary->kdev->kobj,
2479 KOBJ_CHANGE, reset_done_event);
2480 } else {
2481 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2482 }
2483
2484 /*
2485 * Note: The wake_up also serves as a memory barrier so that
2486 * waiters see the update value of the reset counter atomic_t.
2487 */
2488 i915_error_wake_up(dev_priv, true);
2489 }
2490 }
2491
2492 static void i915_report_and_clear_eir(struct drm_device *dev)
2493 {
2494 struct drm_i915_private *dev_priv = dev->dev_private;
2495 uint32_t instdone[I915_NUM_INSTDONE_REG];
2496 u32 eir = I915_READ(EIR);
2497 int pipe, i;
2498
2499 if (!eir)
2500 return;
2501
2502 pr_err("render error detected, EIR: 0x%08x\n", eir);
2503
2504 i915_get_extra_instdone(dev, instdone);
2505
2506 if (IS_G4X(dev)) {
2507 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2508 u32 ipeir = I915_READ(IPEIR_I965);
2509
2510 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2511 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2512 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2513 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2514 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2515 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2516 I915_WRITE(IPEIR_I965, ipeir);
2517 POSTING_READ(IPEIR_I965);
2518 }
2519 if (eir & GM45_ERROR_PAGE_TABLE) {
2520 u32 pgtbl_err = I915_READ(PGTBL_ER);
2521 pr_err("page table error\n");
2522 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2523 I915_WRITE(PGTBL_ER, pgtbl_err);
2524 POSTING_READ(PGTBL_ER);
2525 }
2526 }
2527
2528 if (!IS_GEN2(dev)) {
2529 if (eir & I915_ERROR_PAGE_TABLE) {
2530 u32 pgtbl_err = I915_READ(PGTBL_ER);
2531 pr_err("page table error\n");
2532 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2533 I915_WRITE(PGTBL_ER, pgtbl_err);
2534 POSTING_READ(PGTBL_ER);
2535 }
2536 }
2537
2538 if (eir & I915_ERROR_MEMORY_REFRESH) {
2539 pr_err("memory refresh error:\n");
2540 for_each_pipe(dev_priv, pipe)
2541 pr_err("pipe %c stat: 0x%08x\n",
2542 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2543 /* pipestat has already been acked */
2544 }
2545 if (eir & I915_ERROR_INSTRUCTION) {
2546 pr_err("instruction error\n");
2547 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2548 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2549 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2550 if (INTEL_INFO(dev)->gen < 4) {
2551 u32 ipeir = I915_READ(IPEIR);
2552
2553 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2554 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2555 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2556 I915_WRITE(IPEIR, ipeir);
2557 POSTING_READ(IPEIR);
2558 } else {
2559 u32 ipeir = I915_READ(IPEIR_I965);
2560
2561 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2562 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2563 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2564 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2565 I915_WRITE(IPEIR_I965, ipeir);
2566 POSTING_READ(IPEIR_I965);
2567 }
2568 }
2569
2570 I915_WRITE(EIR, eir);
2571 POSTING_READ(EIR);
2572 eir = I915_READ(EIR);
2573 if (eir) {
2574 /*
2575 * some errors might have become stuck,
2576 * mask them.
2577 */
2578 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2579 I915_WRITE(EMR, I915_READ(EMR) | eir);
2580 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2581 }
2582 }
2583
2584 /**
2585 * i915_handle_error - handle an error interrupt
2586 * @dev: drm device
2587 *
2588 * Do some basic checking of regsiter state at error interrupt time and
2589 * dump it to the syslog. Also call i915_capture_error_state() to make
2590 * sure we get a record and make it available in debugfs. Fire a uevent
2591 * so userspace knows something bad happened (should trigger collection
2592 * of a ring dump etc.).
2593 */
2594 void i915_handle_error(struct drm_device *dev, bool wedged,
2595 const char *fmt, ...)
2596 {
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 va_list args;
2599 char error_msg[80];
2600
2601 va_start(args, fmt);
2602 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2603 va_end(args);
2604
2605 i915_capture_error_state(dev, wedged, error_msg);
2606 i915_report_and_clear_eir(dev);
2607
2608 if (wedged) {
2609 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2610 &dev_priv->gpu_error.reset_counter);
2611
2612 /*
2613 * Wakeup waiting processes so that the reset work function
2614 * i915_error_work_func doesn't deadlock trying to grab various
2615 * locks. By bumping the reset counter first, the woken
2616 * processes will see a reset in progress and back off,
2617 * releasing their locks and then wait for the reset completion.
2618 * We must do this for _all_ gpu waiters that might hold locks
2619 * that the reset work needs to acquire.
2620 *
2621 * Note: The wake_up serves as the required memory barrier to
2622 * ensure that the waiters see the updated value of the reset
2623 * counter atomic_t.
2624 */
2625 i915_error_wake_up(dev_priv, false);
2626 }
2627
2628 /*
2629 * Our reset work can grab modeset locks (since it needs to reset the
2630 * state of outstanding pagelips). Hence it must not be run on our own
2631 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2632 * code will deadlock.
2633 */
2634 schedule_work(&dev_priv->gpu_error.work);
2635 }
2636
2637 /* Called from drm generic code, passed 'crtc' which
2638 * we use as a pipe index
2639 */
2640 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2641 {
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 unsigned long irqflags;
2644
2645 if (!i915_pipe_enabled(dev, pipe))
2646 return -EINVAL;
2647
2648 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2649 if (INTEL_INFO(dev)->gen >= 4)
2650 i915_enable_pipestat(dev_priv, pipe,
2651 PIPE_START_VBLANK_INTERRUPT_STATUS);
2652 else
2653 i915_enable_pipestat(dev_priv, pipe,
2654 PIPE_VBLANK_INTERRUPT_STATUS);
2655 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2656
2657 return 0;
2658 }
2659
2660 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2661 {
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663 unsigned long irqflags;
2664 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2665 DE_PIPE_VBLANK(pipe);
2666
2667 if (!i915_pipe_enabled(dev, pipe))
2668 return -EINVAL;
2669
2670 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2671 ironlake_enable_display_irq(dev_priv, bit);
2672 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2673
2674 return 0;
2675 }
2676
2677 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2678 {
2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680 unsigned long irqflags;
2681
2682 if (!i915_pipe_enabled(dev, pipe))
2683 return -EINVAL;
2684
2685 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2686 i915_enable_pipestat(dev_priv, pipe,
2687 PIPE_START_VBLANK_INTERRUPT_STATUS);
2688 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2689
2690 return 0;
2691 }
2692
2693 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2694 {
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 unsigned long irqflags;
2697
2698 if (!i915_pipe_enabled(dev, pipe))
2699 return -EINVAL;
2700
2701 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2702 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2703 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2704 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2705 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2706 return 0;
2707 }
2708
2709 /* Called from drm generic code, passed 'crtc' which
2710 * we use as a pipe index
2711 */
2712 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2713 {
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 unsigned long irqflags;
2716
2717 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2718 i915_disable_pipestat(dev_priv, pipe,
2719 PIPE_VBLANK_INTERRUPT_STATUS |
2720 PIPE_START_VBLANK_INTERRUPT_STATUS);
2721 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2722 }
2723
2724 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2725 {
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 unsigned long irqflags;
2728 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2729 DE_PIPE_VBLANK(pipe);
2730
2731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2732 ironlake_disable_display_irq(dev_priv, bit);
2733 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2734 }
2735
2736 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2737 {
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 unsigned long irqflags;
2740
2741 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2742 i915_disable_pipestat(dev_priv, pipe,
2743 PIPE_START_VBLANK_INTERRUPT_STATUS);
2744 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2745 }
2746
2747 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2748 {
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 unsigned long irqflags;
2751
2752 if (!i915_pipe_enabled(dev, pipe))
2753 return;
2754
2755 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2756 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2757 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2758 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2759 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2760 }
2761
2762 static struct drm_i915_gem_request *
2763 ring_last_request(struct intel_engine_cs *ring)
2764 {
2765 return list_entry(ring->request_list.prev,
2766 struct drm_i915_gem_request, list);
2767 }
2768
2769 static bool
2770 ring_idle(struct intel_engine_cs *ring)
2771 {
2772 return (list_empty(&ring->request_list) ||
2773 i915_gem_request_completed(ring_last_request(ring), false));
2774 }
2775
2776 static bool
2777 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2778 {
2779 if (INTEL_INFO(dev)->gen >= 8) {
2780 return (ipehr >> 23) == 0x1c;
2781 } else {
2782 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2783 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2784 MI_SEMAPHORE_REGISTER);
2785 }
2786 }
2787
2788 static struct intel_engine_cs *
2789 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2790 {
2791 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2792 struct intel_engine_cs *signaller;
2793 int i;
2794
2795 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2796 for_each_ring(signaller, dev_priv, i) {
2797 if (ring == signaller)
2798 continue;
2799
2800 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2801 return signaller;
2802 }
2803 } else {
2804 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2805
2806 for_each_ring(signaller, dev_priv, i) {
2807 if(ring == signaller)
2808 continue;
2809
2810 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2811 return signaller;
2812 }
2813 }
2814
2815 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2816 ring->id, ipehr, offset);
2817
2818 return NULL;
2819 }
2820
2821 static struct intel_engine_cs *
2822 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2823 {
2824 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2825 u32 cmd, ipehr, head;
2826 u64 offset = 0;
2827 int i, backwards;
2828
2829 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2830 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2831 return NULL;
2832
2833 /*
2834 * HEAD is likely pointing to the dword after the actual command,
2835 * so scan backwards until we find the MBOX. But limit it to just 3
2836 * or 4 dwords depending on the semaphore wait command size.
2837 * Note that we don't care about ACTHD here since that might
2838 * point at at batch, and semaphores are always emitted into the
2839 * ringbuffer itself.
2840 */
2841 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2842 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2843
2844 for (i = backwards; i; --i) {
2845 /*
2846 * Be paranoid and presume the hw has gone off into the wild -
2847 * our ring is smaller than what the hardware (and hence
2848 * HEAD_ADDR) allows. Also handles wrap-around.
2849 */
2850 head &= ring->buffer->size - 1;
2851
2852 /* This here seems to blow up */
2853 cmd = ioread32(ring->buffer->virtual_start + head);
2854 if (cmd == ipehr)
2855 break;
2856
2857 head -= 4;
2858 }
2859
2860 if (!i)
2861 return NULL;
2862
2863 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2864 if (INTEL_INFO(ring->dev)->gen >= 8) {
2865 offset = ioread32(ring->buffer->virtual_start + head + 12);
2866 offset <<= 32;
2867 offset = ioread32(ring->buffer->virtual_start + head + 8);
2868 }
2869 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2870 }
2871
2872 static int semaphore_passed(struct intel_engine_cs *ring)
2873 {
2874 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2875 struct intel_engine_cs *signaller;
2876 u32 seqno;
2877
2878 ring->hangcheck.deadlock++;
2879
2880 signaller = semaphore_waits_for(ring, &seqno);
2881 if (signaller == NULL)
2882 return -1;
2883
2884 /* Prevent pathological recursion due to driver bugs */
2885 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2886 return -1;
2887
2888 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2889 return 1;
2890
2891 /* cursory check for an unkickable deadlock */
2892 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2893 semaphore_passed(signaller) < 0)
2894 return -1;
2895
2896 return 0;
2897 }
2898
2899 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2900 {
2901 struct intel_engine_cs *ring;
2902 int i;
2903
2904 for_each_ring(ring, dev_priv, i)
2905 ring->hangcheck.deadlock = 0;
2906 }
2907
2908 static enum intel_ring_hangcheck_action
2909 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2910 {
2911 struct drm_device *dev = ring->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 u32 tmp;
2914
2915 if (acthd != ring->hangcheck.acthd) {
2916 if (acthd > ring->hangcheck.max_acthd) {
2917 ring->hangcheck.max_acthd = acthd;
2918 return HANGCHECK_ACTIVE;
2919 }
2920
2921 return HANGCHECK_ACTIVE_LOOP;
2922 }
2923
2924 if (IS_GEN2(dev))
2925 return HANGCHECK_HUNG;
2926
2927 /* Is the chip hanging on a WAIT_FOR_EVENT?
2928 * If so we can simply poke the RB_WAIT bit
2929 * and break the hang. This should work on
2930 * all but the second generation chipsets.
2931 */
2932 tmp = I915_READ_CTL(ring);
2933 if (tmp & RING_WAIT) {
2934 i915_handle_error(dev, false,
2935 "Kicking stuck wait on %s",
2936 ring->name);
2937 I915_WRITE_CTL(ring, tmp);
2938 return HANGCHECK_KICK;
2939 }
2940
2941 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2942 switch (semaphore_passed(ring)) {
2943 default:
2944 return HANGCHECK_HUNG;
2945 case 1:
2946 i915_handle_error(dev, false,
2947 "Kicking stuck semaphore on %s",
2948 ring->name);
2949 I915_WRITE_CTL(ring, tmp);
2950 return HANGCHECK_KICK;
2951 case 0:
2952 return HANGCHECK_WAIT;
2953 }
2954 }
2955
2956 return HANGCHECK_HUNG;
2957 }
2958
2959 /**
2960 * This is called when the chip hasn't reported back with completed
2961 * batchbuffers in a long time. We keep track per ring seqno progress and
2962 * if there are no progress, hangcheck score for that ring is increased.
2963 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2964 * we kick the ring. If we see no progress on three subsequent calls
2965 * we assume chip is wedged and try to fix it by resetting the chip.
2966 */
2967 static void i915_hangcheck_elapsed(unsigned long data)
2968 {
2969 struct drm_device *dev = (struct drm_device *)data;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_engine_cs *ring;
2972 int i;
2973 int busy_count = 0, rings_hung = 0;
2974 bool stuck[I915_NUM_RINGS] = { 0 };
2975 #define BUSY 1
2976 #define KICK 5
2977 #define HUNG 20
2978
2979 if (!i915.enable_hangcheck)
2980 return;
2981
2982 for_each_ring(ring, dev_priv, i) {
2983 u64 acthd;
2984 u32 seqno;
2985 bool busy = true;
2986
2987 semaphore_clear_deadlocks(dev_priv);
2988
2989 seqno = ring->get_seqno(ring, false);
2990 acthd = intel_ring_get_active_head(ring);
2991
2992 if (ring->hangcheck.seqno == seqno) {
2993 if (ring_idle(ring)) {
2994 ring->hangcheck.action = HANGCHECK_IDLE;
2995
2996 if (waitqueue_active(&ring->irq_queue)) {
2997 /* Issue a wake-up to catch stuck h/w. */
2998 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2999 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3000 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3001 ring->name);
3002 else
3003 DRM_INFO("Fake missed irq on %s\n",
3004 ring->name);
3005 wake_up_all(&ring->irq_queue);
3006 }
3007 /* Safeguard against driver failure */
3008 ring->hangcheck.score += BUSY;
3009 } else
3010 busy = false;
3011 } else {
3012 /* We always increment the hangcheck score
3013 * if the ring is busy and still processing
3014 * the same request, so that no single request
3015 * can run indefinitely (such as a chain of
3016 * batches). The only time we do not increment
3017 * the hangcheck score on this ring, if this
3018 * ring is in a legitimate wait for another
3019 * ring. In that case the waiting ring is a
3020 * victim and we want to be sure we catch the
3021 * right culprit. Then every time we do kick
3022 * the ring, add a small increment to the
3023 * score so that we can catch a batch that is
3024 * being repeatedly kicked and so responsible
3025 * for stalling the machine.
3026 */
3027 ring->hangcheck.action = ring_stuck(ring,
3028 acthd);
3029
3030 switch (ring->hangcheck.action) {
3031 case HANGCHECK_IDLE:
3032 case HANGCHECK_WAIT:
3033 case HANGCHECK_ACTIVE:
3034 break;
3035 case HANGCHECK_ACTIVE_LOOP:
3036 ring->hangcheck.score += BUSY;
3037 break;
3038 case HANGCHECK_KICK:
3039 ring->hangcheck.score += KICK;
3040 break;
3041 case HANGCHECK_HUNG:
3042 ring->hangcheck.score += HUNG;
3043 stuck[i] = true;
3044 break;
3045 }
3046 }
3047 } else {
3048 ring->hangcheck.action = HANGCHECK_ACTIVE;
3049
3050 /* Gradually reduce the count so that we catch DoS
3051 * attempts across multiple batches.
3052 */
3053 if (ring->hangcheck.score > 0)
3054 ring->hangcheck.score--;
3055
3056 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3057 }
3058
3059 ring->hangcheck.seqno = seqno;
3060 ring->hangcheck.acthd = acthd;
3061 busy_count += busy;
3062 }
3063
3064 for_each_ring(ring, dev_priv, i) {
3065 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3066 DRM_INFO("%s on %s\n",
3067 stuck[i] ? "stuck" : "no progress",
3068 ring->name);
3069 rings_hung++;
3070 }
3071 }
3072
3073 if (rings_hung)
3074 return i915_handle_error(dev, true, "Ring hung");
3075
3076 if (busy_count)
3077 /* Reset timer case chip hangs without another request
3078 * being added */
3079 i915_queue_hangcheck(dev);
3080 }
3081
3082 void i915_queue_hangcheck(struct drm_device *dev)
3083 {
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3086
3087 if (!i915.enable_hangcheck)
3088 return;
3089
3090 /* Don't continually defer the hangcheck, but make sure it is active */
3091 if (timer_pending(timer))
3092 return;
3093 mod_timer(timer,
3094 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3095 }
3096
3097 static void ibx_irq_reset(struct drm_device *dev)
3098 {
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101 if (HAS_PCH_NOP(dev))
3102 return;
3103
3104 GEN5_IRQ_RESET(SDE);
3105
3106 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3107 I915_WRITE(SERR_INT, 0xffffffff);
3108 }
3109
3110 /*
3111 * SDEIER is also touched by the interrupt handler to work around missed PCH
3112 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3113 * instead we unconditionally enable all PCH interrupt sources here, but then
3114 * only unmask them as needed with SDEIMR.
3115 *
3116 * This function needs to be called before interrupts are enabled.
3117 */
3118 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3119 {
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121
3122 if (HAS_PCH_NOP(dev))
3123 return;
3124
3125 WARN_ON(I915_READ(SDEIER) != 0);
3126 I915_WRITE(SDEIER, 0xffffffff);
3127 POSTING_READ(SDEIER);
3128 }
3129
3130 static void gen5_gt_irq_reset(struct drm_device *dev)
3131 {
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133
3134 GEN5_IRQ_RESET(GT);
3135 if (INTEL_INFO(dev)->gen >= 6)
3136 GEN5_IRQ_RESET(GEN6_PM);
3137 }
3138
3139 /* drm_dma.h hooks
3140 */
3141 static void ironlake_irq_reset(struct drm_device *dev)
3142 {
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144
3145 I915_WRITE(HWSTAM, 0xffffffff);
3146
3147 GEN5_IRQ_RESET(DE);
3148 if (IS_GEN7(dev))
3149 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3150
3151 gen5_gt_irq_reset(dev);
3152
3153 ibx_irq_reset(dev);
3154 }
3155
3156 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3157 {
3158 enum pipe pipe;
3159
3160 I915_WRITE(PORT_HOTPLUG_EN, 0);
3161 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3162
3163 for_each_pipe(dev_priv, pipe)
3164 I915_WRITE(PIPESTAT(pipe), 0xffff);
3165
3166 GEN5_IRQ_RESET(VLV_);
3167 }
3168
3169 static void valleyview_irq_preinstall(struct drm_device *dev)
3170 {
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172
3173 /* VLV magic */
3174 I915_WRITE(VLV_IMR, 0);
3175 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3176 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3177 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3178
3179 gen5_gt_irq_reset(dev);
3180
3181 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3182
3183 vlv_display_irq_reset(dev_priv);
3184 }
3185
3186 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3187 {
3188 GEN8_IRQ_RESET_NDX(GT, 0);
3189 GEN8_IRQ_RESET_NDX(GT, 1);
3190 GEN8_IRQ_RESET_NDX(GT, 2);
3191 GEN8_IRQ_RESET_NDX(GT, 3);
3192 }
3193
3194 static void gen8_irq_reset(struct drm_device *dev)
3195 {
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 int pipe;
3198
3199 I915_WRITE(GEN8_MASTER_IRQ, 0);
3200 POSTING_READ(GEN8_MASTER_IRQ);
3201
3202 gen8_gt_irq_reset(dev_priv);
3203
3204 for_each_pipe(dev_priv, pipe)
3205 if (intel_display_power_is_enabled(dev_priv,
3206 POWER_DOMAIN_PIPE(pipe)))
3207 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3208
3209 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3210 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3211 GEN5_IRQ_RESET(GEN8_PCU_);
3212
3213 ibx_irq_reset(dev);
3214 }
3215
3216 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3217 {
3218 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3219
3220 spin_lock_irq(&dev_priv->irq_lock);
3221 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3222 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3223 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3224 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3225 spin_unlock_irq(&dev_priv->irq_lock);
3226 }
3227
3228 static void cherryview_irq_preinstall(struct drm_device *dev)
3229 {
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231
3232 I915_WRITE(GEN8_MASTER_IRQ, 0);
3233 POSTING_READ(GEN8_MASTER_IRQ);
3234
3235 gen8_gt_irq_reset(dev_priv);
3236
3237 GEN5_IRQ_RESET(GEN8_PCU_);
3238
3239 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3240
3241 vlv_display_irq_reset(dev_priv);
3242 }
3243
3244 static void ibx_hpd_irq_setup(struct drm_device *dev)
3245 {
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct intel_encoder *intel_encoder;
3248 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3249
3250 if (HAS_PCH_IBX(dev)) {
3251 hotplug_irqs = SDE_HOTPLUG_MASK;
3252 for_each_intel_encoder(dev, intel_encoder)
3253 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3254 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3255 } else {
3256 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3257 for_each_intel_encoder(dev, intel_encoder)
3258 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3259 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3260 }
3261
3262 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3263
3264 /*
3265 * Enable digital hotplug on the PCH, and configure the DP short pulse
3266 * duration to 2ms (which is the minimum in the Display Port spec)
3267 *
3268 * This register is the same on all known PCH chips.
3269 */
3270 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3271 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3272 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3273 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3274 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3275 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3276 }
3277
3278 static void ibx_irq_postinstall(struct drm_device *dev)
3279 {
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 u32 mask;
3282
3283 if (HAS_PCH_NOP(dev))
3284 return;
3285
3286 if (HAS_PCH_IBX(dev))
3287 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3288 else
3289 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3290
3291 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3292 I915_WRITE(SDEIMR, ~mask);
3293 }
3294
3295 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3296 {
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 u32 pm_irqs, gt_irqs;
3299
3300 pm_irqs = gt_irqs = 0;
3301
3302 dev_priv->gt_irq_mask = ~0;
3303 if (HAS_L3_DPF(dev)) {
3304 /* L3 parity interrupt is always unmasked. */
3305 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3306 gt_irqs |= GT_PARITY_ERROR(dev);
3307 }
3308
3309 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3310 if (IS_GEN5(dev)) {
3311 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3312 ILK_BSD_USER_INTERRUPT;
3313 } else {
3314 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3315 }
3316
3317 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3318
3319 if (INTEL_INFO(dev)->gen >= 6) {
3320 /*
3321 * RPS interrupts will get enabled/disabled on demand when RPS
3322 * itself is enabled/disabled.
3323 */
3324 if (HAS_VEBOX(dev))
3325 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3326
3327 dev_priv->pm_irq_mask = 0xffffffff;
3328 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3329 }
3330 }
3331
3332 static int ironlake_irq_postinstall(struct drm_device *dev)
3333 {
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 u32 display_mask, extra_mask;
3336
3337 if (INTEL_INFO(dev)->gen >= 7) {
3338 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3339 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3340 DE_PLANEB_FLIP_DONE_IVB |
3341 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3342 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3343 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3344 } else {
3345 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3346 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3347 DE_AUX_CHANNEL_A |
3348 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3349 DE_POISON);
3350 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3351 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3352 }
3353
3354 dev_priv->irq_mask = ~display_mask;
3355
3356 I915_WRITE(HWSTAM, 0xeffe);
3357
3358 ibx_irq_pre_postinstall(dev);
3359
3360 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3361
3362 gen5_gt_irq_postinstall(dev);
3363
3364 ibx_irq_postinstall(dev);
3365
3366 if (IS_IRONLAKE_M(dev)) {
3367 /* Enable PCU event interrupts
3368 *
3369 * spinlocking not required here for correctness since interrupt
3370 * setup is guaranteed to run in single-threaded context. But we
3371 * need it to make the assert_spin_locked happy. */
3372 spin_lock_irq(&dev_priv->irq_lock);
3373 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3374 spin_unlock_irq(&dev_priv->irq_lock);
3375 }
3376
3377 return 0;
3378 }
3379
3380 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3381 {
3382 u32 pipestat_mask;
3383 u32 iir_mask;
3384 enum pipe pipe;
3385
3386 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3387 PIPE_FIFO_UNDERRUN_STATUS;
3388
3389 for_each_pipe(dev_priv, pipe)
3390 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3391 POSTING_READ(PIPESTAT(PIPE_A));
3392
3393 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3394 PIPE_CRC_DONE_INTERRUPT_STATUS;
3395
3396 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3397 for_each_pipe(dev_priv, pipe)
3398 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3399
3400 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3401 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3402 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3403 if (IS_CHERRYVIEW(dev_priv))
3404 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3405 dev_priv->irq_mask &= ~iir_mask;
3406
3407 I915_WRITE(VLV_IIR, iir_mask);
3408 I915_WRITE(VLV_IIR, iir_mask);
3409 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3410 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3411 POSTING_READ(VLV_IMR);
3412 }
3413
3414 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3415 {
3416 u32 pipestat_mask;
3417 u32 iir_mask;
3418 enum pipe pipe;
3419
3420 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3421 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3422 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3423 if (IS_CHERRYVIEW(dev_priv))
3424 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3425
3426 dev_priv->irq_mask |= iir_mask;
3427 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3428 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3429 I915_WRITE(VLV_IIR, iir_mask);
3430 I915_WRITE(VLV_IIR, iir_mask);
3431 POSTING_READ(VLV_IIR);
3432
3433 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3434 PIPE_CRC_DONE_INTERRUPT_STATUS;
3435
3436 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3437 for_each_pipe(dev_priv, pipe)
3438 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3439
3440 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3441 PIPE_FIFO_UNDERRUN_STATUS;
3442
3443 for_each_pipe(dev_priv, pipe)
3444 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3445 POSTING_READ(PIPESTAT(PIPE_A));
3446 }
3447
3448 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3449 {
3450 assert_spin_locked(&dev_priv->irq_lock);
3451
3452 if (dev_priv->display_irqs_enabled)
3453 return;
3454
3455 dev_priv->display_irqs_enabled = true;
3456
3457 if (intel_irqs_enabled(dev_priv))
3458 valleyview_display_irqs_install(dev_priv);
3459 }
3460
3461 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3462 {
3463 assert_spin_locked(&dev_priv->irq_lock);
3464
3465 if (!dev_priv->display_irqs_enabled)
3466 return;
3467
3468 dev_priv->display_irqs_enabled = false;
3469
3470 if (intel_irqs_enabled(dev_priv))
3471 valleyview_display_irqs_uninstall(dev_priv);
3472 }
3473
3474 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3475 {
3476 dev_priv->irq_mask = ~0;
3477
3478 I915_WRITE(PORT_HOTPLUG_EN, 0);
3479 POSTING_READ(PORT_HOTPLUG_EN);
3480
3481 I915_WRITE(VLV_IIR, 0xffffffff);
3482 I915_WRITE(VLV_IIR, 0xffffffff);
3483 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3484 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3485 POSTING_READ(VLV_IMR);
3486
3487 /* Interrupt setup is already guaranteed to be single-threaded, this is
3488 * just to make the assert_spin_locked check happy. */
3489 spin_lock_irq(&dev_priv->irq_lock);
3490 if (dev_priv->display_irqs_enabled)
3491 valleyview_display_irqs_install(dev_priv);
3492 spin_unlock_irq(&dev_priv->irq_lock);
3493 }
3494
3495 static int valleyview_irq_postinstall(struct drm_device *dev)
3496 {
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498
3499 vlv_display_irq_postinstall(dev_priv);
3500
3501 gen5_gt_irq_postinstall(dev);
3502
3503 /* ack & enable invalid PTE error interrupts */
3504 #if 0 /* FIXME: add support to irq handler for checking these bits */
3505 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3506 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3507 #endif
3508
3509 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3510
3511 return 0;
3512 }
3513
3514 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3515 {
3516 /* These are interrupts we'll toggle with the ring mask register */
3517 uint32_t gt_interrupts[] = {
3518 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3519 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3520 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3521 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3522 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3523 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3524 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3525 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3526 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3527 0,
3528 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3529 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3530 };
3531
3532 dev_priv->pm_irq_mask = 0xffffffff;
3533 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3534 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3535 /*
3536 * RPS interrupts will get enabled/disabled on demand when RPS itself
3537 * is enabled/disabled.
3538 */
3539 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3540 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3541 }
3542
3543 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3544 {
3545 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3546 uint32_t de_pipe_enables;
3547 int pipe;
3548 u32 aux_en = GEN8_AUX_CHANNEL_A;
3549
3550 if (IS_GEN9(dev_priv)) {
3551 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3552 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3553 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3554 GEN9_AUX_CHANNEL_D;
3555 } else
3556 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3557 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3558
3559 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3560 GEN8_PIPE_FIFO_UNDERRUN;
3561
3562 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3563 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3564 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3565
3566 for_each_pipe(dev_priv, pipe)
3567 if (intel_display_power_is_enabled(dev_priv,
3568 POWER_DOMAIN_PIPE(pipe)))
3569 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3570 dev_priv->de_irq_mask[pipe],
3571 de_pipe_enables);
3572
3573 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3574 }
3575
3576 static int gen8_irq_postinstall(struct drm_device *dev)
3577 {
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579
3580 ibx_irq_pre_postinstall(dev);
3581
3582 gen8_gt_irq_postinstall(dev_priv);
3583 gen8_de_irq_postinstall(dev_priv);
3584
3585 ibx_irq_postinstall(dev);
3586
3587 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3588 POSTING_READ(GEN8_MASTER_IRQ);
3589
3590 return 0;
3591 }
3592
3593 static int cherryview_irq_postinstall(struct drm_device *dev)
3594 {
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596
3597 vlv_display_irq_postinstall(dev_priv);
3598
3599 gen8_gt_irq_postinstall(dev_priv);
3600
3601 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3602 POSTING_READ(GEN8_MASTER_IRQ);
3603
3604 return 0;
3605 }
3606
3607 static void gen8_irq_uninstall(struct drm_device *dev)
3608 {
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610
3611 if (!dev_priv)
3612 return;
3613
3614 gen8_irq_reset(dev);
3615 }
3616
3617 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3618 {
3619 /* Interrupt setup is already guaranteed to be single-threaded, this is
3620 * just to make the assert_spin_locked check happy. */
3621 spin_lock_irq(&dev_priv->irq_lock);
3622 if (dev_priv->display_irqs_enabled)
3623 valleyview_display_irqs_uninstall(dev_priv);
3624 spin_unlock_irq(&dev_priv->irq_lock);
3625
3626 vlv_display_irq_reset(dev_priv);
3627
3628 dev_priv->irq_mask = ~0;
3629 }
3630
3631 static void valleyview_irq_uninstall(struct drm_device *dev)
3632 {
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3634
3635 if (!dev_priv)
3636 return;
3637
3638 I915_WRITE(VLV_MASTER_IER, 0);
3639
3640 gen5_gt_irq_reset(dev);
3641
3642 I915_WRITE(HWSTAM, 0xffffffff);
3643
3644 vlv_display_irq_uninstall(dev_priv);
3645 }
3646
3647 static void cherryview_irq_uninstall(struct drm_device *dev)
3648 {
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650
3651 if (!dev_priv)
3652 return;
3653
3654 I915_WRITE(GEN8_MASTER_IRQ, 0);
3655 POSTING_READ(GEN8_MASTER_IRQ);
3656
3657 gen8_gt_irq_reset(dev_priv);
3658
3659 GEN5_IRQ_RESET(GEN8_PCU_);
3660
3661 vlv_display_irq_uninstall(dev_priv);
3662 }
3663
3664 static void ironlake_irq_uninstall(struct drm_device *dev)
3665 {
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667
3668 if (!dev_priv)
3669 return;
3670
3671 ironlake_irq_reset(dev);
3672 }
3673
3674 static void i8xx_irq_preinstall(struct drm_device * dev)
3675 {
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 int pipe;
3678
3679 for_each_pipe(dev_priv, pipe)
3680 I915_WRITE(PIPESTAT(pipe), 0);
3681 I915_WRITE16(IMR, 0xffff);
3682 I915_WRITE16(IER, 0x0);
3683 POSTING_READ16(IER);
3684 }
3685
3686 static int i8xx_irq_postinstall(struct drm_device *dev)
3687 {
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689
3690 I915_WRITE16(EMR,
3691 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3692
3693 /* Unmask the interrupts that we always want on. */
3694 dev_priv->irq_mask =
3695 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3696 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3697 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3698 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3699 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3700 I915_WRITE16(IMR, dev_priv->irq_mask);
3701
3702 I915_WRITE16(IER,
3703 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3704 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3705 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3706 I915_USER_INTERRUPT);
3707 POSTING_READ16(IER);
3708
3709 /* Interrupt setup is already guaranteed to be single-threaded, this is
3710 * just to make the assert_spin_locked check happy. */
3711 spin_lock_irq(&dev_priv->irq_lock);
3712 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3713 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3714 spin_unlock_irq(&dev_priv->irq_lock);
3715
3716 return 0;
3717 }
3718
3719 /*
3720 * Returns true when a page flip has completed.
3721 */
3722 static bool i8xx_handle_vblank(struct drm_device *dev,
3723 int plane, int pipe, u32 iir)
3724 {
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3727
3728 if (!intel_pipe_handle_vblank(dev, pipe))
3729 return false;
3730
3731 if ((iir & flip_pending) == 0)
3732 goto check_page_flip;
3733
3734 intel_prepare_page_flip(dev, plane);
3735
3736 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3737 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3738 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3739 * the flip is completed (no longer pending). Since this doesn't raise
3740 * an interrupt per se, we watch for the change at vblank.
3741 */
3742 if (I915_READ16(ISR) & flip_pending)
3743 goto check_page_flip;
3744
3745 intel_finish_page_flip(dev, pipe);
3746 return true;
3747
3748 check_page_flip:
3749 intel_check_page_flip(dev, pipe);
3750 return false;
3751 }
3752
3753 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3754 {
3755 struct drm_device *dev = arg;
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 u16 iir, new_iir;
3758 u32 pipe_stats[2];
3759 int pipe;
3760 u16 flip_mask =
3761 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3762 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3763
3764 iir = I915_READ16(IIR);
3765 if (iir == 0)
3766 return IRQ_NONE;
3767
3768 while (iir & ~flip_mask) {
3769 /* Can't rely on pipestat interrupt bit in iir as it might
3770 * have been cleared after the pipestat interrupt was received.
3771 * It doesn't set the bit in iir again, but it still produces
3772 * interrupts (for non-MSI).
3773 */
3774 spin_lock(&dev_priv->irq_lock);
3775 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3776 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3777
3778 for_each_pipe(dev_priv, pipe) {
3779 int reg = PIPESTAT(pipe);
3780 pipe_stats[pipe] = I915_READ(reg);
3781
3782 /*
3783 * Clear the PIPE*STAT regs before the IIR
3784 */
3785 if (pipe_stats[pipe] & 0x8000ffff)
3786 I915_WRITE(reg, pipe_stats[pipe]);
3787 }
3788 spin_unlock(&dev_priv->irq_lock);
3789
3790 I915_WRITE16(IIR, iir & ~flip_mask);
3791 new_iir = I915_READ16(IIR); /* Flush posted writes */
3792
3793 if (iir & I915_USER_INTERRUPT)
3794 notify_ring(dev, &dev_priv->ring[RCS]);
3795
3796 for_each_pipe(dev_priv, pipe) {
3797 int plane = pipe;
3798 if (HAS_FBC(dev))
3799 plane = !plane;
3800
3801 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3802 i8xx_handle_vblank(dev, plane, pipe, iir))
3803 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3804
3805 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3806 i9xx_pipe_crc_irq_handler(dev, pipe);
3807
3808 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3809 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3810 pipe);
3811 }
3812
3813 iir = new_iir;
3814 }
3815
3816 return IRQ_HANDLED;
3817 }
3818
3819 static void i8xx_irq_uninstall(struct drm_device * dev)
3820 {
3821 struct drm_i915_private *dev_priv = dev->dev_private;
3822 int pipe;
3823
3824 for_each_pipe(dev_priv, pipe) {
3825 /* Clear enable bits; then clear status bits */
3826 I915_WRITE(PIPESTAT(pipe), 0);
3827 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3828 }
3829 I915_WRITE16(IMR, 0xffff);
3830 I915_WRITE16(IER, 0x0);
3831 I915_WRITE16(IIR, I915_READ16(IIR));
3832 }
3833
3834 static void i915_irq_preinstall(struct drm_device * dev)
3835 {
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 int pipe;
3838
3839 if (I915_HAS_HOTPLUG(dev)) {
3840 I915_WRITE(PORT_HOTPLUG_EN, 0);
3841 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3842 }
3843
3844 I915_WRITE16(HWSTAM, 0xeffe);
3845 for_each_pipe(dev_priv, pipe)
3846 I915_WRITE(PIPESTAT(pipe), 0);
3847 I915_WRITE(IMR, 0xffffffff);
3848 I915_WRITE(IER, 0x0);
3849 POSTING_READ(IER);
3850 }
3851
3852 static int i915_irq_postinstall(struct drm_device *dev)
3853 {
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 u32 enable_mask;
3856
3857 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3858
3859 /* Unmask the interrupts that we always want on. */
3860 dev_priv->irq_mask =
3861 ~(I915_ASLE_INTERRUPT |
3862 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3863 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3864 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3865 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3866 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3867
3868 enable_mask =
3869 I915_ASLE_INTERRUPT |
3870 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3871 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3872 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3873 I915_USER_INTERRUPT;
3874
3875 if (I915_HAS_HOTPLUG(dev)) {
3876 I915_WRITE(PORT_HOTPLUG_EN, 0);
3877 POSTING_READ(PORT_HOTPLUG_EN);
3878
3879 /* Enable in IER... */
3880 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3881 /* and unmask in IMR */
3882 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3883 }
3884
3885 I915_WRITE(IMR, dev_priv->irq_mask);
3886 I915_WRITE(IER, enable_mask);
3887 POSTING_READ(IER);
3888
3889 i915_enable_asle_pipestat(dev);
3890
3891 /* Interrupt setup is already guaranteed to be single-threaded, this is
3892 * just to make the assert_spin_locked check happy. */
3893 spin_lock_irq(&dev_priv->irq_lock);
3894 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3895 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3896 spin_unlock_irq(&dev_priv->irq_lock);
3897
3898 return 0;
3899 }
3900
3901 /*
3902 * Returns true when a page flip has completed.
3903 */
3904 static bool i915_handle_vblank(struct drm_device *dev,
3905 int plane, int pipe, u32 iir)
3906 {
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3909
3910 if (!intel_pipe_handle_vblank(dev, pipe))
3911 return false;
3912
3913 if ((iir & flip_pending) == 0)
3914 goto check_page_flip;
3915
3916 intel_prepare_page_flip(dev, plane);
3917
3918 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3919 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3920 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3921 * the flip is completed (no longer pending). Since this doesn't raise
3922 * an interrupt per se, we watch for the change at vblank.
3923 */
3924 if (I915_READ(ISR) & flip_pending)
3925 goto check_page_flip;
3926
3927 intel_finish_page_flip(dev, pipe);
3928 return true;
3929
3930 check_page_flip:
3931 intel_check_page_flip(dev, pipe);
3932 return false;
3933 }
3934
3935 static irqreturn_t i915_irq_handler(int irq, void *arg)
3936 {
3937 struct drm_device *dev = arg;
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3940 u32 flip_mask =
3941 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3942 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3943 int pipe, ret = IRQ_NONE;
3944
3945 iir = I915_READ(IIR);
3946 do {
3947 bool irq_received = (iir & ~flip_mask) != 0;
3948 bool blc_event = false;
3949
3950 /* Can't rely on pipestat interrupt bit in iir as it might
3951 * have been cleared after the pipestat interrupt was received.
3952 * It doesn't set the bit in iir again, but it still produces
3953 * interrupts (for non-MSI).
3954 */
3955 spin_lock(&dev_priv->irq_lock);
3956 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3957 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3958
3959 for_each_pipe(dev_priv, pipe) {
3960 int reg = PIPESTAT(pipe);
3961 pipe_stats[pipe] = I915_READ(reg);
3962
3963 /* Clear the PIPE*STAT regs before the IIR */
3964 if (pipe_stats[pipe] & 0x8000ffff) {
3965 I915_WRITE(reg, pipe_stats[pipe]);
3966 irq_received = true;
3967 }
3968 }
3969 spin_unlock(&dev_priv->irq_lock);
3970
3971 if (!irq_received)
3972 break;
3973
3974 /* Consume port. Then clear IIR or we'll miss events */
3975 if (I915_HAS_HOTPLUG(dev) &&
3976 iir & I915_DISPLAY_PORT_INTERRUPT)
3977 i9xx_hpd_irq_handler(dev);
3978
3979 I915_WRITE(IIR, iir & ~flip_mask);
3980 new_iir = I915_READ(IIR); /* Flush posted writes */
3981
3982 if (iir & I915_USER_INTERRUPT)
3983 notify_ring(dev, &dev_priv->ring[RCS]);
3984
3985 for_each_pipe(dev_priv, pipe) {
3986 int plane = pipe;
3987 if (HAS_FBC(dev))
3988 plane = !plane;
3989
3990 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3991 i915_handle_vblank(dev, plane, pipe, iir))
3992 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3993
3994 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3995 blc_event = true;
3996
3997 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3998 i9xx_pipe_crc_irq_handler(dev, pipe);
3999
4000 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4001 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4002 pipe);
4003 }
4004
4005 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4006 intel_opregion_asle_intr(dev);
4007
4008 /* With MSI, interrupts are only generated when iir
4009 * transitions from zero to nonzero. If another bit got
4010 * set while we were handling the existing iir bits, then
4011 * we would never get another interrupt.
4012 *
4013 * This is fine on non-MSI as well, as if we hit this path
4014 * we avoid exiting the interrupt handler only to generate
4015 * another one.
4016 *
4017 * Note that for MSI this could cause a stray interrupt report
4018 * if an interrupt landed in the time between writing IIR and
4019 * the posting read. This should be rare enough to never
4020 * trigger the 99% of 100,000 interrupts test for disabling
4021 * stray interrupts.
4022 */
4023 ret = IRQ_HANDLED;
4024 iir = new_iir;
4025 } while (iir & ~flip_mask);
4026
4027 return ret;
4028 }
4029
4030 static void i915_irq_uninstall(struct drm_device * dev)
4031 {
4032 struct drm_i915_private *dev_priv = dev->dev_private;
4033 int pipe;
4034
4035 if (I915_HAS_HOTPLUG(dev)) {
4036 I915_WRITE(PORT_HOTPLUG_EN, 0);
4037 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4038 }
4039
4040 I915_WRITE16(HWSTAM, 0xffff);
4041 for_each_pipe(dev_priv, pipe) {
4042 /* Clear enable bits; then clear status bits */
4043 I915_WRITE(PIPESTAT(pipe), 0);
4044 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4045 }
4046 I915_WRITE(IMR, 0xffffffff);
4047 I915_WRITE(IER, 0x0);
4048
4049 I915_WRITE(IIR, I915_READ(IIR));
4050 }
4051
4052 static void i965_irq_preinstall(struct drm_device * dev)
4053 {
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 int pipe;
4056
4057 I915_WRITE(PORT_HOTPLUG_EN, 0);
4058 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4059
4060 I915_WRITE(HWSTAM, 0xeffe);
4061 for_each_pipe(dev_priv, pipe)
4062 I915_WRITE(PIPESTAT(pipe), 0);
4063 I915_WRITE(IMR, 0xffffffff);
4064 I915_WRITE(IER, 0x0);
4065 POSTING_READ(IER);
4066 }
4067
4068 static int i965_irq_postinstall(struct drm_device *dev)
4069 {
4070 struct drm_i915_private *dev_priv = dev->dev_private;
4071 u32 enable_mask;
4072 u32 error_mask;
4073
4074 /* Unmask the interrupts that we always want on. */
4075 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4076 I915_DISPLAY_PORT_INTERRUPT |
4077 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4078 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4079 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4080 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4081 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4082
4083 enable_mask = ~dev_priv->irq_mask;
4084 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4085 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4086 enable_mask |= I915_USER_INTERRUPT;
4087
4088 if (IS_G4X(dev))
4089 enable_mask |= I915_BSD_USER_INTERRUPT;
4090
4091 /* Interrupt setup is already guaranteed to be single-threaded, this is
4092 * just to make the assert_spin_locked check happy. */
4093 spin_lock_irq(&dev_priv->irq_lock);
4094 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4095 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4096 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4097 spin_unlock_irq(&dev_priv->irq_lock);
4098
4099 /*
4100 * Enable some error detection, note the instruction error mask
4101 * bit is reserved, so we leave it masked.
4102 */
4103 if (IS_G4X(dev)) {
4104 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4105 GM45_ERROR_MEM_PRIV |
4106 GM45_ERROR_CP_PRIV |
4107 I915_ERROR_MEMORY_REFRESH);
4108 } else {
4109 error_mask = ~(I915_ERROR_PAGE_TABLE |
4110 I915_ERROR_MEMORY_REFRESH);
4111 }
4112 I915_WRITE(EMR, error_mask);
4113
4114 I915_WRITE(IMR, dev_priv->irq_mask);
4115 I915_WRITE(IER, enable_mask);
4116 POSTING_READ(IER);
4117
4118 I915_WRITE(PORT_HOTPLUG_EN, 0);
4119 POSTING_READ(PORT_HOTPLUG_EN);
4120
4121 i915_enable_asle_pipestat(dev);
4122
4123 return 0;
4124 }
4125
4126 static void i915_hpd_irq_setup(struct drm_device *dev)
4127 {
4128 struct drm_i915_private *dev_priv = dev->dev_private;
4129 struct intel_encoder *intel_encoder;
4130 u32 hotplug_en;
4131
4132 assert_spin_locked(&dev_priv->irq_lock);
4133
4134 if (I915_HAS_HOTPLUG(dev)) {
4135 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4136 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4137 /* Note HDMI and DP share hotplug bits */
4138 /* enable bits are the same for all generations */
4139 for_each_intel_encoder(dev, intel_encoder)
4140 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4141 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4142 /* Programming the CRT detection parameters tends
4143 to generate a spurious hotplug event about three
4144 seconds later. So just do it once.
4145 */
4146 if (IS_G4X(dev))
4147 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4148 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4149 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4150
4151 /* Ignore TV since it's buggy */
4152 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4153 }
4154 }
4155
4156 static irqreturn_t i965_irq_handler(int irq, void *arg)
4157 {
4158 struct drm_device *dev = arg;
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4160 u32 iir, new_iir;
4161 u32 pipe_stats[I915_MAX_PIPES];
4162 int ret = IRQ_NONE, pipe;
4163 u32 flip_mask =
4164 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4165 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4166
4167 iir = I915_READ(IIR);
4168
4169 for (;;) {
4170 bool irq_received = (iir & ~flip_mask) != 0;
4171 bool blc_event = false;
4172
4173 /* Can't rely on pipestat interrupt bit in iir as it might
4174 * have been cleared after the pipestat interrupt was received.
4175 * It doesn't set the bit in iir again, but it still produces
4176 * interrupts (for non-MSI).
4177 */
4178 spin_lock(&dev_priv->irq_lock);
4179 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4180 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4181
4182 for_each_pipe(dev_priv, pipe) {
4183 int reg = PIPESTAT(pipe);
4184 pipe_stats[pipe] = I915_READ(reg);
4185
4186 /*
4187 * Clear the PIPE*STAT regs before the IIR
4188 */
4189 if (pipe_stats[pipe] & 0x8000ffff) {
4190 I915_WRITE(reg, pipe_stats[pipe]);
4191 irq_received = true;
4192 }
4193 }
4194 spin_unlock(&dev_priv->irq_lock);
4195
4196 if (!irq_received)
4197 break;
4198
4199 ret = IRQ_HANDLED;
4200
4201 /* Consume port. Then clear IIR or we'll miss events */
4202 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4203 i9xx_hpd_irq_handler(dev);
4204
4205 I915_WRITE(IIR, iir & ~flip_mask);
4206 new_iir = I915_READ(IIR); /* Flush posted writes */
4207
4208 if (iir & I915_USER_INTERRUPT)
4209 notify_ring(dev, &dev_priv->ring[RCS]);
4210 if (iir & I915_BSD_USER_INTERRUPT)
4211 notify_ring(dev, &dev_priv->ring[VCS]);
4212
4213 for_each_pipe(dev_priv, pipe) {
4214 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4215 i915_handle_vblank(dev, pipe, pipe, iir))
4216 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4217
4218 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4219 blc_event = true;
4220
4221 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4222 i9xx_pipe_crc_irq_handler(dev, pipe);
4223
4224 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4225 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4226 }
4227
4228 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4229 intel_opregion_asle_intr(dev);
4230
4231 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4232 gmbus_irq_handler(dev);
4233
4234 /* With MSI, interrupts are only generated when iir
4235 * transitions from zero to nonzero. If another bit got
4236 * set while we were handling the existing iir bits, then
4237 * we would never get another interrupt.
4238 *
4239 * This is fine on non-MSI as well, as if we hit this path
4240 * we avoid exiting the interrupt handler only to generate
4241 * another one.
4242 *
4243 * Note that for MSI this could cause a stray interrupt report
4244 * if an interrupt landed in the time between writing IIR and
4245 * the posting read. This should be rare enough to never
4246 * trigger the 99% of 100,000 interrupts test for disabling
4247 * stray interrupts.
4248 */
4249 iir = new_iir;
4250 }
4251
4252 return ret;
4253 }
4254
4255 static void i965_irq_uninstall(struct drm_device * dev)
4256 {
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int pipe;
4259
4260 if (!dev_priv)
4261 return;
4262
4263 I915_WRITE(PORT_HOTPLUG_EN, 0);
4264 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4265
4266 I915_WRITE(HWSTAM, 0xffffffff);
4267 for_each_pipe(dev_priv, pipe)
4268 I915_WRITE(PIPESTAT(pipe), 0);
4269 I915_WRITE(IMR, 0xffffffff);
4270 I915_WRITE(IER, 0x0);
4271
4272 for_each_pipe(dev_priv, pipe)
4273 I915_WRITE(PIPESTAT(pipe),
4274 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4275 I915_WRITE(IIR, I915_READ(IIR));
4276 }
4277
4278 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4279 {
4280 struct drm_i915_private *dev_priv =
4281 container_of(work, typeof(*dev_priv),
4282 hotplug_reenable_work.work);
4283 struct drm_device *dev = dev_priv->dev;
4284 struct drm_mode_config *mode_config = &dev->mode_config;
4285 int i;
4286
4287 intel_runtime_pm_get(dev_priv);
4288
4289 spin_lock_irq(&dev_priv->irq_lock);
4290 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4291 struct drm_connector *connector;
4292
4293 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4294 continue;
4295
4296 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4297
4298 list_for_each_entry(connector, &mode_config->connector_list, head) {
4299 struct intel_connector *intel_connector = to_intel_connector(connector);
4300
4301 if (intel_connector->encoder->hpd_pin == i) {
4302 if (connector->polled != intel_connector->polled)
4303 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4304 connector->name);
4305 connector->polled = intel_connector->polled;
4306 if (!connector->polled)
4307 connector->polled = DRM_CONNECTOR_POLL_HPD;
4308 }
4309 }
4310 }
4311 if (dev_priv->display.hpd_irq_setup)
4312 dev_priv->display.hpd_irq_setup(dev);
4313 spin_unlock_irq(&dev_priv->irq_lock);
4314
4315 intel_runtime_pm_put(dev_priv);
4316 }
4317
4318 /**
4319 * intel_irq_init - initializes irq support
4320 * @dev_priv: i915 device instance
4321 *
4322 * This function initializes all the irq support including work items, timers
4323 * and all the vtables. It does not setup the interrupt itself though.
4324 */
4325 void intel_irq_init(struct drm_i915_private *dev_priv)
4326 {
4327 struct drm_device *dev = dev_priv->dev;
4328
4329 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4330 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4331 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4332 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4333 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4334
4335 /* Let's track the enabled rps events */
4336 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4337 /* WaGsvRC0ResidencyMethod:vlv */
4338 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4339 else
4340 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4341
4342 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4343 i915_hangcheck_elapsed,
4344 (unsigned long) dev);
4345 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4346 intel_hpd_irq_reenable_work);
4347
4348 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4349
4350 if (IS_GEN2(dev_priv)) {
4351 dev->max_vblank_count = 0;
4352 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4353 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4354 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4355 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4356 } else {
4357 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4358 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4359 }
4360
4361 /*
4362 * Opt out of the vblank disable timer on everything except gen2.
4363 * Gen2 doesn't have a hardware frame counter and so depends on
4364 * vblank interrupts to produce sane vblank seuquence numbers.
4365 */
4366 if (!IS_GEN2(dev_priv))
4367 dev->vblank_disable_immediate = true;
4368
4369 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4370 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4371 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4372 }
4373
4374 if (IS_CHERRYVIEW(dev_priv)) {
4375 dev->driver->irq_handler = cherryview_irq_handler;
4376 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4377 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4378 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4379 dev->driver->enable_vblank = valleyview_enable_vblank;
4380 dev->driver->disable_vblank = valleyview_disable_vblank;
4381 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4382 } else if (IS_VALLEYVIEW(dev_priv)) {
4383 dev->driver->irq_handler = valleyview_irq_handler;
4384 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4385 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4386 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4387 dev->driver->enable_vblank = valleyview_enable_vblank;
4388 dev->driver->disable_vblank = valleyview_disable_vblank;
4389 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4390 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4391 dev->driver->irq_handler = gen8_irq_handler;
4392 dev->driver->irq_preinstall = gen8_irq_reset;
4393 dev->driver->irq_postinstall = gen8_irq_postinstall;
4394 dev->driver->irq_uninstall = gen8_irq_uninstall;
4395 dev->driver->enable_vblank = gen8_enable_vblank;
4396 dev->driver->disable_vblank = gen8_disable_vblank;
4397 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4398 } else if (HAS_PCH_SPLIT(dev)) {
4399 dev->driver->irq_handler = ironlake_irq_handler;
4400 dev->driver->irq_preinstall = ironlake_irq_reset;
4401 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4402 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4403 dev->driver->enable_vblank = ironlake_enable_vblank;
4404 dev->driver->disable_vblank = ironlake_disable_vblank;
4405 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4406 } else {
4407 if (INTEL_INFO(dev_priv)->gen == 2) {
4408 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4409 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4410 dev->driver->irq_handler = i8xx_irq_handler;
4411 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4412 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4413 dev->driver->irq_preinstall = i915_irq_preinstall;
4414 dev->driver->irq_postinstall = i915_irq_postinstall;
4415 dev->driver->irq_uninstall = i915_irq_uninstall;
4416 dev->driver->irq_handler = i915_irq_handler;
4417 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4418 } else {
4419 dev->driver->irq_preinstall = i965_irq_preinstall;
4420 dev->driver->irq_postinstall = i965_irq_postinstall;
4421 dev->driver->irq_uninstall = i965_irq_uninstall;
4422 dev->driver->irq_handler = i965_irq_handler;
4423 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4424 }
4425 dev->driver->enable_vblank = i915_enable_vblank;
4426 dev->driver->disable_vblank = i915_disable_vblank;
4427 }
4428 }
4429
4430 /**
4431 * intel_hpd_init - initializes and enables hpd support
4432 * @dev_priv: i915 device instance
4433 *
4434 * This function enables the hotplug support. It requires that interrupts have
4435 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4436 * poll request can run concurrently to other code, so locking rules must be
4437 * obeyed.
4438 *
4439 * This is a separate step from interrupt enabling to simplify the locking rules
4440 * in the driver load and resume code.
4441 */
4442 void intel_hpd_init(struct drm_i915_private *dev_priv)
4443 {
4444 struct drm_device *dev = dev_priv->dev;
4445 struct drm_mode_config *mode_config = &dev->mode_config;
4446 struct drm_connector *connector;
4447 int i;
4448
4449 for (i = 1; i < HPD_NUM_PINS; i++) {
4450 dev_priv->hpd_stats[i].hpd_cnt = 0;
4451 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4452 }
4453 list_for_each_entry(connector, &mode_config->connector_list, head) {
4454 struct intel_connector *intel_connector = to_intel_connector(connector);
4455 connector->polled = intel_connector->polled;
4456 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4457 connector->polled = DRM_CONNECTOR_POLL_HPD;
4458 if (intel_connector->mst_port)
4459 connector->polled = DRM_CONNECTOR_POLL_HPD;
4460 }
4461
4462 /* Interrupt setup is already guaranteed to be single-threaded, this is
4463 * just to make the assert_spin_locked checks happy. */
4464 spin_lock_irq(&dev_priv->irq_lock);
4465 if (dev_priv->display.hpd_irq_setup)
4466 dev_priv->display.hpd_irq_setup(dev);
4467 spin_unlock_irq(&dev_priv->irq_lock);
4468 }
4469
4470 /**
4471 * intel_irq_install - enables the hardware interrupt
4472 * @dev_priv: i915 device instance
4473 *
4474 * This function enables the hardware interrupt handling, but leaves the hotplug
4475 * handling still disabled. It is called after intel_irq_init().
4476 *
4477 * In the driver load and resume code we need working interrupts in a few places
4478 * but don't want to deal with the hassle of concurrent probe and hotplug
4479 * workers. Hence the split into this two-stage approach.
4480 */
4481 int intel_irq_install(struct drm_i915_private *dev_priv)
4482 {
4483 /*
4484 * We enable some interrupt sources in our postinstall hooks, so mark
4485 * interrupts as enabled _before_ actually enabling them to avoid
4486 * special cases in our ordering checks.
4487 */
4488 dev_priv->pm.irqs_enabled = true;
4489
4490 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4491 }
4492
4493 /**
4494 * intel_irq_uninstall - finilizes all irq handling
4495 * @dev_priv: i915 device instance
4496 *
4497 * This stops interrupt and hotplug handling and unregisters and frees all
4498 * resources acquired in the init functions.
4499 */
4500 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4501 {
4502 drm_irq_uninstall(dev_priv->dev);
4503 intel_hpd_cancel_work(dev_priv);
4504 dev_priv->pm.irqs_enabled = false;
4505 }
4506
4507 /**
4508 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4509 * @dev_priv: i915 device instance
4510 *
4511 * This function is used to disable interrupts at runtime, both in the runtime
4512 * pm and the system suspend/resume code.
4513 */
4514 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4515 {
4516 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4517 dev_priv->pm.irqs_enabled = false;
4518 }
4519
4520 /**
4521 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4522 * @dev_priv: i915 device instance
4523 *
4524 * This function is used to enable interrupts at runtime, both in the runtime
4525 * pm and the system suspend/resume code.
4526 */
4527 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4528 {
4529 dev_priv->pm.irqs_enabled = true;
4530 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4531 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4532 }
Linux kernel - Deliverables
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