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Merge tag 'drm-intel-next-2014-06-20' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92 } while (0)
93
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
102 } while (0)
103
104 /*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117 } while (0)
118
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124 } while (0)
125
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131 } while (0)
132
133 /* For display hotplug interrupt */
134 static void
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136 {
137 assert_spin_locked(&dev_priv->irq_lock);
138
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
140 return;
141
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
145 POSTING_READ(DEIMR);
146 }
147 }
148
149 static void
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151 {
152 assert_spin_locked(&dev_priv->irq_lock);
153
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
155 return;
156
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
160 POSTING_READ(DEIMR);
161 }
162 }
163
164 /**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173 {
174 assert_spin_locked(&dev_priv->irq_lock);
175
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
177 return;
178
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183 }
184
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186 {
187 ilk_update_gt_irq(dev_priv, mask, mask);
188 }
189
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 {
192 ilk_update_gt_irq(dev_priv, mask, 0);
193 }
194
195 /**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204 {
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221 }
222
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224 {
225 snb_update_pm_irq(dev_priv, mask, mask);
226 }
227
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229 {
230 snb_update_pm_irq(dev_priv, mask, 0);
231 }
232
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
234 {
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249 }
250
251 /**
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
256 *
257 * Copied from the snb function, updated with relevant register offsets
258 */
259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
262 {
263 uint32_t new_val;
264
265 assert_spin_locked(&dev_priv->irq_lock);
266
267 if (WARN_ON(dev_priv->pm.irqs_disabled))
268 return;
269
270 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask);
273
274 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2));
278 }
279 }
280
281 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
282 {
283 bdw_update_pm_irq(dev_priv, mask, mask);
284 }
285
286 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
287 {
288 bdw_update_pm_irq(dev_priv, mask, 0);
289 }
290
291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
292 {
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 enum pipe pipe;
295 struct intel_crtc *crtc;
296
297 assert_spin_locked(&dev_priv->irq_lock);
298
299 for_each_pipe(pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301
302 if (crtc->pch_fifo_underrun_disabled)
303 return false;
304 }
305
306 return true;
307 }
308
309 void i9xx_check_fifo_underruns(struct drm_device *dev)
310 {
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *crtc;
313 unsigned long flags;
314
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
316
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
319 u32 pipestat;
320
321 if (crtc->cpu_fifo_underrun_disabled)
322 continue;
323
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
326 continue;
327
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
329 POSTING_READ(reg);
330
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
332 }
333
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
335 }
336
337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
338 enum pipe pipe,
339 bool enable, bool old)
340 {
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 u32 reg = PIPESTAT(pipe);
343 u32 pipestat = I915_READ(reg) & 0xffff0000;
344
345 assert_spin_locked(&dev_priv->irq_lock);
346
347 if (enable) {
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
349 POSTING_READ(reg);
350 } else {
351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
353 }
354 }
355
356 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
357 enum pipe pipe, bool enable)
358 {
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
361 DE_PIPEB_FIFO_UNDERRUN;
362
363 if (enable)
364 ironlake_enable_display_irq(dev_priv, bit);
365 else
366 ironlake_disable_display_irq(dev_priv, bit);
367 }
368
369 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
370 enum pipe pipe,
371 bool enable, bool old)
372 {
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 if (enable) {
375 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
376
377 if (!ivb_can_enable_err_int(dev))
378 return;
379
380 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
381 } else {
382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
383
384 if (old &&
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
387 pipe_name(pipe));
388 }
389 }
390 }
391
392 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
393 enum pipe pipe, bool enable)
394 {
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 assert_spin_locked(&dev_priv->irq_lock);
398
399 if (enable)
400 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
401 else
402 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
403 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
404 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
405 }
406
407 /**
408 * ibx_display_interrupt_update - update SDEIMR
409 * @dev_priv: driver private
410 * @interrupt_mask: mask of interrupt bits to update
411 * @enabled_irq_mask: mask of interrupt bits to enable
412 */
413 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
414 uint32_t interrupt_mask,
415 uint32_t enabled_irq_mask)
416 {
417 uint32_t sdeimr = I915_READ(SDEIMR);
418 sdeimr &= ~interrupt_mask;
419 sdeimr |= (~enabled_irq_mask & interrupt_mask);
420
421 assert_spin_locked(&dev_priv->irq_lock);
422
423 if (WARN_ON(dev_priv->pm.irqs_disabled))
424 return;
425
426 I915_WRITE(SDEIMR, sdeimr);
427 POSTING_READ(SDEIMR);
428 }
429 #define ibx_enable_display_interrupt(dev_priv, bits) \
430 ibx_display_interrupt_update((dev_priv), (bits), (bits))
431 #define ibx_disable_display_interrupt(dev_priv, bits) \
432 ibx_display_interrupt_update((dev_priv), (bits), 0)
433
434 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
435 enum transcoder pch_transcoder,
436 bool enable)
437 {
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
440 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
441
442 if (enable)
443 ibx_enable_display_interrupt(dev_priv, bit);
444 else
445 ibx_disable_display_interrupt(dev_priv, bit);
446 }
447
448 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
449 enum transcoder pch_transcoder,
450 bool enable, bool old)
451 {
452 struct drm_i915_private *dev_priv = dev->dev_private;
453
454 if (enable) {
455 I915_WRITE(SERR_INT,
456 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
457
458 if (!cpt_can_enable_serr_int(dev))
459 return;
460
461 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
462 } else {
463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
464
465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
468 transcoder_name(pch_transcoder));
469 }
470 }
471 }
472
473 /**
474 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
475 * @dev: drm device
476 * @pipe: pipe
477 * @enable: true if we want to report FIFO underrun errors, false otherwise
478 *
479 * This function makes us disable or enable CPU fifo underruns for a specific
480 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
481 * reporting for one pipe may also disable all the other CPU error interruts for
482 * the other pipes, due to the fact that there's just one interrupt mask/enable
483 * bit for all the pipes.
484 *
485 * Returns the previous state of underrun reporting.
486 */
487 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
488 enum pipe pipe, bool enable)
489 {
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
493 bool old;
494
495 assert_spin_locked(&dev_priv->irq_lock);
496
497 old = !intel_crtc->cpu_fifo_underrun_disabled;
498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
508
509 return old;
510 }
511
512 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
513 enum pipe pipe, bool enable)
514 {
515 struct drm_i915_private *dev_priv = dev->dev_private;
516 unsigned long flags;
517 bool ret;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
520 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
521 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
522
523 return ret;
524 }
525
526 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
527 enum pipe pipe)
528 {
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
532
533 return !intel_crtc->cpu_fifo_underrun_disabled;
534 }
535
536 /**
537 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
538 * @dev: drm device
539 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
540 * @enable: true if we want to report FIFO underrun errors, false otherwise
541 *
542 * This function makes us disable or enable PCH fifo underruns for a specific
543 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
544 * underrun reporting for one transcoder may also disable all the other PCH
545 * error interruts for the other transcoders, due to the fact that there's just
546 * one interrupt mask/enable bit for all the transcoders.
547 *
548 * Returns the previous state of underrun reporting.
549 */
550 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
551 enum transcoder pch_transcoder,
552 bool enable)
553 {
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
557 unsigned long flags;
558 bool old;
559
560 /*
561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
562 * has only one pch transcoder A that all pipes can use. To avoid racy
563 * pch transcoder -> pipe lookups from interrupt code simply store the
564 * underrun statistics in crtc A. Since we never expose this anywhere
565 * nor use it outside of the fifo underrun code here using the "wrong"
566 * crtc on LPT won't cause issues.
567 */
568
569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
570
571 old = !intel_crtc->pch_fifo_underrun_disabled;
572 intel_crtc->pch_fifo_underrun_disabled = !enable;
573
574 if (HAS_PCH_IBX(dev))
575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
576 else
577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
578
579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
580 return old;
581 }
582
583
584 static void
585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
586 u32 enable_mask, u32 status_mask)
587 {
588 u32 reg = PIPESTAT(pipe);
589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
590
591 assert_spin_locked(&dev_priv->irq_lock);
592
593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
594 status_mask & ~PIPESTAT_INT_STATUS_MASK,
595 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
596 pipe_name(pipe), enable_mask, status_mask))
597 return;
598
599 if ((pipestat & enable_mask) == enable_mask)
600 return;
601
602 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
603
604 /* Enable the interrupt, clear any pending status */
605 pipestat |= enable_mask | status_mask;
606 I915_WRITE(reg, pipestat);
607 POSTING_READ(reg);
608 }
609
610 static void
611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
612 u32 enable_mask, u32 status_mask)
613 {
614 u32 reg = PIPESTAT(pipe);
615 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
616
617 assert_spin_locked(&dev_priv->irq_lock);
618
619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
620 status_mask & ~PIPESTAT_INT_STATUS_MASK,
621 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
622 pipe_name(pipe), enable_mask, status_mask))
623 return;
624
625 if ((pipestat & enable_mask) == 0)
626 return;
627
628 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
629
630 pipestat &= ~enable_mask;
631 I915_WRITE(reg, pipestat);
632 POSTING_READ(reg);
633 }
634
635 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
636 {
637 u32 enable_mask = status_mask << 16;
638
639 /*
640 * On pipe A we don't support the PSR interrupt yet,
641 * on pipe B and C the same bit MBZ.
642 */
643 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
644 return 0;
645 /*
646 * On pipe B and C we don't support the PSR interrupt yet, on pipe
647 * A the same bit is for perf counters which we don't use either.
648 */
649 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
650 return 0;
651
652 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
653 SPRITE0_FLIP_DONE_INT_EN_VLV |
654 SPRITE1_FLIP_DONE_INT_EN_VLV);
655 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
656 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
657 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
658 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
659
660 return enable_mask;
661 }
662
663 void
664 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
665 u32 status_mask)
666 {
667 u32 enable_mask;
668
669 if (IS_VALLEYVIEW(dev_priv->dev))
670 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
671 status_mask);
672 else
673 enable_mask = status_mask << 16;
674 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
675 }
676
677 void
678 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
679 u32 status_mask)
680 {
681 u32 enable_mask;
682
683 if (IS_VALLEYVIEW(dev_priv->dev))
684 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
685 status_mask);
686 else
687 enable_mask = status_mask << 16;
688 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
689 }
690
691 /**
692 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
693 */
694 static void i915_enable_asle_pipestat(struct drm_device *dev)
695 {
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 unsigned long irqflags;
698
699 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
700 return;
701
702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
703
704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
705 if (INTEL_INFO(dev)->gen >= 4)
706 i915_enable_pipestat(dev_priv, PIPE_A,
707 PIPE_LEGACY_BLC_EVENT_STATUS);
708
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
710 }
711
712 /**
713 * i915_pipe_enabled - check if a pipe is enabled
714 * @dev: DRM device
715 * @pipe: pipe to check
716 *
717 * Reading certain registers when the pipe is disabled can hang the chip.
718 * Use this routine to make sure the PLL is running and the pipe is active
719 * before reading such registers if unsure.
720 */
721 static int
722 i915_pipe_enabled(struct drm_device *dev, int pipe)
723 {
724 struct drm_i915_private *dev_priv = dev->dev_private;
725
726 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
727 /* Locking is horribly broken here, but whatever. */
728 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
730
731 return intel_crtc->active;
732 } else {
733 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
734 }
735 }
736
737 /*
738 * This timing diagram depicts the video signal in and
739 * around the vertical blanking period.
740 *
741 * Assumptions about the fictitious mode used in this example:
742 * vblank_start >= 3
743 * vsync_start = vblank_start + 1
744 * vsync_end = vblank_start + 2
745 * vtotal = vblank_start + 3
746 *
747 * start of vblank:
748 * latch double buffered registers
749 * increment frame counter (ctg+)
750 * generate start of vblank interrupt (gen4+)
751 * |
752 * | frame start:
753 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
754 * | may be shifted forward 1-3 extra lines via PIPECONF
755 * | |
756 * | | start of vsync:
757 * | | generate vsync interrupt
758 * | | |
759 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
760 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
761 * ----va---> <-----------------vb--------------------> <--------va-------------
762 * | | <----vs-----> |
763 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
764 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
765 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
766 * | | |
767 * last visible pixel first visible pixel
768 * | increment frame counter (gen3/4)
769 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
770 *
771 * x = horizontal active
772 * _ = horizontal blanking
773 * hs = horizontal sync
774 * va = vertical active
775 * vb = vertical blanking
776 * vs = vertical sync
777 * vbs = vblank_start (number)
778 *
779 * Summary:
780 * - most events happen at the start of horizontal sync
781 * - frame start happens at the start of horizontal blank, 1-4 lines
782 * (depending on PIPECONF settings) after the start of vblank
783 * - gen3/4 pixel and frame counter are synchronized with the start
784 * of horizontal active on the first line of vertical active
785 */
786
787 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
788 {
789 /* Gen2 doesn't have a hardware frame counter */
790 return 0;
791 }
792
793 /* Called from drm generic code, passed a 'crtc', which
794 * we use as a pipe index
795 */
796 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
797 {
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 unsigned long high_frame;
800 unsigned long low_frame;
801 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
802
803 if (!i915_pipe_enabled(dev, pipe)) {
804 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
805 "pipe %c\n", pipe_name(pipe));
806 return 0;
807 }
808
809 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
810 struct intel_crtc *intel_crtc =
811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
812 const struct drm_display_mode *mode =
813 &intel_crtc->config.adjusted_mode;
814
815 htotal = mode->crtc_htotal;
816 hsync_start = mode->crtc_hsync_start;
817 vbl_start = mode->crtc_vblank_start;
818 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
819 vbl_start = DIV_ROUND_UP(vbl_start, 2);
820 } else {
821 enum transcoder cpu_transcoder = (enum transcoder) pipe;
822
823 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
824 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
825 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
826 if ((I915_READ(PIPECONF(cpu_transcoder)) &
827 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
828 vbl_start = DIV_ROUND_UP(vbl_start, 2);
829 }
830
831 /* Convert to pixel count */
832 vbl_start *= htotal;
833
834 /* Start of vblank event occurs at start of hsync */
835 vbl_start -= htotal - hsync_start;
836
837 high_frame = PIPEFRAME(pipe);
838 low_frame = PIPEFRAMEPIXEL(pipe);
839
840 /*
841 * High & low register fields aren't synchronized, so make sure
842 * we get a low value that's stable across two reads of the high
843 * register.
844 */
845 do {
846 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
847 low = I915_READ(low_frame);
848 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
849 } while (high1 != high2);
850
851 high1 >>= PIPE_FRAME_HIGH_SHIFT;
852 pixel = low & PIPE_PIXEL_MASK;
853 low >>= PIPE_FRAME_LOW_SHIFT;
854
855 /*
856 * The frame counter increments at beginning of active.
857 * Cook up a vblank counter by also checking the pixel
858 * counter against vblank start.
859 */
860 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
861 }
862
863 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
864 {
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 int reg = PIPE_FRMCOUNT_GM45(pipe);
867
868 if (!i915_pipe_enabled(dev, pipe)) {
869 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
870 "pipe %c\n", pipe_name(pipe));
871 return 0;
872 }
873
874 return I915_READ(reg);
875 }
876
877 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
878 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
879
880 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
881 {
882 struct drm_device *dev = crtc->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
885 enum pipe pipe = crtc->pipe;
886 int position, vtotal;
887
888 vtotal = mode->crtc_vtotal;
889 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
890 vtotal /= 2;
891
892 if (IS_GEN2(dev))
893 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
894 else
895 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
896
897 /*
898 * See update_scanline_offset() for the details on the
899 * scanline_offset adjustment.
900 */
901 return (position + crtc->scanline_offset) % vtotal;
902 }
903
904 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
905 unsigned int flags, int *vpos, int *hpos,
906 ktime_t *stime, ktime_t *etime)
907 {
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
911 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
912 int position;
913 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
914 bool in_vbl = true;
915 int ret = 0;
916 unsigned long irqflags;
917
918 if (!intel_crtc->active) {
919 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
920 "pipe %c\n", pipe_name(pipe));
921 return 0;
922 }
923
924 htotal = mode->crtc_htotal;
925 hsync_start = mode->crtc_hsync_start;
926 vtotal = mode->crtc_vtotal;
927 vbl_start = mode->crtc_vblank_start;
928 vbl_end = mode->crtc_vblank_end;
929
930 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
931 vbl_start = DIV_ROUND_UP(vbl_start, 2);
932 vbl_end /= 2;
933 vtotal /= 2;
934 }
935
936 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
937
938 /*
939 * Lock uncore.lock, as we will do multiple timing critical raw
940 * register reads, potentially with preemption disabled, so the
941 * following code must not block on uncore.lock.
942 */
943 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
944
945 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
946
947 /* Get optional system timestamp before query. */
948 if (stime)
949 *stime = ktime_get();
950
951 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
952 /* No obvious pixelcount register. Only query vertical
953 * scanout position from Display scan line register.
954 */
955 position = __intel_get_crtc_scanline(intel_crtc);
956 } else {
957 /* Have access to pixelcount since start of frame.
958 * We can split this into vertical and horizontal
959 * scanout position.
960 */
961 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
962
963 /* convert to pixel counts */
964 vbl_start *= htotal;
965 vbl_end *= htotal;
966 vtotal *= htotal;
967
968 /*
969 * In interlaced modes, the pixel counter counts all pixels,
970 * so one field will have htotal more pixels. In order to avoid
971 * the reported position from jumping backwards when the pixel
972 * counter is beyond the length of the shorter field, just
973 * clamp the position the length of the shorter field. This
974 * matches how the scanline counter based position works since
975 * the scanline counter doesn't count the two half lines.
976 */
977 if (position >= vtotal)
978 position = vtotal - 1;
979
980 /*
981 * Start of vblank interrupt is triggered at start of hsync,
982 * just prior to the first active line of vblank. However we
983 * consider lines to start at the leading edge of horizontal
984 * active. So, should we get here before we've crossed into
985 * the horizontal active of the first line in vblank, we would
986 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
987 * always add htotal-hsync_start to the current pixel position.
988 */
989 position = (position + htotal - hsync_start) % vtotal;
990 }
991
992 /* Get optional system timestamp after query. */
993 if (etime)
994 *etime = ktime_get();
995
996 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
997
998 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
999
1000 in_vbl = position >= vbl_start && position < vbl_end;
1001
1002 /*
1003 * While in vblank, position will be negative
1004 * counting up towards 0 at vbl_end. And outside
1005 * vblank, position will be positive counting
1006 * up since vbl_end.
1007 */
1008 if (position >= vbl_start)
1009 position -= vbl_end;
1010 else
1011 position += vtotal - vbl_end;
1012
1013 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1014 *vpos = position;
1015 *hpos = 0;
1016 } else {
1017 *vpos = position / htotal;
1018 *hpos = position - (*vpos * htotal);
1019 }
1020
1021 /* In vblank? */
1022 if (in_vbl)
1023 ret |= DRM_SCANOUTPOS_INVBL;
1024
1025 return ret;
1026 }
1027
1028 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1029 {
1030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031 unsigned long irqflags;
1032 int position;
1033
1034 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035 position = __intel_get_crtc_scanline(crtc);
1036 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1037
1038 return position;
1039 }
1040
1041 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1042 int *max_error,
1043 struct timeval *vblank_time,
1044 unsigned flags)
1045 {
1046 struct drm_crtc *crtc;
1047
1048 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1049 DRM_ERROR("Invalid crtc %d\n", pipe);
1050 return -EINVAL;
1051 }
1052
1053 /* Get drm_crtc to timestamp: */
1054 crtc = intel_get_crtc_for_pipe(dev, pipe);
1055 if (crtc == NULL) {
1056 DRM_ERROR("Invalid crtc %d\n", pipe);
1057 return -EINVAL;
1058 }
1059
1060 if (!crtc->enabled) {
1061 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1062 return -EBUSY;
1063 }
1064
1065 /* Helper routine in DRM core does all the work: */
1066 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1067 vblank_time, flags,
1068 crtc,
1069 &to_intel_crtc(crtc)->config.adjusted_mode);
1070 }
1071
1072 static bool intel_hpd_irq_event(struct drm_device *dev,
1073 struct drm_connector *connector)
1074 {
1075 enum drm_connector_status old_status;
1076
1077 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078 old_status = connector->status;
1079
1080 connector->status = connector->funcs->detect(connector, false);
1081 if (old_status == connector->status)
1082 return false;
1083
1084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1085 connector->base.id,
1086 connector->name,
1087 drm_get_connector_status_name(old_status),
1088 drm_get_connector_status_name(connector->status));
1089
1090 return true;
1091 }
1092
1093 /*
1094 * Handle hotplug events outside the interrupt handler proper.
1095 */
1096 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1097
1098 static void i915_hotplug_work_func(struct work_struct *work)
1099 {
1100 struct drm_i915_private *dev_priv =
1101 container_of(work, struct drm_i915_private, hotplug_work);
1102 struct drm_device *dev = dev_priv->dev;
1103 struct drm_mode_config *mode_config = &dev->mode_config;
1104 struct intel_connector *intel_connector;
1105 struct intel_encoder *intel_encoder;
1106 struct drm_connector *connector;
1107 unsigned long irqflags;
1108 bool hpd_disabled = false;
1109 bool changed = false;
1110 u32 hpd_event_bits;
1111
1112 mutex_lock(&mode_config->mutex);
1113 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1114
1115 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1116
1117 hpd_event_bits = dev_priv->hpd_event_bits;
1118 dev_priv->hpd_event_bits = 0;
1119 list_for_each_entry(connector, &mode_config->connector_list, head) {
1120 intel_connector = to_intel_connector(connector);
1121 intel_encoder = intel_connector->encoder;
1122 if (intel_encoder->hpd_pin > HPD_NONE &&
1123 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1124 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1125 DRM_INFO("HPD interrupt storm detected on connector %s: "
1126 "switching from hotplug detection to polling\n",
1127 connector->name);
1128 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1129 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1130 | DRM_CONNECTOR_POLL_DISCONNECT;
1131 hpd_disabled = true;
1132 }
1133 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1134 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1135 connector->name, intel_encoder->hpd_pin);
1136 }
1137 }
1138 /* if there were no outputs to poll, poll was disabled,
1139 * therefore make sure it's enabled when disabling HPD on
1140 * some connectors */
1141 if (hpd_disabled) {
1142 drm_kms_helper_poll_enable(dev);
1143 mod_timer(&dev_priv->hotplug_reenable_timer,
1144 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1145 }
1146
1147 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1148
1149 list_for_each_entry(connector, &mode_config->connector_list, head) {
1150 intel_connector = to_intel_connector(connector);
1151 intel_encoder = intel_connector->encoder;
1152 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1153 if (intel_encoder->hot_plug)
1154 intel_encoder->hot_plug(intel_encoder);
1155 if (intel_hpd_irq_event(dev, connector))
1156 changed = true;
1157 }
1158 }
1159 mutex_unlock(&mode_config->mutex);
1160
1161 if (changed)
1162 drm_kms_helper_hotplug_event(dev);
1163 }
1164
1165 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1166 {
1167 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1168 }
1169
1170 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1171 {
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 busy_up, busy_down, max_avg, min_avg;
1174 u8 new_delay;
1175
1176 spin_lock(&mchdev_lock);
1177
1178 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1179
1180 new_delay = dev_priv->ips.cur_delay;
1181
1182 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1183 busy_up = I915_READ(RCPREVBSYTUPAVG);
1184 busy_down = I915_READ(RCPREVBSYTDNAVG);
1185 max_avg = I915_READ(RCBMAXAVG);
1186 min_avg = I915_READ(RCBMINAVG);
1187
1188 /* Handle RCS change request from hw */
1189 if (busy_up > max_avg) {
1190 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1191 new_delay = dev_priv->ips.cur_delay - 1;
1192 if (new_delay < dev_priv->ips.max_delay)
1193 new_delay = dev_priv->ips.max_delay;
1194 } else if (busy_down < min_avg) {
1195 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1196 new_delay = dev_priv->ips.cur_delay + 1;
1197 if (new_delay > dev_priv->ips.min_delay)
1198 new_delay = dev_priv->ips.min_delay;
1199 }
1200
1201 if (ironlake_set_drps(dev, new_delay))
1202 dev_priv->ips.cur_delay = new_delay;
1203
1204 spin_unlock(&mchdev_lock);
1205
1206 return;
1207 }
1208
1209 static void notify_ring(struct drm_device *dev,
1210 struct intel_engine_cs *ring)
1211 {
1212 if (!intel_ring_initialized(ring))
1213 return;
1214
1215 trace_i915_gem_request_complete(ring);
1216
1217 if (drm_core_check_feature(dev, DRIVER_MODESET))
1218 intel_notify_mmio_flip(ring);
1219
1220 wake_up_all(&ring->irq_queue);
1221 i915_queue_hangcheck(dev);
1222 }
1223
1224 static void gen6_pm_rps_work(struct work_struct *work)
1225 {
1226 struct drm_i915_private *dev_priv =
1227 container_of(work, struct drm_i915_private, rps.work);
1228 u32 pm_iir;
1229 int new_delay, adj;
1230
1231 spin_lock_irq(&dev_priv->irq_lock);
1232 pm_iir = dev_priv->rps.pm_iir;
1233 dev_priv->rps.pm_iir = 0;
1234 if (IS_BROADWELL(dev_priv->dev))
1235 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1236 else {
1237 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1238 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1239 }
1240 spin_unlock_irq(&dev_priv->irq_lock);
1241
1242 /* Make sure we didn't queue anything we're not going to process. */
1243 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1244
1245 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1246 return;
1247
1248 mutex_lock(&dev_priv->rps.hw_lock);
1249
1250 adj = dev_priv->rps.last_adj;
1251 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1252 if (adj > 0)
1253 adj *= 2;
1254 else {
1255 /* CHV needs even encode values */
1256 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1257 }
1258 new_delay = dev_priv->rps.cur_freq + adj;
1259
1260 /*
1261 * For better performance, jump directly
1262 * to RPe if we're below it.
1263 */
1264 if (new_delay < dev_priv->rps.efficient_freq)
1265 new_delay = dev_priv->rps.efficient_freq;
1266 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1267 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1268 new_delay = dev_priv->rps.efficient_freq;
1269 else
1270 new_delay = dev_priv->rps.min_freq_softlimit;
1271 adj = 0;
1272 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1273 if (adj < 0)
1274 adj *= 2;
1275 else {
1276 /* CHV needs even encode values */
1277 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1278 }
1279 new_delay = dev_priv->rps.cur_freq + adj;
1280 } else { /* unknown event */
1281 new_delay = dev_priv->rps.cur_freq;
1282 }
1283
1284 /* sysfs frequency interfaces may have snuck in while servicing the
1285 * interrupt
1286 */
1287 new_delay = clamp_t(int, new_delay,
1288 dev_priv->rps.min_freq_softlimit,
1289 dev_priv->rps.max_freq_softlimit);
1290
1291 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1292
1293 if (IS_VALLEYVIEW(dev_priv->dev))
1294 valleyview_set_rps(dev_priv->dev, new_delay);
1295 else
1296 gen6_set_rps(dev_priv->dev, new_delay);
1297
1298 mutex_unlock(&dev_priv->rps.hw_lock);
1299 }
1300
1301
1302 /**
1303 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1304 * occurred.
1305 * @work: workqueue struct
1306 *
1307 * Doesn't actually do anything except notify userspace. As a consequence of
1308 * this event, userspace should try to remap the bad rows since statistically
1309 * it is likely the same row is more likely to go bad again.
1310 */
1311 static void ivybridge_parity_work(struct work_struct *work)
1312 {
1313 struct drm_i915_private *dev_priv =
1314 container_of(work, struct drm_i915_private, l3_parity.error_work);
1315 u32 error_status, row, bank, subbank;
1316 char *parity_event[6];
1317 uint32_t misccpctl;
1318 unsigned long flags;
1319 uint8_t slice = 0;
1320
1321 /* We must turn off DOP level clock gating to access the L3 registers.
1322 * In order to prevent a get/put style interface, acquire struct mutex
1323 * any time we access those registers.
1324 */
1325 mutex_lock(&dev_priv->dev->struct_mutex);
1326
1327 /* If we've screwed up tracking, just let the interrupt fire again */
1328 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1329 goto out;
1330
1331 misccpctl = I915_READ(GEN7_MISCCPCTL);
1332 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1333 POSTING_READ(GEN7_MISCCPCTL);
1334
1335 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1336 u32 reg;
1337
1338 slice--;
1339 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1340 break;
1341
1342 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1343
1344 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1345
1346 error_status = I915_READ(reg);
1347 row = GEN7_PARITY_ERROR_ROW(error_status);
1348 bank = GEN7_PARITY_ERROR_BANK(error_status);
1349 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1350
1351 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1352 POSTING_READ(reg);
1353
1354 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1355 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1356 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1357 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1358 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1359 parity_event[5] = NULL;
1360
1361 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1362 KOBJ_CHANGE, parity_event);
1363
1364 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1365 slice, row, bank, subbank);
1366
1367 kfree(parity_event[4]);
1368 kfree(parity_event[3]);
1369 kfree(parity_event[2]);
1370 kfree(parity_event[1]);
1371 }
1372
1373 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1374
1375 out:
1376 WARN_ON(dev_priv->l3_parity.which_slice);
1377 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1378 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1379 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1380
1381 mutex_unlock(&dev_priv->dev->struct_mutex);
1382 }
1383
1384 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1385 {
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387
1388 if (!HAS_L3_DPF(dev))
1389 return;
1390
1391 spin_lock(&dev_priv->irq_lock);
1392 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1393 spin_unlock(&dev_priv->irq_lock);
1394
1395 iir &= GT_PARITY_ERROR(dev);
1396 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1397 dev_priv->l3_parity.which_slice |= 1 << 1;
1398
1399 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1400 dev_priv->l3_parity.which_slice |= 1 << 0;
1401
1402 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1403 }
1404
1405 static void ilk_gt_irq_handler(struct drm_device *dev,
1406 struct drm_i915_private *dev_priv,
1407 u32 gt_iir)
1408 {
1409 if (gt_iir &
1410 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1411 notify_ring(dev, &dev_priv->ring[RCS]);
1412 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1413 notify_ring(dev, &dev_priv->ring[VCS]);
1414 }
1415
1416 static void snb_gt_irq_handler(struct drm_device *dev,
1417 struct drm_i915_private *dev_priv,
1418 u32 gt_iir)
1419 {
1420
1421 if (gt_iir &
1422 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1423 notify_ring(dev, &dev_priv->ring[RCS]);
1424 if (gt_iir & GT_BSD_USER_INTERRUPT)
1425 notify_ring(dev, &dev_priv->ring[VCS]);
1426 if (gt_iir & GT_BLT_USER_INTERRUPT)
1427 notify_ring(dev, &dev_priv->ring[BCS]);
1428
1429 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1430 GT_BSD_CS_ERROR_INTERRUPT |
1431 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1432 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1433 gt_iir);
1434 }
1435
1436 if (gt_iir & GT_PARITY_ERROR(dev))
1437 ivybridge_parity_error_irq_handler(dev, gt_iir);
1438 }
1439
1440 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1441 {
1442 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1443 return;
1444
1445 spin_lock(&dev_priv->irq_lock);
1446 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1447 bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1448 spin_unlock(&dev_priv->irq_lock);
1449
1450 queue_work(dev_priv->wq, &dev_priv->rps.work);
1451 }
1452
1453 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1454 struct drm_i915_private *dev_priv,
1455 u32 master_ctl)
1456 {
1457 u32 rcs, bcs, vcs;
1458 uint32_t tmp = 0;
1459 irqreturn_t ret = IRQ_NONE;
1460
1461 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1462 tmp = I915_READ(GEN8_GT_IIR(0));
1463 if (tmp) {
1464 I915_WRITE(GEN8_GT_IIR(0), tmp);
1465 ret = IRQ_HANDLED;
1466 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1467 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1468 if (rcs & GT_RENDER_USER_INTERRUPT)
1469 notify_ring(dev, &dev_priv->ring[RCS]);
1470 if (bcs & GT_RENDER_USER_INTERRUPT)
1471 notify_ring(dev, &dev_priv->ring[BCS]);
1472 } else
1473 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1474 }
1475
1476 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1477 tmp = I915_READ(GEN8_GT_IIR(1));
1478 if (tmp) {
1479 I915_WRITE(GEN8_GT_IIR(1), tmp);
1480 ret = IRQ_HANDLED;
1481 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1482 if (vcs & GT_RENDER_USER_INTERRUPT)
1483 notify_ring(dev, &dev_priv->ring[VCS]);
1484 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1485 if (vcs & GT_RENDER_USER_INTERRUPT)
1486 notify_ring(dev, &dev_priv->ring[VCS2]);
1487 } else
1488 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1489 }
1490
1491 if (master_ctl & GEN8_GT_PM_IRQ) {
1492 tmp = I915_READ(GEN8_GT_IIR(2));
1493 if (tmp & dev_priv->pm_rps_events) {
1494 I915_WRITE(GEN8_GT_IIR(2),
1495 tmp & dev_priv->pm_rps_events);
1496 ret = IRQ_HANDLED;
1497 gen8_rps_irq_handler(dev_priv, tmp);
1498 } else
1499 DRM_ERROR("The master control interrupt lied (PM)!\n");
1500 }
1501
1502 if (master_ctl & GEN8_GT_VECS_IRQ) {
1503 tmp = I915_READ(GEN8_GT_IIR(3));
1504 if (tmp) {
1505 I915_WRITE(GEN8_GT_IIR(3), tmp);
1506 ret = IRQ_HANDLED;
1507 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1508 if (vcs & GT_RENDER_USER_INTERRUPT)
1509 notify_ring(dev, &dev_priv->ring[VECS]);
1510 } else
1511 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1512 }
1513
1514 return ret;
1515 }
1516
1517 #define HPD_STORM_DETECT_PERIOD 1000
1518 #define HPD_STORM_THRESHOLD 5
1519
1520 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1521 u32 hotplug_trigger,
1522 const u32 *hpd)
1523 {
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 int i;
1526 bool storm_detected = false;
1527
1528 if (!hotplug_trigger)
1529 return;
1530
1531 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1532 hotplug_trigger);
1533
1534 spin_lock(&dev_priv->irq_lock);
1535 for (i = 1; i < HPD_NUM_PINS; i++) {
1536
1537 if (hpd[i] & hotplug_trigger &&
1538 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1539 /*
1540 * On GMCH platforms the interrupt mask bits only
1541 * prevent irq generation, not the setting of the
1542 * hotplug bits itself. So only WARN about unexpected
1543 * interrupts on saner platforms.
1544 */
1545 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1546 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1547 hotplug_trigger, i, hpd[i]);
1548
1549 continue;
1550 }
1551
1552 if (!(hpd[i] & hotplug_trigger) ||
1553 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1554 continue;
1555
1556 dev_priv->hpd_event_bits |= (1 << i);
1557 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1558 dev_priv->hpd_stats[i].hpd_last_jiffies
1559 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1560 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1561 dev_priv->hpd_stats[i].hpd_cnt = 0;
1562 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1563 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1564 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1565 dev_priv->hpd_event_bits &= ~(1 << i);
1566 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1567 storm_detected = true;
1568 } else {
1569 dev_priv->hpd_stats[i].hpd_cnt++;
1570 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1571 dev_priv->hpd_stats[i].hpd_cnt);
1572 }
1573 }
1574
1575 if (storm_detected)
1576 dev_priv->display.hpd_irq_setup(dev);
1577 spin_unlock(&dev_priv->irq_lock);
1578
1579 /*
1580 * Our hotplug handler can grab modeset locks (by calling down into the
1581 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1582 * queue for otherwise the flush_work in the pageflip code will
1583 * deadlock.
1584 */
1585 schedule_work(&dev_priv->hotplug_work);
1586 }
1587
1588 static void gmbus_irq_handler(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 wake_up_all(&dev_priv->gmbus_wait_queue);
1593 }
1594
1595 static void dp_aux_irq_handler(struct drm_device *dev)
1596 {
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598
1599 wake_up_all(&dev_priv->gmbus_wait_queue);
1600 }
1601
1602 #if defined(CONFIG_DEBUG_FS)
1603 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1604 uint32_t crc0, uint32_t crc1,
1605 uint32_t crc2, uint32_t crc3,
1606 uint32_t crc4)
1607 {
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1610 struct intel_pipe_crc_entry *entry;
1611 int head, tail;
1612
1613 spin_lock(&pipe_crc->lock);
1614
1615 if (!pipe_crc->entries) {
1616 spin_unlock(&pipe_crc->lock);
1617 DRM_ERROR("spurious interrupt\n");
1618 return;
1619 }
1620
1621 head = pipe_crc->head;
1622 tail = pipe_crc->tail;
1623
1624 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1625 spin_unlock(&pipe_crc->lock);
1626 DRM_ERROR("CRC buffer overflowing\n");
1627 return;
1628 }
1629
1630 entry = &pipe_crc->entries[head];
1631
1632 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1633 entry->crc[0] = crc0;
1634 entry->crc[1] = crc1;
1635 entry->crc[2] = crc2;
1636 entry->crc[3] = crc3;
1637 entry->crc[4] = crc4;
1638
1639 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1640 pipe_crc->head = head;
1641
1642 spin_unlock(&pipe_crc->lock);
1643
1644 wake_up_interruptible(&pipe_crc->wq);
1645 }
1646 #else
1647 static inline void
1648 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1649 uint32_t crc0, uint32_t crc1,
1650 uint32_t crc2, uint32_t crc3,
1651 uint32_t crc4) {}
1652 #endif
1653
1654
1655 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1656 {
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658
1659 display_pipe_crc_irq_handler(dev, pipe,
1660 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1661 0, 0, 0, 0);
1662 }
1663
1664 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1665 {
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667
1668 display_pipe_crc_irq_handler(dev, pipe,
1669 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1670 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1671 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1672 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1673 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1674 }
1675
1676 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1677 {
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 uint32_t res1, res2;
1680
1681 if (INTEL_INFO(dev)->gen >= 3)
1682 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1683 else
1684 res1 = 0;
1685
1686 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1687 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1688 else
1689 res2 = 0;
1690
1691 display_pipe_crc_irq_handler(dev, pipe,
1692 I915_READ(PIPE_CRC_RES_RED(pipe)),
1693 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1694 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1695 res1, res2);
1696 }
1697
1698 /* The RPS events need forcewake, so we add them to a work queue and mask their
1699 * IMR bits until the work is done. Other interrupts can be processed without
1700 * the work queue. */
1701 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1702 {
1703 if (pm_iir & dev_priv->pm_rps_events) {
1704 spin_lock(&dev_priv->irq_lock);
1705 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1706 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1707 spin_unlock(&dev_priv->irq_lock);
1708
1709 queue_work(dev_priv->wq, &dev_priv->rps.work);
1710 }
1711
1712 if (HAS_VEBOX(dev_priv->dev)) {
1713 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1714 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1715
1716 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1717 i915_handle_error(dev_priv->dev, false,
1718 "VEBOX CS error interrupt 0x%08x",
1719 pm_iir);
1720 }
1721 }
1722 }
1723
1724 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1725 {
1726 struct intel_crtc *crtc;
1727
1728 if (!drm_handle_vblank(dev, pipe))
1729 return false;
1730
1731 crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1732 wake_up(&crtc->vbl_wait);
1733
1734 return true;
1735 }
1736
1737 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1738 {
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 u32 pipe_stats[I915_MAX_PIPES] = { };
1741 int pipe;
1742
1743 spin_lock(&dev_priv->irq_lock);
1744 for_each_pipe(pipe) {
1745 int reg;
1746 u32 mask, iir_bit = 0;
1747
1748 /*
1749 * PIPESTAT bits get signalled even when the interrupt is
1750 * disabled with the mask bits, and some of the status bits do
1751 * not generate interrupts at all (like the underrun bit). Hence
1752 * we need to be careful that we only handle what we want to
1753 * handle.
1754 */
1755 mask = 0;
1756 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1757 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1758
1759 switch (pipe) {
1760 case PIPE_A:
1761 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1762 break;
1763 case PIPE_B:
1764 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1765 break;
1766 case PIPE_C:
1767 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1768 break;
1769 }
1770 if (iir & iir_bit)
1771 mask |= dev_priv->pipestat_irq_mask[pipe];
1772
1773 if (!mask)
1774 continue;
1775
1776 reg = PIPESTAT(pipe);
1777 mask |= PIPESTAT_INT_ENABLE_MASK;
1778 pipe_stats[pipe] = I915_READ(reg) & mask;
1779
1780 /*
1781 * Clear the PIPE*STAT regs before the IIR
1782 */
1783 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1784 PIPESTAT_INT_STATUS_MASK))
1785 I915_WRITE(reg, pipe_stats[pipe]);
1786 }
1787 spin_unlock(&dev_priv->irq_lock);
1788
1789 for_each_pipe(pipe) {
1790 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1791 intel_pipe_handle_vblank(dev, pipe);
1792
1793 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1794 intel_prepare_page_flip(dev, pipe);
1795 intel_finish_page_flip(dev, pipe);
1796 }
1797
1798 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1799 i9xx_pipe_crc_irq_handler(dev, pipe);
1800
1801 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1802 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1803 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1804 }
1805
1806 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1807 gmbus_irq_handler(dev);
1808 }
1809
1810 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1811 {
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1814
1815 if (hotplug_status) {
1816 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1817 /*
1818 * Make sure hotplug status is cleared before we clear IIR, or else we
1819 * may miss hotplug events.
1820 */
1821 POSTING_READ(PORT_HOTPLUG_STAT);
1822
1823 if (IS_G4X(dev)) {
1824 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1825
1826 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1827 } else {
1828 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1829
1830 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1831 }
1832
1833 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1834 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1835 dp_aux_irq_handler(dev);
1836 }
1837 }
1838
1839 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1840 {
1841 struct drm_device *dev = arg;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 u32 iir, gt_iir, pm_iir;
1844 irqreturn_t ret = IRQ_NONE;
1845
1846 while (true) {
1847 /* Find, clear, then process each source of interrupt */
1848
1849 gt_iir = I915_READ(GTIIR);
1850 if (gt_iir)
1851 I915_WRITE(GTIIR, gt_iir);
1852
1853 pm_iir = I915_READ(GEN6_PMIIR);
1854 if (pm_iir)
1855 I915_WRITE(GEN6_PMIIR, pm_iir);
1856
1857 iir = I915_READ(VLV_IIR);
1858 if (iir) {
1859 /* Consume port before clearing IIR or we'll miss events */
1860 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1861 i9xx_hpd_irq_handler(dev);
1862 I915_WRITE(VLV_IIR, iir);
1863 }
1864
1865 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1866 goto out;
1867
1868 ret = IRQ_HANDLED;
1869
1870 if (gt_iir)
1871 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1872 if (pm_iir)
1873 gen6_rps_irq_handler(dev_priv, pm_iir);
1874 /* Call regardless, as some status bits might not be
1875 * signalled in iir */
1876 valleyview_pipestat_irq_handler(dev, iir);
1877 }
1878
1879 out:
1880 return ret;
1881 }
1882
1883 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1884 {
1885 struct drm_device *dev = arg;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 u32 master_ctl, iir;
1888 irqreturn_t ret = IRQ_NONE;
1889
1890 for (;;) {
1891 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1892 iir = I915_READ(VLV_IIR);
1893
1894 if (master_ctl == 0 && iir == 0)
1895 break;
1896
1897 ret = IRQ_HANDLED;
1898
1899 I915_WRITE(GEN8_MASTER_IRQ, 0);
1900
1901 /* Find, clear, then process each source of interrupt */
1902
1903 if (iir) {
1904 /* Consume port before clearing IIR or we'll miss events */
1905 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1906 i9xx_hpd_irq_handler(dev);
1907 I915_WRITE(VLV_IIR, iir);
1908 }
1909
1910 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1911
1912 /* Call regardless, as some status bits might not be
1913 * signalled in iir */
1914 valleyview_pipestat_irq_handler(dev, iir);
1915
1916 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1917 POSTING_READ(GEN8_MASTER_IRQ);
1918 }
1919
1920 return ret;
1921 }
1922
1923 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1924 {
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 int pipe;
1927 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1928
1929 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1930
1931 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1932 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1933 SDE_AUDIO_POWER_SHIFT);
1934 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1935 port_name(port));
1936 }
1937
1938 if (pch_iir & SDE_AUX_MASK)
1939 dp_aux_irq_handler(dev);
1940
1941 if (pch_iir & SDE_GMBUS)
1942 gmbus_irq_handler(dev);
1943
1944 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1945 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1946
1947 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1948 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1949
1950 if (pch_iir & SDE_POISON)
1951 DRM_ERROR("PCH poison interrupt\n");
1952
1953 if (pch_iir & SDE_FDI_MASK)
1954 for_each_pipe(pipe)
1955 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1956 pipe_name(pipe),
1957 I915_READ(FDI_RX_IIR(pipe)));
1958
1959 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1960 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1961
1962 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1963 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1964
1965 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1966 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1967 false))
1968 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1969
1970 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1971 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1972 false))
1973 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1974 }
1975
1976 static void ivb_err_int_handler(struct drm_device *dev)
1977 {
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 u32 err_int = I915_READ(GEN7_ERR_INT);
1980 enum pipe pipe;
1981
1982 if (err_int & ERR_INT_POISON)
1983 DRM_ERROR("Poison interrupt\n");
1984
1985 for_each_pipe(pipe) {
1986 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1987 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1988 false))
1989 DRM_ERROR("Pipe %c FIFO underrun\n",
1990 pipe_name(pipe));
1991 }
1992
1993 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1994 if (IS_IVYBRIDGE(dev))
1995 ivb_pipe_crc_irq_handler(dev, pipe);
1996 else
1997 hsw_pipe_crc_irq_handler(dev, pipe);
1998 }
1999 }
2000
2001 I915_WRITE(GEN7_ERR_INT, err_int);
2002 }
2003
2004 static void cpt_serr_int_handler(struct drm_device *dev)
2005 {
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 u32 serr_int = I915_READ(SERR_INT);
2008
2009 if (serr_int & SERR_INT_POISON)
2010 DRM_ERROR("PCH poison interrupt\n");
2011
2012 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2013 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2014 false))
2015 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2016
2017 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2018 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2019 false))
2020 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2021
2022 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2023 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2024 false))
2025 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2026
2027 I915_WRITE(SERR_INT, serr_int);
2028 }
2029
2030 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2031 {
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033 int pipe;
2034 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2035
2036 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
2037
2038 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2039 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2040 SDE_AUDIO_POWER_SHIFT_CPT);
2041 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2042 port_name(port));
2043 }
2044
2045 if (pch_iir & SDE_AUX_MASK_CPT)
2046 dp_aux_irq_handler(dev);
2047
2048 if (pch_iir & SDE_GMBUS_CPT)
2049 gmbus_irq_handler(dev);
2050
2051 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2052 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2053
2054 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2055 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2056
2057 if (pch_iir & SDE_FDI_MASK_CPT)
2058 for_each_pipe(pipe)
2059 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2060 pipe_name(pipe),
2061 I915_READ(FDI_RX_IIR(pipe)));
2062
2063 if (pch_iir & SDE_ERROR_CPT)
2064 cpt_serr_int_handler(dev);
2065 }
2066
2067 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2068 {
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 enum pipe pipe;
2071
2072 if (de_iir & DE_AUX_CHANNEL_A)
2073 dp_aux_irq_handler(dev);
2074
2075 if (de_iir & DE_GSE)
2076 intel_opregion_asle_intr(dev);
2077
2078 if (de_iir & DE_POISON)
2079 DRM_ERROR("Poison interrupt\n");
2080
2081 for_each_pipe(pipe) {
2082 if (de_iir & DE_PIPE_VBLANK(pipe))
2083 intel_pipe_handle_vblank(dev, pipe);
2084
2085 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2086 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2087 DRM_ERROR("Pipe %c FIFO underrun\n",
2088 pipe_name(pipe));
2089
2090 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2091 i9xx_pipe_crc_irq_handler(dev, pipe);
2092
2093 /* plane/pipes map 1:1 on ilk+ */
2094 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2095 intel_prepare_page_flip(dev, pipe);
2096 intel_finish_page_flip_plane(dev, pipe);
2097 }
2098 }
2099
2100 /* check event from PCH */
2101 if (de_iir & DE_PCH_EVENT) {
2102 u32 pch_iir = I915_READ(SDEIIR);
2103
2104 if (HAS_PCH_CPT(dev))
2105 cpt_irq_handler(dev, pch_iir);
2106 else
2107 ibx_irq_handler(dev, pch_iir);
2108
2109 /* should clear PCH hotplug event before clear CPU irq */
2110 I915_WRITE(SDEIIR, pch_iir);
2111 }
2112
2113 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2114 ironlake_rps_change_irq_handler(dev);
2115 }
2116
2117 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2118 {
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 enum pipe pipe;
2121
2122 if (de_iir & DE_ERR_INT_IVB)
2123 ivb_err_int_handler(dev);
2124
2125 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2126 dp_aux_irq_handler(dev);
2127
2128 if (de_iir & DE_GSE_IVB)
2129 intel_opregion_asle_intr(dev);
2130
2131 for_each_pipe(pipe) {
2132 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2133 intel_pipe_handle_vblank(dev, pipe);
2134
2135 /* plane/pipes map 1:1 on ilk+ */
2136 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2137 intel_prepare_page_flip(dev, pipe);
2138 intel_finish_page_flip_plane(dev, pipe);
2139 }
2140 }
2141
2142 /* check event from PCH */
2143 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2144 u32 pch_iir = I915_READ(SDEIIR);
2145
2146 cpt_irq_handler(dev, pch_iir);
2147
2148 /* clear PCH hotplug event before clear CPU irq */
2149 I915_WRITE(SDEIIR, pch_iir);
2150 }
2151 }
2152
2153 /*
2154 * To handle irqs with the minimum potential races with fresh interrupts, we:
2155 * 1 - Disable Master Interrupt Control.
2156 * 2 - Find the source(s) of the interrupt.
2157 * 3 - Clear the Interrupt Identity bits (IIR).
2158 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2159 * 5 - Re-enable Master Interrupt Control.
2160 */
2161 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2162 {
2163 struct drm_device *dev = arg;
2164 struct drm_i915_private *dev_priv = dev->dev_private;
2165 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2166 irqreturn_t ret = IRQ_NONE;
2167
2168 /* We get interrupts on unclaimed registers, so check for this before we
2169 * do any I915_{READ,WRITE}. */
2170 intel_uncore_check_errors(dev);
2171
2172 /* disable master interrupt before clearing iir */
2173 de_ier = I915_READ(DEIER);
2174 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2175 POSTING_READ(DEIER);
2176
2177 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2178 * interrupts will will be stored on its back queue, and then we'll be
2179 * able to process them after we restore SDEIER (as soon as we restore
2180 * it, we'll get an interrupt if SDEIIR still has something to process
2181 * due to its back queue). */
2182 if (!HAS_PCH_NOP(dev)) {
2183 sde_ier = I915_READ(SDEIER);
2184 I915_WRITE(SDEIER, 0);
2185 POSTING_READ(SDEIER);
2186 }
2187
2188 /* Find, clear, then process each source of interrupt */
2189
2190 gt_iir = I915_READ(GTIIR);
2191 if (gt_iir) {
2192 I915_WRITE(GTIIR, gt_iir);
2193 ret = IRQ_HANDLED;
2194 if (INTEL_INFO(dev)->gen >= 6)
2195 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2196 else
2197 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2198 }
2199
2200 de_iir = I915_READ(DEIIR);
2201 if (de_iir) {
2202 I915_WRITE(DEIIR, de_iir);
2203 ret = IRQ_HANDLED;
2204 if (INTEL_INFO(dev)->gen >= 7)
2205 ivb_display_irq_handler(dev, de_iir);
2206 else
2207 ilk_display_irq_handler(dev, de_iir);
2208 }
2209
2210 if (INTEL_INFO(dev)->gen >= 6) {
2211 u32 pm_iir = I915_READ(GEN6_PMIIR);
2212 if (pm_iir) {
2213 I915_WRITE(GEN6_PMIIR, pm_iir);
2214 ret = IRQ_HANDLED;
2215 gen6_rps_irq_handler(dev_priv, pm_iir);
2216 }
2217 }
2218
2219 I915_WRITE(DEIER, de_ier);
2220 POSTING_READ(DEIER);
2221 if (!HAS_PCH_NOP(dev)) {
2222 I915_WRITE(SDEIER, sde_ier);
2223 POSTING_READ(SDEIER);
2224 }
2225
2226 return ret;
2227 }
2228
2229 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2230 {
2231 struct drm_device *dev = arg;
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 u32 master_ctl;
2234 irqreturn_t ret = IRQ_NONE;
2235 uint32_t tmp = 0;
2236 enum pipe pipe;
2237
2238 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2239 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2240 if (!master_ctl)
2241 return IRQ_NONE;
2242
2243 I915_WRITE(GEN8_MASTER_IRQ, 0);
2244 POSTING_READ(GEN8_MASTER_IRQ);
2245
2246 /* Find, clear, then process each source of interrupt */
2247
2248 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2249
2250 if (master_ctl & GEN8_DE_MISC_IRQ) {
2251 tmp = I915_READ(GEN8_DE_MISC_IIR);
2252 if (tmp) {
2253 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2254 ret = IRQ_HANDLED;
2255 if (tmp & GEN8_DE_MISC_GSE)
2256 intel_opregion_asle_intr(dev);
2257 else
2258 DRM_ERROR("Unexpected DE Misc interrupt\n");
2259 }
2260 else
2261 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2262 }
2263
2264 if (master_ctl & GEN8_DE_PORT_IRQ) {
2265 tmp = I915_READ(GEN8_DE_PORT_IIR);
2266 if (tmp) {
2267 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2268 ret = IRQ_HANDLED;
2269 if (tmp & GEN8_AUX_CHANNEL_A)
2270 dp_aux_irq_handler(dev);
2271 else
2272 DRM_ERROR("Unexpected DE Port interrupt\n");
2273 }
2274 else
2275 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2276 }
2277
2278 for_each_pipe(pipe) {
2279 uint32_t pipe_iir;
2280
2281 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2282 continue;
2283
2284 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2285 if (pipe_iir) {
2286 ret = IRQ_HANDLED;
2287 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2288 if (pipe_iir & GEN8_PIPE_VBLANK)
2289 intel_pipe_handle_vblank(dev, pipe);
2290
2291 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2292 intel_prepare_page_flip(dev, pipe);
2293 intel_finish_page_flip_plane(dev, pipe);
2294 }
2295
2296 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2297 hsw_pipe_crc_irq_handler(dev, pipe);
2298
2299 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2300 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2301 false))
2302 DRM_ERROR("Pipe %c FIFO underrun\n",
2303 pipe_name(pipe));
2304 }
2305
2306 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2307 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2308 pipe_name(pipe),
2309 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2310 }
2311 } else
2312 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2313 }
2314
2315 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2316 /*
2317 * FIXME(BDW): Assume for now that the new interrupt handling
2318 * scheme also closed the SDE interrupt handling race we've seen
2319 * on older pch-split platforms. But this needs testing.
2320 */
2321 u32 pch_iir = I915_READ(SDEIIR);
2322 if (pch_iir) {
2323 I915_WRITE(SDEIIR, pch_iir);
2324 ret = IRQ_HANDLED;
2325 cpt_irq_handler(dev, pch_iir);
2326 } else
2327 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2328
2329 }
2330
2331 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2332 POSTING_READ(GEN8_MASTER_IRQ);
2333
2334 return ret;
2335 }
2336
2337 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2338 bool reset_completed)
2339 {
2340 struct intel_engine_cs *ring;
2341 int i;
2342
2343 /*
2344 * Notify all waiters for GPU completion events that reset state has
2345 * been changed, and that they need to restart their wait after
2346 * checking for potential errors (and bail out to drop locks if there is
2347 * a gpu reset pending so that i915_error_work_func can acquire them).
2348 */
2349
2350 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2351 for_each_ring(ring, dev_priv, i)
2352 wake_up_all(&ring->irq_queue);
2353
2354 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2355 wake_up_all(&dev_priv->pending_flip_queue);
2356
2357 /*
2358 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2359 * reset state is cleared.
2360 */
2361 if (reset_completed)
2362 wake_up_all(&dev_priv->gpu_error.reset_queue);
2363 }
2364
2365 /**
2366 * i915_error_work_func - do process context error handling work
2367 * @work: work struct
2368 *
2369 * Fire an error uevent so userspace can see that a hang or error
2370 * was detected.
2371 */
2372 static void i915_error_work_func(struct work_struct *work)
2373 {
2374 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2375 work);
2376 struct drm_i915_private *dev_priv =
2377 container_of(error, struct drm_i915_private, gpu_error);
2378 struct drm_device *dev = dev_priv->dev;
2379 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2380 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2381 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2382 int ret;
2383
2384 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2385
2386 /*
2387 * Note that there's only one work item which does gpu resets, so we
2388 * need not worry about concurrent gpu resets potentially incrementing
2389 * error->reset_counter twice. We only need to take care of another
2390 * racing irq/hangcheck declaring the gpu dead for a second time. A
2391 * quick check for that is good enough: schedule_work ensures the
2392 * correct ordering between hang detection and this work item, and since
2393 * the reset in-progress bit is only ever set by code outside of this
2394 * work we don't need to worry about any other races.
2395 */
2396 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2397 DRM_DEBUG_DRIVER("resetting chip\n");
2398 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2399 reset_event);
2400
2401 /*
2402 * In most cases it's guaranteed that we get here with an RPM
2403 * reference held, for example because there is a pending GPU
2404 * request that won't finish until the reset is done. This
2405 * isn't the case at least when we get here by doing a
2406 * simulated reset via debugs, so get an RPM reference.
2407 */
2408 intel_runtime_pm_get(dev_priv);
2409 /*
2410 * All state reset _must_ be completed before we update the
2411 * reset counter, for otherwise waiters might miss the reset
2412 * pending state and not properly drop locks, resulting in
2413 * deadlocks with the reset work.
2414 */
2415 ret = i915_reset(dev);
2416
2417 intel_display_handle_reset(dev);
2418
2419 intel_runtime_pm_put(dev_priv);
2420
2421 if (ret == 0) {
2422 /*
2423 * After all the gem state is reset, increment the reset
2424 * counter and wake up everyone waiting for the reset to
2425 * complete.
2426 *
2427 * Since unlock operations are a one-sided barrier only,
2428 * we need to insert a barrier here to order any seqno
2429 * updates before
2430 * the counter increment.
2431 */
2432 smp_mb__before_atomic();
2433 atomic_inc(&dev_priv->gpu_error.reset_counter);
2434
2435 kobject_uevent_env(&dev->primary->kdev->kobj,
2436 KOBJ_CHANGE, reset_done_event);
2437 } else {
2438 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2439 }
2440
2441 /*
2442 * Note: The wake_up also serves as a memory barrier so that
2443 * waiters see the update value of the reset counter atomic_t.
2444 */
2445 i915_error_wake_up(dev_priv, true);
2446 }
2447 }
2448
2449 static void i915_report_and_clear_eir(struct drm_device *dev)
2450 {
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452 uint32_t instdone[I915_NUM_INSTDONE_REG];
2453 u32 eir = I915_READ(EIR);
2454 int pipe, i;
2455
2456 if (!eir)
2457 return;
2458
2459 pr_err("render error detected, EIR: 0x%08x\n", eir);
2460
2461 i915_get_extra_instdone(dev, instdone);
2462
2463 if (IS_G4X(dev)) {
2464 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2465 u32 ipeir = I915_READ(IPEIR_I965);
2466
2467 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2468 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2469 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2470 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2471 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2472 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2473 I915_WRITE(IPEIR_I965, ipeir);
2474 POSTING_READ(IPEIR_I965);
2475 }
2476 if (eir & GM45_ERROR_PAGE_TABLE) {
2477 u32 pgtbl_err = I915_READ(PGTBL_ER);
2478 pr_err("page table error\n");
2479 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2480 I915_WRITE(PGTBL_ER, pgtbl_err);
2481 POSTING_READ(PGTBL_ER);
2482 }
2483 }
2484
2485 if (!IS_GEN2(dev)) {
2486 if (eir & I915_ERROR_PAGE_TABLE) {
2487 u32 pgtbl_err = I915_READ(PGTBL_ER);
2488 pr_err("page table error\n");
2489 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2490 I915_WRITE(PGTBL_ER, pgtbl_err);
2491 POSTING_READ(PGTBL_ER);
2492 }
2493 }
2494
2495 if (eir & I915_ERROR_MEMORY_REFRESH) {
2496 pr_err("memory refresh error:\n");
2497 for_each_pipe(pipe)
2498 pr_err("pipe %c stat: 0x%08x\n",
2499 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2500 /* pipestat has already been acked */
2501 }
2502 if (eir & I915_ERROR_INSTRUCTION) {
2503 pr_err("instruction error\n");
2504 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2505 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2506 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2507 if (INTEL_INFO(dev)->gen < 4) {
2508 u32 ipeir = I915_READ(IPEIR);
2509
2510 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2511 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2512 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2513 I915_WRITE(IPEIR, ipeir);
2514 POSTING_READ(IPEIR);
2515 } else {
2516 u32 ipeir = I915_READ(IPEIR_I965);
2517
2518 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2519 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2520 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2521 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2522 I915_WRITE(IPEIR_I965, ipeir);
2523 POSTING_READ(IPEIR_I965);
2524 }
2525 }
2526
2527 I915_WRITE(EIR, eir);
2528 POSTING_READ(EIR);
2529 eir = I915_READ(EIR);
2530 if (eir) {
2531 /*
2532 * some errors might have become stuck,
2533 * mask them.
2534 */
2535 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2536 I915_WRITE(EMR, I915_READ(EMR) | eir);
2537 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2538 }
2539 }
2540
2541 /**
2542 * i915_handle_error - handle an error interrupt
2543 * @dev: drm device
2544 *
2545 * Do some basic checking of regsiter state at error interrupt time and
2546 * dump it to the syslog. Also call i915_capture_error_state() to make
2547 * sure we get a record and make it available in debugfs. Fire a uevent
2548 * so userspace knows something bad happened (should trigger collection
2549 * of a ring dump etc.).
2550 */
2551 void i915_handle_error(struct drm_device *dev, bool wedged,
2552 const char *fmt, ...)
2553 {
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 va_list args;
2556 char error_msg[80];
2557
2558 va_start(args, fmt);
2559 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2560 va_end(args);
2561
2562 i915_capture_error_state(dev, wedged, error_msg);
2563 i915_report_and_clear_eir(dev);
2564
2565 if (wedged) {
2566 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2567 &dev_priv->gpu_error.reset_counter);
2568
2569 /*
2570 * Wakeup waiting processes so that the reset work function
2571 * i915_error_work_func doesn't deadlock trying to grab various
2572 * locks. By bumping the reset counter first, the woken
2573 * processes will see a reset in progress and back off,
2574 * releasing their locks and then wait for the reset completion.
2575 * We must do this for _all_ gpu waiters that might hold locks
2576 * that the reset work needs to acquire.
2577 *
2578 * Note: The wake_up serves as the required memory barrier to
2579 * ensure that the waiters see the updated value of the reset
2580 * counter atomic_t.
2581 */
2582 i915_error_wake_up(dev_priv, false);
2583 }
2584
2585 /*
2586 * Our reset work can grab modeset locks (since it needs to reset the
2587 * state of outstanding pagelips). Hence it must not be run on our own
2588 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2589 * code will deadlock.
2590 */
2591 schedule_work(&dev_priv->gpu_error.work);
2592 }
2593
2594 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2595 {
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 struct drm_i915_gem_object *obj;
2600 struct intel_unpin_work *work;
2601 unsigned long flags;
2602 bool stall_detected;
2603
2604 /* Ignore early vblank irqs */
2605 if (intel_crtc == NULL)
2606 return;
2607
2608 spin_lock_irqsave(&dev->event_lock, flags);
2609 work = intel_crtc->unpin_work;
2610
2611 if (work == NULL ||
2612 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2613 !work->enable_stall_check) {
2614 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2615 spin_unlock_irqrestore(&dev->event_lock, flags);
2616 return;
2617 }
2618
2619 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2620 obj = work->pending_flip_obj;
2621 if (INTEL_INFO(dev)->gen >= 4) {
2622 int dspsurf = DSPSURF(intel_crtc->plane);
2623 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2624 i915_gem_obj_ggtt_offset(obj);
2625 } else {
2626 int dspaddr = DSPADDR(intel_crtc->plane);
2627 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2628 crtc->y * crtc->primary->fb->pitches[0] +
2629 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2630 }
2631
2632 spin_unlock_irqrestore(&dev->event_lock, flags);
2633
2634 if (stall_detected) {
2635 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2636 intel_prepare_page_flip(dev, intel_crtc->plane);
2637 }
2638 }
2639
2640 /* Called from drm generic code, passed 'crtc' which
2641 * we use as a pipe index
2642 */
2643 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2644 {
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 unsigned long irqflags;
2647
2648 if (!i915_pipe_enabled(dev, pipe))
2649 return -EINVAL;
2650
2651 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2652 if (INTEL_INFO(dev)->gen >= 4)
2653 i915_enable_pipestat(dev_priv, pipe,
2654 PIPE_START_VBLANK_INTERRUPT_STATUS);
2655 else
2656 i915_enable_pipestat(dev_priv, pipe,
2657 PIPE_VBLANK_INTERRUPT_STATUS);
2658 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2659
2660 return 0;
2661 }
2662
2663 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2664 {
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 unsigned long irqflags;
2667 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2668 DE_PIPE_VBLANK(pipe);
2669
2670 if (!i915_pipe_enabled(dev, pipe))
2671 return -EINVAL;
2672
2673 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2674 ironlake_enable_display_irq(dev_priv, bit);
2675 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2676
2677 return 0;
2678 }
2679
2680 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2681 {
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 unsigned long irqflags;
2684
2685 if (!i915_pipe_enabled(dev, pipe))
2686 return -EINVAL;
2687
2688 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2689 i915_enable_pipestat(dev_priv, pipe,
2690 PIPE_START_VBLANK_INTERRUPT_STATUS);
2691 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2692
2693 return 0;
2694 }
2695
2696 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2697 {
2698 struct drm_i915_private *dev_priv = dev->dev_private;
2699 unsigned long irqflags;
2700
2701 if (!i915_pipe_enabled(dev, pipe))
2702 return -EINVAL;
2703
2704 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2705 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2706 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2707 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2708 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2709 return 0;
2710 }
2711
2712 /* Called from drm generic code, passed 'crtc' which
2713 * we use as a pipe index
2714 */
2715 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2716 {
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 unsigned long irqflags;
2719
2720 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2721 i915_disable_pipestat(dev_priv, pipe,
2722 PIPE_VBLANK_INTERRUPT_STATUS |
2723 PIPE_START_VBLANK_INTERRUPT_STATUS);
2724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2725 }
2726
2727 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2728 {
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 unsigned long irqflags;
2731 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2732 DE_PIPE_VBLANK(pipe);
2733
2734 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2735 ironlake_disable_display_irq(dev_priv, bit);
2736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2737 }
2738
2739 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2740 {
2741 struct drm_i915_private *dev_priv = dev->dev_private;
2742 unsigned long irqflags;
2743
2744 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2745 i915_disable_pipestat(dev_priv, pipe,
2746 PIPE_START_VBLANK_INTERRUPT_STATUS);
2747 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2748 }
2749
2750 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2751 {
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 unsigned long irqflags;
2754
2755 if (!i915_pipe_enabled(dev, pipe))
2756 return;
2757
2758 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2759 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2760 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2761 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2762 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2763 }
2764
2765 static u32
2766 ring_last_seqno(struct intel_engine_cs *ring)
2767 {
2768 return list_entry(ring->request_list.prev,
2769 struct drm_i915_gem_request, list)->seqno;
2770 }
2771
2772 static bool
2773 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2774 {
2775 return (list_empty(&ring->request_list) ||
2776 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2777 }
2778
2779 static bool
2780 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2781 {
2782 if (INTEL_INFO(dev)->gen >= 8) {
2783 /*
2784 * FIXME: gen8 semaphore support - currently we don't emit
2785 * semaphores on bdw anyway, but this needs to be addressed when
2786 * we merge that code.
2787 */
2788 return false;
2789 } else {
2790 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2791 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2792 MI_SEMAPHORE_REGISTER);
2793 }
2794 }
2795
2796 static struct intel_engine_cs *
2797 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
2798 {
2799 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2800 struct intel_engine_cs *signaller;
2801 int i;
2802
2803 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2804 /*
2805 * FIXME: gen8 semaphore support - currently we don't emit
2806 * semaphores on bdw anyway, but this needs to be addressed when
2807 * we merge that code.
2808 */
2809 return NULL;
2810 } else {
2811 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2812
2813 for_each_ring(signaller, dev_priv, i) {
2814 if(ring == signaller)
2815 continue;
2816
2817 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2818 return signaller;
2819 }
2820 }
2821
2822 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2823 ring->id, ipehr);
2824
2825 return NULL;
2826 }
2827
2828 static struct intel_engine_cs *
2829 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2830 {
2831 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2832 u32 cmd, ipehr, head;
2833 int i;
2834
2835 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2836 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2837 return NULL;
2838
2839 /*
2840 * HEAD is likely pointing to the dword after the actual command,
2841 * so scan backwards until we find the MBOX. But limit it to just 3
2842 * dwords. Note that we don't care about ACTHD here since that might
2843 * point at at batch, and semaphores are always emitted into the
2844 * ringbuffer itself.
2845 */
2846 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2847
2848 for (i = 4; i; --i) {
2849 /*
2850 * Be paranoid and presume the hw has gone off into the wild -
2851 * our ring is smaller than what the hardware (and hence
2852 * HEAD_ADDR) allows. Also handles wrap-around.
2853 */
2854 head &= ring->buffer->size - 1;
2855
2856 /* This here seems to blow up */
2857 cmd = ioread32(ring->buffer->virtual_start + head);
2858 if (cmd == ipehr)
2859 break;
2860
2861 head -= 4;
2862 }
2863
2864 if (!i)
2865 return NULL;
2866
2867 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2868 return semaphore_wait_to_signaller_ring(ring, ipehr);
2869 }
2870
2871 static int semaphore_passed(struct intel_engine_cs *ring)
2872 {
2873 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2874 struct intel_engine_cs *signaller;
2875 u32 seqno, ctl;
2876
2877 ring->hangcheck.deadlock++;
2878
2879 signaller = semaphore_waits_for(ring, &seqno);
2880 if (signaller == NULL)
2881 return -1;
2882
2883 /* Prevent pathological recursion due to driver bugs */
2884 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2885 return -1;
2886
2887 /* cursory check for an unkickable deadlock */
2888 ctl = I915_READ_CTL(signaller);
2889 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2890 return -1;
2891
2892 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2893 return 1;
2894
2895 if (signaller->hangcheck.deadlock)
2896 return -1;
2897
2898 return 0;
2899 }
2900
2901 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2902 {
2903 struct intel_engine_cs *ring;
2904 int i;
2905
2906 for_each_ring(ring, dev_priv, i)
2907 ring->hangcheck.deadlock = 0;
2908 }
2909
2910 static enum intel_ring_hangcheck_action
2911 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2912 {
2913 struct drm_device *dev = ring->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 tmp;
2916
2917 if (ring->hangcheck.acthd != acthd)
2918 return HANGCHECK_ACTIVE;
2919
2920 if (IS_GEN2(dev))
2921 return HANGCHECK_HUNG;
2922
2923 /* Is the chip hanging on a WAIT_FOR_EVENT?
2924 * If so we can simply poke the RB_WAIT bit
2925 * and break the hang. This should work on
2926 * all but the second generation chipsets.
2927 */
2928 tmp = I915_READ_CTL(ring);
2929 if (tmp & RING_WAIT) {
2930 i915_handle_error(dev, false,
2931 "Kicking stuck wait on %s",
2932 ring->name);
2933 I915_WRITE_CTL(ring, tmp);
2934 return HANGCHECK_KICK;
2935 }
2936
2937 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2938 switch (semaphore_passed(ring)) {
2939 default:
2940 return HANGCHECK_HUNG;
2941 case 1:
2942 i915_handle_error(dev, false,
2943 "Kicking stuck semaphore on %s",
2944 ring->name);
2945 I915_WRITE_CTL(ring, tmp);
2946 return HANGCHECK_KICK;
2947 case 0:
2948 return HANGCHECK_WAIT;
2949 }
2950 }
2951
2952 return HANGCHECK_HUNG;
2953 }
2954
2955 /**
2956 * This is called when the chip hasn't reported back with completed
2957 * batchbuffers in a long time. We keep track per ring seqno progress and
2958 * if there are no progress, hangcheck score for that ring is increased.
2959 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2960 * we kick the ring. If we see no progress on three subsequent calls
2961 * we assume chip is wedged and try to fix it by resetting the chip.
2962 */
2963 static void i915_hangcheck_elapsed(unsigned long data)
2964 {
2965 struct drm_device *dev = (struct drm_device *)data;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967 struct intel_engine_cs *ring;
2968 int i;
2969 int busy_count = 0, rings_hung = 0;
2970 bool stuck[I915_NUM_RINGS] = { 0 };
2971 #define BUSY 1
2972 #define KICK 5
2973 #define HUNG 20
2974
2975 if (!i915.enable_hangcheck)
2976 return;
2977
2978 for_each_ring(ring, dev_priv, i) {
2979 u64 acthd;
2980 u32 seqno;
2981 bool busy = true;
2982
2983 semaphore_clear_deadlocks(dev_priv);
2984
2985 seqno = ring->get_seqno(ring, false);
2986 acthd = intel_ring_get_active_head(ring);
2987
2988 if (ring->hangcheck.seqno == seqno) {
2989 if (ring_idle(ring, seqno)) {
2990 ring->hangcheck.action = HANGCHECK_IDLE;
2991
2992 if (waitqueue_active(&ring->irq_queue)) {
2993 /* Issue a wake-up to catch stuck h/w. */
2994 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2995 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2996 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2997 ring->name);
2998 else
2999 DRM_INFO("Fake missed irq on %s\n",
3000 ring->name);
3001 wake_up_all(&ring->irq_queue);
3002 }
3003 /* Safeguard against driver failure */
3004 ring->hangcheck.score += BUSY;
3005 } else
3006 busy = false;
3007 } else {
3008 /* We always increment the hangcheck score
3009 * if the ring is busy and still processing
3010 * the same request, so that no single request
3011 * can run indefinitely (such as a chain of
3012 * batches). The only time we do not increment
3013 * the hangcheck score on this ring, if this
3014 * ring is in a legitimate wait for another
3015 * ring. In that case the waiting ring is a
3016 * victim and we want to be sure we catch the
3017 * right culprit. Then every time we do kick
3018 * the ring, add a small increment to the
3019 * score so that we can catch a batch that is
3020 * being repeatedly kicked and so responsible
3021 * for stalling the machine.
3022 */
3023 ring->hangcheck.action = ring_stuck(ring,
3024 acthd);
3025
3026 switch (ring->hangcheck.action) {
3027 case HANGCHECK_IDLE:
3028 case HANGCHECK_WAIT:
3029 break;
3030 case HANGCHECK_ACTIVE:
3031 ring->hangcheck.score += BUSY;
3032 break;
3033 case HANGCHECK_KICK:
3034 ring->hangcheck.score += KICK;
3035 break;
3036 case HANGCHECK_HUNG:
3037 ring->hangcheck.score += HUNG;
3038 stuck[i] = true;
3039 break;
3040 }
3041 }
3042 } else {
3043 ring->hangcheck.action = HANGCHECK_ACTIVE;
3044
3045 /* Gradually reduce the count so that we catch DoS
3046 * attempts across multiple batches.
3047 */
3048 if (ring->hangcheck.score > 0)
3049 ring->hangcheck.score--;
3050 }
3051
3052 ring->hangcheck.seqno = seqno;
3053 ring->hangcheck.acthd = acthd;
3054 busy_count += busy;
3055 }
3056
3057 for_each_ring(ring, dev_priv, i) {
3058 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3059 DRM_INFO("%s on %s\n",
3060 stuck[i] ? "stuck" : "no progress",
3061 ring->name);
3062 rings_hung++;
3063 }
3064 }
3065
3066 if (rings_hung)
3067 return i915_handle_error(dev, true, "Ring hung");
3068
3069 if (busy_count)
3070 /* Reset timer case chip hangs without another request
3071 * being added */
3072 i915_queue_hangcheck(dev);
3073 }
3074
3075 void i915_queue_hangcheck(struct drm_device *dev)
3076 {
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 if (!i915.enable_hangcheck)
3079 return;
3080
3081 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3082 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3083 }
3084
3085 static void ibx_irq_reset(struct drm_device *dev)
3086 {
3087 struct drm_i915_private *dev_priv = dev->dev_private;
3088
3089 if (HAS_PCH_NOP(dev))
3090 return;
3091
3092 GEN5_IRQ_RESET(SDE);
3093
3094 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3095 I915_WRITE(SERR_INT, 0xffffffff);
3096 }
3097
3098 /*
3099 * SDEIER is also touched by the interrupt handler to work around missed PCH
3100 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3101 * instead we unconditionally enable all PCH interrupt sources here, but then
3102 * only unmask them as needed with SDEIMR.
3103 *
3104 * This function needs to be called before interrupts are enabled.
3105 */
3106 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3107 {
3108 struct drm_i915_private *dev_priv = dev->dev_private;
3109
3110 if (HAS_PCH_NOP(dev))
3111 return;
3112
3113 WARN_ON(I915_READ(SDEIER) != 0);
3114 I915_WRITE(SDEIER, 0xffffffff);
3115 POSTING_READ(SDEIER);
3116 }
3117
3118 static void gen5_gt_irq_reset(struct drm_device *dev)
3119 {
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121
3122 GEN5_IRQ_RESET(GT);
3123 if (INTEL_INFO(dev)->gen >= 6)
3124 GEN5_IRQ_RESET(GEN6_PM);
3125 }
3126
3127 /* drm_dma.h hooks
3128 */
3129 static void ironlake_irq_reset(struct drm_device *dev)
3130 {
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132
3133 I915_WRITE(HWSTAM, 0xffffffff);
3134
3135 GEN5_IRQ_RESET(DE);
3136 if (IS_GEN7(dev))
3137 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3138
3139 gen5_gt_irq_reset(dev);
3140
3141 ibx_irq_reset(dev);
3142 }
3143
3144 static void valleyview_irq_preinstall(struct drm_device *dev)
3145 {
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int pipe;
3148
3149 /* VLV magic */
3150 I915_WRITE(VLV_IMR, 0);
3151 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3152 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3153 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3154
3155 /* and GT */
3156 I915_WRITE(GTIIR, I915_READ(GTIIR));
3157 I915_WRITE(GTIIR, I915_READ(GTIIR));
3158
3159 gen5_gt_irq_reset(dev);
3160
3161 I915_WRITE(DPINVGTT, 0xff);
3162
3163 I915_WRITE(PORT_HOTPLUG_EN, 0);
3164 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3165 for_each_pipe(pipe)
3166 I915_WRITE(PIPESTAT(pipe), 0xffff);
3167 I915_WRITE(VLV_IIR, 0xffffffff);
3168 I915_WRITE(VLV_IMR, 0xffffffff);
3169 I915_WRITE(VLV_IER, 0x0);
3170 POSTING_READ(VLV_IER);
3171 }
3172
3173 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3174 {
3175 GEN8_IRQ_RESET_NDX(GT, 0);
3176 GEN8_IRQ_RESET_NDX(GT, 1);
3177 GEN8_IRQ_RESET_NDX(GT, 2);
3178 GEN8_IRQ_RESET_NDX(GT, 3);
3179 }
3180
3181 static void gen8_irq_reset(struct drm_device *dev)
3182 {
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184 int pipe;
3185
3186 I915_WRITE(GEN8_MASTER_IRQ, 0);
3187 POSTING_READ(GEN8_MASTER_IRQ);
3188
3189 gen8_gt_irq_reset(dev_priv);
3190
3191 for_each_pipe(pipe)
3192 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3193
3194 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3195 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3196 GEN5_IRQ_RESET(GEN8_PCU_);
3197
3198 ibx_irq_reset(dev);
3199 }
3200
3201 static void cherryview_irq_preinstall(struct drm_device *dev)
3202 {
3203 struct drm_i915_private *dev_priv = dev->dev_private;
3204 int pipe;
3205
3206 I915_WRITE(GEN8_MASTER_IRQ, 0);
3207 POSTING_READ(GEN8_MASTER_IRQ);
3208
3209 gen8_gt_irq_reset(dev_priv);
3210
3211 GEN5_IRQ_RESET(GEN8_PCU_);
3212
3213 POSTING_READ(GEN8_PCU_IIR);
3214
3215 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3216
3217 I915_WRITE(PORT_HOTPLUG_EN, 0);
3218 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3219
3220 for_each_pipe(pipe)
3221 I915_WRITE(PIPESTAT(pipe), 0xffff);
3222
3223 I915_WRITE(VLV_IMR, 0xffffffff);
3224 I915_WRITE(VLV_IER, 0x0);
3225 I915_WRITE(VLV_IIR, 0xffffffff);
3226 POSTING_READ(VLV_IIR);
3227 }
3228
3229 static void ibx_hpd_irq_setup(struct drm_device *dev)
3230 {
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 struct drm_mode_config *mode_config = &dev->mode_config;
3233 struct intel_encoder *intel_encoder;
3234 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3235
3236 if (HAS_PCH_IBX(dev)) {
3237 hotplug_irqs = SDE_HOTPLUG_MASK;
3238 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3239 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3240 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3241 } else {
3242 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3243 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3244 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3245 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3246 }
3247
3248 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3249
3250 /*
3251 * Enable digital hotplug on the PCH, and configure the DP short pulse
3252 * duration to 2ms (which is the minimum in the Display Port spec)
3253 *
3254 * This register is the same on all known PCH chips.
3255 */
3256 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3257 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3258 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3259 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3260 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3261 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3262 }
3263
3264 static void ibx_irq_postinstall(struct drm_device *dev)
3265 {
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 u32 mask;
3268
3269 if (HAS_PCH_NOP(dev))
3270 return;
3271
3272 if (HAS_PCH_IBX(dev))
3273 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3274 else
3275 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3276
3277 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3278 I915_WRITE(SDEIMR, ~mask);
3279 }
3280
3281 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3282 {
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 u32 pm_irqs, gt_irqs;
3285
3286 pm_irqs = gt_irqs = 0;
3287
3288 dev_priv->gt_irq_mask = ~0;
3289 if (HAS_L3_DPF(dev)) {
3290 /* L3 parity interrupt is always unmasked. */
3291 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3292 gt_irqs |= GT_PARITY_ERROR(dev);
3293 }
3294
3295 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3296 if (IS_GEN5(dev)) {
3297 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3298 ILK_BSD_USER_INTERRUPT;
3299 } else {
3300 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3301 }
3302
3303 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3304
3305 if (INTEL_INFO(dev)->gen >= 6) {
3306 pm_irqs |= dev_priv->pm_rps_events;
3307
3308 if (HAS_VEBOX(dev))
3309 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3310
3311 dev_priv->pm_irq_mask = 0xffffffff;
3312 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3313 }
3314 }
3315
3316 static int ironlake_irq_postinstall(struct drm_device *dev)
3317 {
3318 unsigned long irqflags;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 u32 display_mask, extra_mask;
3321
3322 if (INTEL_INFO(dev)->gen >= 7) {
3323 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3324 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3325 DE_PLANEB_FLIP_DONE_IVB |
3326 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3327 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3328 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3329 } else {
3330 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3331 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3332 DE_AUX_CHANNEL_A |
3333 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3334 DE_POISON);
3335 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3336 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3337 }
3338
3339 dev_priv->irq_mask = ~display_mask;
3340
3341 I915_WRITE(HWSTAM, 0xeffe);
3342
3343 ibx_irq_pre_postinstall(dev);
3344
3345 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3346
3347 gen5_gt_irq_postinstall(dev);
3348
3349 ibx_irq_postinstall(dev);
3350
3351 if (IS_IRONLAKE_M(dev)) {
3352 /* Enable PCU event interrupts
3353 *
3354 * spinlocking not required here for correctness since interrupt
3355 * setup is guaranteed to run in single-threaded context. But we
3356 * need it to make the assert_spin_locked happy. */
3357 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3358 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3359 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3360 }
3361
3362 return 0;
3363 }
3364
3365 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3366 {
3367 u32 pipestat_mask;
3368 u32 iir_mask;
3369
3370 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3371 PIPE_FIFO_UNDERRUN_STATUS;
3372
3373 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3374 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3375 POSTING_READ(PIPESTAT(PIPE_A));
3376
3377 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3378 PIPE_CRC_DONE_INTERRUPT_STATUS;
3379
3380 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3381 PIPE_GMBUS_INTERRUPT_STATUS);
3382 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3383
3384 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3385 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3386 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3387 dev_priv->irq_mask &= ~iir_mask;
3388
3389 I915_WRITE(VLV_IIR, iir_mask);
3390 I915_WRITE(VLV_IIR, iir_mask);
3391 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3392 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3393 POSTING_READ(VLV_IER);
3394 }
3395
3396 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3397 {
3398 u32 pipestat_mask;
3399 u32 iir_mask;
3400
3401 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3402 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3403 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3404
3405 dev_priv->irq_mask |= iir_mask;
3406 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3407 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3408 I915_WRITE(VLV_IIR, iir_mask);
3409 I915_WRITE(VLV_IIR, iir_mask);
3410 POSTING_READ(VLV_IIR);
3411
3412 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3413 PIPE_CRC_DONE_INTERRUPT_STATUS;
3414
3415 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3416 PIPE_GMBUS_INTERRUPT_STATUS);
3417 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3418
3419 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3420 PIPE_FIFO_UNDERRUN_STATUS;
3421 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3422 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3423 POSTING_READ(PIPESTAT(PIPE_A));
3424 }
3425
3426 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3427 {
3428 assert_spin_locked(&dev_priv->irq_lock);
3429
3430 if (dev_priv->display_irqs_enabled)
3431 return;
3432
3433 dev_priv->display_irqs_enabled = true;
3434
3435 if (dev_priv->dev->irq_enabled)
3436 valleyview_display_irqs_install(dev_priv);
3437 }
3438
3439 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3440 {
3441 assert_spin_locked(&dev_priv->irq_lock);
3442
3443 if (!dev_priv->display_irqs_enabled)
3444 return;
3445
3446 dev_priv->display_irqs_enabled = false;
3447
3448 if (dev_priv->dev->irq_enabled)
3449 valleyview_display_irqs_uninstall(dev_priv);
3450 }
3451
3452 static int valleyview_irq_postinstall(struct drm_device *dev)
3453 {
3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455 unsigned long irqflags;
3456
3457 dev_priv->irq_mask = ~0;
3458
3459 I915_WRITE(PORT_HOTPLUG_EN, 0);
3460 POSTING_READ(PORT_HOTPLUG_EN);
3461
3462 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3463 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3464 I915_WRITE(VLV_IIR, 0xffffffff);
3465 POSTING_READ(VLV_IER);
3466
3467 /* Interrupt setup is already guaranteed to be single-threaded, this is
3468 * just to make the assert_spin_locked check happy. */
3469 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3470 if (dev_priv->display_irqs_enabled)
3471 valleyview_display_irqs_install(dev_priv);
3472 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3473
3474 I915_WRITE(VLV_IIR, 0xffffffff);
3475 I915_WRITE(VLV_IIR, 0xffffffff);
3476
3477 gen5_gt_irq_postinstall(dev);
3478
3479 /* ack & enable invalid PTE error interrupts */
3480 #if 0 /* FIXME: add support to irq handler for checking these bits */
3481 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3482 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3483 #endif
3484
3485 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3486
3487 return 0;
3488 }
3489
3490 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3491 {
3492 int i;
3493
3494 /* These are interrupts we'll toggle with the ring mask register */
3495 uint32_t gt_interrupts[] = {
3496 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3497 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3498 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3499 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3500 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3501 0,
3502 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3503 };
3504
3505 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3506 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3507
3508 dev_priv->pm_irq_mask = 0xffffffff;
3509 }
3510
3511 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3512 {
3513 struct drm_device *dev = dev_priv->dev;
3514 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3515 GEN8_PIPE_CDCLK_CRC_DONE |
3516 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3517 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3518 GEN8_PIPE_FIFO_UNDERRUN;
3519 int pipe;
3520 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3521 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3522 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3523
3524 for_each_pipe(pipe)
3525 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3526 de_pipe_enables);
3527
3528 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3529 }
3530
3531 static int gen8_irq_postinstall(struct drm_device *dev)
3532 {
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534
3535 ibx_irq_pre_postinstall(dev);
3536
3537 gen8_gt_irq_postinstall(dev_priv);
3538 gen8_de_irq_postinstall(dev_priv);
3539
3540 ibx_irq_postinstall(dev);
3541
3542 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3543 POSTING_READ(GEN8_MASTER_IRQ);
3544
3545 return 0;
3546 }
3547
3548 static int cherryview_irq_postinstall(struct drm_device *dev)
3549 {
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3552 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3553 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3554 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3555 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3556 PIPE_CRC_DONE_INTERRUPT_STATUS;
3557 unsigned long irqflags;
3558 int pipe;
3559
3560 /*
3561 * Leave vblank interrupts masked initially. enable/disable will
3562 * toggle them based on usage.
3563 */
3564 dev_priv->irq_mask = ~enable_mask;
3565
3566 for_each_pipe(pipe)
3567 I915_WRITE(PIPESTAT(pipe), 0xffff);
3568
3569 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3570 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3571 for_each_pipe(pipe)
3572 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3573 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3574
3575 I915_WRITE(VLV_IIR, 0xffffffff);
3576 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3577 I915_WRITE(VLV_IER, enable_mask);
3578
3579 gen8_gt_irq_postinstall(dev_priv);
3580
3581 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3582 POSTING_READ(GEN8_MASTER_IRQ);
3583
3584 return 0;
3585 }
3586
3587 static void gen8_irq_uninstall(struct drm_device *dev)
3588 {
3589 struct drm_i915_private *dev_priv = dev->dev_private;
3590
3591 if (!dev_priv)
3592 return;
3593
3594 intel_hpd_irq_uninstall(dev_priv);
3595
3596 gen8_irq_reset(dev);
3597 }
3598
3599 static void valleyview_irq_uninstall(struct drm_device *dev)
3600 {
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 unsigned long irqflags;
3603 int pipe;
3604
3605 if (!dev_priv)
3606 return;
3607
3608 I915_WRITE(VLV_MASTER_IER, 0);
3609
3610 intel_hpd_irq_uninstall(dev_priv);
3611
3612 for_each_pipe(pipe)
3613 I915_WRITE(PIPESTAT(pipe), 0xffff);
3614
3615 I915_WRITE(HWSTAM, 0xffffffff);
3616 I915_WRITE(PORT_HOTPLUG_EN, 0);
3617 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3618
3619 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3620 if (dev_priv->display_irqs_enabled)
3621 valleyview_display_irqs_uninstall(dev_priv);
3622 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3623
3624 dev_priv->irq_mask = 0;
3625
3626 I915_WRITE(VLV_IIR, 0xffffffff);
3627 I915_WRITE(VLV_IMR, 0xffffffff);
3628 I915_WRITE(VLV_IER, 0x0);
3629 POSTING_READ(VLV_IER);
3630 }
3631
3632 static void cherryview_irq_uninstall(struct drm_device *dev)
3633 {
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 int pipe;
3636
3637 if (!dev_priv)
3638 return;
3639
3640 I915_WRITE(GEN8_MASTER_IRQ, 0);
3641 POSTING_READ(GEN8_MASTER_IRQ);
3642
3643 #define GEN8_IRQ_FINI_NDX(type, which) \
3644 do { \
3645 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3646 I915_WRITE(GEN8_##type##_IER(which), 0); \
3647 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3648 POSTING_READ(GEN8_##type##_IIR(which)); \
3649 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3650 } while (0)
3651
3652 #define GEN8_IRQ_FINI(type) \
3653 do { \
3654 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3655 I915_WRITE(GEN8_##type##_IER, 0); \
3656 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3657 POSTING_READ(GEN8_##type##_IIR); \
3658 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3659 } while (0)
3660
3661 GEN8_IRQ_FINI_NDX(GT, 0);
3662 GEN8_IRQ_FINI_NDX(GT, 1);
3663 GEN8_IRQ_FINI_NDX(GT, 2);
3664 GEN8_IRQ_FINI_NDX(GT, 3);
3665
3666 GEN8_IRQ_FINI(PCU);
3667
3668 #undef GEN8_IRQ_FINI
3669 #undef GEN8_IRQ_FINI_NDX
3670
3671 I915_WRITE(PORT_HOTPLUG_EN, 0);
3672 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3673
3674 for_each_pipe(pipe)
3675 I915_WRITE(PIPESTAT(pipe), 0xffff);
3676
3677 I915_WRITE(VLV_IMR, 0xffffffff);
3678 I915_WRITE(VLV_IER, 0x0);
3679 I915_WRITE(VLV_IIR, 0xffffffff);
3680 POSTING_READ(VLV_IIR);
3681 }
3682
3683 static void ironlake_irq_uninstall(struct drm_device *dev)
3684 {
3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686
3687 if (!dev_priv)
3688 return;
3689
3690 intel_hpd_irq_uninstall(dev_priv);
3691
3692 ironlake_irq_reset(dev);
3693 }
3694
3695 static void i8xx_irq_preinstall(struct drm_device * dev)
3696 {
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698 int pipe;
3699
3700 for_each_pipe(pipe)
3701 I915_WRITE(PIPESTAT(pipe), 0);
3702 I915_WRITE16(IMR, 0xffff);
3703 I915_WRITE16(IER, 0x0);
3704 POSTING_READ16(IER);
3705 }
3706
3707 static int i8xx_irq_postinstall(struct drm_device *dev)
3708 {
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710 unsigned long irqflags;
3711
3712 I915_WRITE16(EMR,
3713 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3714
3715 /* Unmask the interrupts that we always want on. */
3716 dev_priv->irq_mask =
3717 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3718 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3719 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3720 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3721 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3722 I915_WRITE16(IMR, dev_priv->irq_mask);
3723
3724 I915_WRITE16(IER,
3725 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3726 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3727 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3728 I915_USER_INTERRUPT);
3729 POSTING_READ16(IER);
3730
3731 /* Interrupt setup is already guaranteed to be single-threaded, this is
3732 * just to make the assert_spin_locked check happy. */
3733 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3734 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3735 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3737
3738 return 0;
3739 }
3740
3741 /*
3742 * Returns true when a page flip has completed.
3743 */
3744 static bool i8xx_handle_vblank(struct drm_device *dev,
3745 int plane, int pipe, u32 iir)
3746 {
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3749
3750 if (!intel_pipe_handle_vblank(dev, pipe))
3751 return false;
3752
3753 if ((iir & flip_pending) == 0)
3754 return false;
3755
3756 intel_prepare_page_flip(dev, plane);
3757
3758 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3759 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3760 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3761 * the flip is completed (no longer pending). Since this doesn't raise
3762 * an interrupt per se, we watch for the change at vblank.
3763 */
3764 if (I915_READ16(ISR) & flip_pending)
3765 return false;
3766
3767 intel_finish_page_flip(dev, pipe);
3768
3769 return true;
3770 }
3771
3772 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3773 {
3774 struct drm_device *dev = arg;
3775 struct drm_i915_private *dev_priv = dev->dev_private;
3776 u16 iir, new_iir;
3777 u32 pipe_stats[2];
3778 unsigned long irqflags;
3779 int pipe;
3780 u16 flip_mask =
3781 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3782 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3783
3784 iir = I915_READ16(IIR);
3785 if (iir == 0)
3786 return IRQ_NONE;
3787
3788 while (iir & ~flip_mask) {
3789 /* Can't rely on pipestat interrupt bit in iir as it might
3790 * have been cleared after the pipestat interrupt was received.
3791 * It doesn't set the bit in iir again, but it still produces
3792 * interrupts (for non-MSI).
3793 */
3794 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3795 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3796 i915_handle_error(dev, false,
3797 "Command parser error, iir 0x%08x",
3798 iir);
3799
3800 for_each_pipe(pipe) {
3801 int reg = PIPESTAT(pipe);
3802 pipe_stats[pipe] = I915_READ(reg);
3803
3804 /*
3805 * Clear the PIPE*STAT regs before the IIR
3806 */
3807 if (pipe_stats[pipe] & 0x8000ffff)
3808 I915_WRITE(reg, pipe_stats[pipe]);
3809 }
3810 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3811
3812 I915_WRITE16(IIR, iir & ~flip_mask);
3813 new_iir = I915_READ16(IIR); /* Flush posted writes */
3814
3815 i915_update_dri1_breadcrumb(dev);
3816
3817 if (iir & I915_USER_INTERRUPT)
3818 notify_ring(dev, &dev_priv->ring[RCS]);
3819
3820 for_each_pipe(pipe) {
3821 int plane = pipe;
3822 if (HAS_FBC(dev))
3823 plane = !plane;
3824
3825 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3826 i8xx_handle_vblank(dev, plane, pipe, iir))
3827 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3828
3829 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3830 i9xx_pipe_crc_irq_handler(dev, pipe);
3831
3832 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3833 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3834 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3835 }
3836
3837 iir = new_iir;
3838 }
3839
3840 return IRQ_HANDLED;
3841 }
3842
3843 static void i8xx_irq_uninstall(struct drm_device * dev)
3844 {
3845 struct drm_i915_private *dev_priv = dev->dev_private;
3846 int pipe;
3847
3848 for_each_pipe(pipe) {
3849 /* Clear enable bits; then clear status bits */
3850 I915_WRITE(PIPESTAT(pipe), 0);
3851 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3852 }
3853 I915_WRITE16(IMR, 0xffff);
3854 I915_WRITE16(IER, 0x0);
3855 I915_WRITE16(IIR, I915_READ16(IIR));
3856 }
3857
3858 static void i915_irq_preinstall(struct drm_device * dev)
3859 {
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 int pipe;
3862
3863 if (I915_HAS_HOTPLUG(dev)) {
3864 I915_WRITE(PORT_HOTPLUG_EN, 0);
3865 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3866 }
3867
3868 I915_WRITE16(HWSTAM, 0xeffe);
3869 for_each_pipe(pipe)
3870 I915_WRITE(PIPESTAT(pipe), 0);
3871 I915_WRITE(IMR, 0xffffffff);
3872 I915_WRITE(IER, 0x0);
3873 POSTING_READ(IER);
3874 }
3875
3876 static int i915_irq_postinstall(struct drm_device *dev)
3877 {
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879 u32 enable_mask;
3880 unsigned long irqflags;
3881
3882 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3883
3884 /* Unmask the interrupts that we always want on. */
3885 dev_priv->irq_mask =
3886 ~(I915_ASLE_INTERRUPT |
3887 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3888 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3889 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3890 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3891 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3892
3893 enable_mask =
3894 I915_ASLE_INTERRUPT |
3895 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3896 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3897 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3898 I915_USER_INTERRUPT;
3899
3900 if (I915_HAS_HOTPLUG(dev)) {
3901 I915_WRITE(PORT_HOTPLUG_EN, 0);
3902 POSTING_READ(PORT_HOTPLUG_EN);
3903
3904 /* Enable in IER... */
3905 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3906 /* and unmask in IMR */
3907 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3908 }
3909
3910 I915_WRITE(IMR, dev_priv->irq_mask);
3911 I915_WRITE(IER, enable_mask);
3912 POSTING_READ(IER);
3913
3914 i915_enable_asle_pipestat(dev);
3915
3916 /* Interrupt setup is already guaranteed to be single-threaded, this is
3917 * just to make the assert_spin_locked check happy. */
3918 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3919 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3920 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3921 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3922
3923 return 0;
3924 }
3925
3926 /*
3927 * Returns true when a page flip has completed.
3928 */
3929 static bool i915_handle_vblank(struct drm_device *dev,
3930 int plane, int pipe, u32 iir)
3931 {
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3934
3935 if (!intel_pipe_handle_vblank(dev, pipe))
3936 return false;
3937
3938 if ((iir & flip_pending) == 0)
3939 return false;
3940
3941 intel_prepare_page_flip(dev, plane);
3942
3943 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3944 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3945 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3946 * the flip is completed (no longer pending). Since this doesn't raise
3947 * an interrupt per se, we watch for the change at vblank.
3948 */
3949 if (I915_READ(ISR) & flip_pending)
3950 return false;
3951
3952 intel_finish_page_flip(dev, pipe);
3953
3954 return true;
3955 }
3956
3957 static irqreturn_t i915_irq_handler(int irq, void *arg)
3958 {
3959 struct drm_device *dev = arg;
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3962 unsigned long irqflags;
3963 u32 flip_mask =
3964 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3965 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3966 int pipe, ret = IRQ_NONE;
3967
3968 iir = I915_READ(IIR);
3969 do {
3970 bool irq_received = (iir & ~flip_mask) != 0;
3971 bool blc_event = false;
3972
3973 /* Can't rely on pipestat interrupt bit in iir as it might
3974 * have been cleared after the pipestat interrupt was received.
3975 * It doesn't set the bit in iir again, but it still produces
3976 * interrupts (for non-MSI).
3977 */
3978 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3979 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3980 i915_handle_error(dev, false,
3981 "Command parser error, iir 0x%08x",
3982 iir);
3983
3984 for_each_pipe(pipe) {
3985 int reg = PIPESTAT(pipe);
3986 pipe_stats[pipe] = I915_READ(reg);
3987
3988 /* Clear the PIPE*STAT regs before the IIR */
3989 if (pipe_stats[pipe] & 0x8000ffff) {
3990 I915_WRITE(reg, pipe_stats[pipe]);
3991 irq_received = true;
3992 }
3993 }
3994 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3995
3996 if (!irq_received)
3997 break;
3998
3999 /* Consume port. Then clear IIR or we'll miss events */
4000 if (I915_HAS_HOTPLUG(dev) &&
4001 iir & I915_DISPLAY_PORT_INTERRUPT)
4002 i9xx_hpd_irq_handler(dev);
4003
4004 I915_WRITE(IIR, iir & ~flip_mask);
4005 new_iir = I915_READ(IIR); /* Flush posted writes */
4006
4007 if (iir & I915_USER_INTERRUPT)
4008 notify_ring(dev, &dev_priv->ring[RCS]);
4009
4010 for_each_pipe(pipe) {
4011 int plane = pipe;
4012 if (HAS_FBC(dev))
4013 plane = !plane;
4014
4015 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4016 i915_handle_vblank(dev, plane, pipe, iir))
4017 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4018
4019 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4020 blc_event = true;
4021
4022 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4023 i9xx_pipe_crc_irq_handler(dev, pipe);
4024
4025 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4026 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4027 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4028 }
4029
4030 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4031 intel_opregion_asle_intr(dev);
4032
4033 /* With MSI, interrupts are only generated when iir
4034 * transitions from zero to nonzero. If another bit got
4035 * set while we were handling the existing iir bits, then
4036 * we would never get another interrupt.
4037 *
4038 * This is fine on non-MSI as well, as if we hit this path
4039 * we avoid exiting the interrupt handler only to generate
4040 * another one.
4041 *
4042 * Note that for MSI this could cause a stray interrupt report
4043 * if an interrupt landed in the time between writing IIR and
4044 * the posting read. This should be rare enough to never
4045 * trigger the 99% of 100,000 interrupts test for disabling
4046 * stray interrupts.
4047 */
4048 ret = IRQ_HANDLED;
4049 iir = new_iir;
4050 } while (iir & ~flip_mask);
4051
4052 i915_update_dri1_breadcrumb(dev);
4053
4054 return ret;
4055 }
4056
4057 static void i915_irq_uninstall(struct drm_device * dev)
4058 {
4059 struct drm_i915_private *dev_priv = dev->dev_private;
4060 int pipe;
4061
4062 intel_hpd_irq_uninstall(dev_priv);
4063
4064 if (I915_HAS_HOTPLUG(dev)) {
4065 I915_WRITE(PORT_HOTPLUG_EN, 0);
4066 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4067 }
4068
4069 I915_WRITE16(HWSTAM, 0xffff);
4070 for_each_pipe(pipe) {
4071 /* Clear enable bits; then clear status bits */
4072 I915_WRITE(PIPESTAT(pipe), 0);
4073 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4074 }
4075 I915_WRITE(IMR, 0xffffffff);
4076 I915_WRITE(IER, 0x0);
4077
4078 I915_WRITE(IIR, I915_READ(IIR));
4079 }
4080
4081 static void i965_irq_preinstall(struct drm_device * dev)
4082 {
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 int pipe;
4085
4086 I915_WRITE(PORT_HOTPLUG_EN, 0);
4087 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4088
4089 I915_WRITE(HWSTAM, 0xeffe);
4090 for_each_pipe(pipe)
4091 I915_WRITE(PIPESTAT(pipe), 0);
4092 I915_WRITE(IMR, 0xffffffff);
4093 I915_WRITE(IER, 0x0);
4094 POSTING_READ(IER);
4095 }
4096
4097 static int i965_irq_postinstall(struct drm_device *dev)
4098 {
4099 struct drm_i915_private *dev_priv = dev->dev_private;
4100 u32 enable_mask;
4101 u32 error_mask;
4102 unsigned long irqflags;
4103
4104 /* Unmask the interrupts that we always want on. */
4105 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4106 I915_DISPLAY_PORT_INTERRUPT |
4107 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4108 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4109 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4110 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4111 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4112
4113 enable_mask = ~dev_priv->irq_mask;
4114 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4115 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4116 enable_mask |= I915_USER_INTERRUPT;
4117
4118 if (IS_G4X(dev))
4119 enable_mask |= I915_BSD_USER_INTERRUPT;
4120
4121 /* Interrupt setup is already guaranteed to be single-threaded, this is
4122 * just to make the assert_spin_locked check happy. */
4123 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4124 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4125 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4126 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4127 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4128
4129 /*
4130 * Enable some error detection, note the instruction error mask
4131 * bit is reserved, so we leave it masked.
4132 */
4133 if (IS_G4X(dev)) {
4134 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4135 GM45_ERROR_MEM_PRIV |
4136 GM45_ERROR_CP_PRIV |
4137 I915_ERROR_MEMORY_REFRESH);
4138 } else {
4139 error_mask = ~(I915_ERROR_PAGE_TABLE |
4140 I915_ERROR_MEMORY_REFRESH);
4141 }
4142 I915_WRITE(EMR, error_mask);
4143
4144 I915_WRITE(IMR, dev_priv->irq_mask);
4145 I915_WRITE(IER, enable_mask);
4146 POSTING_READ(IER);
4147
4148 I915_WRITE(PORT_HOTPLUG_EN, 0);
4149 POSTING_READ(PORT_HOTPLUG_EN);
4150
4151 i915_enable_asle_pipestat(dev);
4152
4153 return 0;
4154 }
4155
4156 static void i915_hpd_irq_setup(struct drm_device *dev)
4157 {
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 struct drm_mode_config *mode_config = &dev->mode_config;
4160 struct intel_encoder *intel_encoder;
4161 u32 hotplug_en;
4162
4163 assert_spin_locked(&dev_priv->irq_lock);
4164
4165 if (I915_HAS_HOTPLUG(dev)) {
4166 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4167 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4168 /* Note HDMI and DP share hotplug bits */
4169 /* enable bits are the same for all generations */
4170 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
4171 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4172 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4173 /* Programming the CRT detection parameters tends
4174 to generate a spurious hotplug event about three
4175 seconds later. So just do it once.
4176 */
4177 if (IS_G4X(dev))
4178 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4179 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4180 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4181
4182 /* Ignore TV since it's buggy */
4183 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4184 }
4185 }
4186
4187 static irqreturn_t i965_irq_handler(int irq, void *arg)
4188 {
4189 struct drm_device *dev = arg;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 u32 iir, new_iir;
4192 u32 pipe_stats[I915_MAX_PIPES];
4193 unsigned long irqflags;
4194 int ret = IRQ_NONE, pipe;
4195 u32 flip_mask =
4196 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4197 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4198
4199 iir = I915_READ(IIR);
4200
4201 for (;;) {
4202 bool irq_received = (iir & ~flip_mask) != 0;
4203 bool blc_event = false;
4204
4205 /* Can't rely on pipestat interrupt bit in iir as it might
4206 * have been cleared after the pipestat interrupt was received.
4207 * It doesn't set the bit in iir again, but it still produces
4208 * interrupts (for non-MSI).
4209 */
4210 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4211 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4212 i915_handle_error(dev, false,
4213 "Command parser error, iir 0x%08x",
4214 iir);
4215
4216 for_each_pipe(pipe) {
4217 int reg = PIPESTAT(pipe);
4218 pipe_stats[pipe] = I915_READ(reg);
4219
4220 /*
4221 * Clear the PIPE*STAT regs before the IIR
4222 */
4223 if (pipe_stats[pipe] & 0x8000ffff) {
4224 I915_WRITE(reg, pipe_stats[pipe]);
4225 irq_received = true;
4226 }
4227 }
4228 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4229
4230 if (!irq_received)
4231 break;
4232
4233 ret = IRQ_HANDLED;
4234
4235 /* Consume port. Then clear IIR or we'll miss events */
4236 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4237 i9xx_hpd_irq_handler(dev);
4238
4239 I915_WRITE(IIR, iir & ~flip_mask);
4240 new_iir = I915_READ(IIR); /* Flush posted writes */
4241
4242 if (iir & I915_USER_INTERRUPT)
4243 notify_ring(dev, &dev_priv->ring[RCS]);
4244 if (iir & I915_BSD_USER_INTERRUPT)
4245 notify_ring(dev, &dev_priv->ring[VCS]);
4246
4247 for_each_pipe(pipe) {
4248 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4249 i915_handle_vblank(dev, pipe, pipe, iir))
4250 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4251
4252 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4253 blc_event = true;
4254
4255 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4256 i9xx_pipe_crc_irq_handler(dev, pipe);
4257
4258 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4259 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4260 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4261 }
4262
4263 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4264 intel_opregion_asle_intr(dev);
4265
4266 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4267 gmbus_irq_handler(dev);
4268
4269 /* With MSI, interrupts are only generated when iir
4270 * transitions from zero to nonzero. If another bit got
4271 * set while we were handling the existing iir bits, then
4272 * we would never get another interrupt.
4273 *
4274 * This is fine on non-MSI as well, as if we hit this path
4275 * we avoid exiting the interrupt handler only to generate
4276 * another one.
4277 *
4278 * Note that for MSI this could cause a stray interrupt report
4279 * if an interrupt landed in the time between writing IIR and
4280 * the posting read. This should be rare enough to never
4281 * trigger the 99% of 100,000 interrupts test for disabling
4282 * stray interrupts.
4283 */
4284 iir = new_iir;
4285 }
4286
4287 i915_update_dri1_breadcrumb(dev);
4288
4289 return ret;
4290 }
4291
4292 static void i965_irq_uninstall(struct drm_device * dev)
4293 {
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int pipe;
4296
4297 if (!dev_priv)
4298 return;
4299
4300 intel_hpd_irq_uninstall(dev_priv);
4301
4302 I915_WRITE(PORT_HOTPLUG_EN, 0);
4303 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4304
4305 I915_WRITE(HWSTAM, 0xffffffff);
4306 for_each_pipe(pipe)
4307 I915_WRITE(PIPESTAT(pipe), 0);
4308 I915_WRITE(IMR, 0xffffffff);
4309 I915_WRITE(IER, 0x0);
4310
4311 for_each_pipe(pipe)
4312 I915_WRITE(PIPESTAT(pipe),
4313 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4314 I915_WRITE(IIR, I915_READ(IIR));
4315 }
4316
4317 static void intel_hpd_irq_reenable(unsigned long data)
4318 {
4319 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4320 struct drm_device *dev = dev_priv->dev;
4321 struct drm_mode_config *mode_config = &dev->mode_config;
4322 unsigned long irqflags;
4323 int i;
4324
4325 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4326 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4327 struct drm_connector *connector;
4328
4329 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4330 continue;
4331
4332 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4333
4334 list_for_each_entry(connector, &mode_config->connector_list, head) {
4335 struct intel_connector *intel_connector = to_intel_connector(connector);
4336
4337 if (intel_connector->encoder->hpd_pin == i) {
4338 if (connector->polled != intel_connector->polled)
4339 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4340 connector->name);
4341 connector->polled = intel_connector->polled;
4342 if (!connector->polled)
4343 connector->polled = DRM_CONNECTOR_POLL_HPD;
4344 }
4345 }
4346 }
4347 if (dev_priv->display.hpd_irq_setup)
4348 dev_priv->display.hpd_irq_setup(dev);
4349 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4350 }
4351
4352 void intel_irq_init(struct drm_device *dev)
4353 {
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4355
4356 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4357 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4358 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4359 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4360
4361 /* Let's track the enabled rps events */
4362 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4363
4364 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4365 i915_hangcheck_elapsed,
4366 (unsigned long) dev);
4367 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4368 (unsigned long) dev_priv);
4369
4370 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4371
4372 if (IS_GEN2(dev)) {
4373 dev->max_vblank_count = 0;
4374 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4375 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4376 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4377 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4378 } else {
4379 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4380 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4381 }
4382
4383 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4384 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4385 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4386 }
4387
4388 if (IS_CHERRYVIEW(dev)) {
4389 dev->driver->irq_handler = cherryview_irq_handler;
4390 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4391 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4392 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4393 dev->driver->enable_vblank = valleyview_enable_vblank;
4394 dev->driver->disable_vblank = valleyview_disable_vblank;
4395 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4396 } else if (IS_VALLEYVIEW(dev)) {
4397 dev->driver->irq_handler = valleyview_irq_handler;
4398 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4399 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4400 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4401 dev->driver->enable_vblank = valleyview_enable_vblank;
4402 dev->driver->disable_vblank = valleyview_disable_vblank;
4403 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4404 } else if (IS_GEN8(dev)) {
4405 dev->driver->irq_handler = gen8_irq_handler;
4406 dev->driver->irq_preinstall = gen8_irq_reset;
4407 dev->driver->irq_postinstall = gen8_irq_postinstall;
4408 dev->driver->irq_uninstall = gen8_irq_uninstall;
4409 dev->driver->enable_vblank = gen8_enable_vblank;
4410 dev->driver->disable_vblank = gen8_disable_vblank;
4411 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4412 } else if (HAS_PCH_SPLIT(dev)) {
4413 dev->driver->irq_handler = ironlake_irq_handler;
4414 dev->driver->irq_preinstall = ironlake_irq_reset;
4415 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4416 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4417 dev->driver->enable_vblank = ironlake_enable_vblank;
4418 dev->driver->disable_vblank = ironlake_disable_vblank;
4419 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4420 } else {
4421 if (INTEL_INFO(dev)->gen == 2) {
4422 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4423 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4424 dev->driver->irq_handler = i8xx_irq_handler;
4425 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4426 } else if (INTEL_INFO(dev)->gen == 3) {
4427 dev->driver->irq_preinstall = i915_irq_preinstall;
4428 dev->driver->irq_postinstall = i915_irq_postinstall;
4429 dev->driver->irq_uninstall = i915_irq_uninstall;
4430 dev->driver->irq_handler = i915_irq_handler;
4431 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4432 } else {
4433 dev->driver->irq_preinstall = i965_irq_preinstall;
4434 dev->driver->irq_postinstall = i965_irq_postinstall;
4435 dev->driver->irq_uninstall = i965_irq_uninstall;
4436 dev->driver->irq_handler = i965_irq_handler;
4437 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4438 }
4439 dev->driver->enable_vblank = i915_enable_vblank;
4440 dev->driver->disable_vblank = i915_disable_vblank;
4441 }
4442 }
4443
4444 void intel_hpd_init(struct drm_device *dev)
4445 {
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447 struct drm_mode_config *mode_config = &dev->mode_config;
4448 struct drm_connector *connector;
4449 unsigned long irqflags;
4450 int i;
4451
4452 for (i = 1; i < HPD_NUM_PINS; i++) {
4453 dev_priv->hpd_stats[i].hpd_cnt = 0;
4454 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4455 }
4456 list_for_each_entry(connector, &mode_config->connector_list, head) {
4457 struct intel_connector *intel_connector = to_intel_connector(connector);
4458 connector->polled = intel_connector->polled;
4459 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4460 connector->polled = DRM_CONNECTOR_POLL_HPD;
4461 }
4462
4463 /* Interrupt setup is already guaranteed to be single-threaded, this is
4464 * just to make the assert_spin_locked checks happy. */
4465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4466 if (dev_priv->display.hpd_irq_setup)
4467 dev_priv->display.hpd_irq_setup(dev);
4468 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4469 }
4470
4471 /* Disable interrupts so we can allow runtime PM. */
4472 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4473 {
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475
4476 dev->driver->irq_uninstall(dev);
4477 dev_priv->pm.irqs_disabled = true;
4478 }
4479
4480 /* Restore interrupts so we can recover from runtime PM. */
4481 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4482 {
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484
4485 dev_priv->pm.irqs_disabled = false;
4486 dev->driver->irq_preinstall(dev);
4487 dev->driver->irq_postinstall(dev);
4488 }
Linux kernel - Deliverables
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