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Merge commit 'Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux'
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "intel_drv.h"
38
39 static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45 };
46
47 static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53 };
54
55 static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62 };
63
64 static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71 };
72
73 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 /* For display hotplug interrupt */
83 static void
84 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85 {
86 assert_spin_locked(&dev_priv->irq_lock);
87
88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
91 POSTING_READ(DEIMR);
92 }
93 }
94
95 static void
96 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
97 {
98 assert_spin_locked(&dev_priv->irq_lock);
99
100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
103 POSTING_READ(DEIMR);
104 }
105 }
106
107 static bool ivb_can_enable_err_int(struct drm_device *dev)
108 {
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
113 assert_spin_locked(&dev_priv->irq_lock);
114
115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123 }
124
125 static bool cpt_can_enable_serr_int(struct drm_device *dev)
126 {
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
131 assert_spin_locked(&dev_priv->irq_lock);
132
133 for_each_pipe(pipe) {
134 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
135
136 if (crtc->pch_fifo_underrun_disabled)
137 return false;
138 }
139
140 return true;
141 }
142
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
144 enum pipe pipe, bool enable)
145 {
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
148 DE_PIPEB_FIFO_UNDERRUN;
149
150 if (enable)
151 ironlake_enable_display_irq(dev_priv, bit);
152 else
153 ironlake_disable_display_irq(dev_priv, bit);
154 }
155
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
157 enum pipe pipe, bool enable)
158 {
159 struct drm_i915_private *dev_priv = dev->dev_private;
160 if (enable) {
161 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
162
163 if (!ivb_can_enable_err_int(dev))
164 return;
165
166 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
167 } else {
168 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
169
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
172
173 if (!was_enabled &&
174 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
176 pipe_name(pipe));
177 }
178 }
179 }
180
181 /**
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
186 */
187 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
188 uint32_t interrupt_mask,
189 uint32_t enabled_irq_mask)
190 {
191 uint32_t sdeimr = I915_READ(SDEIMR);
192 sdeimr &= ~interrupt_mask;
193 sdeimr |= (~enabled_irq_mask & interrupt_mask);
194
195 assert_spin_locked(&dev_priv->irq_lock);
196
197 I915_WRITE(SDEIMR, sdeimr);
198 POSTING_READ(SDEIMR);
199 }
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
204
205 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
206 enum transcoder pch_transcoder,
207 bool enable)
208 {
209 struct drm_i915_private *dev_priv = dev->dev_private;
210 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
211 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
212
213 if (enable)
214 ibx_enable_display_interrupt(dev_priv, bit);
215 else
216 ibx_disable_display_interrupt(dev_priv, bit);
217 }
218
219 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
220 enum transcoder pch_transcoder,
221 bool enable)
222 {
223 struct drm_i915_private *dev_priv = dev->dev_private;
224
225 if (enable) {
226 I915_WRITE(SERR_INT,
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
228
229 if (!cpt_can_enable_serr_int(dev))
230 return;
231
232 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
233 } else {
234 uint32_t tmp = I915_READ(SERR_INT);
235 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
236
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
239
240 if (!was_enabled &&
241 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder));
244 }
245 }
246 }
247
248 /**
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
250 * @dev: drm device
251 * @pipe: pipe
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
253 *
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
259 *
260 * Returns the previous state of underrun reporting.
261 */
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
263 enum pipe pipe, bool enable)
264 {
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
268 unsigned long flags;
269 bool ret;
270
271 spin_lock_irqsave(&dev_priv->irq_lock, flags);
272
273 ret = !intel_crtc->cpu_fifo_underrun_disabled;
274
275 if (enable == ret)
276 goto done;
277
278 intel_crtc->cpu_fifo_underrun_disabled = !enable;
279
280 if (IS_GEN5(dev) || IS_GEN6(dev))
281 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
282 else if (IS_GEN7(dev))
283 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
284
285 done:
286 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
287 return ret;
288 }
289
290 /**
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
292 * @dev: drm device
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
295 *
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
301 *
302 * Returns the previous state of underrun reporting.
303 */
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
305 enum transcoder pch_transcoder,
306 bool enable)
307 {
308 struct drm_i915_private *dev_priv = dev->dev_private;
309 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
311 unsigned long flags;
312 bool ret;
313
314 /*
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
321 */
322
323 spin_lock_irqsave(&dev_priv->irq_lock, flags);
324
325 ret = !intel_crtc->pch_fifo_underrun_disabled;
326
327 if (enable == ret)
328 goto done;
329
330 intel_crtc->pch_fifo_underrun_disabled = !enable;
331
332 if (HAS_PCH_IBX(dev))
333 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
334 else
335 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
336
337 done:
338 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
339 return ret;
340 }
341
342
343 void
344 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
345 {
346 u32 reg = PIPESTAT(pipe);
347 u32 pipestat = I915_READ(reg) & 0x7fff0000;
348
349 assert_spin_locked(&dev_priv->irq_lock);
350
351 if ((pipestat & mask) == mask)
352 return;
353
354 /* Enable the interrupt, clear any pending status */
355 pipestat |= mask | (mask >> 16);
356 I915_WRITE(reg, pipestat);
357 POSTING_READ(reg);
358 }
359
360 void
361 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
362 {
363 u32 reg = PIPESTAT(pipe);
364 u32 pipestat = I915_READ(reg) & 0x7fff0000;
365
366 assert_spin_locked(&dev_priv->irq_lock);
367
368 if ((pipestat & mask) == 0)
369 return;
370
371 pipestat &= ~mask;
372 I915_WRITE(reg, pipestat);
373 POSTING_READ(reg);
374 }
375
376 /**
377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
378 */
379 static void i915_enable_asle_pipestat(struct drm_device *dev)
380 {
381 drm_i915_private_t *dev_priv = dev->dev_private;
382 unsigned long irqflags;
383
384 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
385 return;
386
387 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
388
389 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
390 if (INTEL_INFO(dev)->gen >= 4)
391 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
392
393 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
394 }
395
396 /**
397 * i915_pipe_enabled - check if a pipe is enabled
398 * @dev: DRM device
399 * @pipe: pipe to check
400 *
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
404 */
405 static int
406 i915_pipe_enabled(struct drm_device *dev, int pipe)
407 {
408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
409
410 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
414
415 return intel_crtc->active;
416 } else {
417 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
418 }
419 }
420
421 /* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
423 */
424 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
425 {
426 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
427 unsigned long high_frame;
428 unsigned long low_frame;
429 u32 high1, high2, low;
430
431 if (!i915_pipe_enabled(dev, pipe)) {
432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
433 "pipe %c\n", pipe_name(pipe));
434 return 0;
435 }
436
437 high_frame = PIPEFRAME(pipe);
438 low_frame = PIPEFRAMEPIXEL(pipe);
439
440 /*
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
443 * register.
444 */
445 do {
446 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
447 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
448 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
449 } while (high1 != high2);
450
451 high1 >>= PIPE_FRAME_HIGH_SHIFT;
452 low >>= PIPE_FRAME_LOW_SHIFT;
453 return (high1 << 8) | low;
454 }
455
456 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
457 {
458 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
459 int reg = PIPE_FRMCOUNT_GM45(pipe);
460
461 if (!i915_pipe_enabled(dev, pipe)) {
462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
463 "pipe %c\n", pipe_name(pipe));
464 return 0;
465 }
466
467 return I915_READ(reg);
468 }
469
470 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
471 int *vpos, int *hpos)
472 {
473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
474 u32 vbl = 0, position = 0;
475 int vbl_start, vbl_end, htotal, vtotal;
476 bool in_vbl = true;
477 int ret = 0;
478 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
479 pipe);
480
481 if (!i915_pipe_enabled(dev, pipe)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
483 "pipe %c\n", pipe_name(pipe));
484 return 0;
485 }
486
487 /* Get vtotal. */
488 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
489
490 if (INTEL_INFO(dev)->gen >= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
493 */
494 position = I915_READ(PIPEDSL(pipe));
495
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
498 */
499 *vpos = position & 0x1fff;
500 *hpos = 0;
501 } else {
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
504 * scanout position.
505 */
506 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
507
508 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
509 *vpos = position / htotal;
510 *hpos = position - (*vpos * htotal);
511 }
512
513 /* Query vblank area. */
514 vbl = I915_READ(VBLANK(cpu_transcoder));
515
516 /* Test position against vblank region. */
517 vbl_start = vbl & 0x1fff;
518 vbl_end = (vbl >> 16) & 0x1fff;
519
520 if ((*vpos < vbl_start) || (*vpos > vbl_end))
521 in_vbl = false;
522
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl && (*vpos >= vbl_start))
525 *vpos = *vpos - vtotal;
526
527 /* Readouts valid? */
528 if (vbl > 0)
529 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
530
531 /* In vblank? */
532 if (in_vbl)
533 ret |= DRM_SCANOUTPOS_INVBL;
534
535 return ret;
536 }
537
538 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
539 int *max_error,
540 struct timeval *vblank_time,
541 unsigned flags)
542 {
543 struct drm_crtc *crtc;
544
545 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
546 DRM_ERROR("Invalid crtc %d\n", pipe);
547 return -EINVAL;
548 }
549
550 /* Get drm_crtc to timestamp: */
551 crtc = intel_get_crtc_for_pipe(dev, pipe);
552 if (crtc == NULL) {
553 DRM_ERROR("Invalid crtc %d\n", pipe);
554 return -EINVAL;
555 }
556
557 if (!crtc->enabled) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
559 return -EBUSY;
560 }
561
562 /* Helper routine in DRM core does all the work: */
563 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
564 vblank_time, flags,
565 crtc);
566 }
567
568 static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
569 {
570 enum drm_connector_status old_status;
571
572 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
573 old_status = connector->status;
574
575 connector->status = connector->funcs->detect(connector, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
577 connector->base.id,
578 drm_get_connector_name(connector),
579 old_status, connector->status);
580 return (old_status != connector->status);
581 }
582
583 /*
584 * Handle hotplug events outside the interrupt handler proper.
585 */
586 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
587
588 static void i915_hotplug_work_func(struct work_struct *work)
589 {
590 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
591 hotplug_work);
592 struct drm_device *dev = dev_priv->dev;
593 struct drm_mode_config *mode_config = &dev->mode_config;
594 struct intel_connector *intel_connector;
595 struct intel_encoder *intel_encoder;
596 struct drm_connector *connector;
597 unsigned long irqflags;
598 bool hpd_disabled = false;
599 bool changed = false;
600 u32 hpd_event_bits;
601
602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv->enable_hotplug_processing)
604 return;
605
606 mutex_lock(&mode_config->mutex);
607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
608
609 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
610
611 hpd_event_bits = dev_priv->hpd_event_bits;
612 dev_priv->hpd_event_bits = 0;
613 list_for_each_entry(connector, &mode_config->connector_list, head) {
614 intel_connector = to_intel_connector(connector);
615 intel_encoder = intel_connector->encoder;
616 if (intel_encoder->hpd_pin > HPD_NONE &&
617 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
618 connector->polled == DRM_CONNECTOR_POLL_HPD) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector));
622 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
623 connector->polled = DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT;
625 hpd_disabled = true;
626 }
627 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector), intel_encoder->hpd_pin);
630 }
631 }
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
634 * some connectors */
635 if (hpd_disabled) {
636 drm_kms_helper_poll_enable(dev);
637 mod_timer(&dev_priv->hotplug_reenable_timer,
638 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
639 }
640
641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
642
643 list_for_each_entry(connector, &mode_config->connector_list, head) {
644 intel_connector = to_intel_connector(connector);
645 intel_encoder = intel_connector->encoder;
646 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
647 if (intel_encoder->hot_plug)
648 intel_encoder->hot_plug(intel_encoder);
649 if (intel_hpd_irq_event(dev, connector))
650 changed = true;
651 }
652 }
653 mutex_unlock(&mode_config->mutex);
654
655 if (changed)
656 drm_kms_helper_hotplug_event(dev);
657 }
658
659 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
660 {
661 drm_i915_private_t *dev_priv = dev->dev_private;
662 u32 busy_up, busy_down, max_avg, min_avg;
663 u8 new_delay;
664
665 spin_lock(&mchdev_lock);
666
667 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
668
669 new_delay = dev_priv->ips.cur_delay;
670
671 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
672 busy_up = I915_READ(RCPREVBSYTUPAVG);
673 busy_down = I915_READ(RCPREVBSYTDNAVG);
674 max_avg = I915_READ(RCBMAXAVG);
675 min_avg = I915_READ(RCBMINAVG);
676
677 /* Handle RCS change request from hw */
678 if (busy_up > max_avg) {
679 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
680 new_delay = dev_priv->ips.cur_delay - 1;
681 if (new_delay < dev_priv->ips.max_delay)
682 new_delay = dev_priv->ips.max_delay;
683 } else if (busy_down < min_avg) {
684 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
685 new_delay = dev_priv->ips.cur_delay + 1;
686 if (new_delay > dev_priv->ips.min_delay)
687 new_delay = dev_priv->ips.min_delay;
688 }
689
690 if (ironlake_set_drps(dev, new_delay))
691 dev_priv->ips.cur_delay = new_delay;
692
693 spin_unlock(&mchdev_lock);
694
695 return;
696 }
697
698 static void notify_ring(struct drm_device *dev,
699 struct intel_ring_buffer *ring)
700 {
701 if (ring->obj == NULL)
702 return;
703
704 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
705
706 wake_up_all(&ring->irq_queue);
707 i915_queue_hangcheck(dev);
708 }
709
710 static void gen6_pm_rps_work(struct work_struct *work)
711 {
712 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
713 rps.work);
714 u32 pm_iir, pm_imr;
715 u8 new_delay;
716
717 spin_lock_irq(&dev_priv->irq_lock);
718 pm_iir = dev_priv->rps.pm_iir;
719 dev_priv->rps.pm_iir = 0;
720 pm_imr = I915_READ(GEN6_PMIMR);
721 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
722 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
723 spin_unlock_irq(&dev_priv->irq_lock);
724
725 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
726 return;
727
728 mutex_lock(&dev_priv->rps.hw_lock);
729
730 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
731 new_delay = dev_priv->rps.cur_delay + 1;
732
733 /*
734 * For better performance, jump directly
735 * to RPe if we're below it.
736 */
737 if (IS_VALLEYVIEW(dev_priv->dev) &&
738 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
739 new_delay = dev_priv->rps.rpe_delay;
740 } else
741 new_delay = dev_priv->rps.cur_delay - 1;
742
743 /* sysfs frequency interfaces may have snuck in while servicing the
744 * interrupt
745 */
746 if (new_delay >= dev_priv->rps.min_delay &&
747 new_delay <= dev_priv->rps.max_delay) {
748 if (IS_VALLEYVIEW(dev_priv->dev))
749 valleyview_set_rps(dev_priv->dev, new_delay);
750 else
751 gen6_set_rps(dev_priv->dev, new_delay);
752 }
753
754 if (IS_VALLEYVIEW(dev_priv->dev)) {
755 /*
756 * On VLV, when we enter RC6 we may not be at the minimum
757 * voltage level, so arm a timer to check. It should only
758 * fire when there's activity or once after we've entered
759 * RC6, and then won't be re-armed until the next RPS interrupt.
760 */
761 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
762 msecs_to_jiffies(100));
763 }
764
765 mutex_unlock(&dev_priv->rps.hw_lock);
766 }
767
768
769 /**
770 * ivybridge_parity_work - Workqueue called when a parity error interrupt
771 * occurred.
772 * @work: workqueue struct
773 *
774 * Doesn't actually do anything except notify userspace. As a consequence of
775 * this event, userspace should try to remap the bad rows since statistically
776 * it is likely the same row is more likely to go bad again.
777 */
778 static void ivybridge_parity_work(struct work_struct *work)
779 {
780 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
781 l3_parity.error_work);
782 u32 error_status, row, bank, subbank;
783 char *parity_event[5];
784 uint32_t misccpctl;
785 unsigned long flags;
786
787 /* We must turn off DOP level clock gating to access the L3 registers.
788 * In order to prevent a get/put style interface, acquire struct mutex
789 * any time we access those registers.
790 */
791 mutex_lock(&dev_priv->dev->struct_mutex);
792
793 misccpctl = I915_READ(GEN7_MISCCPCTL);
794 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
795 POSTING_READ(GEN7_MISCCPCTL);
796
797 error_status = I915_READ(GEN7_L3CDERRST1);
798 row = GEN7_PARITY_ERROR_ROW(error_status);
799 bank = GEN7_PARITY_ERROR_BANK(error_status);
800 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
801
802 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
803 GEN7_L3CDERRST1_ENABLE);
804 POSTING_READ(GEN7_L3CDERRST1);
805
806 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
807
808 spin_lock_irqsave(&dev_priv->irq_lock, flags);
809 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
810 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
811 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
812
813 mutex_unlock(&dev_priv->dev->struct_mutex);
814
815 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
816 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
817 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
818 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
819 parity_event[4] = NULL;
820
821 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
822 KOBJ_CHANGE, parity_event);
823
824 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
825 row, bank, subbank);
826
827 kfree(parity_event[3]);
828 kfree(parity_event[2]);
829 kfree(parity_event[1]);
830 }
831
832 static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
833 {
834 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
835
836 if (!HAS_L3_GPU_CACHE(dev))
837 return;
838
839 spin_lock(&dev_priv->irq_lock);
840 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
841 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
842 spin_unlock(&dev_priv->irq_lock);
843
844 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
845 }
846
847 static void ilk_gt_irq_handler(struct drm_device *dev,
848 struct drm_i915_private *dev_priv,
849 u32 gt_iir)
850 {
851 if (gt_iir &
852 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
853 notify_ring(dev, &dev_priv->ring[RCS]);
854 if (gt_iir & ILK_BSD_USER_INTERRUPT)
855 notify_ring(dev, &dev_priv->ring[VCS]);
856 }
857
858 static void snb_gt_irq_handler(struct drm_device *dev,
859 struct drm_i915_private *dev_priv,
860 u32 gt_iir)
861 {
862
863 if (gt_iir &
864 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
865 notify_ring(dev, &dev_priv->ring[RCS]);
866 if (gt_iir & GT_BSD_USER_INTERRUPT)
867 notify_ring(dev, &dev_priv->ring[VCS]);
868 if (gt_iir & GT_BLT_USER_INTERRUPT)
869 notify_ring(dev, &dev_priv->ring[BCS]);
870
871 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
872 GT_BSD_CS_ERROR_INTERRUPT |
873 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
874 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
875 i915_handle_error(dev, false);
876 }
877
878 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
879 ivybridge_parity_error_irq_handler(dev);
880 }
881
882 /* Legacy way of handling PM interrupts */
883 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv,
884 u32 pm_iir)
885 {
886 /*
887 * IIR bits should never already be set because IMR should
888 * prevent an interrupt from being shown in IIR. The warning
889 * displays a case where we've unsafely cleared
890 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
891 * type is not a problem, it displays a problem in the logic.
892 *
893 * The mask bit in IMR is cleared by dev_priv->rps.work.
894 */
895
896 spin_lock(&dev_priv->irq_lock);
897 dev_priv->rps.pm_iir |= pm_iir;
898 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
899 POSTING_READ(GEN6_PMIMR);
900 spin_unlock(&dev_priv->irq_lock);
901
902 queue_work(dev_priv->wq, &dev_priv->rps.work);
903 }
904
905 #define HPD_STORM_DETECT_PERIOD 1000
906 #define HPD_STORM_THRESHOLD 5
907
908 static inline void intel_hpd_irq_handler(struct drm_device *dev,
909 u32 hotplug_trigger,
910 const u32 *hpd)
911 {
912 drm_i915_private_t *dev_priv = dev->dev_private;
913 int i;
914 bool storm_detected = false;
915
916 if (!hotplug_trigger)
917 return;
918
919 spin_lock(&dev_priv->irq_lock);
920 for (i = 1; i < HPD_NUM_PINS; i++) {
921
922 if (!(hpd[i] & hotplug_trigger) ||
923 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
924 continue;
925
926 dev_priv->hpd_event_bits |= (1 << i);
927 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
928 dev_priv->hpd_stats[i].hpd_last_jiffies
929 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
930 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
931 dev_priv->hpd_stats[i].hpd_cnt = 0;
932 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
933 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
934 dev_priv->hpd_event_bits &= ~(1 << i);
935 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
936 storm_detected = true;
937 } else {
938 dev_priv->hpd_stats[i].hpd_cnt++;
939 }
940 }
941
942 if (storm_detected)
943 dev_priv->display.hpd_irq_setup(dev);
944 spin_unlock(&dev_priv->irq_lock);
945
946 queue_work(dev_priv->wq,
947 &dev_priv->hotplug_work);
948 }
949
950 static void gmbus_irq_handler(struct drm_device *dev)
951 {
952 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
953
954 wake_up_all(&dev_priv->gmbus_wait_queue);
955 }
956
957 static void dp_aux_irq_handler(struct drm_device *dev)
958 {
959 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
960
961 wake_up_all(&dev_priv->gmbus_wait_queue);
962 }
963
964 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
965 * we must be able to deal with other PM interrupts. This is complicated because
966 * of the way in which we use the masks to defer the RPS work (which for
967 * posterity is necessary because of forcewake).
968 */
969 static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
970 u32 pm_iir)
971 {
972 if (pm_iir & GEN6_PM_RPS_EVENTS) {
973 spin_lock(&dev_priv->irq_lock);
974 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
975 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
976 /* never want to mask useful interrupts. (also posting read) */
977 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
978 spin_unlock(&dev_priv->irq_lock);
979
980 queue_work(dev_priv->wq, &dev_priv->rps.work);
981 }
982
983 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
984 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
985
986 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
987 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
988 i915_handle_error(dev_priv->dev, false);
989 }
990 }
991
992 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
993 {
994 struct drm_device *dev = (struct drm_device *) arg;
995 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
996 u32 iir, gt_iir, pm_iir;
997 irqreturn_t ret = IRQ_NONE;
998 unsigned long irqflags;
999 int pipe;
1000 u32 pipe_stats[I915_MAX_PIPES];
1001
1002 atomic_inc(&dev_priv->irq_received);
1003
1004 while (true) {
1005 iir = I915_READ(VLV_IIR);
1006 gt_iir = I915_READ(GTIIR);
1007 pm_iir = I915_READ(GEN6_PMIIR);
1008
1009 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1010 goto out;
1011
1012 ret = IRQ_HANDLED;
1013
1014 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1015
1016 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1017 for_each_pipe(pipe) {
1018 int reg = PIPESTAT(pipe);
1019 pipe_stats[pipe] = I915_READ(reg);
1020
1021 /*
1022 * Clear the PIPE*STAT regs before the IIR
1023 */
1024 if (pipe_stats[pipe] & 0x8000ffff) {
1025 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1026 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1027 pipe_name(pipe));
1028 I915_WRITE(reg, pipe_stats[pipe]);
1029 }
1030 }
1031 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1032
1033 for_each_pipe(pipe) {
1034 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1035 drm_handle_vblank(dev, pipe);
1036
1037 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1038 intel_prepare_page_flip(dev, pipe);
1039 intel_finish_page_flip(dev, pipe);
1040 }
1041 }
1042
1043 /* Consume port. Then clear IIR or we'll miss events */
1044 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1045 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1046 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1047
1048 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1049 hotplug_status);
1050
1051 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1052
1053 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1054 I915_READ(PORT_HOTPLUG_STAT);
1055 }
1056
1057 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1058 gmbus_irq_handler(dev);
1059
1060 if (pm_iir & GEN6_PM_RPS_EVENTS)
1061 gen6_rps_irq_handler(dev_priv, pm_iir);
1062
1063 I915_WRITE(GTIIR, gt_iir);
1064 I915_WRITE(GEN6_PMIIR, pm_iir);
1065 I915_WRITE(VLV_IIR, iir);
1066 }
1067
1068 out:
1069 return ret;
1070 }
1071
1072 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1073 {
1074 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1075 int pipe;
1076 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1077
1078 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1079
1080 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1081 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1082 SDE_AUDIO_POWER_SHIFT);
1083 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1084 port_name(port));
1085 }
1086
1087 if (pch_iir & SDE_AUX_MASK)
1088 dp_aux_irq_handler(dev);
1089
1090 if (pch_iir & SDE_GMBUS)
1091 gmbus_irq_handler(dev);
1092
1093 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1094 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1095
1096 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1097 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1098
1099 if (pch_iir & SDE_POISON)
1100 DRM_ERROR("PCH poison interrupt\n");
1101
1102 if (pch_iir & SDE_FDI_MASK)
1103 for_each_pipe(pipe)
1104 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1105 pipe_name(pipe),
1106 I915_READ(FDI_RX_IIR(pipe)));
1107
1108 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1109 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1110
1111 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1112 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1113
1114 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1115 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1116 false))
1117 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1118
1119 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1120 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1121 false))
1122 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1123 }
1124
1125 static void ivb_err_int_handler(struct drm_device *dev)
1126 {
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128 u32 err_int = I915_READ(GEN7_ERR_INT);
1129
1130 if (err_int & ERR_INT_POISON)
1131 DRM_ERROR("Poison interrupt\n");
1132
1133 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1134 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1135 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1136
1137 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1138 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1139 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1140
1141 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1142 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1143 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1144
1145 I915_WRITE(GEN7_ERR_INT, err_int);
1146 }
1147
1148 static void cpt_serr_int_handler(struct drm_device *dev)
1149 {
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 u32 serr_int = I915_READ(SERR_INT);
1152
1153 if (serr_int & SERR_INT_POISON)
1154 DRM_ERROR("PCH poison interrupt\n");
1155
1156 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1157 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1158 false))
1159 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1160
1161 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1162 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1163 false))
1164 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1165
1166 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1167 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1168 false))
1169 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1170
1171 I915_WRITE(SERR_INT, serr_int);
1172 }
1173
1174 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1175 {
1176 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1177 int pipe;
1178 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1179
1180 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1181
1182 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1183 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1184 SDE_AUDIO_POWER_SHIFT_CPT);
1185 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1186 port_name(port));
1187 }
1188
1189 if (pch_iir & SDE_AUX_MASK_CPT)
1190 dp_aux_irq_handler(dev);
1191
1192 if (pch_iir & SDE_GMBUS_CPT)
1193 gmbus_irq_handler(dev);
1194
1195 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1196 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1197
1198 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1199 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1200
1201 if (pch_iir & SDE_FDI_MASK_CPT)
1202 for_each_pipe(pipe)
1203 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1204 pipe_name(pipe),
1205 I915_READ(FDI_RX_IIR(pipe)));
1206
1207 if (pch_iir & SDE_ERROR_CPT)
1208 cpt_serr_int_handler(dev);
1209 }
1210
1211 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1212 {
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215 if (de_iir & DE_AUX_CHANNEL_A)
1216 dp_aux_irq_handler(dev);
1217
1218 if (de_iir & DE_GSE)
1219 intel_opregion_asle_intr(dev);
1220
1221 if (de_iir & DE_PIPEA_VBLANK)
1222 drm_handle_vblank(dev, 0);
1223
1224 if (de_iir & DE_PIPEB_VBLANK)
1225 drm_handle_vblank(dev, 1);
1226
1227 if (de_iir & DE_POISON)
1228 DRM_ERROR("Poison interrupt\n");
1229
1230 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1231 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1232 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1233
1234 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1235 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1236 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1237
1238 if (de_iir & DE_PLANEA_FLIP_DONE) {
1239 intel_prepare_page_flip(dev, 0);
1240 intel_finish_page_flip_plane(dev, 0);
1241 }
1242
1243 if (de_iir & DE_PLANEB_FLIP_DONE) {
1244 intel_prepare_page_flip(dev, 1);
1245 intel_finish_page_flip_plane(dev, 1);
1246 }
1247
1248 /* check event from PCH */
1249 if (de_iir & DE_PCH_EVENT) {
1250 u32 pch_iir = I915_READ(SDEIIR);
1251
1252 if (HAS_PCH_CPT(dev))
1253 cpt_irq_handler(dev, pch_iir);
1254 else
1255 ibx_irq_handler(dev, pch_iir);
1256
1257 /* should clear PCH hotplug event before clear CPU irq */
1258 I915_WRITE(SDEIIR, pch_iir);
1259 }
1260
1261 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1262 ironlake_rps_change_irq_handler(dev);
1263 }
1264
1265 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1266 {
1267 struct drm_i915_private *dev_priv = dev->dev_private;
1268 int i;
1269
1270 if (de_iir & DE_ERR_INT_IVB)
1271 ivb_err_int_handler(dev);
1272
1273 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1274 dp_aux_irq_handler(dev);
1275
1276 if (de_iir & DE_GSE_IVB)
1277 intel_opregion_asle_intr(dev);
1278
1279 for (i = 0; i < 3; i++) {
1280 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1281 drm_handle_vblank(dev, i);
1282 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1283 intel_prepare_page_flip(dev, i);
1284 intel_finish_page_flip_plane(dev, i);
1285 }
1286 }
1287
1288 /* check event from PCH */
1289 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1290 u32 pch_iir = I915_READ(SDEIIR);
1291
1292 cpt_irq_handler(dev, pch_iir);
1293
1294 /* clear PCH hotplug event before clear CPU irq */
1295 I915_WRITE(SDEIIR, pch_iir);
1296 }
1297 }
1298
1299 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1300 {
1301 struct drm_device *dev = (struct drm_device *) arg;
1302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1303 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1304 irqreturn_t ret = IRQ_NONE;
1305
1306 atomic_inc(&dev_priv->irq_received);
1307
1308 /* We get interrupts on unclaimed registers, so check for this before we
1309 * do any I915_{READ,WRITE}. */
1310 if (IS_HASWELL(dev) &&
1311 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1312 DRM_ERROR("Unclaimed register before interrupt\n");
1313 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1314 }
1315
1316 /* disable master interrupt before clearing iir */
1317 de_ier = I915_READ(DEIER);
1318 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1319 POSTING_READ(DEIER);
1320
1321 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1322 * interrupts will will be stored on its back queue, and then we'll be
1323 * able to process them after we restore SDEIER (as soon as we restore
1324 * it, we'll get an interrupt if SDEIIR still has something to process
1325 * due to its back queue). */
1326 if (!HAS_PCH_NOP(dev)) {
1327 sde_ier = I915_READ(SDEIER);
1328 I915_WRITE(SDEIER, 0);
1329 POSTING_READ(SDEIER);
1330 }
1331
1332 /* On Haswell, also mask ERR_INT because we don't want to risk
1333 * generating "unclaimed register" interrupts from inside the interrupt
1334 * handler. */
1335 if (IS_HASWELL(dev)) {
1336 spin_lock(&dev_priv->irq_lock);
1337 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1338 spin_unlock(&dev_priv->irq_lock);
1339 }
1340
1341 gt_iir = I915_READ(GTIIR);
1342 if (gt_iir) {
1343 if (INTEL_INFO(dev)->gen >= 6)
1344 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1345 else
1346 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1347 I915_WRITE(GTIIR, gt_iir);
1348 ret = IRQ_HANDLED;
1349 }
1350
1351 de_iir = I915_READ(DEIIR);
1352 if (de_iir) {
1353 if (INTEL_INFO(dev)->gen >= 7)
1354 ivb_display_irq_handler(dev, de_iir);
1355 else
1356 ilk_display_irq_handler(dev, de_iir);
1357 I915_WRITE(DEIIR, de_iir);
1358 ret = IRQ_HANDLED;
1359 }
1360
1361 if (INTEL_INFO(dev)->gen >= 6) {
1362 u32 pm_iir = I915_READ(GEN6_PMIIR);
1363 if (pm_iir) {
1364 if (IS_HASWELL(dev))
1365 hsw_pm_irq_handler(dev_priv, pm_iir);
1366 else if (pm_iir & GEN6_PM_RPS_EVENTS)
1367 gen6_rps_irq_handler(dev_priv, pm_iir);
1368 I915_WRITE(GEN6_PMIIR, pm_iir);
1369 ret = IRQ_HANDLED;
1370 }
1371 }
1372
1373 if (IS_HASWELL(dev)) {
1374 spin_lock(&dev_priv->irq_lock);
1375 if (ivb_can_enable_err_int(dev))
1376 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1377 spin_unlock(&dev_priv->irq_lock);
1378 }
1379
1380 I915_WRITE(DEIER, de_ier);
1381 POSTING_READ(DEIER);
1382 if (!HAS_PCH_NOP(dev)) {
1383 I915_WRITE(SDEIER, sde_ier);
1384 POSTING_READ(SDEIER);
1385 }
1386
1387 return ret;
1388 }
1389
1390 /**
1391 * i915_error_work_func - do process context error handling work
1392 * @work: work struct
1393 *
1394 * Fire an error uevent so userspace can see that a hang or error
1395 * was detected.
1396 */
1397 static void i915_error_work_func(struct work_struct *work)
1398 {
1399 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1400 work);
1401 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1402 gpu_error);
1403 struct drm_device *dev = dev_priv->dev;
1404 struct intel_ring_buffer *ring;
1405 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1406 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1407 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1408 int i, ret;
1409
1410 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1411
1412 /*
1413 * Note that there's only one work item which does gpu resets, so we
1414 * need not worry about concurrent gpu resets potentially incrementing
1415 * error->reset_counter twice. We only need to take care of another
1416 * racing irq/hangcheck declaring the gpu dead for a second time. A
1417 * quick check for that is good enough: schedule_work ensures the
1418 * correct ordering between hang detection and this work item, and since
1419 * the reset in-progress bit is only ever set by code outside of this
1420 * work we don't need to worry about any other races.
1421 */
1422 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1423 DRM_DEBUG_DRIVER("resetting chip\n");
1424 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1425 reset_event);
1426
1427 ret = i915_reset(dev);
1428
1429 if (ret == 0) {
1430 /*
1431 * After all the gem state is reset, increment the reset
1432 * counter and wake up everyone waiting for the reset to
1433 * complete.
1434 *
1435 * Since unlock operations are a one-sided barrier only,
1436 * we need to insert a barrier here to order any seqno
1437 * updates before
1438 * the counter increment.
1439 */
1440 smp_mb__before_atomic_inc();
1441 atomic_inc(&dev_priv->gpu_error.reset_counter);
1442
1443 kobject_uevent_env(&dev->primary->kdev.kobj,
1444 KOBJ_CHANGE, reset_done_event);
1445 } else {
1446 atomic_set(&error->reset_counter, I915_WEDGED);
1447 }
1448
1449 for_each_ring(ring, dev_priv, i)
1450 wake_up_all(&ring->irq_queue);
1451
1452 intel_display_handle_reset(dev);
1453
1454 wake_up_all(&dev_priv->gpu_error.reset_queue);
1455 }
1456 }
1457
1458 static void i915_report_and_clear_eir(struct drm_device *dev)
1459 {
1460 struct drm_i915_private *dev_priv = dev->dev_private;
1461 uint32_t instdone[I915_NUM_INSTDONE_REG];
1462 u32 eir = I915_READ(EIR);
1463 int pipe, i;
1464
1465 if (!eir)
1466 return;
1467
1468 pr_err("render error detected, EIR: 0x%08x\n", eir);
1469
1470 i915_get_extra_instdone(dev, instdone);
1471
1472 if (IS_G4X(dev)) {
1473 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1474 u32 ipeir = I915_READ(IPEIR_I965);
1475
1476 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1477 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1478 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1479 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1480 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1481 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1482 I915_WRITE(IPEIR_I965, ipeir);
1483 POSTING_READ(IPEIR_I965);
1484 }
1485 if (eir & GM45_ERROR_PAGE_TABLE) {
1486 u32 pgtbl_err = I915_READ(PGTBL_ER);
1487 pr_err("page table error\n");
1488 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1489 I915_WRITE(PGTBL_ER, pgtbl_err);
1490 POSTING_READ(PGTBL_ER);
1491 }
1492 }
1493
1494 if (!IS_GEN2(dev)) {
1495 if (eir & I915_ERROR_PAGE_TABLE) {
1496 u32 pgtbl_err = I915_READ(PGTBL_ER);
1497 pr_err("page table error\n");
1498 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1499 I915_WRITE(PGTBL_ER, pgtbl_err);
1500 POSTING_READ(PGTBL_ER);
1501 }
1502 }
1503
1504 if (eir & I915_ERROR_MEMORY_REFRESH) {
1505 pr_err("memory refresh error:\n");
1506 for_each_pipe(pipe)
1507 pr_err("pipe %c stat: 0x%08x\n",
1508 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1509 /* pipestat has already been acked */
1510 }
1511 if (eir & I915_ERROR_INSTRUCTION) {
1512 pr_err("instruction error\n");
1513 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1514 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1515 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1516 if (INTEL_INFO(dev)->gen < 4) {
1517 u32 ipeir = I915_READ(IPEIR);
1518
1519 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1520 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1521 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1522 I915_WRITE(IPEIR, ipeir);
1523 POSTING_READ(IPEIR);
1524 } else {
1525 u32 ipeir = I915_READ(IPEIR_I965);
1526
1527 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1528 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1529 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1530 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1531 I915_WRITE(IPEIR_I965, ipeir);
1532 POSTING_READ(IPEIR_I965);
1533 }
1534 }
1535
1536 I915_WRITE(EIR, eir);
1537 POSTING_READ(EIR);
1538 eir = I915_READ(EIR);
1539 if (eir) {
1540 /*
1541 * some errors might have become stuck,
1542 * mask them.
1543 */
1544 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1545 I915_WRITE(EMR, I915_READ(EMR) | eir);
1546 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1547 }
1548 }
1549
1550 /**
1551 * i915_handle_error - handle an error interrupt
1552 * @dev: drm device
1553 *
1554 * Do some basic checking of regsiter state at error interrupt time and
1555 * dump it to the syslog. Also call i915_capture_error_state() to make
1556 * sure we get a record and make it available in debugfs. Fire a uevent
1557 * so userspace knows something bad happened (should trigger collection
1558 * of a ring dump etc.).
1559 */
1560 void i915_handle_error(struct drm_device *dev, bool wedged)
1561 {
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 struct intel_ring_buffer *ring;
1564 int i;
1565
1566 i915_capture_error_state(dev);
1567 i915_report_and_clear_eir(dev);
1568
1569 if (wedged) {
1570 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1571 &dev_priv->gpu_error.reset_counter);
1572
1573 /*
1574 * Wakeup waiting processes so that the reset work item
1575 * doesn't deadlock trying to grab various locks.
1576 */
1577 for_each_ring(ring, dev_priv, i)
1578 wake_up_all(&ring->irq_queue);
1579 }
1580
1581 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1582 }
1583
1584 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1585 {
1586 drm_i915_private_t *dev_priv = dev->dev_private;
1587 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1589 struct drm_i915_gem_object *obj;
1590 struct intel_unpin_work *work;
1591 unsigned long flags;
1592 bool stall_detected;
1593
1594 /* Ignore early vblank irqs */
1595 if (intel_crtc == NULL)
1596 return;
1597
1598 spin_lock_irqsave(&dev->event_lock, flags);
1599 work = intel_crtc->unpin_work;
1600
1601 if (work == NULL ||
1602 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1603 !work->enable_stall_check) {
1604 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1605 spin_unlock_irqrestore(&dev->event_lock, flags);
1606 return;
1607 }
1608
1609 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1610 obj = work->pending_flip_obj;
1611 if (INTEL_INFO(dev)->gen >= 4) {
1612 int dspsurf = DSPSURF(intel_crtc->plane);
1613 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1614 i915_gem_obj_ggtt_offset(obj);
1615 } else {
1616 int dspaddr = DSPADDR(intel_crtc->plane);
1617 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
1618 crtc->y * crtc->fb->pitches[0] +
1619 crtc->x * crtc->fb->bits_per_pixel/8);
1620 }
1621
1622 spin_unlock_irqrestore(&dev->event_lock, flags);
1623
1624 if (stall_detected) {
1625 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1626 intel_prepare_page_flip(dev, intel_crtc->plane);
1627 }
1628 }
1629
1630 /* Called from drm generic code, passed 'crtc' which
1631 * we use as a pipe index
1632 */
1633 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1634 {
1635 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1636 unsigned long irqflags;
1637
1638 if (!i915_pipe_enabled(dev, pipe))
1639 return -EINVAL;
1640
1641 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1642 if (INTEL_INFO(dev)->gen >= 4)
1643 i915_enable_pipestat(dev_priv, pipe,
1644 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1645 else
1646 i915_enable_pipestat(dev_priv, pipe,
1647 PIPE_VBLANK_INTERRUPT_ENABLE);
1648
1649 /* maintain vblank delivery even in deep C-states */
1650 if (dev_priv->info->gen == 3)
1651 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1652 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1653
1654 return 0;
1655 }
1656
1657 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1658 {
1659 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1660 unsigned long irqflags;
1661 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1662 DE_PIPE_VBLANK_ILK(pipe);
1663
1664 if (!i915_pipe_enabled(dev, pipe))
1665 return -EINVAL;
1666
1667 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1668 ironlake_enable_display_irq(dev_priv, bit);
1669 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1670
1671 return 0;
1672 }
1673
1674 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1675 {
1676 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1677 unsigned long irqflags;
1678 u32 imr;
1679
1680 if (!i915_pipe_enabled(dev, pipe))
1681 return -EINVAL;
1682
1683 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1684 imr = I915_READ(VLV_IMR);
1685 if (pipe == 0)
1686 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1687 else
1688 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1689 I915_WRITE(VLV_IMR, imr);
1690 i915_enable_pipestat(dev_priv, pipe,
1691 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1692 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1693
1694 return 0;
1695 }
1696
1697 /* Called from drm generic code, passed 'crtc' which
1698 * we use as a pipe index
1699 */
1700 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1701 {
1702 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1703 unsigned long irqflags;
1704
1705 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1706 if (dev_priv->info->gen == 3)
1707 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1708
1709 i915_disable_pipestat(dev_priv, pipe,
1710 PIPE_VBLANK_INTERRUPT_ENABLE |
1711 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1712 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1713 }
1714
1715 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1716 {
1717 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1718 unsigned long irqflags;
1719 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1720 DE_PIPE_VBLANK_ILK(pipe);
1721
1722 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1723 ironlake_disable_display_irq(dev_priv, bit);
1724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1725 }
1726
1727 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1728 {
1729 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1730 unsigned long irqflags;
1731 u32 imr;
1732
1733 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1734 i915_disable_pipestat(dev_priv, pipe,
1735 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1736 imr = I915_READ(VLV_IMR);
1737 if (pipe == 0)
1738 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1739 else
1740 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1741 I915_WRITE(VLV_IMR, imr);
1742 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1743 }
1744
1745 static u32
1746 ring_last_seqno(struct intel_ring_buffer *ring)
1747 {
1748 return list_entry(ring->request_list.prev,
1749 struct drm_i915_gem_request, list)->seqno;
1750 }
1751
1752 static bool
1753 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1754 {
1755 return (list_empty(&ring->request_list) ||
1756 i915_seqno_passed(seqno, ring_last_seqno(ring)));
1757 }
1758
1759 static struct intel_ring_buffer *
1760 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
1761 {
1762 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1763 u32 cmd, ipehr, acthd, acthd_min;
1764
1765 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1766 if ((ipehr & ~(0x3 << 16)) !=
1767 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1768 return NULL;
1769
1770 /* ACTHD is likely pointing to the dword after the actual command,
1771 * so scan backwards until we find the MBOX.
1772 */
1773 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1774 acthd_min = max((int)acthd - 3 * 4, 0);
1775 do {
1776 cmd = ioread32(ring->virtual_start + acthd);
1777 if (cmd == ipehr)
1778 break;
1779
1780 acthd -= 4;
1781 if (acthd < acthd_min)
1782 return NULL;
1783 } while (1);
1784
1785 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1786 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1787 }
1788
1789 static int semaphore_passed(struct intel_ring_buffer *ring)
1790 {
1791 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1792 struct intel_ring_buffer *signaller;
1793 u32 seqno, ctl;
1794
1795 ring->hangcheck.deadlock = true;
1796
1797 signaller = semaphore_waits_for(ring, &seqno);
1798 if (signaller == NULL || signaller->hangcheck.deadlock)
1799 return -1;
1800
1801 /* cursory check for an unkickable deadlock */
1802 ctl = I915_READ_CTL(signaller);
1803 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1804 return -1;
1805
1806 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1807 }
1808
1809 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1810 {
1811 struct intel_ring_buffer *ring;
1812 int i;
1813
1814 for_each_ring(ring, dev_priv, i)
1815 ring->hangcheck.deadlock = false;
1816 }
1817
1818 static enum intel_ring_hangcheck_action
1819 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1820 {
1821 struct drm_device *dev = ring->dev;
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 u32 tmp;
1824
1825 if (ring->hangcheck.acthd != acthd)
1826 return active;
1827
1828 if (IS_GEN2(dev))
1829 return hung;
1830
1831 /* Is the chip hanging on a WAIT_FOR_EVENT?
1832 * If so we can simply poke the RB_WAIT bit
1833 * and break the hang. This should work on
1834 * all but the second generation chipsets.
1835 */
1836 tmp = I915_READ_CTL(ring);
1837 if (tmp & RING_WAIT) {
1838 DRM_ERROR("Kicking stuck wait on %s\n",
1839 ring->name);
1840 I915_WRITE_CTL(ring, tmp);
1841 return kick;
1842 }
1843
1844 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1845 switch (semaphore_passed(ring)) {
1846 default:
1847 return hung;
1848 case 1:
1849 DRM_ERROR("Kicking stuck semaphore on %s\n",
1850 ring->name);
1851 I915_WRITE_CTL(ring, tmp);
1852 return kick;
1853 case 0:
1854 return wait;
1855 }
1856 }
1857
1858 return hung;
1859 }
1860
1861 /**
1862 * This is called when the chip hasn't reported back with completed
1863 * batchbuffers in a long time. We keep track per ring seqno progress and
1864 * if there are no progress, hangcheck score for that ring is increased.
1865 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1866 * we kick the ring. If we see no progress on three subsequent calls
1867 * we assume chip is wedged and try to fix it by resetting the chip.
1868 */
1869 void i915_hangcheck_elapsed(unsigned long data)
1870 {
1871 struct drm_device *dev = (struct drm_device *)data;
1872 drm_i915_private_t *dev_priv = dev->dev_private;
1873 struct intel_ring_buffer *ring;
1874 int i;
1875 int busy_count = 0, rings_hung = 0;
1876 bool stuck[I915_NUM_RINGS] = { 0 };
1877 #define BUSY 1
1878 #define KICK 5
1879 #define HUNG 20
1880 #define FIRE 30
1881
1882 if (!i915_enable_hangcheck)
1883 return;
1884
1885 for_each_ring(ring, dev_priv, i) {
1886 u32 seqno, acthd;
1887 bool busy = true;
1888
1889 semaphore_clear_deadlocks(dev_priv);
1890
1891 seqno = ring->get_seqno(ring, false);
1892 acthd = intel_ring_get_active_head(ring);
1893
1894 if (ring->hangcheck.seqno == seqno) {
1895 if (ring_idle(ring, seqno)) {
1896 if (waitqueue_active(&ring->irq_queue)) {
1897 /* Issue a wake-up to catch stuck h/w. */
1898 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1899 ring->name);
1900 wake_up_all(&ring->irq_queue);
1901 ring->hangcheck.score += HUNG;
1902 } else
1903 busy = false;
1904 } else {
1905 int score;
1906
1907 /* We always increment the hangcheck score
1908 * if the ring is busy and still processing
1909 * the same request, so that no single request
1910 * can run indefinitely (such as a chain of
1911 * batches). The only time we do not increment
1912 * the hangcheck score on this ring, if this
1913 * ring is in a legitimate wait for another
1914 * ring. In that case the waiting ring is a
1915 * victim and we want to be sure we catch the
1916 * right culprit. Then every time we do kick
1917 * the ring, add a small increment to the
1918 * score so that we can catch a batch that is
1919 * being repeatedly kicked and so responsible
1920 * for stalling the machine.
1921 */
1922 ring->hangcheck.action = ring_stuck(ring,
1923 acthd);
1924
1925 switch (ring->hangcheck.action) {
1926 case wait:
1927 score = 0;
1928 break;
1929 case active:
1930 score = BUSY;
1931 break;
1932 case kick:
1933 score = KICK;
1934 break;
1935 case hung:
1936 score = HUNG;
1937 stuck[i] = true;
1938 break;
1939 }
1940 ring->hangcheck.score += score;
1941 }
1942 } else {
1943 /* Gradually reduce the count so that we catch DoS
1944 * attempts across multiple batches.
1945 */
1946 if (ring->hangcheck.score > 0)
1947 ring->hangcheck.score--;
1948 }
1949
1950 ring->hangcheck.seqno = seqno;
1951 ring->hangcheck.acthd = acthd;
1952 busy_count += busy;
1953 }
1954
1955 for_each_ring(ring, dev_priv, i) {
1956 if (ring->hangcheck.score > FIRE) {
1957 DRM_ERROR("%s on %s\n",
1958 stuck[i] ? "stuck" : "no progress",
1959 ring->name);
1960 rings_hung++;
1961 }
1962 }
1963
1964 if (rings_hung)
1965 return i915_handle_error(dev, true);
1966
1967 if (busy_count)
1968 /* Reset timer case chip hangs without another request
1969 * being added */
1970 i915_queue_hangcheck(dev);
1971 }
1972
1973 void i915_queue_hangcheck(struct drm_device *dev)
1974 {
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 if (!i915_enable_hangcheck)
1977 return;
1978
1979 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1980 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1981 }
1982
1983 static void ibx_irq_preinstall(struct drm_device *dev)
1984 {
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986
1987 if (HAS_PCH_NOP(dev))
1988 return;
1989
1990 /* south display irq */
1991 I915_WRITE(SDEIMR, 0xffffffff);
1992 /*
1993 * SDEIER is also touched by the interrupt handler to work around missed
1994 * PCH interrupts. Hence we can't update it after the interrupt handler
1995 * is enabled - instead we unconditionally enable all PCH interrupt
1996 * sources here, but then only unmask them as needed with SDEIMR.
1997 */
1998 I915_WRITE(SDEIER, 0xffffffff);
1999 POSTING_READ(SDEIER);
2000 }
2001
2002 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2003 {
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005
2006 /* and GT */
2007 I915_WRITE(GTIMR, 0xffffffff);
2008 I915_WRITE(GTIER, 0x0);
2009 POSTING_READ(GTIER);
2010
2011 if (INTEL_INFO(dev)->gen >= 6) {
2012 /* and PM */
2013 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2014 I915_WRITE(GEN6_PMIER, 0x0);
2015 POSTING_READ(GEN6_PMIER);
2016 }
2017 }
2018
2019 /* drm_dma.h hooks
2020 */
2021 static void ironlake_irq_preinstall(struct drm_device *dev)
2022 {
2023 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2024
2025 atomic_set(&dev_priv->irq_received, 0);
2026
2027 I915_WRITE(HWSTAM, 0xeffe);
2028
2029 I915_WRITE(DEIMR, 0xffffffff);
2030 I915_WRITE(DEIER, 0x0);
2031 POSTING_READ(DEIER);
2032
2033 gen5_gt_irq_preinstall(dev);
2034
2035 ibx_irq_preinstall(dev);
2036 }
2037
2038 static void valleyview_irq_preinstall(struct drm_device *dev)
2039 {
2040 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2041 int pipe;
2042
2043 atomic_set(&dev_priv->irq_received, 0);
2044
2045 /* VLV magic */
2046 I915_WRITE(VLV_IMR, 0);
2047 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2048 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2049 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2050
2051 /* and GT */
2052 I915_WRITE(GTIIR, I915_READ(GTIIR));
2053 I915_WRITE(GTIIR, I915_READ(GTIIR));
2054
2055 gen5_gt_irq_preinstall(dev);
2056
2057 I915_WRITE(DPINVGTT, 0xff);
2058
2059 I915_WRITE(PORT_HOTPLUG_EN, 0);
2060 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2061 for_each_pipe(pipe)
2062 I915_WRITE(PIPESTAT(pipe), 0xffff);
2063 I915_WRITE(VLV_IIR, 0xffffffff);
2064 I915_WRITE(VLV_IMR, 0xffffffff);
2065 I915_WRITE(VLV_IER, 0x0);
2066 POSTING_READ(VLV_IER);
2067 }
2068
2069 static void ibx_hpd_irq_setup(struct drm_device *dev)
2070 {
2071 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2072 struct drm_mode_config *mode_config = &dev->mode_config;
2073 struct intel_encoder *intel_encoder;
2074 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2075
2076 if (HAS_PCH_IBX(dev)) {
2077 hotplug_irqs = SDE_HOTPLUG_MASK;
2078 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2079 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2080 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2081 } else {
2082 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2083 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2084 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2085 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2086 }
2087
2088 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2089
2090 /*
2091 * Enable digital hotplug on the PCH, and configure the DP short pulse
2092 * duration to 2ms (which is the minimum in the Display Port spec)
2093 *
2094 * This register is the same on all known PCH chips.
2095 */
2096 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2097 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2098 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2099 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2100 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2101 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2102 }
2103
2104 static void ibx_irq_postinstall(struct drm_device *dev)
2105 {
2106 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2107 u32 mask;
2108
2109 if (HAS_PCH_NOP(dev))
2110 return;
2111
2112 if (HAS_PCH_IBX(dev)) {
2113 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2114 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2115 } else {
2116 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2117
2118 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2119 }
2120
2121 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2122 I915_WRITE(SDEIMR, ~mask);
2123 }
2124
2125 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2126 {
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2128 u32 pm_irqs, gt_irqs;
2129
2130 pm_irqs = gt_irqs = 0;
2131
2132 dev_priv->gt_irq_mask = ~0;
2133 if (HAS_L3_GPU_CACHE(dev)) {
2134 /* L3 parity interrupt is always unmasked. */
2135 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2136 gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2137 }
2138
2139 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2140 if (IS_GEN5(dev)) {
2141 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2142 ILK_BSD_USER_INTERRUPT;
2143 } else {
2144 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2145 }
2146
2147 I915_WRITE(GTIIR, I915_READ(GTIIR));
2148 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2149 I915_WRITE(GTIER, gt_irqs);
2150 POSTING_READ(GTIER);
2151
2152 if (INTEL_INFO(dev)->gen >= 6) {
2153 pm_irqs |= GEN6_PM_RPS_EVENTS;
2154
2155 if (HAS_VEBOX(dev))
2156 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2157
2158 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2159 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2160 I915_WRITE(GEN6_PMIER, pm_irqs);
2161 POSTING_READ(GEN6_PMIER);
2162 }
2163 }
2164
2165 static int ironlake_irq_postinstall(struct drm_device *dev)
2166 {
2167 unsigned long irqflags;
2168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2169 u32 display_mask, extra_mask;
2170
2171 if (INTEL_INFO(dev)->gen >= 7) {
2172 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2173 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2174 DE_PLANEB_FLIP_DONE_IVB |
2175 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2176 DE_ERR_INT_IVB);
2177 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2178 DE_PIPEA_VBLANK_IVB);
2179
2180 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2181 } else {
2182 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2183 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2184 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2185 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2186 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2187 }
2188
2189 dev_priv->irq_mask = ~display_mask;
2190
2191 /* should always can generate irq */
2192 I915_WRITE(DEIIR, I915_READ(DEIIR));
2193 I915_WRITE(DEIMR, dev_priv->irq_mask);
2194 I915_WRITE(DEIER, display_mask | extra_mask);
2195 POSTING_READ(DEIER);
2196
2197 gen5_gt_irq_postinstall(dev);
2198
2199 ibx_irq_postinstall(dev);
2200
2201 if (IS_IRONLAKE_M(dev)) {
2202 /* Enable PCU event interrupts
2203 *
2204 * spinlocking not required here for correctness since interrupt
2205 * setup is guaranteed to run in single-threaded context. But we
2206 * need it to make the assert_spin_locked happy. */
2207 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2208 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2209 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2210 }
2211
2212 return 0;
2213 }
2214
2215 static int valleyview_irq_postinstall(struct drm_device *dev)
2216 {
2217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2218 u32 enable_mask;
2219 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2220 unsigned long irqflags;
2221
2222 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2223 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2224 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2225 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2226 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2227
2228 /*
2229 *Leave vblank interrupts masked initially. enable/disable will
2230 * toggle them based on usage.
2231 */
2232 dev_priv->irq_mask = (~enable_mask) |
2233 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2234 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2235
2236 I915_WRITE(PORT_HOTPLUG_EN, 0);
2237 POSTING_READ(PORT_HOTPLUG_EN);
2238
2239 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2240 I915_WRITE(VLV_IER, enable_mask);
2241 I915_WRITE(VLV_IIR, 0xffffffff);
2242 I915_WRITE(PIPESTAT(0), 0xffff);
2243 I915_WRITE(PIPESTAT(1), 0xffff);
2244 POSTING_READ(VLV_IER);
2245
2246 /* Interrupt setup is already guaranteed to be single-threaded, this is
2247 * just to make the assert_spin_locked check happy. */
2248 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2249 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2250 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2251 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2252 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2253
2254 I915_WRITE(VLV_IIR, 0xffffffff);
2255 I915_WRITE(VLV_IIR, 0xffffffff);
2256
2257 gen5_gt_irq_postinstall(dev);
2258
2259 /* ack & enable invalid PTE error interrupts */
2260 #if 0 /* FIXME: add support to irq handler for checking these bits */
2261 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2262 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2263 #endif
2264
2265 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2266
2267 return 0;
2268 }
2269
2270 static void valleyview_irq_uninstall(struct drm_device *dev)
2271 {
2272 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2273 int pipe;
2274
2275 if (!dev_priv)
2276 return;
2277
2278 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2279
2280 for_each_pipe(pipe)
2281 I915_WRITE(PIPESTAT(pipe), 0xffff);
2282
2283 I915_WRITE(HWSTAM, 0xffffffff);
2284 I915_WRITE(PORT_HOTPLUG_EN, 0);
2285 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2286 for_each_pipe(pipe)
2287 I915_WRITE(PIPESTAT(pipe), 0xffff);
2288 I915_WRITE(VLV_IIR, 0xffffffff);
2289 I915_WRITE(VLV_IMR, 0xffffffff);
2290 I915_WRITE(VLV_IER, 0x0);
2291 POSTING_READ(VLV_IER);
2292 }
2293
2294 static void ironlake_irq_uninstall(struct drm_device *dev)
2295 {
2296 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2297
2298 if (!dev_priv)
2299 return;
2300
2301 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2302
2303 I915_WRITE(HWSTAM, 0xffffffff);
2304
2305 I915_WRITE(DEIMR, 0xffffffff);
2306 I915_WRITE(DEIER, 0x0);
2307 I915_WRITE(DEIIR, I915_READ(DEIIR));
2308 if (IS_GEN7(dev))
2309 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2310
2311 I915_WRITE(GTIMR, 0xffffffff);
2312 I915_WRITE(GTIER, 0x0);
2313 I915_WRITE(GTIIR, I915_READ(GTIIR));
2314
2315 if (HAS_PCH_NOP(dev))
2316 return;
2317
2318 I915_WRITE(SDEIMR, 0xffffffff);
2319 I915_WRITE(SDEIER, 0x0);
2320 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2321 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2322 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2323 }
2324
2325 static void i8xx_irq_preinstall(struct drm_device * dev)
2326 {
2327 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2328 int pipe;
2329
2330 atomic_set(&dev_priv->irq_received, 0);
2331
2332 for_each_pipe(pipe)
2333 I915_WRITE(PIPESTAT(pipe), 0);
2334 I915_WRITE16(IMR, 0xffff);
2335 I915_WRITE16(IER, 0x0);
2336 POSTING_READ16(IER);
2337 }
2338
2339 static int i8xx_irq_postinstall(struct drm_device *dev)
2340 {
2341 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2342
2343 I915_WRITE16(EMR,
2344 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2345
2346 /* Unmask the interrupts that we always want on. */
2347 dev_priv->irq_mask =
2348 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2349 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2350 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2351 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2352 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2353 I915_WRITE16(IMR, dev_priv->irq_mask);
2354
2355 I915_WRITE16(IER,
2356 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2357 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2358 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2359 I915_USER_INTERRUPT);
2360 POSTING_READ16(IER);
2361
2362 return 0;
2363 }
2364
2365 /*
2366 * Returns true when a page flip has completed.
2367 */
2368 static bool i8xx_handle_vblank(struct drm_device *dev,
2369 int pipe, u16 iir)
2370 {
2371 drm_i915_private_t *dev_priv = dev->dev_private;
2372 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2373
2374 if (!drm_handle_vblank(dev, pipe))
2375 return false;
2376
2377 if ((iir & flip_pending) == 0)
2378 return false;
2379
2380 intel_prepare_page_flip(dev, pipe);
2381
2382 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2383 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2384 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2385 * the flip is completed (no longer pending). Since this doesn't raise
2386 * an interrupt per se, we watch for the change at vblank.
2387 */
2388 if (I915_READ16(ISR) & flip_pending)
2389 return false;
2390
2391 intel_finish_page_flip(dev, pipe);
2392
2393 return true;
2394 }
2395
2396 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2397 {
2398 struct drm_device *dev = (struct drm_device *) arg;
2399 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2400 u16 iir, new_iir;
2401 u32 pipe_stats[2];
2402 unsigned long irqflags;
2403 int irq_received;
2404 int pipe;
2405 u16 flip_mask =
2406 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2407 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2408
2409 atomic_inc(&dev_priv->irq_received);
2410
2411 iir = I915_READ16(IIR);
2412 if (iir == 0)
2413 return IRQ_NONE;
2414
2415 while (iir & ~flip_mask) {
2416 /* Can't rely on pipestat interrupt bit in iir as it might
2417 * have been cleared after the pipestat interrupt was received.
2418 * It doesn't set the bit in iir again, but it still produces
2419 * interrupts (for non-MSI).
2420 */
2421 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2422 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2423 i915_handle_error(dev, false);
2424
2425 for_each_pipe(pipe) {
2426 int reg = PIPESTAT(pipe);
2427 pipe_stats[pipe] = I915_READ(reg);
2428
2429 /*
2430 * Clear the PIPE*STAT regs before the IIR
2431 */
2432 if (pipe_stats[pipe] & 0x8000ffff) {
2433 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2434 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2435 pipe_name(pipe));
2436 I915_WRITE(reg, pipe_stats[pipe]);
2437 irq_received = 1;
2438 }
2439 }
2440 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2441
2442 I915_WRITE16(IIR, iir & ~flip_mask);
2443 new_iir = I915_READ16(IIR); /* Flush posted writes */
2444
2445 i915_update_dri1_breadcrumb(dev);
2446
2447 if (iir & I915_USER_INTERRUPT)
2448 notify_ring(dev, &dev_priv->ring[RCS]);
2449
2450 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2451 i8xx_handle_vblank(dev, 0, iir))
2452 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2453
2454 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2455 i8xx_handle_vblank(dev, 1, iir))
2456 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2457
2458 iir = new_iir;
2459 }
2460
2461 return IRQ_HANDLED;
2462 }
2463
2464 static void i8xx_irq_uninstall(struct drm_device * dev)
2465 {
2466 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2467 int pipe;
2468
2469 for_each_pipe(pipe) {
2470 /* Clear enable bits; then clear status bits */
2471 I915_WRITE(PIPESTAT(pipe), 0);
2472 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2473 }
2474 I915_WRITE16(IMR, 0xffff);
2475 I915_WRITE16(IER, 0x0);
2476 I915_WRITE16(IIR, I915_READ16(IIR));
2477 }
2478
2479 static void i915_irq_preinstall(struct drm_device * dev)
2480 {
2481 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2482 int pipe;
2483
2484 atomic_set(&dev_priv->irq_received, 0);
2485
2486 if (I915_HAS_HOTPLUG(dev)) {
2487 I915_WRITE(PORT_HOTPLUG_EN, 0);
2488 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2489 }
2490
2491 I915_WRITE16(HWSTAM, 0xeffe);
2492 for_each_pipe(pipe)
2493 I915_WRITE(PIPESTAT(pipe), 0);
2494 I915_WRITE(IMR, 0xffffffff);
2495 I915_WRITE(IER, 0x0);
2496 POSTING_READ(IER);
2497 }
2498
2499 static int i915_irq_postinstall(struct drm_device *dev)
2500 {
2501 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2502 u32 enable_mask;
2503
2504 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2505
2506 /* Unmask the interrupts that we always want on. */
2507 dev_priv->irq_mask =
2508 ~(I915_ASLE_INTERRUPT |
2509 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2510 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2511 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2512 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2513 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2514
2515 enable_mask =
2516 I915_ASLE_INTERRUPT |
2517 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2518 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2519 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2520 I915_USER_INTERRUPT;
2521
2522 if (I915_HAS_HOTPLUG(dev)) {
2523 I915_WRITE(PORT_HOTPLUG_EN, 0);
2524 POSTING_READ(PORT_HOTPLUG_EN);
2525
2526 /* Enable in IER... */
2527 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2528 /* and unmask in IMR */
2529 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2530 }
2531
2532 I915_WRITE(IMR, dev_priv->irq_mask);
2533 I915_WRITE(IER, enable_mask);
2534 POSTING_READ(IER);
2535
2536 i915_enable_asle_pipestat(dev);
2537
2538 return 0;
2539 }
2540
2541 /*
2542 * Returns true when a page flip has completed.
2543 */
2544 static bool i915_handle_vblank(struct drm_device *dev,
2545 int plane, int pipe, u32 iir)
2546 {
2547 drm_i915_private_t *dev_priv = dev->dev_private;
2548 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2549
2550 if (!drm_handle_vblank(dev, pipe))
2551 return false;
2552
2553 if ((iir & flip_pending) == 0)
2554 return false;
2555
2556 intel_prepare_page_flip(dev, plane);
2557
2558 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2559 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2560 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2561 * the flip is completed (no longer pending). Since this doesn't raise
2562 * an interrupt per se, we watch for the change at vblank.
2563 */
2564 if (I915_READ(ISR) & flip_pending)
2565 return false;
2566
2567 intel_finish_page_flip(dev, pipe);
2568
2569 return true;
2570 }
2571
2572 static irqreturn_t i915_irq_handler(int irq, void *arg)
2573 {
2574 struct drm_device *dev = (struct drm_device *) arg;
2575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2576 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2577 unsigned long irqflags;
2578 u32 flip_mask =
2579 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2580 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2581 int pipe, ret = IRQ_NONE;
2582
2583 atomic_inc(&dev_priv->irq_received);
2584
2585 iir = I915_READ(IIR);
2586 do {
2587 bool irq_received = (iir & ~flip_mask) != 0;
2588 bool blc_event = false;
2589
2590 /* Can't rely on pipestat interrupt bit in iir as it might
2591 * have been cleared after the pipestat interrupt was received.
2592 * It doesn't set the bit in iir again, but it still produces
2593 * interrupts (for non-MSI).
2594 */
2595 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2596 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2597 i915_handle_error(dev, false);
2598
2599 for_each_pipe(pipe) {
2600 int reg = PIPESTAT(pipe);
2601 pipe_stats[pipe] = I915_READ(reg);
2602
2603 /* Clear the PIPE*STAT regs before the IIR */
2604 if (pipe_stats[pipe] & 0x8000ffff) {
2605 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2606 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2607 pipe_name(pipe));
2608 I915_WRITE(reg, pipe_stats[pipe]);
2609 irq_received = true;
2610 }
2611 }
2612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2613
2614 if (!irq_received)
2615 break;
2616
2617 /* Consume port. Then clear IIR or we'll miss events */
2618 if ((I915_HAS_HOTPLUG(dev)) &&
2619 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2620 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2621 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2622
2623 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2624 hotplug_status);
2625
2626 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2627
2628 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2629 POSTING_READ(PORT_HOTPLUG_STAT);
2630 }
2631
2632 I915_WRITE(IIR, iir & ~flip_mask);
2633 new_iir = I915_READ(IIR); /* Flush posted writes */
2634
2635 if (iir & I915_USER_INTERRUPT)
2636 notify_ring(dev, &dev_priv->ring[RCS]);
2637
2638 for_each_pipe(pipe) {
2639 int plane = pipe;
2640 if (IS_MOBILE(dev))
2641 plane = !plane;
2642
2643 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2644 i915_handle_vblank(dev, plane, pipe, iir))
2645 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2646
2647 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2648 blc_event = true;
2649 }
2650
2651 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2652 intel_opregion_asle_intr(dev);
2653
2654 /* With MSI, interrupts are only generated when iir
2655 * transitions from zero to nonzero. If another bit got
2656 * set while we were handling the existing iir bits, then
2657 * we would never get another interrupt.
2658 *
2659 * This is fine on non-MSI as well, as if we hit this path
2660 * we avoid exiting the interrupt handler only to generate
2661 * another one.
2662 *
2663 * Note that for MSI this could cause a stray interrupt report
2664 * if an interrupt landed in the time between writing IIR and
2665 * the posting read. This should be rare enough to never
2666 * trigger the 99% of 100,000 interrupts test for disabling
2667 * stray interrupts.
2668 */
2669 ret = IRQ_HANDLED;
2670 iir = new_iir;
2671 } while (iir & ~flip_mask);
2672
2673 i915_update_dri1_breadcrumb(dev);
2674
2675 return ret;
2676 }
2677
2678 static void i915_irq_uninstall(struct drm_device * dev)
2679 {
2680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2681 int pipe;
2682
2683 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2684
2685 if (I915_HAS_HOTPLUG(dev)) {
2686 I915_WRITE(PORT_HOTPLUG_EN, 0);
2687 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2688 }
2689
2690 I915_WRITE16(HWSTAM, 0xffff);
2691 for_each_pipe(pipe) {
2692 /* Clear enable bits; then clear status bits */
2693 I915_WRITE(PIPESTAT(pipe), 0);
2694 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2695 }
2696 I915_WRITE(IMR, 0xffffffff);
2697 I915_WRITE(IER, 0x0);
2698
2699 I915_WRITE(IIR, I915_READ(IIR));
2700 }
2701
2702 static void i965_irq_preinstall(struct drm_device * dev)
2703 {
2704 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2705 int pipe;
2706
2707 atomic_set(&dev_priv->irq_received, 0);
2708
2709 I915_WRITE(PORT_HOTPLUG_EN, 0);
2710 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2711
2712 I915_WRITE(HWSTAM, 0xeffe);
2713 for_each_pipe(pipe)
2714 I915_WRITE(PIPESTAT(pipe), 0);
2715 I915_WRITE(IMR, 0xffffffff);
2716 I915_WRITE(IER, 0x0);
2717 POSTING_READ(IER);
2718 }
2719
2720 static int i965_irq_postinstall(struct drm_device *dev)
2721 {
2722 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2723 u32 enable_mask;
2724 u32 error_mask;
2725 unsigned long irqflags;
2726
2727 /* Unmask the interrupts that we always want on. */
2728 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2729 I915_DISPLAY_PORT_INTERRUPT |
2730 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2731 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2732 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2733 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2734 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2735
2736 enable_mask = ~dev_priv->irq_mask;
2737 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2738 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2739 enable_mask |= I915_USER_INTERRUPT;
2740
2741 if (IS_G4X(dev))
2742 enable_mask |= I915_BSD_USER_INTERRUPT;
2743
2744 /* Interrupt setup is already guaranteed to be single-threaded, this is
2745 * just to make the assert_spin_locked check happy. */
2746 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2747 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2748 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2749
2750 /*
2751 * Enable some error detection, note the instruction error mask
2752 * bit is reserved, so we leave it masked.
2753 */
2754 if (IS_G4X(dev)) {
2755 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2756 GM45_ERROR_MEM_PRIV |
2757 GM45_ERROR_CP_PRIV |
2758 I915_ERROR_MEMORY_REFRESH);
2759 } else {
2760 error_mask = ~(I915_ERROR_PAGE_TABLE |
2761 I915_ERROR_MEMORY_REFRESH);
2762 }
2763 I915_WRITE(EMR, error_mask);
2764
2765 I915_WRITE(IMR, dev_priv->irq_mask);
2766 I915_WRITE(IER, enable_mask);
2767 POSTING_READ(IER);
2768
2769 I915_WRITE(PORT_HOTPLUG_EN, 0);
2770 POSTING_READ(PORT_HOTPLUG_EN);
2771
2772 i915_enable_asle_pipestat(dev);
2773
2774 return 0;
2775 }
2776
2777 static void i915_hpd_irq_setup(struct drm_device *dev)
2778 {
2779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2780 struct drm_mode_config *mode_config = &dev->mode_config;
2781 struct intel_encoder *intel_encoder;
2782 u32 hotplug_en;
2783
2784 assert_spin_locked(&dev_priv->irq_lock);
2785
2786 if (I915_HAS_HOTPLUG(dev)) {
2787 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2788 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2789 /* Note HDMI and DP share hotplug bits */
2790 /* enable bits are the same for all generations */
2791 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2792 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2793 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
2794 /* Programming the CRT detection parameters tends
2795 to generate a spurious hotplug event about three
2796 seconds later. So just do it once.
2797 */
2798 if (IS_G4X(dev))
2799 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2800 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2801 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2802
2803 /* Ignore TV since it's buggy */
2804 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2805 }
2806 }
2807
2808 static irqreturn_t i965_irq_handler(int irq, void *arg)
2809 {
2810 struct drm_device *dev = (struct drm_device *) arg;
2811 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2812 u32 iir, new_iir;
2813 u32 pipe_stats[I915_MAX_PIPES];
2814 unsigned long irqflags;
2815 int irq_received;
2816 int ret = IRQ_NONE, pipe;
2817 u32 flip_mask =
2818 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2819 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2820
2821 atomic_inc(&dev_priv->irq_received);
2822
2823 iir = I915_READ(IIR);
2824
2825 for (;;) {
2826 bool blc_event = false;
2827
2828 irq_received = (iir & ~flip_mask) != 0;
2829
2830 /* Can't rely on pipestat interrupt bit in iir as it might
2831 * have been cleared after the pipestat interrupt was received.
2832 * It doesn't set the bit in iir again, but it still produces
2833 * interrupts (for non-MSI).
2834 */
2835 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2836 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2837 i915_handle_error(dev, false);
2838
2839 for_each_pipe(pipe) {
2840 int reg = PIPESTAT(pipe);
2841 pipe_stats[pipe] = I915_READ(reg);
2842
2843 /*
2844 * Clear the PIPE*STAT regs before the IIR
2845 */
2846 if (pipe_stats[pipe] & 0x8000ffff) {
2847 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2848 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2849 pipe_name(pipe));
2850 I915_WRITE(reg, pipe_stats[pipe]);
2851 irq_received = 1;
2852 }
2853 }
2854 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2855
2856 if (!irq_received)
2857 break;
2858
2859 ret = IRQ_HANDLED;
2860
2861 /* Consume port. Then clear IIR or we'll miss events */
2862 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2863 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2864 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2865 HOTPLUG_INT_STATUS_G4X :
2866 HOTPLUG_INT_STATUS_I915);
2867
2868 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2869 hotplug_status);
2870
2871 intel_hpd_irq_handler(dev, hotplug_trigger,
2872 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
2873
2874 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2875 I915_READ(PORT_HOTPLUG_STAT);
2876 }
2877
2878 I915_WRITE(IIR, iir & ~flip_mask);
2879 new_iir = I915_READ(IIR); /* Flush posted writes */
2880
2881 if (iir & I915_USER_INTERRUPT)
2882 notify_ring(dev, &dev_priv->ring[RCS]);
2883 if (iir & I915_BSD_USER_INTERRUPT)
2884 notify_ring(dev, &dev_priv->ring[VCS]);
2885
2886 for_each_pipe(pipe) {
2887 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2888 i915_handle_vblank(dev, pipe, pipe, iir))
2889 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2890
2891 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2892 blc_event = true;
2893 }
2894
2895
2896 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2897 intel_opregion_asle_intr(dev);
2898
2899 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2900 gmbus_irq_handler(dev);
2901
2902 /* With MSI, interrupts are only generated when iir
2903 * transitions from zero to nonzero. If another bit got
2904 * set while we were handling the existing iir bits, then
2905 * we would never get another interrupt.
2906 *
2907 * This is fine on non-MSI as well, as if we hit this path
2908 * we avoid exiting the interrupt handler only to generate
2909 * another one.
2910 *
2911 * Note that for MSI this could cause a stray interrupt report
2912 * if an interrupt landed in the time between writing IIR and
2913 * the posting read. This should be rare enough to never
2914 * trigger the 99% of 100,000 interrupts test for disabling
2915 * stray interrupts.
2916 */
2917 iir = new_iir;
2918 }
2919
2920 i915_update_dri1_breadcrumb(dev);
2921
2922 return ret;
2923 }
2924
2925 static void i965_irq_uninstall(struct drm_device * dev)
2926 {
2927 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2928 int pipe;
2929
2930 if (!dev_priv)
2931 return;
2932
2933 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2934
2935 I915_WRITE(PORT_HOTPLUG_EN, 0);
2936 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2937
2938 I915_WRITE(HWSTAM, 0xffffffff);
2939 for_each_pipe(pipe)
2940 I915_WRITE(PIPESTAT(pipe), 0);
2941 I915_WRITE(IMR, 0xffffffff);
2942 I915_WRITE(IER, 0x0);
2943
2944 for_each_pipe(pipe)
2945 I915_WRITE(PIPESTAT(pipe),
2946 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2947 I915_WRITE(IIR, I915_READ(IIR));
2948 }
2949
2950 static void i915_reenable_hotplug_timer_func(unsigned long data)
2951 {
2952 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
2953 struct drm_device *dev = dev_priv->dev;
2954 struct drm_mode_config *mode_config = &dev->mode_config;
2955 unsigned long irqflags;
2956 int i;
2957
2958 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2959 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
2960 struct drm_connector *connector;
2961
2962 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
2963 continue;
2964
2965 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
2966
2967 list_for_each_entry(connector, &mode_config->connector_list, head) {
2968 struct intel_connector *intel_connector = to_intel_connector(connector);
2969
2970 if (intel_connector->encoder->hpd_pin == i) {
2971 if (connector->polled != intel_connector->polled)
2972 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
2973 drm_get_connector_name(connector));
2974 connector->polled = intel_connector->polled;
2975 if (!connector->polled)
2976 connector->polled = DRM_CONNECTOR_POLL_HPD;
2977 }
2978 }
2979 }
2980 if (dev_priv->display.hpd_irq_setup)
2981 dev_priv->display.hpd_irq_setup(dev);
2982 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2983 }
2984
2985 void intel_irq_init(struct drm_device *dev)
2986 {
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988
2989 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2990 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2991 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2992 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2993
2994 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2995 i915_hangcheck_elapsed,
2996 (unsigned long) dev);
2997 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
2998 (unsigned long) dev_priv);
2999
3000 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3001
3002 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3003 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3004 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3005 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3006 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3007 }
3008
3009 if (drm_core_check_feature(dev, DRIVER_MODESET))
3010 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3011 else
3012 dev->driver->get_vblank_timestamp = NULL;
3013 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3014
3015 if (IS_VALLEYVIEW(dev)) {
3016 dev->driver->irq_handler = valleyview_irq_handler;
3017 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3018 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3019 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3020 dev->driver->enable_vblank = valleyview_enable_vblank;
3021 dev->driver->disable_vblank = valleyview_disable_vblank;
3022 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3023 } else if (HAS_PCH_SPLIT(dev)) {
3024 dev->driver->irq_handler = ironlake_irq_handler;
3025 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3026 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3027 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3028 dev->driver->enable_vblank = ironlake_enable_vblank;
3029 dev->driver->disable_vblank = ironlake_disable_vblank;
3030 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3031 } else {
3032 if (INTEL_INFO(dev)->gen == 2) {
3033 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3034 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3035 dev->driver->irq_handler = i8xx_irq_handler;
3036 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3037 } else if (INTEL_INFO(dev)->gen == 3) {
3038 dev->driver->irq_preinstall = i915_irq_preinstall;
3039 dev->driver->irq_postinstall = i915_irq_postinstall;
3040 dev->driver->irq_uninstall = i915_irq_uninstall;
3041 dev->driver->irq_handler = i915_irq_handler;
3042 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3043 } else {
3044 dev->driver->irq_preinstall = i965_irq_preinstall;
3045 dev->driver->irq_postinstall = i965_irq_postinstall;
3046 dev->driver->irq_uninstall = i965_irq_uninstall;
3047 dev->driver->irq_handler = i965_irq_handler;
3048 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3049 }
3050 dev->driver->enable_vblank = i915_enable_vblank;
3051 dev->driver->disable_vblank = i915_disable_vblank;
3052 }
3053 }
3054
3055 void intel_hpd_init(struct drm_device *dev)
3056 {
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 struct drm_mode_config *mode_config = &dev->mode_config;
3059 struct drm_connector *connector;
3060 unsigned long irqflags;
3061 int i;
3062
3063 for (i = 1; i < HPD_NUM_PINS; i++) {
3064 dev_priv->hpd_stats[i].hpd_cnt = 0;
3065 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3066 }
3067 list_for_each_entry(connector, &mode_config->connector_list, head) {
3068 struct intel_connector *intel_connector = to_intel_connector(connector);
3069 connector->polled = intel_connector->polled;
3070 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3071 connector->polled = DRM_CONNECTOR_POLL_HPD;
3072 }
3073
3074 /* Interrupt setup is already guaranteed to be single-threaded, this is
3075 * just to make the assert_spin_locked checks happy. */
3076 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3077 if (dev_priv->display.hpd_irq_setup)
3078 dev_priv->display.hpd_irq_setup(dev);
3079 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3080 }
Linux kernel - Deliverables
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