1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
107 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
110 struct intel_crtc
*crtc
;
113 assert_spin_locked(&dev_priv
->irq_lock
);
115 for_each_pipe(pipe
) {
116 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
118 if (crtc
->cpu_fifo_underrun_disabled
)
125 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
129 struct intel_crtc
*crtc
;
131 assert_spin_locked(&dev_priv
->irq_lock
);
133 for_each_pipe(pipe
) {
134 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
136 if (crtc
->pch_fifo_underrun_disabled
)
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
144 enum pipe pipe
, bool enable
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
147 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
148 DE_PIPEB_FIFO_UNDERRUN
;
151 ironlake_enable_display_irq(dev_priv
, bit
);
153 ironlake_disable_display_irq(dev_priv
, bit
);
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
157 enum pipe pipe
, bool enable
)
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
163 if (!ivb_can_enable_err_int(dev
))
166 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
168 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
174 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
187 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
188 uint32_t interrupt_mask
,
189 uint32_t enabled_irq_mask
)
191 uint32_t sdeimr
= I915_READ(SDEIMR
);
192 sdeimr
&= ~interrupt_mask
;
193 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
195 assert_spin_locked(&dev_priv
->irq_lock
);
197 I915_WRITE(SDEIMR
, sdeimr
);
198 POSTING_READ(SDEIMR
);
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
205 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
206 enum transcoder pch_transcoder
,
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
211 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
214 ibx_enable_display_interrupt(dev_priv
, bit
);
216 ibx_disable_display_interrupt(dev_priv
, bit
);
219 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum transcoder pch_transcoder
,
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
229 if (!cpt_can_enable_serr_int(dev
))
232 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
234 uint32_t tmp
= I915_READ(SERR_INT
);
235 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
241 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder
));
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
260 * Returns the previous state of underrun reporting.
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
263 enum pipe pipe
, bool enable
)
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
271 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
273 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
278 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
280 if (IS_GEN5(dev
) || IS_GEN6(dev
))
281 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
282 else if (IS_GEN7(dev
))
283 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
286 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
302 * Returns the previous state of underrun reporting.
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
305 enum transcoder pch_transcoder
,
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
323 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
325 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
330 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
332 if (HAS_PCH_IBX(dev
))
333 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
335 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
338 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
344 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
346 u32 reg
= PIPESTAT(pipe
);
347 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
349 assert_spin_locked(&dev_priv
->irq_lock
);
351 if ((pipestat
& mask
) == mask
)
354 /* Enable the interrupt, clear any pending status */
355 pipestat
|= mask
| (mask
>> 16);
356 I915_WRITE(reg
, pipestat
);
361 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
363 u32 reg
= PIPESTAT(pipe
);
364 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
366 assert_spin_locked(&dev_priv
->irq_lock
);
368 if ((pipestat
& mask
) == 0)
372 I915_WRITE(reg
, pipestat
);
377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
379 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
381 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
382 unsigned long irqflags
;
384 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
387 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
389 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
390 if (INTEL_INFO(dev
)->gen
>= 4)
391 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
393 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
397 * i915_pipe_enabled - check if a pipe is enabled
399 * @pipe: pipe to check
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
406 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
408 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
410 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 return intel_crtc
->active
;
417 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
421 /* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
424 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
427 unsigned long high_frame
;
428 unsigned long low_frame
;
429 u32 high1
, high2
, low
;
431 if (!i915_pipe_enabled(dev
, pipe
)) {
432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
433 "pipe %c\n", pipe_name(pipe
));
437 high_frame
= PIPEFRAME(pipe
);
438 low_frame
= PIPEFRAMEPIXEL(pipe
);
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
446 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
447 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
448 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
449 } while (high1
!= high2
);
451 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
452 low
>>= PIPE_FRAME_LOW_SHIFT
;
453 return (high1
<< 8) | low
;
456 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
458 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
459 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
461 if (!i915_pipe_enabled(dev
, pipe
)) {
462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
463 "pipe %c\n", pipe_name(pipe
));
467 return I915_READ(reg
);
470 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
471 int *vpos
, int *hpos
)
473 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
474 u32 vbl
= 0, position
= 0;
475 int vbl_start
, vbl_end
, htotal
, vtotal
;
478 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
481 if (!i915_pipe_enabled(dev
, pipe
)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
483 "pipe %c\n", pipe_name(pipe
));
488 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
490 if (INTEL_INFO(dev
)->gen
>= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
494 position
= I915_READ(PIPEDSL(pipe
));
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
499 *vpos
= position
& 0x1fff;
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
506 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
508 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
509 *vpos
= position
/ htotal
;
510 *hpos
= position
- (*vpos
* htotal
);
513 /* Query vblank area. */
514 vbl
= I915_READ(VBLANK(cpu_transcoder
));
516 /* Test position against vblank region. */
517 vbl_start
= vbl
& 0x1fff;
518 vbl_end
= (vbl
>> 16) & 0x1fff;
520 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl
&& (*vpos
>= vbl_start
))
525 *vpos
= *vpos
- vtotal
;
527 /* Readouts valid? */
529 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
533 ret
|= DRM_SCANOUTPOS_INVBL
;
538 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
540 struct timeval
*vblank_time
,
543 struct drm_crtc
*crtc
;
545 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
546 DRM_ERROR("Invalid crtc %d\n", pipe
);
550 /* Get drm_crtc to timestamp: */
551 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
553 DRM_ERROR("Invalid crtc %d\n", pipe
);
557 if (!crtc
->enabled
) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
562 /* Helper routine in DRM core does all the work: */
563 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
568 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
570 enum drm_connector_status old_status
;
572 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
573 old_status
= connector
->status
;
575 connector
->status
= connector
->funcs
->detect(connector
, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
578 drm_get_connector_name(connector
),
579 old_status
, connector
->status
);
580 return (old_status
!= connector
->status
);
584 * Handle hotplug events outside the interrupt handler proper.
586 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
588 static void i915_hotplug_work_func(struct work_struct
*work
)
590 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
592 struct drm_device
*dev
= dev_priv
->dev
;
593 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
594 struct intel_connector
*intel_connector
;
595 struct intel_encoder
*intel_encoder
;
596 struct drm_connector
*connector
;
597 unsigned long irqflags
;
598 bool hpd_disabled
= false;
599 bool changed
= false;
602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv
->enable_hotplug_processing
)
606 mutex_lock(&mode_config
->mutex
);
607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
609 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
611 hpd_event_bits
= dev_priv
->hpd_event_bits
;
612 dev_priv
->hpd_event_bits
= 0;
613 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
614 intel_connector
= to_intel_connector(connector
);
615 intel_encoder
= intel_connector
->encoder
;
616 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
617 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
618 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector
));
622 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
623 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT
;
627 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
636 drm_kms_helper_poll_enable(dev
);
637 mod_timer(&dev_priv
->hotplug_reenable_timer
,
638 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
641 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
643 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
644 intel_connector
= to_intel_connector(connector
);
645 intel_encoder
= intel_connector
->encoder
;
646 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
647 if (intel_encoder
->hot_plug
)
648 intel_encoder
->hot_plug(intel_encoder
);
649 if (intel_hpd_irq_event(dev
, connector
))
653 mutex_unlock(&mode_config
->mutex
);
656 drm_kms_helper_hotplug_event(dev
);
659 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 u32 busy_up
, busy_down
, max_avg
, min_avg
;
665 spin_lock(&mchdev_lock
);
667 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
669 new_delay
= dev_priv
->ips
.cur_delay
;
671 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
672 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
673 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
674 max_avg
= I915_READ(RCBMAXAVG
);
675 min_avg
= I915_READ(RCBMINAVG
);
677 /* Handle RCS change request from hw */
678 if (busy_up
> max_avg
) {
679 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
680 new_delay
= dev_priv
->ips
.cur_delay
- 1;
681 if (new_delay
< dev_priv
->ips
.max_delay
)
682 new_delay
= dev_priv
->ips
.max_delay
;
683 } else if (busy_down
< min_avg
) {
684 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
685 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
686 if (new_delay
> dev_priv
->ips
.min_delay
)
687 new_delay
= dev_priv
->ips
.min_delay
;
690 if (ironlake_set_drps(dev
, new_delay
))
691 dev_priv
->ips
.cur_delay
= new_delay
;
693 spin_unlock(&mchdev_lock
);
698 static void notify_ring(struct drm_device
*dev
,
699 struct intel_ring_buffer
*ring
)
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
703 if (ring
->obj
== NULL
)
706 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
708 wake_up_all(&ring
->irq_queue
);
709 if (i915_enable_hangcheck
) {
710 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
711 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
715 static void gen6_pm_rps_work(struct work_struct
*work
)
717 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
722 spin_lock_irq(&dev_priv
->irq_lock
);
723 pm_iir
= dev_priv
->rps
.pm_iir
;
724 dev_priv
->rps
.pm_iir
= 0;
725 pm_imr
= I915_READ(GEN6_PMIMR
);
726 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
727 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
728 spin_unlock_irq(&dev_priv
->irq_lock
);
730 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
733 mutex_lock(&dev_priv
->rps
.hw_lock
);
735 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
736 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
739 * For better performance, jump directly
740 * to RPe if we're below it.
742 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
743 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
744 new_delay
= dev_priv
->rps
.rpe_delay
;
746 new_delay
= dev_priv
->rps
.cur_delay
- 1;
748 /* sysfs frequency interfaces may have snuck in while servicing the
751 if (new_delay
>= dev_priv
->rps
.min_delay
&&
752 new_delay
<= dev_priv
->rps
.max_delay
) {
753 if (IS_VALLEYVIEW(dev_priv
->dev
))
754 valleyview_set_rps(dev_priv
->dev
, new_delay
);
756 gen6_set_rps(dev_priv
->dev
, new_delay
);
759 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
761 * On VLV, when we enter RC6 we may not be at the minimum
762 * voltage level, so arm a timer to check. It should only
763 * fire when there's activity or once after we've entered
764 * RC6, and then won't be re-armed until the next RPS interrupt.
766 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
767 msecs_to_jiffies(100));
770 mutex_unlock(&dev_priv
->rps
.hw_lock
);
775 * ivybridge_parity_work - Workqueue called when a parity error interrupt
777 * @work: workqueue struct
779 * Doesn't actually do anything except notify userspace. As a consequence of
780 * this event, userspace should try to remap the bad rows since statistically
781 * it is likely the same row is more likely to go bad again.
783 static void ivybridge_parity_work(struct work_struct
*work
)
785 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
786 l3_parity
.error_work
);
787 u32 error_status
, row
, bank
, subbank
;
788 char *parity_event
[5];
792 /* We must turn off DOP level clock gating to access the L3 registers.
793 * In order to prevent a get/put style interface, acquire struct mutex
794 * any time we access those registers.
796 mutex_lock(&dev_priv
->dev
->struct_mutex
);
798 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
799 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
800 POSTING_READ(GEN7_MISCCPCTL
);
802 error_status
= I915_READ(GEN7_L3CDERRST1
);
803 row
= GEN7_PARITY_ERROR_ROW(error_status
);
804 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
805 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
807 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
808 GEN7_L3CDERRST1_ENABLE
);
809 POSTING_READ(GEN7_L3CDERRST1
);
811 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
813 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
814 dev_priv
->gt_irq_mask
&= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
815 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
816 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
818 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
820 parity_event
[0] = "L3_PARITY_ERROR=1";
821 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
822 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
823 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
824 parity_event
[4] = NULL
;
826 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
827 KOBJ_CHANGE
, parity_event
);
829 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
832 kfree(parity_event
[3]);
833 kfree(parity_event
[2]);
834 kfree(parity_event
[1]);
837 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
839 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
841 if (!HAS_L3_GPU_CACHE(dev
))
844 spin_lock(&dev_priv
->irq_lock
);
845 dev_priv
->gt_irq_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
846 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
847 spin_unlock(&dev_priv
->irq_lock
);
849 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
852 static void snb_gt_irq_handler(struct drm_device
*dev
,
853 struct drm_i915_private
*dev_priv
,
858 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
859 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
860 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
861 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
862 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
863 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
865 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
866 GT_BSD_CS_ERROR_INTERRUPT
|
867 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
868 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
869 i915_handle_error(dev
, false);
872 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
873 ivybridge_parity_error_irq_handler(dev
);
876 /* Legacy way of handling PM interrupts */
877 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
,
881 * IIR bits should never already be set because IMR should
882 * prevent an interrupt from being shown in IIR. The warning
883 * displays a case where we've unsafely cleared
884 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
885 * type is not a problem, it displays a problem in the logic.
887 * The mask bit in IMR is cleared by dev_priv->rps.work.
890 spin_lock(&dev_priv
->irq_lock
);
891 dev_priv
->rps
.pm_iir
|= pm_iir
;
892 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
893 POSTING_READ(GEN6_PMIMR
);
894 spin_unlock(&dev_priv
->irq_lock
);
896 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
899 #define HPD_STORM_DETECT_PERIOD 1000
900 #define HPD_STORM_THRESHOLD 5
902 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
908 bool storm_detected
= false;
910 if (!hotplug_trigger
)
913 spin_lock(&dev_priv
->irq_lock
);
914 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
916 if (!(hpd
[i
] & hotplug_trigger
) ||
917 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
920 dev_priv
->hpd_event_bits
|= (1 << i
);
921 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
922 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
923 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
924 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
925 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
926 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
927 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
928 dev_priv
->hpd_event_bits
&= ~(1 << i
);
929 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
930 storm_detected
= true;
932 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
937 dev_priv
->display
.hpd_irq_setup(dev
);
938 spin_unlock(&dev_priv
->irq_lock
);
940 queue_work(dev_priv
->wq
,
941 &dev_priv
->hotplug_work
);
944 static void gmbus_irq_handler(struct drm_device
*dev
)
946 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
948 wake_up_all(&dev_priv
->gmbus_wait_queue
);
951 static void dp_aux_irq_handler(struct drm_device
*dev
)
953 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
955 wake_up_all(&dev_priv
->gmbus_wait_queue
);
958 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
959 * we must be able to deal with other PM interrupts. This is complicated because
960 * of the way in which we use the masks to defer the RPS work (which for
961 * posterity is necessary because of forcewake).
963 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
966 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
967 spin_lock(&dev_priv
->irq_lock
);
968 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
969 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
970 /* never want to mask useful interrupts. (also posting read) */
971 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
972 spin_unlock(&dev_priv
->irq_lock
);
974 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
977 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
978 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
980 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
981 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
982 i915_handle_error(dev_priv
->dev
, false);
986 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
988 struct drm_device
*dev
= (struct drm_device
*) arg
;
989 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
990 u32 iir
, gt_iir
, pm_iir
;
991 irqreturn_t ret
= IRQ_NONE
;
992 unsigned long irqflags
;
994 u32 pipe_stats
[I915_MAX_PIPES
];
996 atomic_inc(&dev_priv
->irq_received
);
999 iir
= I915_READ(VLV_IIR
);
1000 gt_iir
= I915_READ(GTIIR
);
1001 pm_iir
= I915_READ(GEN6_PMIIR
);
1003 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1008 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1010 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1011 for_each_pipe(pipe
) {
1012 int reg
= PIPESTAT(pipe
);
1013 pipe_stats
[pipe
] = I915_READ(reg
);
1016 * Clear the PIPE*STAT regs before the IIR
1018 if (pipe_stats
[pipe
] & 0x8000ffff) {
1019 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1020 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1022 I915_WRITE(reg
, pipe_stats
[pipe
]);
1025 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1027 for_each_pipe(pipe
) {
1028 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1029 drm_handle_vblank(dev
, pipe
);
1031 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1032 intel_prepare_page_flip(dev
, pipe
);
1033 intel_finish_page_flip(dev
, pipe
);
1037 /* Consume port. Then clear IIR or we'll miss events */
1038 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1039 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1040 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1042 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1045 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1047 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1048 I915_READ(PORT_HOTPLUG_STAT
);
1051 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1052 gmbus_irq_handler(dev
);
1054 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1055 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1057 I915_WRITE(GTIIR
, gt_iir
);
1058 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1059 I915_WRITE(VLV_IIR
, iir
);
1066 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1068 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1070 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1072 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1074 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1075 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1076 SDE_AUDIO_POWER_SHIFT
);
1077 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1081 if (pch_iir
& SDE_AUX_MASK
)
1082 dp_aux_irq_handler(dev
);
1084 if (pch_iir
& SDE_GMBUS
)
1085 gmbus_irq_handler(dev
);
1087 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1088 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1090 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1091 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1093 if (pch_iir
& SDE_POISON
)
1094 DRM_ERROR("PCH poison interrupt\n");
1096 if (pch_iir
& SDE_FDI_MASK
)
1098 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1100 I915_READ(FDI_RX_IIR(pipe
)));
1102 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1103 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1105 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1106 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1108 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1109 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1111 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1113 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1114 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1116 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1119 static void ivb_err_int_handler(struct drm_device
*dev
)
1121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1122 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1124 if (err_int
& ERR_INT_POISON
)
1125 DRM_ERROR("Poison interrupt\n");
1127 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1128 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1129 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1131 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1132 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1133 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1135 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1136 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1137 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1139 I915_WRITE(GEN7_ERR_INT
, err_int
);
1142 static void cpt_serr_int_handler(struct drm_device
*dev
)
1144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1145 u32 serr_int
= I915_READ(SERR_INT
);
1147 if (serr_int
& SERR_INT_POISON
)
1148 DRM_ERROR("PCH poison interrupt\n");
1150 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1151 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1153 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1155 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1156 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1158 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1160 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1161 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1163 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1165 I915_WRITE(SERR_INT
, serr_int
);
1168 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1170 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1172 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1174 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1176 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1177 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1178 SDE_AUDIO_POWER_SHIFT_CPT
);
1179 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1183 if (pch_iir
& SDE_AUX_MASK_CPT
)
1184 dp_aux_irq_handler(dev
);
1186 if (pch_iir
& SDE_GMBUS_CPT
)
1187 gmbus_irq_handler(dev
);
1189 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1190 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1192 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1193 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1195 if (pch_iir
& SDE_FDI_MASK_CPT
)
1197 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1199 I915_READ(FDI_RX_IIR(pipe
)));
1201 if (pch_iir
& SDE_ERROR_CPT
)
1202 cpt_serr_int_handler(dev
);
1205 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
1207 struct drm_device
*dev
= (struct drm_device
*) arg
;
1208 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1209 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
= 0;
1210 irqreturn_t ret
= IRQ_NONE
;
1213 atomic_inc(&dev_priv
->irq_received
);
1215 /* We get interrupts on unclaimed registers, so check for this before we
1216 * do any I915_{READ,WRITE}. */
1217 if (IS_HASWELL(dev
) &&
1218 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1219 DRM_ERROR("Unclaimed register before interrupt\n");
1220 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1223 /* disable master interrupt before clearing iir */
1224 de_ier
= I915_READ(DEIER
);
1225 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1227 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1228 * interrupts will will be stored on its back queue, and then we'll be
1229 * able to process them after we restore SDEIER (as soon as we restore
1230 * it, we'll get an interrupt if SDEIIR still has something to process
1231 * due to its back queue). */
1232 if (!HAS_PCH_NOP(dev
)) {
1233 sde_ier
= I915_READ(SDEIER
);
1234 I915_WRITE(SDEIER
, 0);
1235 POSTING_READ(SDEIER
);
1238 /* On Haswell, also mask ERR_INT because we don't want to risk
1239 * generating "unclaimed register" interrupts from inside the interrupt
1241 if (IS_HASWELL(dev
)) {
1242 spin_lock(&dev_priv
->irq_lock
);
1243 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1244 spin_unlock(&dev_priv
->irq_lock
);
1247 gt_iir
= I915_READ(GTIIR
);
1249 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1250 I915_WRITE(GTIIR
, gt_iir
);
1254 de_iir
= I915_READ(DEIIR
);
1256 if (de_iir
& DE_ERR_INT_IVB
)
1257 ivb_err_int_handler(dev
);
1259 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1260 dp_aux_irq_handler(dev
);
1262 if (de_iir
& DE_GSE_IVB
)
1263 intel_opregion_asle_intr(dev
);
1265 for (i
= 0; i
< 3; i
++) {
1266 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1267 drm_handle_vblank(dev
, i
);
1268 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1269 intel_prepare_page_flip(dev
, i
);
1270 intel_finish_page_flip_plane(dev
, i
);
1274 /* check event from PCH */
1275 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1276 u32 pch_iir
= I915_READ(SDEIIR
);
1278 cpt_irq_handler(dev
, pch_iir
);
1280 /* clear PCH hotplug event before clear CPU irq */
1281 I915_WRITE(SDEIIR
, pch_iir
);
1284 I915_WRITE(DEIIR
, de_iir
);
1288 pm_iir
= I915_READ(GEN6_PMIIR
);
1290 if (IS_HASWELL(dev
))
1291 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1292 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1293 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1294 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1298 if (IS_HASWELL(dev
)) {
1299 spin_lock(&dev_priv
->irq_lock
);
1300 if (ivb_can_enable_err_int(dev
))
1301 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1302 spin_unlock(&dev_priv
->irq_lock
);
1305 I915_WRITE(DEIER
, de_ier
);
1306 POSTING_READ(DEIER
);
1307 if (!HAS_PCH_NOP(dev
)) {
1308 I915_WRITE(SDEIER
, sde_ier
);
1309 POSTING_READ(SDEIER
);
1315 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1316 struct drm_i915_private
*dev_priv
,
1320 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1321 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1322 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1323 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1326 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1328 struct drm_device
*dev
= (struct drm_device
*) arg
;
1329 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1331 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
1333 atomic_inc(&dev_priv
->irq_received
);
1335 /* disable master interrupt before clearing iir */
1336 de_ier
= I915_READ(DEIER
);
1337 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1338 POSTING_READ(DEIER
);
1340 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1341 * interrupts will will be stored on its back queue, and then we'll be
1342 * able to process them after we restore SDEIER (as soon as we restore
1343 * it, we'll get an interrupt if SDEIIR still has something to process
1344 * due to its back queue). */
1345 sde_ier
= I915_READ(SDEIER
);
1346 I915_WRITE(SDEIER
, 0);
1347 POSTING_READ(SDEIER
);
1349 de_iir
= I915_READ(DEIIR
);
1350 gt_iir
= I915_READ(GTIIR
);
1351 pm_iir
= I915_READ(GEN6_PMIIR
);
1353 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
1359 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1361 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1363 if (de_iir
& DE_AUX_CHANNEL_A
)
1364 dp_aux_irq_handler(dev
);
1366 if (de_iir
& DE_GSE
)
1367 intel_opregion_asle_intr(dev
);
1369 if (de_iir
& DE_PIPEA_VBLANK
)
1370 drm_handle_vblank(dev
, 0);
1372 if (de_iir
& DE_PIPEB_VBLANK
)
1373 drm_handle_vblank(dev
, 1);
1375 if (de_iir
& DE_POISON
)
1376 DRM_ERROR("Poison interrupt\n");
1378 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1379 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1380 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1382 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1383 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1384 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1386 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1387 intel_prepare_page_flip(dev
, 0);
1388 intel_finish_page_flip_plane(dev
, 0);
1391 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1392 intel_prepare_page_flip(dev
, 1);
1393 intel_finish_page_flip_plane(dev
, 1);
1396 /* check event from PCH */
1397 if (de_iir
& DE_PCH_EVENT
) {
1398 u32 pch_iir
= I915_READ(SDEIIR
);
1400 if (HAS_PCH_CPT(dev
))
1401 cpt_irq_handler(dev
, pch_iir
);
1403 ibx_irq_handler(dev
, pch_iir
);
1405 /* should clear PCH hotplug event before clear CPU irq */
1406 I915_WRITE(SDEIIR
, pch_iir
);
1409 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1410 ironlake_rps_change_irq_handler(dev
);
1412 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_RPS_EVENTS
)
1413 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1415 I915_WRITE(GTIIR
, gt_iir
);
1416 I915_WRITE(DEIIR
, de_iir
);
1417 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1420 I915_WRITE(DEIER
, de_ier
);
1421 POSTING_READ(DEIER
);
1422 I915_WRITE(SDEIER
, sde_ier
);
1423 POSTING_READ(SDEIER
);
1429 * i915_error_work_func - do process context error handling work
1430 * @work: work struct
1432 * Fire an error uevent so userspace can see that a hang or error
1435 static void i915_error_work_func(struct work_struct
*work
)
1437 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1439 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1441 struct drm_device
*dev
= dev_priv
->dev
;
1442 struct intel_ring_buffer
*ring
;
1443 char *error_event
[] = { "ERROR=1", NULL
};
1444 char *reset_event
[] = { "RESET=1", NULL
};
1445 char *reset_done_event
[] = { "ERROR=0", NULL
};
1448 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1451 * Note that there's only one work item which does gpu resets, so we
1452 * need not worry about concurrent gpu resets potentially incrementing
1453 * error->reset_counter twice. We only need to take care of another
1454 * racing irq/hangcheck declaring the gpu dead for a second time. A
1455 * quick check for that is good enough: schedule_work ensures the
1456 * correct ordering between hang detection and this work item, and since
1457 * the reset in-progress bit is only ever set by code outside of this
1458 * work we don't need to worry about any other races.
1460 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1461 DRM_DEBUG_DRIVER("resetting chip\n");
1462 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1465 ret
= i915_reset(dev
);
1469 * After all the gem state is reset, increment the reset
1470 * counter and wake up everyone waiting for the reset to
1473 * Since unlock operations are a one-sided barrier only,
1474 * we need to insert a barrier here to order any seqno
1476 * the counter increment.
1478 smp_mb__before_atomic_inc();
1479 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1481 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1482 KOBJ_CHANGE
, reset_done_event
);
1484 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1487 for_each_ring(ring
, dev_priv
, i
)
1488 wake_up_all(&ring
->irq_queue
);
1490 intel_display_handle_reset(dev
);
1492 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1496 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1499 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1500 u32 eir
= I915_READ(EIR
);
1506 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1508 i915_get_extra_instdone(dev
, instdone
);
1511 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1512 u32 ipeir
= I915_READ(IPEIR_I965
);
1514 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1515 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1516 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1517 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1518 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1519 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1520 I915_WRITE(IPEIR_I965
, ipeir
);
1521 POSTING_READ(IPEIR_I965
);
1523 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1524 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1525 pr_err("page table error\n");
1526 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1527 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1528 POSTING_READ(PGTBL_ER
);
1532 if (!IS_GEN2(dev
)) {
1533 if (eir
& I915_ERROR_PAGE_TABLE
) {
1534 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1535 pr_err("page table error\n");
1536 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1537 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1538 POSTING_READ(PGTBL_ER
);
1542 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1543 pr_err("memory refresh error:\n");
1545 pr_err("pipe %c stat: 0x%08x\n",
1546 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1547 /* pipestat has already been acked */
1549 if (eir
& I915_ERROR_INSTRUCTION
) {
1550 pr_err("instruction error\n");
1551 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1552 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1553 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1554 if (INTEL_INFO(dev
)->gen
< 4) {
1555 u32 ipeir
= I915_READ(IPEIR
);
1557 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1558 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1559 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1560 I915_WRITE(IPEIR
, ipeir
);
1561 POSTING_READ(IPEIR
);
1563 u32 ipeir
= I915_READ(IPEIR_I965
);
1565 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1566 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1567 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1568 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1569 I915_WRITE(IPEIR_I965
, ipeir
);
1570 POSTING_READ(IPEIR_I965
);
1574 I915_WRITE(EIR
, eir
);
1576 eir
= I915_READ(EIR
);
1579 * some errors might have become stuck,
1582 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1583 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1584 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1589 * i915_handle_error - handle an error interrupt
1592 * Do some basic checking of regsiter state at error interrupt time and
1593 * dump it to the syslog. Also call i915_capture_error_state() to make
1594 * sure we get a record and make it available in debugfs. Fire a uevent
1595 * so userspace knows something bad happened (should trigger collection
1596 * of a ring dump etc.).
1598 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 struct intel_ring_buffer
*ring
;
1604 i915_capture_error_state(dev
);
1605 i915_report_and_clear_eir(dev
);
1608 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1609 &dev_priv
->gpu_error
.reset_counter
);
1612 * Wakeup waiting processes so that the reset work item
1613 * doesn't deadlock trying to grab various locks.
1615 for_each_ring(ring
, dev_priv
, i
)
1616 wake_up_all(&ring
->irq_queue
);
1619 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1622 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1624 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1625 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1627 struct drm_i915_gem_object
*obj
;
1628 struct intel_unpin_work
*work
;
1629 unsigned long flags
;
1630 bool stall_detected
;
1632 /* Ignore early vblank irqs */
1633 if (intel_crtc
== NULL
)
1636 spin_lock_irqsave(&dev
->event_lock
, flags
);
1637 work
= intel_crtc
->unpin_work
;
1640 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1641 !work
->enable_stall_check
) {
1642 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1643 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1647 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1648 obj
= work
->pending_flip_obj
;
1649 if (INTEL_INFO(dev
)->gen
>= 4) {
1650 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1651 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1652 i915_gem_obj_ggtt_offset(obj
);
1654 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1655 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1656 crtc
->y
* crtc
->fb
->pitches
[0] +
1657 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1660 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1662 if (stall_detected
) {
1663 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1664 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1668 /* Called from drm generic code, passed 'crtc' which
1669 * we use as a pipe index
1671 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1673 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1674 unsigned long irqflags
;
1676 if (!i915_pipe_enabled(dev
, pipe
))
1679 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1680 if (INTEL_INFO(dev
)->gen
>= 4)
1681 i915_enable_pipestat(dev_priv
, pipe
,
1682 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1684 i915_enable_pipestat(dev_priv
, pipe
,
1685 PIPE_VBLANK_INTERRUPT_ENABLE
);
1687 /* maintain vblank delivery even in deep C-states */
1688 if (dev_priv
->info
->gen
== 3)
1689 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1690 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1695 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1697 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1698 unsigned long irqflags
;
1700 if (!i915_pipe_enabled(dev
, pipe
))
1703 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1704 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1705 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1706 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1711 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1713 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1714 unsigned long irqflags
;
1716 if (!i915_pipe_enabled(dev
, pipe
))
1719 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1720 ironlake_enable_display_irq(dev_priv
,
1721 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
1722 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1727 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1729 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1730 unsigned long irqflags
;
1733 if (!i915_pipe_enabled(dev
, pipe
))
1736 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1737 imr
= I915_READ(VLV_IMR
);
1739 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1741 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1742 I915_WRITE(VLV_IMR
, imr
);
1743 i915_enable_pipestat(dev_priv
, pipe
,
1744 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1745 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1750 /* Called from drm generic code, passed 'crtc' which
1751 * we use as a pipe index
1753 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1755 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1756 unsigned long irqflags
;
1758 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1759 if (dev_priv
->info
->gen
== 3)
1760 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1762 i915_disable_pipestat(dev_priv
, pipe
,
1763 PIPE_VBLANK_INTERRUPT_ENABLE
|
1764 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1765 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1768 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1770 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1771 unsigned long irqflags
;
1773 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1774 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1775 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1776 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1779 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1781 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1782 unsigned long irqflags
;
1784 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1785 ironlake_disable_display_irq(dev_priv
,
1786 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
1787 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1790 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1792 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1793 unsigned long irqflags
;
1796 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1797 i915_disable_pipestat(dev_priv
, pipe
,
1798 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1799 imr
= I915_READ(VLV_IMR
);
1801 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1803 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1804 I915_WRITE(VLV_IMR
, imr
);
1805 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1809 ring_last_seqno(struct intel_ring_buffer
*ring
)
1811 return list_entry(ring
->request_list
.prev
,
1812 struct drm_i915_gem_request
, list
)->seqno
;
1816 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1818 return (list_empty(&ring
->request_list
) ||
1819 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1822 static struct intel_ring_buffer
*
1823 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1825 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1826 u32 cmd
, ipehr
, acthd
, acthd_min
;
1828 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1829 if ((ipehr
& ~(0x3 << 16)) !=
1830 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1833 /* ACTHD is likely pointing to the dword after the actual command,
1834 * so scan backwards until we find the MBOX.
1836 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1837 acthd_min
= max((int)acthd
- 3 * 4, 0);
1839 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1844 if (acthd
< acthd_min
)
1848 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1849 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1852 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1854 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1855 struct intel_ring_buffer
*signaller
;
1858 ring
->hangcheck
.deadlock
= true;
1860 signaller
= semaphore_waits_for(ring
, &seqno
);
1861 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1864 /* cursory check for an unkickable deadlock */
1865 ctl
= I915_READ_CTL(signaller
);
1866 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1869 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1872 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1874 struct intel_ring_buffer
*ring
;
1877 for_each_ring(ring
, dev_priv
, i
)
1878 ring
->hangcheck
.deadlock
= false;
1881 static enum intel_ring_hangcheck_action
1882 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1884 struct drm_device
*dev
= ring
->dev
;
1885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1888 if (ring
->hangcheck
.acthd
!= acthd
)
1894 /* Is the chip hanging on a WAIT_FOR_EVENT?
1895 * If so we can simply poke the RB_WAIT bit
1896 * and break the hang. This should work on
1897 * all but the second generation chipsets.
1899 tmp
= I915_READ_CTL(ring
);
1900 if (tmp
& RING_WAIT
) {
1901 DRM_ERROR("Kicking stuck wait on %s\n",
1903 I915_WRITE_CTL(ring
, tmp
);
1907 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1908 switch (semaphore_passed(ring
)) {
1912 DRM_ERROR("Kicking stuck semaphore on %s\n",
1914 I915_WRITE_CTL(ring
, tmp
);
1925 * This is called when the chip hasn't reported back with completed
1926 * batchbuffers in a long time. We keep track per ring seqno progress and
1927 * if there are no progress, hangcheck score for that ring is increased.
1928 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1929 * we kick the ring. If we see no progress on three subsequent calls
1930 * we assume chip is wedged and try to fix it by resetting the chip.
1932 void i915_hangcheck_elapsed(unsigned long data
)
1934 struct drm_device
*dev
= (struct drm_device
*)data
;
1935 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1936 struct intel_ring_buffer
*ring
;
1938 int busy_count
= 0, rings_hung
= 0;
1939 bool stuck
[I915_NUM_RINGS
] = { 0 };
1945 if (!i915_enable_hangcheck
)
1948 for_each_ring(ring
, dev_priv
, i
) {
1952 semaphore_clear_deadlocks(dev_priv
);
1954 seqno
= ring
->get_seqno(ring
, false);
1955 acthd
= intel_ring_get_active_head(ring
);
1957 if (ring
->hangcheck
.seqno
== seqno
) {
1958 if (ring_idle(ring
, seqno
)) {
1959 if (waitqueue_active(&ring
->irq_queue
)) {
1960 /* Issue a wake-up to catch stuck h/w. */
1961 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1963 wake_up_all(&ring
->irq_queue
);
1964 ring
->hangcheck
.score
+= HUNG
;
1970 /* We always increment the hangcheck score
1971 * if the ring is busy and still processing
1972 * the same request, so that no single request
1973 * can run indefinitely (such as a chain of
1974 * batches). The only time we do not increment
1975 * the hangcheck score on this ring, if this
1976 * ring is in a legitimate wait for another
1977 * ring. In that case the waiting ring is a
1978 * victim and we want to be sure we catch the
1979 * right culprit. Then every time we do kick
1980 * the ring, add a small increment to the
1981 * score so that we can catch a batch that is
1982 * being repeatedly kicked and so responsible
1983 * for stalling the machine.
1985 ring
->hangcheck
.action
= ring_stuck(ring
,
1988 switch (ring
->hangcheck
.action
) {
2003 ring
->hangcheck
.score
+= score
;
2006 /* Gradually reduce the count so that we catch DoS
2007 * attempts across multiple batches.
2009 if (ring
->hangcheck
.score
> 0)
2010 ring
->hangcheck
.score
--;
2013 ring
->hangcheck
.seqno
= seqno
;
2014 ring
->hangcheck
.acthd
= acthd
;
2018 for_each_ring(ring
, dev_priv
, i
) {
2019 if (ring
->hangcheck
.score
> FIRE
) {
2020 DRM_ERROR("%s on %s\n",
2021 stuck
[i
] ? "stuck" : "no progress",
2028 return i915_handle_error(dev
, true);
2031 /* Reset timer case chip hangs without another request
2033 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2034 round_jiffies_up(jiffies
+
2035 DRM_I915_HANGCHECK_JIFFIES
));
2038 static void ibx_irq_preinstall(struct drm_device
*dev
)
2040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2042 if (HAS_PCH_NOP(dev
))
2045 /* south display irq */
2046 I915_WRITE(SDEIMR
, 0xffffffff);
2048 * SDEIER is also touched by the interrupt handler to work around missed
2049 * PCH interrupts. Hence we can't update it after the interrupt handler
2050 * is enabled - instead we unconditionally enable all PCH interrupt
2051 * sources here, but then only unmask them as needed with SDEIMR.
2053 I915_WRITE(SDEIER
, 0xffffffff);
2054 POSTING_READ(SDEIER
);
2057 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2062 I915_WRITE(GTIMR
, 0xffffffff);
2063 I915_WRITE(GTIER
, 0x0);
2064 POSTING_READ(GTIER
);
2066 if (INTEL_INFO(dev
)->gen
>= 6) {
2068 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2069 I915_WRITE(GEN6_PMIER
, 0x0);
2070 POSTING_READ(GEN6_PMIER
);
2076 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2078 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2080 atomic_set(&dev_priv
->irq_received
, 0);
2082 I915_WRITE(HWSTAM
, 0xeffe);
2084 I915_WRITE(DEIMR
, 0xffffffff);
2085 I915_WRITE(DEIER
, 0x0);
2086 POSTING_READ(DEIER
);
2088 gen5_gt_irq_preinstall(dev
);
2090 ibx_irq_preinstall(dev
);
2093 static void ivybridge_irq_preinstall(struct drm_device
*dev
)
2095 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2097 atomic_set(&dev_priv
->irq_received
, 0);
2099 I915_WRITE(HWSTAM
, 0xeffe);
2101 /* XXX hotplug from PCH */
2103 I915_WRITE(DEIMR
, 0xffffffff);
2104 I915_WRITE(DEIER
, 0x0);
2105 POSTING_READ(DEIER
);
2107 gen5_gt_irq_preinstall(dev
);
2109 ibx_irq_preinstall(dev
);
2112 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2114 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2117 atomic_set(&dev_priv
->irq_received
, 0);
2120 I915_WRITE(VLV_IMR
, 0);
2121 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2122 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2123 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2126 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2127 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2129 gen5_gt_irq_preinstall(dev
);
2131 I915_WRITE(DPINVGTT
, 0xff);
2133 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2134 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2136 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2137 I915_WRITE(VLV_IIR
, 0xffffffff);
2138 I915_WRITE(VLV_IMR
, 0xffffffff);
2139 I915_WRITE(VLV_IER
, 0x0);
2140 POSTING_READ(VLV_IER
);
2143 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2145 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2146 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2147 struct intel_encoder
*intel_encoder
;
2148 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2150 if (HAS_PCH_IBX(dev
)) {
2151 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2152 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2153 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2154 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2156 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2157 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2158 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2159 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2162 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2165 * Enable digital hotplug on the PCH, and configure the DP short pulse
2166 * duration to 2ms (which is the minimum in the Display Port spec)
2168 * This register is the same on all known PCH chips.
2170 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2171 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2172 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2173 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2174 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2175 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2178 static void ibx_irq_postinstall(struct drm_device
*dev
)
2180 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2183 if (HAS_PCH_NOP(dev
))
2186 if (HAS_PCH_IBX(dev
)) {
2187 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2188 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2190 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2192 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2195 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2196 I915_WRITE(SDEIMR
, ~mask
);
2199 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2201 unsigned long irqflags
;
2203 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2204 /* enable kind of interrupts always enabled */
2205 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2206 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2207 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2208 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2211 dev_priv
->irq_mask
= ~display_mask
;
2213 /* should always can generate irq */
2214 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2215 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2216 I915_WRITE(DEIER
, display_mask
|
2217 DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
);
2218 POSTING_READ(DEIER
);
2220 dev_priv
->gt_irq_mask
= ~0;
2222 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2223 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2225 gt_irqs
= GT_RENDER_USER_INTERRUPT
;
2228 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2230 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2231 ILK_BSD_USER_INTERRUPT
;
2233 I915_WRITE(GTIER
, gt_irqs
);
2234 POSTING_READ(GTIER
);
2236 ibx_irq_postinstall(dev
);
2238 if (IS_IRONLAKE_M(dev
)) {
2239 /* Enable PCU event interrupts
2241 * spinlocking not required here for correctness since interrupt
2242 * setup is guaranteed to run in single-threaded context. But we
2243 * need it to make the assert_spin_locked happy. */
2244 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2245 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2246 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2252 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2254 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2255 /* enable kind of interrupts always enabled */
2257 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2258 DE_PLANEC_FLIP_DONE_IVB
|
2259 DE_PLANEB_FLIP_DONE_IVB
|
2260 DE_PLANEA_FLIP_DONE_IVB
|
2261 DE_AUX_CHANNEL_A_IVB
|
2263 u32 pm_irqs
= GEN6_PM_RPS_EVENTS
;
2266 dev_priv
->irq_mask
= ~display_mask
;
2268 /* should always can generate irq */
2269 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2270 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2271 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2274 DE_PIPEC_VBLANK_IVB
|
2275 DE_PIPEB_VBLANK_IVB
|
2276 DE_PIPEA_VBLANK_IVB
);
2277 POSTING_READ(DEIER
);
2279 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2281 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2282 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2284 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2285 GT_BLT_USER_INTERRUPT
| GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2286 I915_WRITE(GTIER
, gt_irqs
);
2287 POSTING_READ(GTIER
);
2289 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2291 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2293 /* Our enable/disable rps functions may touch these registers so
2294 * make sure to set a known state for only the non-RPS bits.
2295 * The RMW is extra paranoia since this should be called after being set
2296 * to a known state in preinstall.
2298 I915_WRITE(GEN6_PMIMR
,
2299 (I915_READ(GEN6_PMIMR
) | ~GEN6_PM_RPS_EVENTS
) & ~pm_irqs
);
2300 I915_WRITE(GEN6_PMIER
,
2301 (I915_READ(GEN6_PMIER
) & GEN6_PM_RPS_EVENTS
) | pm_irqs
);
2302 POSTING_READ(GEN6_PMIER
);
2304 ibx_irq_postinstall(dev
);
2309 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2311 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2314 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2315 unsigned long irqflags
;
2317 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2318 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2319 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2320 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2321 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2324 *Leave vblank interrupts masked initially. enable/disable will
2325 * toggle them based on usage.
2327 dev_priv
->irq_mask
= (~enable_mask
) |
2328 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2329 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2331 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2332 POSTING_READ(PORT_HOTPLUG_EN
);
2334 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2335 I915_WRITE(VLV_IER
, enable_mask
);
2336 I915_WRITE(VLV_IIR
, 0xffffffff);
2337 I915_WRITE(PIPESTAT(0), 0xffff);
2338 I915_WRITE(PIPESTAT(1), 0xffff);
2339 POSTING_READ(VLV_IER
);
2341 /* Interrupt setup is already guaranteed to be single-threaded, this is
2342 * just to make the assert_spin_locked check happy. */
2343 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2344 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2345 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2346 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2347 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2349 I915_WRITE(VLV_IIR
, 0xffffffff);
2350 I915_WRITE(VLV_IIR
, 0xffffffff);
2352 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2353 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2355 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2356 GT_BLT_USER_INTERRUPT
;
2357 I915_WRITE(GTIER
, gt_irqs
);
2358 POSTING_READ(GTIER
);
2360 /* ack & enable invalid PTE error interrupts */
2361 #if 0 /* FIXME: add support to irq handler for checking these bits */
2362 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2363 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2366 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2371 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2373 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2379 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2382 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2384 I915_WRITE(HWSTAM
, 0xffffffff);
2385 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2386 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2388 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2389 I915_WRITE(VLV_IIR
, 0xffffffff);
2390 I915_WRITE(VLV_IMR
, 0xffffffff);
2391 I915_WRITE(VLV_IER
, 0x0);
2392 POSTING_READ(VLV_IER
);
2395 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2397 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2402 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2404 I915_WRITE(HWSTAM
, 0xffffffff);
2406 I915_WRITE(DEIMR
, 0xffffffff);
2407 I915_WRITE(DEIER
, 0x0);
2408 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2410 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2412 I915_WRITE(GTIMR
, 0xffffffff);
2413 I915_WRITE(GTIER
, 0x0);
2414 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2416 if (HAS_PCH_NOP(dev
))
2419 I915_WRITE(SDEIMR
, 0xffffffff);
2420 I915_WRITE(SDEIER
, 0x0);
2421 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2422 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2423 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2426 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2428 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2431 atomic_set(&dev_priv
->irq_received
, 0);
2434 I915_WRITE(PIPESTAT(pipe
), 0);
2435 I915_WRITE16(IMR
, 0xffff);
2436 I915_WRITE16(IER
, 0x0);
2437 POSTING_READ16(IER
);
2440 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2442 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2445 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2447 /* Unmask the interrupts that we always want on. */
2448 dev_priv
->irq_mask
=
2449 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2450 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2451 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2452 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2453 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2454 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2457 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2458 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2459 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2460 I915_USER_INTERRUPT
);
2461 POSTING_READ16(IER
);
2467 * Returns true when a page flip has completed.
2469 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2472 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2473 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2475 if (!drm_handle_vblank(dev
, pipe
))
2478 if ((iir
& flip_pending
) == 0)
2481 intel_prepare_page_flip(dev
, pipe
);
2483 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2484 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2485 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2486 * the flip is completed (no longer pending). Since this doesn't raise
2487 * an interrupt per se, we watch for the change at vblank.
2489 if (I915_READ16(ISR
) & flip_pending
)
2492 intel_finish_page_flip(dev
, pipe
);
2497 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2499 struct drm_device
*dev
= (struct drm_device
*) arg
;
2500 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2503 unsigned long irqflags
;
2507 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2508 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2510 atomic_inc(&dev_priv
->irq_received
);
2512 iir
= I915_READ16(IIR
);
2516 while (iir
& ~flip_mask
) {
2517 /* Can't rely on pipestat interrupt bit in iir as it might
2518 * have been cleared after the pipestat interrupt was received.
2519 * It doesn't set the bit in iir again, but it still produces
2520 * interrupts (for non-MSI).
2522 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2523 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2524 i915_handle_error(dev
, false);
2526 for_each_pipe(pipe
) {
2527 int reg
= PIPESTAT(pipe
);
2528 pipe_stats
[pipe
] = I915_READ(reg
);
2531 * Clear the PIPE*STAT regs before the IIR
2533 if (pipe_stats
[pipe
] & 0x8000ffff) {
2534 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2535 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2537 I915_WRITE(reg
, pipe_stats
[pipe
]);
2541 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2543 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2544 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2546 i915_update_dri1_breadcrumb(dev
);
2548 if (iir
& I915_USER_INTERRUPT
)
2549 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2551 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2552 i8xx_handle_vblank(dev
, 0, iir
))
2553 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2555 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2556 i8xx_handle_vblank(dev
, 1, iir
))
2557 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2565 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2567 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2570 for_each_pipe(pipe
) {
2571 /* Clear enable bits; then clear status bits */
2572 I915_WRITE(PIPESTAT(pipe
), 0);
2573 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2575 I915_WRITE16(IMR
, 0xffff);
2576 I915_WRITE16(IER
, 0x0);
2577 I915_WRITE16(IIR
, I915_READ16(IIR
));
2580 static void i915_irq_preinstall(struct drm_device
* dev
)
2582 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2585 atomic_set(&dev_priv
->irq_received
, 0);
2587 if (I915_HAS_HOTPLUG(dev
)) {
2588 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2589 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2592 I915_WRITE16(HWSTAM
, 0xeffe);
2594 I915_WRITE(PIPESTAT(pipe
), 0);
2595 I915_WRITE(IMR
, 0xffffffff);
2596 I915_WRITE(IER
, 0x0);
2600 static int i915_irq_postinstall(struct drm_device
*dev
)
2602 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2605 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2607 /* Unmask the interrupts that we always want on. */
2608 dev_priv
->irq_mask
=
2609 ~(I915_ASLE_INTERRUPT
|
2610 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2611 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2612 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2613 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2614 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2617 I915_ASLE_INTERRUPT
|
2618 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2619 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2620 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2621 I915_USER_INTERRUPT
;
2623 if (I915_HAS_HOTPLUG(dev
)) {
2624 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2625 POSTING_READ(PORT_HOTPLUG_EN
);
2627 /* Enable in IER... */
2628 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2629 /* and unmask in IMR */
2630 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2633 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2634 I915_WRITE(IER
, enable_mask
);
2637 i915_enable_asle_pipestat(dev
);
2643 * Returns true when a page flip has completed.
2645 static bool i915_handle_vblank(struct drm_device
*dev
,
2646 int plane
, int pipe
, u32 iir
)
2648 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2649 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2651 if (!drm_handle_vblank(dev
, pipe
))
2654 if ((iir
& flip_pending
) == 0)
2657 intel_prepare_page_flip(dev
, plane
);
2659 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2660 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2661 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2662 * the flip is completed (no longer pending). Since this doesn't raise
2663 * an interrupt per se, we watch for the change at vblank.
2665 if (I915_READ(ISR
) & flip_pending
)
2668 intel_finish_page_flip(dev
, pipe
);
2673 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2675 struct drm_device
*dev
= (struct drm_device
*) arg
;
2676 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2677 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2678 unsigned long irqflags
;
2680 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2681 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2682 int pipe
, ret
= IRQ_NONE
;
2684 atomic_inc(&dev_priv
->irq_received
);
2686 iir
= I915_READ(IIR
);
2688 bool irq_received
= (iir
& ~flip_mask
) != 0;
2689 bool blc_event
= false;
2691 /* Can't rely on pipestat interrupt bit in iir as it might
2692 * have been cleared after the pipestat interrupt was received.
2693 * It doesn't set the bit in iir again, but it still produces
2694 * interrupts (for non-MSI).
2696 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2697 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2698 i915_handle_error(dev
, false);
2700 for_each_pipe(pipe
) {
2701 int reg
= PIPESTAT(pipe
);
2702 pipe_stats
[pipe
] = I915_READ(reg
);
2704 /* Clear the PIPE*STAT regs before the IIR */
2705 if (pipe_stats
[pipe
] & 0x8000ffff) {
2706 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2707 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2709 I915_WRITE(reg
, pipe_stats
[pipe
]);
2710 irq_received
= true;
2713 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2718 /* Consume port. Then clear IIR or we'll miss events */
2719 if ((I915_HAS_HOTPLUG(dev
)) &&
2720 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2721 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2722 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2724 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2727 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2729 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2730 POSTING_READ(PORT_HOTPLUG_STAT
);
2733 I915_WRITE(IIR
, iir
& ~flip_mask
);
2734 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2736 if (iir
& I915_USER_INTERRUPT
)
2737 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2739 for_each_pipe(pipe
) {
2744 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2745 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2746 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2748 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2752 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2753 intel_opregion_asle_intr(dev
);
2755 /* With MSI, interrupts are only generated when iir
2756 * transitions from zero to nonzero. If another bit got
2757 * set while we were handling the existing iir bits, then
2758 * we would never get another interrupt.
2760 * This is fine on non-MSI as well, as if we hit this path
2761 * we avoid exiting the interrupt handler only to generate
2764 * Note that for MSI this could cause a stray interrupt report
2765 * if an interrupt landed in the time between writing IIR and
2766 * the posting read. This should be rare enough to never
2767 * trigger the 99% of 100,000 interrupts test for disabling
2772 } while (iir
& ~flip_mask
);
2774 i915_update_dri1_breadcrumb(dev
);
2779 static void i915_irq_uninstall(struct drm_device
* dev
)
2781 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2784 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2786 if (I915_HAS_HOTPLUG(dev
)) {
2787 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2788 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2791 I915_WRITE16(HWSTAM
, 0xffff);
2792 for_each_pipe(pipe
) {
2793 /* Clear enable bits; then clear status bits */
2794 I915_WRITE(PIPESTAT(pipe
), 0);
2795 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2797 I915_WRITE(IMR
, 0xffffffff);
2798 I915_WRITE(IER
, 0x0);
2800 I915_WRITE(IIR
, I915_READ(IIR
));
2803 static void i965_irq_preinstall(struct drm_device
* dev
)
2805 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2808 atomic_set(&dev_priv
->irq_received
, 0);
2810 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2811 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2813 I915_WRITE(HWSTAM
, 0xeffe);
2815 I915_WRITE(PIPESTAT(pipe
), 0);
2816 I915_WRITE(IMR
, 0xffffffff);
2817 I915_WRITE(IER
, 0x0);
2821 static int i965_irq_postinstall(struct drm_device
*dev
)
2823 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2826 unsigned long irqflags
;
2828 /* Unmask the interrupts that we always want on. */
2829 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2830 I915_DISPLAY_PORT_INTERRUPT
|
2831 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2832 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2833 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2834 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2835 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2837 enable_mask
= ~dev_priv
->irq_mask
;
2838 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2839 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2840 enable_mask
|= I915_USER_INTERRUPT
;
2843 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2845 /* Interrupt setup is already guaranteed to be single-threaded, this is
2846 * just to make the assert_spin_locked check happy. */
2847 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2848 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2849 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2852 * Enable some error detection, note the instruction error mask
2853 * bit is reserved, so we leave it masked.
2856 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2857 GM45_ERROR_MEM_PRIV
|
2858 GM45_ERROR_CP_PRIV
|
2859 I915_ERROR_MEMORY_REFRESH
);
2861 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2862 I915_ERROR_MEMORY_REFRESH
);
2864 I915_WRITE(EMR
, error_mask
);
2866 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2867 I915_WRITE(IER
, enable_mask
);
2870 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2871 POSTING_READ(PORT_HOTPLUG_EN
);
2873 i915_enable_asle_pipestat(dev
);
2878 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2880 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2881 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2882 struct intel_encoder
*intel_encoder
;
2885 assert_spin_locked(&dev_priv
->irq_lock
);
2887 if (I915_HAS_HOTPLUG(dev
)) {
2888 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2889 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2890 /* Note HDMI and DP share hotplug bits */
2891 /* enable bits are the same for all generations */
2892 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2893 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2894 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2895 /* Programming the CRT detection parameters tends
2896 to generate a spurious hotplug event about three
2897 seconds later. So just do it once.
2900 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2901 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2902 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2904 /* Ignore TV since it's buggy */
2905 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2909 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2911 struct drm_device
*dev
= (struct drm_device
*) arg
;
2912 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2914 u32 pipe_stats
[I915_MAX_PIPES
];
2915 unsigned long irqflags
;
2917 int ret
= IRQ_NONE
, pipe
;
2919 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2920 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2922 atomic_inc(&dev_priv
->irq_received
);
2924 iir
= I915_READ(IIR
);
2927 bool blc_event
= false;
2929 irq_received
= (iir
& ~flip_mask
) != 0;
2931 /* Can't rely on pipestat interrupt bit in iir as it might
2932 * have been cleared after the pipestat interrupt was received.
2933 * It doesn't set the bit in iir again, but it still produces
2934 * interrupts (for non-MSI).
2936 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2937 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2938 i915_handle_error(dev
, false);
2940 for_each_pipe(pipe
) {
2941 int reg
= PIPESTAT(pipe
);
2942 pipe_stats
[pipe
] = I915_READ(reg
);
2945 * Clear the PIPE*STAT regs before the IIR
2947 if (pipe_stats
[pipe
] & 0x8000ffff) {
2948 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2949 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2951 I915_WRITE(reg
, pipe_stats
[pipe
]);
2955 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2962 /* Consume port. Then clear IIR or we'll miss events */
2963 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2964 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2965 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2966 HOTPLUG_INT_STATUS_G4X
:
2967 HOTPLUG_INT_STATUS_I915
);
2969 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2972 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2973 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2975 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2976 I915_READ(PORT_HOTPLUG_STAT
);
2979 I915_WRITE(IIR
, iir
& ~flip_mask
);
2980 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2982 if (iir
& I915_USER_INTERRUPT
)
2983 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2984 if (iir
& I915_BSD_USER_INTERRUPT
)
2985 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2987 for_each_pipe(pipe
) {
2988 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2989 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2990 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2992 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2997 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2998 intel_opregion_asle_intr(dev
);
3000 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3001 gmbus_irq_handler(dev
);
3003 /* With MSI, interrupts are only generated when iir
3004 * transitions from zero to nonzero. If another bit got
3005 * set while we were handling the existing iir bits, then
3006 * we would never get another interrupt.
3008 * This is fine on non-MSI as well, as if we hit this path
3009 * we avoid exiting the interrupt handler only to generate
3012 * Note that for MSI this could cause a stray interrupt report
3013 * if an interrupt landed in the time between writing IIR and
3014 * the posting read. This should be rare enough to never
3015 * trigger the 99% of 100,000 interrupts test for disabling
3021 i915_update_dri1_breadcrumb(dev
);
3026 static void i965_irq_uninstall(struct drm_device
* dev
)
3028 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3034 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3036 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3037 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3039 I915_WRITE(HWSTAM
, 0xffffffff);
3041 I915_WRITE(PIPESTAT(pipe
), 0);
3042 I915_WRITE(IMR
, 0xffffffff);
3043 I915_WRITE(IER
, 0x0);
3046 I915_WRITE(PIPESTAT(pipe
),
3047 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3048 I915_WRITE(IIR
, I915_READ(IIR
));
3051 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3053 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3054 struct drm_device
*dev
= dev_priv
->dev
;
3055 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3056 unsigned long irqflags
;
3059 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3060 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3061 struct drm_connector
*connector
;
3063 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3066 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3068 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3069 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3071 if (intel_connector
->encoder
->hpd_pin
== i
) {
3072 if (connector
->polled
!= intel_connector
->polled
)
3073 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3074 drm_get_connector_name(connector
));
3075 connector
->polled
= intel_connector
->polled
;
3076 if (!connector
->polled
)
3077 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3081 if (dev_priv
->display
.hpd_irq_setup
)
3082 dev_priv
->display
.hpd_irq_setup(dev
);
3083 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3086 void intel_irq_init(struct drm_device
*dev
)
3088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3090 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3091 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3092 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3093 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3095 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3096 i915_hangcheck_elapsed
,
3097 (unsigned long) dev
);
3098 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3099 (unsigned long) dev_priv
);
3101 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3103 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3104 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3105 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3106 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3107 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3110 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3111 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3113 dev
->driver
->get_vblank_timestamp
= NULL
;
3114 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3116 if (IS_VALLEYVIEW(dev
)) {
3117 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3118 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3119 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3120 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3121 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3122 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3123 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3124 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3125 /* Share uninstall handlers with ILK/SNB */
3126 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
3127 dev
->driver
->irq_preinstall
= ivybridge_irq_preinstall
;
3128 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3129 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3130 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3131 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3132 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3133 } else if (HAS_PCH_SPLIT(dev
)) {
3134 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3135 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3136 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3137 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3138 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3139 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3140 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3142 if (INTEL_INFO(dev
)->gen
== 2) {
3143 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3144 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3145 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3146 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3147 } else if (INTEL_INFO(dev
)->gen
== 3) {
3148 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3149 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3150 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3151 dev
->driver
->irq_handler
= i915_irq_handler
;
3152 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3154 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3155 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3156 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3157 dev
->driver
->irq_handler
= i965_irq_handler
;
3158 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3160 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3161 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3165 void intel_hpd_init(struct drm_device
*dev
)
3167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3168 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3169 struct drm_connector
*connector
;
3170 unsigned long irqflags
;
3173 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3174 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3175 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3177 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3178 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3179 connector
->polled
= intel_connector
->polled
;
3180 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3181 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3184 /* Interrupt setup is already guaranteed to be single-threaded, this is
3185 * just to make the assert_spin_locked checks happy. */
3186 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3187 if (dev_priv
->display
.hpd_irq_setup
)
3188 dev_priv
->display
.hpd_irq_setup(dev
);
3189 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);