1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
107 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
110 struct intel_crtc
*crtc
;
113 assert_spin_locked(&dev_priv
->irq_lock
);
115 for_each_pipe(pipe
) {
116 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
118 if (crtc
->cpu_fifo_underrun_disabled
)
125 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
129 struct intel_crtc
*crtc
;
131 assert_spin_locked(&dev_priv
->irq_lock
);
133 for_each_pipe(pipe
) {
134 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
136 if (crtc
->pch_fifo_underrun_disabled
)
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
144 enum pipe pipe
, bool enable
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
147 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
148 DE_PIPEB_FIFO_UNDERRUN
;
151 ironlake_enable_display_irq(dev_priv
, bit
);
153 ironlake_disable_display_irq(dev_priv
, bit
);
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
157 enum pipe pipe
, bool enable
)
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
163 if (!ivb_can_enable_err_int(dev
))
166 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
168 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
174 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
187 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
188 uint32_t interrupt_mask
,
189 uint32_t enabled_irq_mask
)
191 uint32_t sdeimr
= I915_READ(SDEIMR
);
192 sdeimr
&= ~interrupt_mask
;
193 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
195 assert_spin_locked(&dev_priv
->irq_lock
);
197 I915_WRITE(SDEIMR
, sdeimr
);
198 POSTING_READ(SDEIMR
);
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
205 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
206 enum transcoder pch_transcoder
,
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
211 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
214 ibx_enable_display_interrupt(dev_priv
, bit
);
216 ibx_disable_display_interrupt(dev_priv
, bit
);
219 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum transcoder pch_transcoder
,
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
229 if (!cpt_can_enable_serr_int(dev
))
232 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
234 uint32_t tmp
= I915_READ(SERR_INT
);
235 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
241 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder
));
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
260 * Returns the previous state of underrun reporting.
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
263 enum pipe pipe
, bool enable
)
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
271 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
273 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
278 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
280 if (IS_GEN5(dev
) || IS_GEN6(dev
))
281 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
282 else if (IS_GEN7(dev
))
283 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
286 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
302 * Returns the previous state of underrun reporting.
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
305 enum transcoder pch_transcoder
,
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
323 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
325 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
330 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
332 if (HAS_PCH_IBX(dev
))
333 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
335 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
338 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
344 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
346 u32 reg
= PIPESTAT(pipe
);
347 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
349 assert_spin_locked(&dev_priv
->irq_lock
);
351 if ((pipestat
& mask
) == mask
)
354 /* Enable the interrupt, clear any pending status */
355 pipestat
|= mask
| (mask
>> 16);
356 I915_WRITE(reg
, pipestat
);
361 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
363 u32 reg
= PIPESTAT(pipe
);
364 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
366 assert_spin_locked(&dev_priv
->irq_lock
);
368 if ((pipestat
& mask
) == 0)
372 I915_WRITE(reg
, pipestat
);
377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
379 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
381 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
382 unsigned long irqflags
;
384 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
387 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
389 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
390 if (INTEL_INFO(dev
)->gen
>= 4)
391 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
393 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
397 * i915_pipe_enabled - check if a pipe is enabled
399 * @pipe: pipe to check
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
406 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
408 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
410 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 return intel_crtc
->active
;
417 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
421 /* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
424 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
427 unsigned long high_frame
;
428 unsigned long low_frame
;
429 u32 high1
, high2
, low
;
431 if (!i915_pipe_enabled(dev
, pipe
)) {
432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
433 "pipe %c\n", pipe_name(pipe
));
437 high_frame
= PIPEFRAME(pipe
);
438 low_frame
= PIPEFRAMEPIXEL(pipe
);
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
446 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
447 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
448 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
449 } while (high1
!= high2
);
451 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
452 low
>>= PIPE_FRAME_LOW_SHIFT
;
453 return (high1
<< 8) | low
;
456 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
458 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
459 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
461 if (!i915_pipe_enabled(dev
, pipe
)) {
462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
463 "pipe %c\n", pipe_name(pipe
));
467 return I915_READ(reg
);
470 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
471 int *vpos
, int *hpos
)
473 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
474 u32 vbl
= 0, position
= 0;
475 int vbl_start
, vbl_end
, htotal
, vtotal
;
478 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
481 if (!i915_pipe_enabled(dev
, pipe
)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
483 "pipe %c\n", pipe_name(pipe
));
488 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
490 if (INTEL_INFO(dev
)->gen
>= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
494 position
= I915_READ(PIPEDSL(pipe
));
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
499 *vpos
= position
& 0x1fff;
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
506 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
508 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
509 *vpos
= position
/ htotal
;
510 *hpos
= position
- (*vpos
* htotal
);
513 /* Query vblank area. */
514 vbl
= I915_READ(VBLANK(cpu_transcoder
));
516 /* Test position against vblank region. */
517 vbl_start
= vbl
& 0x1fff;
518 vbl_end
= (vbl
>> 16) & 0x1fff;
520 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl
&& (*vpos
>= vbl_start
))
525 *vpos
= *vpos
- vtotal
;
527 /* Readouts valid? */
529 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
533 ret
|= DRM_SCANOUTPOS_INVBL
;
538 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
540 struct timeval
*vblank_time
,
543 struct drm_crtc
*crtc
;
545 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
546 DRM_ERROR("Invalid crtc %d\n", pipe
);
550 /* Get drm_crtc to timestamp: */
551 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
553 DRM_ERROR("Invalid crtc %d\n", pipe
);
557 if (!crtc
->enabled
) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
562 /* Helper routine in DRM core does all the work: */
563 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
568 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
570 enum drm_connector_status old_status
;
572 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
573 old_status
= connector
->status
;
575 connector
->status
= connector
->funcs
->detect(connector
, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
578 drm_get_connector_name(connector
),
579 old_status
, connector
->status
);
580 return (old_status
!= connector
->status
);
584 * Handle hotplug events outside the interrupt handler proper.
586 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
588 static void i915_hotplug_work_func(struct work_struct
*work
)
590 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
592 struct drm_device
*dev
= dev_priv
->dev
;
593 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
594 struct intel_connector
*intel_connector
;
595 struct intel_encoder
*intel_encoder
;
596 struct drm_connector
*connector
;
597 unsigned long irqflags
;
598 bool hpd_disabled
= false;
599 bool changed
= false;
602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv
->enable_hotplug_processing
)
606 mutex_lock(&mode_config
->mutex
);
607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
609 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
611 hpd_event_bits
= dev_priv
->hpd_event_bits
;
612 dev_priv
->hpd_event_bits
= 0;
613 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
614 intel_connector
= to_intel_connector(connector
);
615 intel_encoder
= intel_connector
->encoder
;
616 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
617 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
618 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector
));
622 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
623 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT
;
627 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
636 drm_kms_helper_poll_enable(dev
);
637 mod_timer(&dev_priv
->hotplug_reenable_timer
,
638 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
641 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
643 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
644 intel_connector
= to_intel_connector(connector
);
645 intel_encoder
= intel_connector
->encoder
;
646 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
647 if (intel_encoder
->hot_plug
)
648 intel_encoder
->hot_plug(intel_encoder
);
649 if (intel_hpd_irq_event(dev
, connector
))
653 mutex_unlock(&mode_config
->mutex
);
656 drm_kms_helper_hotplug_event(dev
);
659 static void ironlake_handle_rps_change(struct drm_device
*dev
)
661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 u32 busy_up
, busy_down
, max_avg
, min_avg
;
666 spin_lock_irqsave(&mchdev_lock
, flags
);
668 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
670 new_delay
= dev_priv
->ips
.cur_delay
;
672 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
673 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
674 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
675 max_avg
= I915_READ(RCBMAXAVG
);
676 min_avg
= I915_READ(RCBMINAVG
);
678 /* Handle RCS change request from hw */
679 if (busy_up
> max_avg
) {
680 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
681 new_delay
= dev_priv
->ips
.cur_delay
- 1;
682 if (new_delay
< dev_priv
->ips
.max_delay
)
683 new_delay
= dev_priv
->ips
.max_delay
;
684 } else if (busy_down
< min_avg
) {
685 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
686 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
687 if (new_delay
> dev_priv
->ips
.min_delay
)
688 new_delay
= dev_priv
->ips
.min_delay
;
691 if (ironlake_set_drps(dev
, new_delay
))
692 dev_priv
->ips
.cur_delay
= new_delay
;
694 spin_unlock_irqrestore(&mchdev_lock
, flags
);
699 static void notify_ring(struct drm_device
*dev
,
700 struct intel_ring_buffer
*ring
)
702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
704 if (ring
->obj
== NULL
)
707 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
709 wake_up_all(&ring
->irq_queue
);
710 if (i915_enable_hangcheck
) {
711 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
712 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
716 static void gen6_pm_rps_work(struct work_struct
*work
)
718 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
723 spin_lock_irq(&dev_priv
->rps
.lock
);
724 pm_iir
= dev_priv
->rps
.pm_iir
;
725 dev_priv
->rps
.pm_iir
= 0;
726 pm_imr
= I915_READ(GEN6_PMIMR
);
727 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
728 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
729 spin_unlock_irq(&dev_priv
->rps
.lock
);
731 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
734 mutex_lock(&dev_priv
->rps
.hw_lock
);
736 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
737 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
740 * For better performance, jump directly
741 * to RPe if we're below it.
743 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
744 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
745 new_delay
= dev_priv
->rps
.rpe_delay
;
747 new_delay
= dev_priv
->rps
.cur_delay
- 1;
749 /* sysfs frequency interfaces may have snuck in while servicing the
752 if (new_delay
>= dev_priv
->rps
.min_delay
&&
753 new_delay
<= dev_priv
->rps
.max_delay
) {
754 if (IS_VALLEYVIEW(dev_priv
->dev
))
755 valleyview_set_rps(dev_priv
->dev
, new_delay
);
757 gen6_set_rps(dev_priv
->dev
, new_delay
);
760 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
762 * On VLV, when we enter RC6 we may not be at the minimum
763 * voltage level, so arm a timer to check. It should only
764 * fire when there's activity or once after we've entered
765 * RC6, and then won't be re-armed until the next RPS interrupt.
767 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
768 msecs_to_jiffies(100));
771 mutex_unlock(&dev_priv
->rps
.hw_lock
);
776 * ivybridge_parity_work - Workqueue called when a parity error interrupt
778 * @work: workqueue struct
780 * Doesn't actually do anything except notify userspace. As a consequence of
781 * this event, userspace should try to remap the bad rows since statistically
782 * it is likely the same row is more likely to go bad again.
784 static void ivybridge_parity_work(struct work_struct
*work
)
786 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
787 l3_parity
.error_work
);
788 u32 error_status
, row
, bank
, subbank
;
789 char *parity_event
[5];
793 /* We must turn off DOP level clock gating to access the L3 registers.
794 * In order to prevent a get/put style interface, acquire struct mutex
795 * any time we access those registers.
797 mutex_lock(&dev_priv
->dev
->struct_mutex
);
799 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
800 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
801 POSTING_READ(GEN7_MISCCPCTL
);
803 error_status
= I915_READ(GEN7_L3CDERRST1
);
804 row
= GEN7_PARITY_ERROR_ROW(error_status
);
805 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
806 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
808 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
809 GEN7_L3CDERRST1_ENABLE
);
810 POSTING_READ(GEN7_L3CDERRST1
);
812 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
814 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
815 dev_priv
->gt_irq_mask
&= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
816 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
817 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
819 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
821 parity_event
[0] = "L3_PARITY_ERROR=1";
822 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
823 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
824 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
825 parity_event
[4] = NULL
;
827 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
828 KOBJ_CHANGE
, parity_event
);
830 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
833 kfree(parity_event
[3]);
834 kfree(parity_event
[2]);
835 kfree(parity_event
[1]);
838 static void ivybridge_handle_parity_error(struct drm_device
*dev
)
840 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
843 if (!HAS_L3_GPU_CACHE(dev
))
846 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
847 dev_priv
->gt_irq_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
848 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
849 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
851 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
854 static void snb_gt_irq_handler(struct drm_device
*dev
,
855 struct drm_i915_private
*dev_priv
,
860 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
861 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
862 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
863 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
864 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
865 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
867 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
868 GT_BSD_CS_ERROR_INTERRUPT
|
869 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
870 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
871 i915_handle_error(dev
, false);
874 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
875 ivybridge_handle_parity_error(dev
);
878 /* Legacy way of handling PM interrupts */
879 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
885 * IIR bits should never already be set because IMR should
886 * prevent an interrupt from being shown in IIR. The warning
887 * displays a case where we've unsafely cleared
888 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
889 * type is not a problem, it displays a problem in the logic.
891 * The mask bit in IMR is cleared by dev_priv->rps.work.
894 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
895 dev_priv
->rps
.pm_iir
|= pm_iir
;
896 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
897 POSTING_READ(GEN6_PMIMR
);
898 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
900 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
903 #define HPD_STORM_DETECT_PERIOD 1000
904 #define HPD_STORM_THRESHOLD 5
906 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
910 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
912 bool storm_detected
= false;
914 if (!hotplug_trigger
)
917 spin_lock(&dev_priv
->irq_lock
);
918 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
920 if (!(hpd
[i
] & hotplug_trigger
) ||
921 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
924 dev_priv
->hpd_event_bits
|= (1 << i
);
925 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
926 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
927 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
928 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
929 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
930 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
931 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
932 dev_priv
->hpd_event_bits
&= ~(1 << i
);
933 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
934 storm_detected
= true;
936 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
941 dev_priv
->display
.hpd_irq_setup(dev
);
942 spin_unlock(&dev_priv
->irq_lock
);
944 queue_work(dev_priv
->wq
,
945 &dev_priv
->hotplug_work
);
948 static void gmbus_irq_handler(struct drm_device
*dev
)
950 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
952 wake_up_all(&dev_priv
->gmbus_wait_queue
);
955 static void dp_aux_irq_handler(struct drm_device
*dev
)
957 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
959 wake_up_all(&dev_priv
->gmbus_wait_queue
);
962 /* Unlike gen6_queue_rps_work() from which this function is originally derived,
963 * we must be able to deal with other PM interrupts. This is complicated because
964 * of the way in which we use the masks to defer the RPS work (which for
965 * posterity is necessary because of forcewake).
967 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
972 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
973 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
974 if (dev_priv
->rps
.pm_iir
) {
975 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
976 /* never want to mask useful interrupts. (also posting read) */
977 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
978 /* TODO: if queue_work is slow, move it out of the spinlock */
979 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
981 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
983 if (pm_iir
& ~GEN6_PM_RPS_EVENTS
) {
984 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
985 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
987 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
988 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
989 i915_handle_error(dev_priv
->dev
, false);
994 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
996 struct drm_device
*dev
= (struct drm_device
*) arg
;
997 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
998 u32 iir
, gt_iir
, pm_iir
;
999 irqreturn_t ret
= IRQ_NONE
;
1000 unsigned long irqflags
;
1002 u32 pipe_stats
[I915_MAX_PIPES
];
1004 atomic_inc(&dev_priv
->irq_received
);
1007 iir
= I915_READ(VLV_IIR
);
1008 gt_iir
= I915_READ(GTIIR
);
1009 pm_iir
= I915_READ(GEN6_PMIIR
);
1011 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1016 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1018 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1019 for_each_pipe(pipe
) {
1020 int reg
= PIPESTAT(pipe
);
1021 pipe_stats
[pipe
] = I915_READ(reg
);
1024 * Clear the PIPE*STAT regs before the IIR
1026 if (pipe_stats
[pipe
] & 0x8000ffff) {
1027 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1028 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1030 I915_WRITE(reg
, pipe_stats
[pipe
]);
1033 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1035 for_each_pipe(pipe
) {
1036 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1037 drm_handle_vblank(dev
, pipe
);
1039 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1040 intel_prepare_page_flip(dev
, pipe
);
1041 intel_finish_page_flip(dev
, pipe
);
1045 /* Consume port. Then clear IIR or we'll miss events */
1046 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1047 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1048 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1050 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1053 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1055 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1056 I915_READ(PORT_HOTPLUG_STAT
);
1059 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1060 gmbus_irq_handler(dev
);
1062 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1063 gen6_queue_rps_work(dev_priv
, pm_iir
);
1065 I915_WRITE(GTIIR
, gt_iir
);
1066 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1067 I915_WRITE(VLV_IIR
, iir
);
1074 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1076 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1078 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1080 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1082 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1083 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1084 SDE_AUDIO_POWER_SHIFT
);
1085 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1089 if (pch_iir
& SDE_AUX_MASK
)
1090 dp_aux_irq_handler(dev
);
1092 if (pch_iir
& SDE_GMBUS
)
1093 gmbus_irq_handler(dev
);
1095 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1096 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1098 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1099 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1101 if (pch_iir
& SDE_POISON
)
1102 DRM_ERROR("PCH poison interrupt\n");
1104 if (pch_iir
& SDE_FDI_MASK
)
1106 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1108 I915_READ(FDI_RX_IIR(pipe
)));
1110 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1111 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1113 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1114 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1116 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1117 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1119 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1121 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1122 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1124 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1127 static void ivb_err_int_handler(struct drm_device
*dev
)
1129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1130 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1132 if (err_int
& ERR_INT_POISON
)
1133 DRM_ERROR("Poison interrupt\n");
1135 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1136 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1137 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1139 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1140 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1141 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1143 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1144 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1145 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1147 I915_WRITE(GEN7_ERR_INT
, err_int
);
1150 static void cpt_serr_int_handler(struct drm_device
*dev
)
1152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1153 u32 serr_int
= I915_READ(SERR_INT
);
1155 if (serr_int
& SERR_INT_POISON
)
1156 DRM_ERROR("PCH poison interrupt\n");
1158 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1159 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1161 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1163 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1164 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1166 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1168 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1169 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1171 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1173 I915_WRITE(SERR_INT
, serr_int
);
1176 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1178 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1180 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1182 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1184 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1185 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1186 SDE_AUDIO_POWER_SHIFT_CPT
);
1187 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1191 if (pch_iir
& SDE_AUX_MASK_CPT
)
1192 dp_aux_irq_handler(dev
);
1194 if (pch_iir
& SDE_GMBUS_CPT
)
1195 gmbus_irq_handler(dev
);
1197 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1198 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1200 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1201 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1203 if (pch_iir
& SDE_FDI_MASK_CPT
)
1205 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1207 I915_READ(FDI_RX_IIR(pipe
)));
1209 if (pch_iir
& SDE_ERROR_CPT
)
1210 cpt_serr_int_handler(dev
);
1213 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
1215 struct drm_device
*dev
= (struct drm_device
*) arg
;
1216 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1217 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
= 0;
1218 irqreturn_t ret
= IRQ_NONE
;
1221 atomic_inc(&dev_priv
->irq_received
);
1223 /* We get interrupts on unclaimed registers, so check for this before we
1224 * do any I915_{READ,WRITE}. */
1225 if (IS_HASWELL(dev
) &&
1226 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1227 DRM_ERROR("Unclaimed register before interrupt\n");
1228 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1231 /* disable master interrupt before clearing iir */
1232 de_ier
= I915_READ(DEIER
);
1233 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1235 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1236 * interrupts will will be stored on its back queue, and then we'll be
1237 * able to process them after we restore SDEIER (as soon as we restore
1238 * it, we'll get an interrupt if SDEIIR still has something to process
1239 * due to its back queue). */
1240 if (!HAS_PCH_NOP(dev
)) {
1241 sde_ier
= I915_READ(SDEIER
);
1242 I915_WRITE(SDEIER
, 0);
1243 POSTING_READ(SDEIER
);
1246 /* On Haswell, also mask ERR_INT because we don't want to risk
1247 * generating "unclaimed register" interrupts from inside the interrupt
1249 if (IS_HASWELL(dev
)) {
1250 spin_lock(&dev_priv
->irq_lock
);
1251 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1252 spin_unlock(&dev_priv
->irq_lock
);
1255 gt_iir
= I915_READ(GTIIR
);
1257 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1258 I915_WRITE(GTIIR
, gt_iir
);
1262 de_iir
= I915_READ(DEIIR
);
1264 if (de_iir
& DE_ERR_INT_IVB
)
1265 ivb_err_int_handler(dev
);
1267 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1268 dp_aux_irq_handler(dev
);
1270 if (de_iir
& DE_GSE_IVB
)
1271 intel_opregion_asle_intr(dev
);
1273 for (i
= 0; i
< 3; i
++) {
1274 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1275 drm_handle_vblank(dev
, i
);
1276 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1277 intel_prepare_page_flip(dev
, i
);
1278 intel_finish_page_flip_plane(dev
, i
);
1282 /* check event from PCH */
1283 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1284 u32 pch_iir
= I915_READ(SDEIIR
);
1286 cpt_irq_handler(dev
, pch_iir
);
1288 /* clear PCH hotplug event before clear CPU irq */
1289 I915_WRITE(SDEIIR
, pch_iir
);
1292 I915_WRITE(DEIIR
, de_iir
);
1296 pm_iir
= I915_READ(GEN6_PMIIR
);
1298 if (IS_HASWELL(dev
))
1299 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1300 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1301 gen6_queue_rps_work(dev_priv
, pm_iir
);
1302 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1306 if (IS_HASWELL(dev
)) {
1307 spin_lock(&dev_priv
->irq_lock
);
1308 if (ivb_can_enable_err_int(dev
))
1309 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1310 spin_unlock(&dev_priv
->irq_lock
);
1313 I915_WRITE(DEIER
, de_ier
);
1314 POSTING_READ(DEIER
);
1315 if (!HAS_PCH_NOP(dev
)) {
1316 I915_WRITE(SDEIER
, sde_ier
);
1317 POSTING_READ(SDEIER
);
1323 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1324 struct drm_i915_private
*dev_priv
,
1328 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1329 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1330 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1331 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1334 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1336 struct drm_device
*dev
= (struct drm_device
*) arg
;
1337 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1339 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
1341 atomic_inc(&dev_priv
->irq_received
);
1343 /* disable master interrupt before clearing iir */
1344 de_ier
= I915_READ(DEIER
);
1345 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1346 POSTING_READ(DEIER
);
1348 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1349 * interrupts will will be stored on its back queue, and then we'll be
1350 * able to process them after we restore SDEIER (as soon as we restore
1351 * it, we'll get an interrupt if SDEIIR still has something to process
1352 * due to its back queue). */
1353 sde_ier
= I915_READ(SDEIER
);
1354 I915_WRITE(SDEIER
, 0);
1355 POSTING_READ(SDEIER
);
1357 de_iir
= I915_READ(DEIIR
);
1358 gt_iir
= I915_READ(GTIIR
);
1359 pm_iir
= I915_READ(GEN6_PMIIR
);
1361 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
1367 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1369 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1371 if (de_iir
& DE_AUX_CHANNEL_A
)
1372 dp_aux_irq_handler(dev
);
1374 if (de_iir
& DE_GSE
)
1375 intel_opregion_asle_intr(dev
);
1377 if (de_iir
& DE_PIPEA_VBLANK
)
1378 drm_handle_vblank(dev
, 0);
1380 if (de_iir
& DE_PIPEB_VBLANK
)
1381 drm_handle_vblank(dev
, 1);
1383 if (de_iir
& DE_POISON
)
1384 DRM_ERROR("Poison interrupt\n");
1386 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1387 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1388 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1390 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1391 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1392 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1394 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1395 intel_prepare_page_flip(dev
, 0);
1396 intel_finish_page_flip_plane(dev
, 0);
1399 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1400 intel_prepare_page_flip(dev
, 1);
1401 intel_finish_page_flip_plane(dev
, 1);
1404 /* check event from PCH */
1405 if (de_iir
& DE_PCH_EVENT
) {
1406 u32 pch_iir
= I915_READ(SDEIIR
);
1408 if (HAS_PCH_CPT(dev
))
1409 cpt_irq_handler(dev
, pch_iir
);
1411 ibx_irq_handler(dev
, pch_iir
);
1413 /* should clear PCH hotplug event before clear CPU irq */
1414 I915_WRITE(SDEIIR
, pch_iir
);
1417 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1418 ironlake_handle_rps_change(dev
);
1420 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_RPS_EVENTS
)
1421 gen6_queue_rps_work(dev_priv
, pm_iir
);
1423 I915_WRITE(GTIIR
, gt_iir
);
1424 I915_WRITE(DEIIR
, de_iir
);
1425 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1428 I915_WRITE(DEIER
, de_ier
);
1429 POSTING_READ(DEIER
);
1430 I915_WRITE(SDEIER
, sde_ier
);
1431 POSTING_READ(SDEIER
);
1437 * i915_error_work_func - do process context error handling work
1438 * @work: work struct
1440 * Fire an error uevent so userspace can see that a hang or error
1443 static void i915_error_work_func(struct work_struct
*work
)
1445 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1447 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1449 struct drm_device
*dev
= dev_priv
->dev
;
1450 struct intel_ring_buffer
*ring
;
1451 char *error_event
[] = { "ERROR=1", NULL
};
1452 char *reset_event
[] = { "RESET=1", NULL
};
1453 char *reset_done_event
[] = { "ERROR=0", NULL
};
1456 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1459 * Note that there's only one work item which does gpu resets, so we
1460 * need not worry about concurrent gpu resets potentially incrementing
1461 * error->reset_counter twice. We only need to take care of another
1462 * racing irq/hangcheck declaring the gpu dead for a second time. A
1463 * quick check for that is good enough: schedule_work ensures the
1464 * correct ordering between hang detection and this work item, and since
1465 * the reset in-progress bit is only ever set by code outside of this
1466 * work we don't need to worry about any other races.
1468 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1469 DRM_DEBUG_DRIVER("resetting chip\n");
1470 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1473 ret
= i915_reset(dev
);
1477 * After all the gem state is reset, increment the reset
1478 * counter and wake up everyone waiting for the reset to
1481 * Since unlock operations are a one-sided barrier only,
1482 * we need to insert a barrier here to order any seqno
1484 * the counter increment.
1486 smp_mb__before_atomic_inc();
1487 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1489 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1490 KOBJ_CHANGE
, reset_done_event
);
1492 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1495 for_each_ring(ring
, dev_priv
, i
)
1496 wake_up_all(&ring
->irq_queue
);
1498 intel_display_handle_reset(dev
);
1500 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1504 /* NB: please notice the memset */
1505 static void i915_get_extra_instdone(struct drm_device
*dev
,
1508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1509 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
1511 switch(INTEL_INFO(dev
)->gen
) {
1514 instdone
[0] = I915_READ(INSTDONE
);
1519 instdone
[0] = I915_READ(INSTDONE_I965
);
1520 instdone
[1] = I915_READ(INSTDONE1
);
1523 WARN_ONCE(1, "Unsupported platform\n");
1525 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
1526 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
1527 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
1528 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
1533 #ifdef CONFIG_DEBUG_FS
1534 static struct drm_i915_error_object
*
1535 i915_error_object_create_sized(struct drm_i915_private
*dev_priv
,
1536 struct drm_i915_gem_object
*src
,
1537 const int num_pages
)
1539 struct drm_i915_error_object
*dst
;
1543 if (src
== NULL
|| src
->pages
== NULL
)
1546 dst
= kmalloc(sizeof(*dst
) + num_pages
* sizeof(u32
*), GFP_ATOMIC
);
1550 reloc_offset
= dst
->gtt_offset
= i915_gem_obj_ggtt_offset(src
);
1551 for (i
= 0; i
< num_pages
; i
++) {
1552 unsigned long flags
;
1555 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
1559 local_irq_save(flags
);
1560 if (reloc_offset
< dev_priv
->gtt
.mappable_end
&&
1561 src
->has_global_gtt_mapping
) {
1564 /* Simply ignore tiling or any overlapping fence.
1565 * It's part of the error state, and this hopefully
1566 * captures what the GPU read.
1569 s
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
1571 memcpy_fromio(d
, s
, PAGE_SIZE
);
1572 io_mapping_unmap_atomic(s
);
1573 } else if (src
->stolen
) {
1574 unsigned long offset
;
1576 offset
= dev_priv
->mm
.stolen_base
;
1577 offset
+= src
->stolen
->start
;
1578 offset
+= i
<< PAGE_SHIFT
;
1580 memcpy_fromio(d
, (void __iomem
*) offset
, PAGE_SIZE
);
1585 page
= i915_gem_object_get_page(src
, i
);
1587 drm_clflush_pages(&page
, 1);
1589 s
= kmap_atomic(page
);
1590 memcpy(d
, s
, PAGE_SIZE
);
1593 drm_clflush_pages(&page
, 1);
1595 local_irq_restore(flags
);
1599 reloc_offset
+= PAGE_SIZE
;
1601 dst
->page_count
= num_pages
;
1607 kfree(dst
->pages
[i
]);
1611 #define i915_error_object_create(dev_priv, src) \
1612 i915_error_object_create_sized((dev_priv), (src), \
1613 (src)->base.size>>PAGE_SHIFT)
1616 i915_error_object_free(struct drm_i915_error_object
*obj
)
1623 for (page
= 0; page
< obj
->page_count
; page
++)
1624 kfree(obj
->pages
[page
]);
1630 i915_error_state_free(struct kref
*error_ref
)
1632 struct drm_i915_error_state
*error
= container_of(error_ref
,
1633 typeof(*error
), ref
);
1636 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
1637 i915_error_object_free(error
->ring
[i
].batchbuffer
);
1638 i915_error_object_free(error
->ring
[i
].ringbuffer
);
1639 i915_error_object_free(error
->ring
[i
].ctx
);
1640 kfree(error
->ring
[i
].requests
);
1643 kfree(error
->active_bo
);
1644 kfree(error
->overlay
);
1645 kfree(error
->display
);
1648 static void capture_bo(struct drm_i915_error_buffer
*err
,
1649 struct drm_i915_gem_object
*obj
)
1651 err
->size
= obj
->base
.size
;
1652 err
->name
= obj
->base
.name
;
1653 err
->rseqno
= obj
->last_read_seqno
;
1654 err
->wseqno
= obj
->last_write_seqno
;
1655 err
->gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
1656 err
->read_domains
= obj
->base
.read_domains
;
1657 err
->write_domain
= obj
->base
.write_domain
;
1658 err
->fence_reg
= obj
->fence_reg
;
1660 if (obj
->pin_count
> 0)
1662 if (obj
->user_pin_count
> 0)
1664 err
->tiling
= obj
->tiling_mode
;
1665 err
->dirty
= obj
->dirty
;
1666 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1667 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1668 err
->cache_level
= obj
->cache_level
;
1671 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1672 int count
, struct list_head
*head
)
1674 struct drm_i915_gem_object
*obj
;
1677 list_for_each_entry(obj
, head
, mm_list
) {
1678 capture_bo(err
++, obj
);
1686 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1687 int count
, struct list_head
*head
)
1689 struct drm_i915_gem_object
*obj
;
1692 list_for_each_entry(obj
, head
, global_list
) {
1693 if (obj
->pin_count
== 0)
1696 capture_bo(err
++, obj
);
1704 static void i915_gem_record_fences(struct drm_device
*dev
,
1705 struct drm_i915_error_state
*error
)
1707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1711 switch (INTEL_INFO(dev
)->gen
) {
1714 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++)
1715 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1719 for (i
= 0; i
< 16; i
++)
1720 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1723 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1724 for (i
= 0; i
< 8; i
++)
1725 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1727 for (i
= 0; i
< 8; i
++)
1728 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1736 static struct drm_i915_error_object
*
1737 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1738 struct intel_ring_buffer
*ring
)
1740 struct drm_i915_gem_object
*obj
;
1743 if (!ring
->get_seqno
)
1746 if (HAS_BROKEN_CS_TLB(dev_priv
->dev
)) {
1747 u32 acthd
= I915_READ(ACTHD
);
1749 if (WARN_ON(ring
->id
!= RCS
))
1752 obj
= ring
->private;
1753 if (acthd
>= i915_gem_obj_ggtt_offset(obj
) &&
1754 acthd
< i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
)
1755 return i915_error_object_create(dev_priv
, obj
);
1758 seqno
= ring
->get_seqno(ring
, false);
1759 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1760 if (obj
->ring
!= ring
)
1763 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1766 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1769 /* We need to copy these to an anonymous buffer as the simplest
1770 * method to avoid being overwritten by userspace.
1772 return i915_error_object_create(dev_priv
, obj
);
1778 static void i915_record_ring_state(struct drm_device
*dev
,
1779 struct drm_i915_error_state
*error
,
1780 struct intel_ring_buffer
*ring
)
1782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1784 if (INTEL_INFO(dev
)->gen
>= 6) {
1785 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1786 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1787 error
->semaphore_mboxes
[ring
->id
][0]
1788 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1789 error
->semaphore_mboxes
[ring
->id
][1]
1790 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1791 error
->semaphore_seqno
[ring
->id
][0] = ring
->sync_seqno
[0];
1792 error
->semaphore_seqno
[ring
->id
][1] = ring
->sync_seqno
[1];
1795 if (INTEL_INFO(dev
)->gen
>= 4) {
1796 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1797 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1798 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1799 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1800 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1801 if (ring
->id
== RCS
)
1802 error
->bbaddr
= I915_READ64(BB_ADDR
);
1804 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1805 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1806 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1807 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1810 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1811 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1812 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1813 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1814 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1815 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1816 error
->ctl
[ring
->id
] = I915_READ_CTL(ring
);
1818 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1819 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1823 static void i915_gem_record_active_context(struct intel_ring_buffer
*ring
,
1824 struct drm_i915_error_state
*error
,
1825 struct drm_i915_error_ring
*ering
)
1827 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1828 struct drm_i915_gem_object
*obj
;
1830 /* Currently render ring is the only HW context user */
1831 if (ring
->id
!= RCS
|| !error
->ccid
)
1834 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1835 if ((error
->ccid
& PAGE_MASK
) == i915_gem_obj_ggtt_offset(obj
)) {
1836 ering
->ctx
= i915_error_object_create_sized(dev_priv
,
1843 static void i915_gem_record_rings(struct drm_device
*dev
,
1844 struct drm_i915_error_state
*error
)
1846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1847 struct intel_ring_buffer
*ring
;
1848 struct drm_i915_gem_request
*request
;
1851 for_each_ring(ring
, dev_priv
, i
) {
1852 i915_record_ring_state(dev
, error
, ring
);
1854 error
->ring
[i
].batchbuffer
=
1855 i915_error_first_batchbuffer(dev_priv
, ring
);
1857 error
->ring
[i
].ringbuffer
=
1858 i915_error_object_create(dev_priv
, ring
->obj
);
1861 i915_gem_record_active_context(ring
, error
, &error
->ring
[i
]);
1864 list_for_each_entry(request
, &ring
->request_list
, list
)
1867 error
->ring
[i
].num_requests
= count
;
1868 error
->ring
[i
].requests
=
1869 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1871 if (error
->ring
[i
].requests
== NULL
) {
1872 error
->ring
[i
].num_requests
= 0;
1877 list_for_each_entry(request
, &ring
->request_list
, list
) {
1878 struct drm_i915_error_request
*erq
;
1880 erq
= &error
->ring
[i
].requests
[count
++];
1881 erq
->seqno
= request
->seqno
;
1882 erq
->jiffies
= request
->emitted_jiffies
;
1883 erq
->tail
= request
->tail
;
1888 static void i915_gem_capture_buffers(struct drm_i915_private
*dev_priv
,
1889 struct drm_i915_error_state
*error
)
1891 struct drm_i915_gem_object
*obj
;
1895 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1897 error
->active_bo_count
= i
;
1898 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1901 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1904 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1906 if (error
->active_bo
)
1908 error
->active_bo
+ error
->active_bo_count
;
1911 if (error
->active_bo
)
1912 error
->active_bo_count
=
1913 capture_active_bo(error
->active_bo
,
1914 error
->active_bo_count
,
1915 &dev_priv
->mm
.active_list
);
1917 if (error
->pinned_bo
)
1918 error
->pinned_bo_count
=
1919 capture_pinned_bo(error
->pinned_bo
,
1920 error
->pinned_bo_count
,
1921 &dev_priv
->mm
.bound_list
);
1925 * i915_capture_error_state - capture an error record for later analysis
1928 * Should be called when an error is detected (either a hang or an error
1929 * interrupt) to capture error state from the time of the error. Fills
1930 * out a structure which becomes available in debugfs for user level tools
1933 static void i915_capture_error_state(struct drm_device
*dev
)
1935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1936 struct drm_i915_error_state
*error
;
1937 unsigned long flags
;
1940 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1941 error
= dev_priv
->gpu_error
.first_error
;
1942 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1946 /* Account for pipe specific data like PIPE*STAT */
1947 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1949 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1953 DRM_INFO("capturing error event; look for more information in "
1954 "/sys/class/drm/card%d/error\n", dev
->primary
->index
);
1956 kref_init(&error
->ref
);
1957 error
->eir
= I915_READ(EIR
);
1958 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1959 if (HAS_HW_CONTEXTS(dev
))
1960 error
->ccid
= I915_READ(CCID
);
1962 if (HAS_PCH_SPLIT(dev
))
1963 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1964 else if (IS_VALLEYVIEW(dev
))
1965 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1966 else if (IS_GEN2(dev
))
1967 error
->ier
= I915_READ16(IER
);
1969 error
->ier
= I915_READ(IER
);
1971 if (INTEL_INFO(dev
)->gen
>= 6)
1972 error
->derrmr
= I915_READ(DERRMR
);
1974 if (IS_VALLEYVIEW(dev
))
1975 error
->forcewake
= I915_READ(FORCEWAKE_VLV
);
1976 else if (INTEL_INFO(dev
)->gen
>= 7)
1977 error
->forcewake
= I915_READ(FORCEWAKE_MT
);
1978 else if (INTEL_INFO(dev
)->gen
== 6)
1979 error
->forcewake
= I915_READ(FORCEWAKE
);
1981 if (!HAS_PCH_SPLIT(dev
))
1983 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1985 if (INTEL_INFO(dev
)->gen
>= 6) {
1986 error
->error
= I915_READ(ERROR_GEN6
);
1987 error
->done_reg
= I915_READ(DONE_REG
);
1990 if (INTEL_INFO(dev
)->gen
== 7)
1991 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1993 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1995 i915_gem_capture_buffers(dev_priv
, error
);
1996 i915_gem_record_fences(dev
, error
);
1997 i915_gem_record_rings(dev
, error
);
1999 do_gettimeofday(&error
->time
);
2001 error
->overlay
= intel_overlay_capture_error_state(dev
);
2002 error
->display
= intel_display_capture_error_state(dev
);
2004 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
2005 if (dev_priv
->gpu_error
.first_error
== NULL
) {
2006 dev_priv
->gpu_error
.first_error
= error
;
2009 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
2012 i915_error_state_free(&error
->ref
);
2015 void i915_destroy_error_state(struct drm_device
*dev
)
2017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2018 struct drm_i915_error_state
*error
;
2019 unsigned long flags
;
2021 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
2022 error
= dev_priv
->gpu_error
.first_error
;
2023 dev_priv
->gpu_error
.first_error
= NULL
;
2024 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
2027 kref_put(&error
->ref
, i915_error_state_free
);
2030 #define i915_capture_error_state(x)
2033 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2036 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2037 u32 eir
= I915_READ(EIR
);
2043 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2045 i915_get_extra_instdone(dev
, instdone
);
2048 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2049 u32 ipeir
= I915_READ(IPEIR_I965
);
2051 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2052 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2053 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2054 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2055 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2056 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2057 I915_WRITE(IPEIR_I965
, ipeir
);
2058 POSTING_READ(IPEIR_I965
);
2060 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2061 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2062 pr_err("page table error\n");
2063 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2064 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2065 POSTING_READ(PGTBL_ER
);
2069 if (!IS_GEN2(dev
)) {
2070 if (eir
& I915_ERROR_PAGE_TABLE
) {
2071 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2072 pr_err("page table error\n");
2073 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2074 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2075 POSTING_READ(PGTBL_ER
);
2079 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2080 pr_err("memory refresh error:\n");
2082 pr_err("pipe %c stat: 0x%08x\n",
2083 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2084 /* pipestat has already been acked */
2086 if (eir
& I915_ERROR_INSTRUCTION
) {
2087 pr_err("instruction error\n");
2088 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2089 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2090 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2091 if (INTEL_INFO(dev
)->gen
< 4) {
2092 u32 ipeir
= I915_READ(IPEIR
);
2094 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2095 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2096 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2097 I915_WRITE(IPEIR
, ipeir
);
2098 POSTING_READ(IPEIR
);
2100 u32 ipeir
= I915_READ(IPEIR_I965
);
2102 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2103 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2104 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2105 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2106 I915_WRITE(IPEIR_I965
, ipeir
);
2107 POSTING_READ(IPEIR_I965
);
2111 I915_WRITE(EIR
, eir
);
2113 eir
= I915_READ(EIR
);
2116 * some errors might have become stuck,
2119 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2120 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2121 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2126 * i915_handle_error - handle an error interrupt
2129 * Do some basic checking of regsiter state at error interrupt time and
2130 * dump it to the syslog. Also call i915_capture_error_state() to make
2131 * sure we get a record and make it available in debugfs. Fire a uevent
2132 * so userspace knows something bad happened (should trigger collection
2133 * of a ring dump etc.).
2135 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
2137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2138 struct intel_ring_buffer
*ring
;
2141 i915_capture_error_state(dev
);
2142 i915_report_and_clear_eir(dev
);
2145 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2146 &dev_priv
->gpu_error
.reset_counter
);
2149 * Wakeup waiting processes so that the reset work item
2150 * doesn't deadlock trying to grab various locks.
2152 for_each_ring(ring
, dev_priv
, i
)
2153 wake_up_all(&ring
->irq_queue
);
2156 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
2159 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2161 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2162 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2164 struct drm_i915_gem_object
*obj
;
2165 struct intel_unpin_work
*work
;
2166 unsigned long flags
;
2167 bool stall_detected
;
2169 /* Ignore early vblank irqs */
2170 if (intel_crtc
== NULL
)
2173 spin_lock_irqsave(&dev
->event_lock
, flags
);
2174 work
= intel_crtc
->unpin_work
;
2177 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2178 !work
->enable_stall_check
) {
2179 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2180 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2184 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2185 obj
= work
->pending_flip_obj
;
2186 if (INTEL_INFO(dev
)->gen
>= 4) {
2187 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2188 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2189 i915_gem_obj_ggtt_offset(obj
);
2191 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2192 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
2193 crtc
->y
* crtc
->fb
->pitches
[0] +
2194 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
2197 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2199 if (stall_detected
) {
2200 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2201 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2205 /* Called from drm generic code, passed 'crtc' which
2206 * we use as a pipe index
2208 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2210 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2211 unsigned long irqflags
;
2213 if (!i915_pipe_enabled(dev
, pipe
))
2216 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2217 if (INTEL_INFO(dev
)->gen
>= 4)
2218 i915_enable_pipestat(dev_priv
, pipe
,
2219 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2221 i915_enable_pipestat(dev_priv
, pipe
,
2222 PIPE_VBLANK_INTERRUPT_ENABLE
);
2224 /* maintain vblank delivery even in deep C-states */
2225 if (dev_priv
->info
->gen
== 3)
2226 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2227 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2232 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2234 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2235 unsigned long irqflags
;
2237 if (!i915_pipe_enabled(dev
, pipe
))
2240 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2241 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
2242 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2243 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2248 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
2250 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2251 unsigned long irqflags
;
2253 if (!i915_pipe_enabled(dev
, pipe
))
2256 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2257 ironlake_enable_display_irq(dev_priv
,
2258 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
2259 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2264 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2266 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2267 unsigned long irqflags
;
2270 if (!i915_pipe_enabled(dev
, pipe
))
2273 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2274 imr
= I915_READ(VLV_IMR
);
2276 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2278 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2279 I915_WRITE(VLV_IMR
, imr
);
2280 i915_enable_pipestat(dev_priv
, pipe
,
2281 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2282 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2287 /* Called from drm generic code, passed 'crtc' which
2288 * we use as a pipe index
2290 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2292 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2293 unsigned long irqflags
;
2295 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2296 if (dev_priv
->info
->gen
== 3)
2297 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2299 i915_disable_pipestat(dev_priv
, pipe
,
2300 PIPE_VBLANK_INTERRUPT_ENABLE
|
2301 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2302 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2305 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2307 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2308 unsigned long irqflags
;
2310 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2311 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
2312 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2313 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2316 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
2318 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2319 unsigned long irqflags
;
2321 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2322 ironlake_disable_display_irq(dev_priv
,
2323 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
2324 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2327 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2329 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2330 unsigned long irqflags
;
2333 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2334 i915_disable_pipestat(dev_priv
, pipe
,
2335 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2336 imr
= I915_READ(VLV_IMR
);
2338 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2340 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2341 I915_WRITE(VLV_IMR
, imr
);
2342 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2346 ring_last_seqno(struct intel_ring_buffer
*ring
)
2348 return list_entry(ring
->request_list
.prev
,
2349 struct drm_i915_gem_request
, list
)->seqno
;
2353 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2355 return (list_empty(&ring
->request_list
) ||
2356 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2359 static struct intel_ring_buffer
*
2360 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2362 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2363 u32 cmd
, ipehr
, acthd
, acthd_min
;
2365 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2366 if ((ipehr
& ~(0x3 << 16)) !=
2367 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2370 /* ACTHD is likely pointing to the dword after the actual command,
2371 * so scan backwards until we find the MBOX.
2373 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2374 acthd_min
= max((int)acthd
- 3 * 4, 0);
2376 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2381 if (acthd
< acthd_min
)
2385 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2386 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2389 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2391 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2392 struct intel_ring_buffer
*signaller
;
2395 ring
->hangcheck
.deadlock
= true;
2397 signaller
= semaphore_waits_for(ring
, &seqno
);
2398 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2401 /* cursory check for an unkickable deadlock */
2402 ctl
= I915_READ_CTL(signaller
);
2403 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2406 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2409 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2411 struct intel_ring_buffer
*ring
;
2414 for_each_ring(ring
, dev_priv
, i
)
2415 ring
->hangcheck
.deadlock
= false;
2418 static enum intel_ring_hangcheck_action
2419 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2421 struct drm_device
*dev
= ring
->dev
;
2422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2425 if (ring
->hangcheck
.acthd
!= acthd
)
2431 /* Is the chip hanging on a WAIT_FOR_EVENT?
2432 * If so we can simply poke the RB_WAIT bit
2433 * and break the hang. This should work on
2434 * all but the second generation chipsets.
2436 tmp
= I915_READ_CTL(ring
);
2437 if (tmp
& RING_WAIT
) {
2438 DRM_ERROR("Kicking stuck wait on %s\n",
2440 I915_WRITE_CTL(ring
, tmp
);
2444 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2445 switch (semaphore_passed(ring
)) {
2449 DRM_ERROR("Kicking stuck semaphore on %s\n",
2451 I915_WRITE_CTL(ring
, tmp
);
2462 * This is called when the chip hasn't reported back with completed
2463 * batchbuffers in a long time. We keep track per ring seqno progress and
2464 * if there are no progress, hangcheck score for that ring is increased.
2465 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2466 * we kick the ring. If we see no progress on three subsequent calls
2467 * we assume chip is wedged and try to fix it by resetting the chip.
2469 void i915_hangcheck_elapsed(unsigned long data
)
2471 struct drm_device
*dev
= (struct drm_device
*)data
;
2472 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2473 struct intel_ring_buffer
*ring
;
2475 int busy_count
= 0, rings_hung
= 0;
2476 bool stuck
[I915_NUM_RINGS
] = { 0 };
2482 if (!i915_enable_hangcheck
)
2485 for_each_ring(ring
, dev_priv
, i
) {
2489 semaphore_clear_deadlocks(dev_priv
);
2491 seqno
= ring
->get_seqno(ring
, false);
2492 acthd
= intel_ring_get_active_head(ring
);
2494 if (ring
->hangcheck
.seqno
== seqno
) {
2495 if (ring_idle(ring
, seqno
)) {
2496 if (waitqueue_active(&ring
->irq_queue
)) {
2497 /* Issue a wake-up to catch stuck h/w. */
2498 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2500 wake_up_all(&ring
->irq_queue
);
2501 ring
->hangcheck
.score
+= HUNG
;
2507 /* We always increment the hangcheck score
2508 * if the ring is busy and still processing
2509 * the same request, so that no single request
2510 * can run indefinitely (such as a chain of
2511 * batches). The only time we do not increment
2512 * the hangcheck score on this ring, if this
2513 * ring is in a legitimate wait for another
2514 * ring. In that case the waiting ring is a
2515 * victim and we want to be sure we catch the
2516 * right culprit. Then every time we do kick
2517 * the ring, add a small increment to the
2518 * score so that we can catch a batch that is
2519 * being repeatedly kicked and so responsible
2520 * for stalling the machine.
2522 ring
->hangcheck
.action
= ring_stuck(ring
,
2525 switch (ring
->hangcheck
.action
) {
2540 ring
->hangcheck
.score
+= score
;
2543 /* Gradually reduce the count so that we catch DoS
2544 * attempts across multiple batches.
2546 if (ring
->hangcheck
.score
> 0)
2547 ring
->hangcheck
.score
--;
2550 ring
->hangcheck
.seqno
= seqno
;
2551 ring
->hangcheck
.acthd
= acthd
;
2555 for_each_ring(ring
, dev_priv
, i
) {
2556 if (ring
->hangcheck
.score
> FIRE
) {
2557 DRM_ERROR("%s on %s\n",
2558 stuck
[i
] ? "stuck" : "no progress",
2565 return i915_handle_error(dev
, true);
2568 /* Reset timer case chip hangs without another request
2570 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2571 round_jiffies_up(jiffies
+
2572 DRM_I915_HANGCHECK_JIFFIES
));
2575 static void ibx_irq_preinstall(struct drm_device
*dev
)
2577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2579 if (HAS_PCH_NOP(dev
))
2582 /* south display irq */
2583 I915_WRITE(SDEIMR
, 0xffffffff);
2585 * SDEIER is also touched by the interrupt handler to work around missed
2586 * PCH interrupts. Hence we can't update it after the interrupt handler
2587 * is enabled - instead we unconditionally enable all PCH interrupt
2588 * sources here, but then only unmask them as needed with SDEIMR.
2590 I915_WRITE(SDEIER
, 0xffffffff);
2591 POSTING_READ(SDEIER
);
2596 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2598 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2600 atomic_set(&dev_priv
->irq_received
, 0);
2602 I915_WRITE(HWSTAM
, 0xeffe);
2604 /* XXX hotplug from PCH */
2606 I915_WRITE(DEIMR
, 0xffffffff);
2607 I915_WRITE(DEIER
, 0x0);
2608 POSTING_READ(DEIER
);
2611 I915_WRITE(GTIMR
, 0xffffffff);
2612 I915_WRITE(GTIER
, 0x0);
2613 POSTING_READ(GTIER
);
2615 ibx_irq_preinstall(dev
);
2618 static void ivybridge_irq_preinstall(struct drm_device
*dev
)
2620 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2622 atomic_set(&dev_priv
->irq_received
, 0);
2624 I915_WRITE(HWSTAM
, 0xeffe);
2626 /* XXX hotplug from PCH */
2628 I915_WRITE(DEIMR
, 0xffffffff);
2629 I915_WRITE(DEIER
, 0x0);
2630 POSTING_READ(DEIER
);
2633 I915_WRITE(GTIMR
, 0xffffffff);
2634 I915_WRITE(GTIER
, 0x0);
2635 POSTING_READ(GTIER
);
2637 /* Power management */
2638 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2639 I915_WRITE(GEN6_PMIER
, 0x0);
2640 POSTING_READ(GEN6_PMIER
);
2642 ibx_irq_preinstall(dev
);
2645 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2647 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2650 atomic_set(&dev_priv
->irq_received
, 0);
2653 I915_WRITE(VLV_IMR
, 0);
2654 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2655 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2656 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2659 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2660 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2661 I915_WRITE(GTIMR
, 0xffffffff);
2662 I915_WRITE(GTIER
, 0x0);
2663 POSTING_READ(GTIER
);
2665 I915_WRITE(DPINVGTT
, 0xff);
2667 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2668 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2670 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2671 I915_WRITE(VLV_IIR
, 0xffffffff);
2672 I915_WRITE(VLV_IMR
, 0xffffffff);
2673 I915_WRITE(VLV_IER
, 0x0);
2674 POSTING_READ(VLV_IER
);
2677 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2679 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2680 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2681 struct intel_encoder
*intel_encoder
;
2682 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2684 if (HAS_PCH_IBX(dev
)) {
2685 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2686 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2687 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2688 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2690 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2691 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2692 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2693 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2696 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2699 * Enable digital hotplug on the PCH, and configure the DP short pulse
2700 * duration to 2ms (which is the minimum in the Display Port spec)
2702 * This register is the same on all known PCH chips.
2704 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2705 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2706 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2707 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2708 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2709 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2712 static void ibx_irq_postinstall(struct drm_device
*dev
)
2714 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2717 if (HAS_PCH_NOP(dev
))
2720 if (HAS_PCH_IBX(dev
)) {
2721 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2722 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2724 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2726 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2729 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2730 I915_WRITE(SDEIMR
, ~mask
);
2733 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2735 unsigned long irqflags
;
2737 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2738 /* enable kind of interrupts always enabled */
2739 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2740 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2741 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2742 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2745 dev_priv
->irq_mask
= ~display_mask
;
2747 /* should always can generate irq */
2748 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2749 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2750 I915_WRITE(DEIER
, display_mask
|
2751 DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
);
2752 POSTING_READ(DEIER
);
2754 dev_priv
->gt_irq_mask
= ~0;
2756 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2757 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2759 gt_irqs
= GT_RENDER_USER_INTERRUPT
;
2762 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2764 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2765 ILK_BSD_USER_INTERRUPT
;
2767 I915_WRITE(GTIER
, gt_irqs
);
2768 POSTING_READ(GTIER
);
2770 ibx_irq_postinstall(dev
);
2772 if (IS_IRONLAKE_M(dev
)) {
2773 /* Enable PCU event interrupts
2775 * spinlocking not required here for correctness since interrupt
2776 * setup is guaranteed to run in single-threaded context. But we
2777 * need it to make the assert_spin_locked happy. */
2778 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2779 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2780 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2786 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2788 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2789 /* enable kind of interrupts always enabled */
2791 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2792 DE_PLANEC_FLIP_DONE_IVB
|
2793 DE_PLANEB_FLIP_DONE_IVB
|
2794 DE_PLANEA_FLIP_DONE_IVB
|
2795 DE_AUX_CHANNEL_A_IVB
|
2797 u32 pm_irqs
= GEN6_PM_RPS_EVENTS
;
2800 dev_priv
->irq_mask
= ~display_mask
;
2802 /* should always can generate irq */
2803 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2804 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2805 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2808 DE_PIPEC_VBLANK_IVB
|
2809 DE_PIPEB_VBLANK_IVB
|
2810 DE_PIPEA_VBLANK_IVB
);
2811 POSTING_READ(DEIER
);
2813 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2815 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2816 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2818 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2819 GT_BLT_USER_INTERRUPT
| GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2820 I915_WRITE(GTIER
, gt_irqs
);
2821 POSTING_READ(GTIER
);
2823 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2825 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
|
2826 PM_VEBOX_CS_ERROR_INTERRUPT
;
2828 /* Our enable/disable rps functions may touch these registers so
2829 * make sure to set a known state for only the non-RPS bits.
2830 * The RMW is extra paranoia since this should be called after being set
2831 * to a known state in preinstall.
2833 I915_WRITE(GEN6_PMIMR
,
2834 (I915_READ(GEN6_PMIMR
) | ~GEN6_PM_RPS_EVENTS
) & ~pm_irqs
);
2835 I915_WRITE(GEN6_PMIER
,
2836 (I915_READ(GEN6_PMIER
) & GEN6_PM_RPS_EVENTS
) | pm_irqs
);
2837 POSTING_READ(GEN6_PMIER
);
2839 ibx_irq_postinstall(dev
);
2844 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2846 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2849 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2850 unsigned long irqflags
;
2852 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2853 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2854 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2855 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2856 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2859 *Leave vblank interrupts masked initially. enable/disable will
2860 * toggle them based on usage.
2862 dev_priv
->irq_mask
= (~enable_mask
) |
2863 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2864 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2866 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2867 POSTING_READ(PORT_HOTPLUG_EN
);
2869 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2870 I915_WRITE(VLV_IER
, enable_mask
);
2871 I915_WRITE(VLV_IIR
, 0xffffffff);
2872 I915_WRITE(PIPESTAT(0), 0xffff);
2873 I915_WRITE(PIPESTAT(1), 0xffff);
2874 POSTING_READ(VLV_IER
);
2876 /* Interrupt setup is already guaranteed to be single-threaded, this is
2877 * just to make the assert_spin_locked check happy. */
2878 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2879 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2880 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2881 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2882 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2884 I915_WRITE(VLV_IIR
, 0xffffffff);
2885 I915_WRITE(VLV_IIR
, 0xffffffff);
2887 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2888 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2890 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2891 GT_BLT_USER_INTERRUPT
;
2892 I915_WRITE(GTIER
, gt_irqs
);
2893 POSTING_READ(GTIER
);
2895 /* ack & enable invalid PTE error interrupts */
2896 #if 0 /* FIXME: add support to irq handler for checking these bits */
2897 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2898 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2901 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2906 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2908 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2914 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2917 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2919 I915_WRITE(HWSTAM
, 0xffffffff);
2920 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2921 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2923 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2924 I915_WRITE(VLV_IIR
, 0xffffffff);
2925 I915_WRITE(VLV_IMR
, 0xffffffff);
2926 I915_WRITE(VLV_IER
, 0x0);
2927 POSTING_READ(VLV_IER
);
2930 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2932 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2937 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2939 I915_WRITE(HWSTAM
, 0xffffffff);
2941 I915_WRITE(DEIMR
, 0xffffffff);
2942 I915_WRITE(DEIER
, 0x0);
2943 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2945 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2947 I915_WRITE(GTIMR
, 0xffffffff);
2948 I915_WRITE(GTIER
, 0x0);
2949 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2951 if (HAS_PCH_NOP(dev
))
2954 I915_WRITE(SDEIMR
, 0xffffffff);
2955 I915_WRITE(SDEIER
, 0x0);
2956 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2957 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2958 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2961 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2963 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2966 atomic_set(&dev_priv
->irq_received
, 0);
2969 I915_WRITE(PIPESTAT(pipe
), 0);
2970 I915_WRITE16(IMR
, 0xffff);
2971 I915_WRITE16(IER
, 0x0);
2972 POSTING_READ16(IER
);
2975 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2977 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2980 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2982 /* Unmask the interrupts that we always want on. */
2983 dev_priv
->irq_mask
=
2984 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2985 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2986 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2987 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2988 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2989 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2992 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2993 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2994 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2995 I915_USER_INTERRUPT
);
2996 POSTING_READ16(IER
);
3002 * Returns true when a page flip has completed.
3004 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3007 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3008 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
3010 if (!drm_handle_vblank(dev
, pipe
))
3013 if ((iir
& flip_pending
) == 0)
3016 intel_prepare_page_flip(dev
, pipe
);
3018 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3019 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3020 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3021 * the flip is completed (no longer pending). Since this doesn't raise
3022 * an interrupt per se, we watch for the change at vblank.
3024 if (I915_READ16(ISR
) & flip_pending
)
3027 intel_finish_page_flip(dev
, pipe
);
3032 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3034 struct drm_device
*dev
= (struct drm_device
*) arg
;
3035 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3038 unsigned long irqflags
;
3042 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3043 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3045 atomic_inc(&dev_priv
->irq_received
);
3047 iir
= I915_READ16(IIR
);
3051 while (iir
& ~flip_mask
) {
3052 /* Can't rely on pipestat interrupt bit in iir as it might
3053 * have been cleared after the pipestat interrupt was received.
3054 * It doesn't set the bit in iir again, but it still produces
3055 * interrupts (for non-MSI).
3057 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3058 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3059 i915_handle_error(dev
, false);
3061 for_each_pipe(pipe
) {
3062 int reg
= PIPESTAT(pipe
);
3063 pipe_stats
[pipe
] = I915_READ(reg
);
3066 * Clear the PIPE*STAT regs before the IIR
3068 if (pipe_stats
[pipe
] & 0x8000ffff) {
3069 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3070 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3072 I915_WRITE(reg
, pipe_stats
[pipe
]);
3076 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3078 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3079 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3081 i915_update_dri1_breadcrumb(dev
);
3083 if (iir
& I915_USER_INTERRUPT
)
3084 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3086 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3087 i8xx_handle_vblank(dev
, 0, iir
))
3088 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
3090 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3091 i8xx_handle_vblank(dev
, 1, iir
))
3092 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
3100 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3102 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3105 for_each_pipe(pipe
) {
3106 /* Clear enable bits; then clear status bits */
3107 I915_WRITE(PIPESTAT(pipe
), 0);
3108 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3110 I915_WRITE16(IMR
, 0xffff);
3111 I915_WRITE16(IER
, 0x0);
3112 I915_WRITE16(IIR
, I915_READ16(IIR
));
3115 static void i915_irq_preinstall(struct drm_device
* dev
)
3117 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3120 atomic_set(&dev_priv
->irq_received
, 0);
3122 if (I915_HAS_HOTPLUG(dev
)) {
3123 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3124 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3127 I915_WRITE16(HWSTAM
, 0xeffe);
3129 I915_WRITE(PIPESTAT(pipe
), 0);
3130 I915_WRITE(IMR
, 0xffffffff);
3131 I915_WRITE(IER
, 0x0);
3135 static int i915_irq_postinstall(struct drm_device
*dev
)
3137 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3140 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3142 /* Unmask the interrupts that we always want on. */
3143 dev_priv
->irq_mask
=
3144 ~(I915_ASLE_INTERRUPT
|
3145 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3146 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3147 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3148 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3149 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3152 I915_ASLE_INTERRUPT
|
3153 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3154 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3155 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3156 I915_USER_INTERRUPT
;
3158 if (I915_HAS_HOTPLUG(dev
)) {
3159 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3160 POSTING_READ(PORT_HOTPLUG_EN
);
3162 /* Enable in IER... */
3163 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3164 /* and unmask in IMR */
3165 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3168 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3169 I915_WRITE(IER
, enable_mask
);
3172 i915_enable_asle_pipestat(dev
);
3178 * Returns true when a page flip has completed.
3180 static bool i915_handle_vblank(struct drm_device
*dev
,
3181 int plane
, int pipe
, u32 iir
)
3183 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3184 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3186 if (!drm_handle_vblank(dev
, pipe
))
3189 if ((iir
& flip_pending
) == 0)
3192 intel_prepare_page_flip(dev
, plane
);
3194 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3195 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3196 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3197 * the flip is completed (no longer pending). Since this doesn't raise
3198 * an interrupt per se, we watch for the change at vblank.
3200 if (I915_READ(ISR
) & flip_pending
)
3203 intel_finish_page_flip(dev
, pipe
);
3208 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3210 struct drm_device
*dev
= (struct drm_device
*) arg
;
3211 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3212 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3213 unsigned long irqflags
;
3215 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3216 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3217 int pipe
, ret
= IRQ_NONE
;
3219 atomic_inc(&dev_priv
->irq_received
);
3221 iir
= I915_READ(IIR
);
3223 bool irq_received
= (iir
& ~flip_mask
) != 0;
3224 bool blc_event
= false;
3226 /* Can't rely on pipestat interrupt bit in iir as it might
3227 * have been cleared after the pipestat interrupt was received.
3228 * It doesn't set the bit in iir again, but it still produces
3229 * interrupts (for non-MSI).
3231 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3232 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3233 i915_handle_error(dev
, false);
3235 for_each_pipe(pipe
) {
3236 int reg
= PIPESTAT(pipe
);
3237 pipe_stats
[pipe
] = I915_READ(reg
);
3239 /* Clear the PIPE*STAT regs before the IIR */
3240 if (pipe_stats
[pipe
] & 0x8000ffff) {
3241 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3242 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3244 I915_WRITE(reg
, pipe_stats
[pipe
]);
3245 irq_received
= true;
3248 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3253 /* Consume port. Then clear IIR or we'll miss events */
3254 if ((I915_HAS_HOTPLUG(dev
)) &&
3255 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
3256 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3257 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
3259 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3262 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
3264 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3265 POSTING_READ(PORT_HOTPLUG_STAT
);
3268 I915_WRITE(IIR
, iir
& ~flip_mask
);
3269 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3271 if (iir
& I915_USER_INTERRUPT
)
3272 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3274 for_each_pipe(pipe
) {
3279 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3280 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3281 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3283 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3287 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3288 intel_opregion_asle_intr(dev
);
3290 /* With MSI, interrupts are only generated when iir
3291 * transitions from zero to nonzero. If another bit got
3292 * set while we were handling the existing iir bits, then
3293 * we would never get another interrupt.
3295 * This is fine on non-MSI as well, as if we hit this path
3296 * we avoid exiting the interrupt handler only to generate
3299 * Note that for MSI this could cause a stray interrupt report
3300 * if an interrupt landed in the time between writing IIR and
3301 * the posting read. This should be rare enough to never
3302 * trigger the 99% of 100,000 interrupts test for disabling
3307 } while (iir
& ~flip_mask
);
3309 i915_update_dri1_breadcrumb(dev
);
3314 static void i915_irq_uninstall(struct drm_device
* dev
)
3316 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3319 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3321 if (I915_HAS_HOTPLUG(dev
)) {
3322 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3323 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3326 I915_WRITE16(HWSTAM
, 0xffff);
3327 for_each_pipe(pipe
) {
3328 /* Clear enable bits; then clear status bits */
3329 I915_WRITE(PIPESTAT(pipe
), 0);
3330 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3332 I915_WRITE(IMR
, 0xffffffff);
3333 I915_WRITE(IER
, 0x0);
3335 I915_WRITE(IIR
, I915_READ(IIR
));
3338 static void i965_irq_preinstall(struct drm_device
* dev
)
3340 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3343 atomic_set(&dev_priv
->irq_received
, 0);
3345 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3346 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3348 I915_WRITE(HWSTAM
, 0xeffe);
3350 I915_WRITE(PIPESTAT(pipe
), 0);
3351 I915_WRITE(IMR
, 0xffffffff);
3352 I915_WRITE(IER
, 0x0);
3356 static int i965_irq_postinstall(struct drm_device
*dev
)
3358 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3361 unsigned long irqflags
;
3363 /* Unmask the interrupts that we always want on. */
3364 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3365 I915_DISPLAY_PORT_INTERRUPT
|
3366 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3367 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3368 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3369 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3370 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3372 enable_mask
= ~dev_priv
->irq_mask
;
3373 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3374 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3375 enable_mask
|= I915_USER_INTERRUPT
;
3378 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3380 /* Interrupt setup is already guaranteed to be single-threaded, this is
3381 * just to make the assert_spin_locked check happy. */
3382 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3383 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
3384 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3387 * Enable some error detection, note the instruction error mask
3388 * bit is reserved, so we leave it masked.
3391 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3392 GM45_ERROR_MEM_PRIV
|
3393 GM45_ERROR_CP_PRIV
|
3394 I915_ERROR_MEMORY_REFRESH
);
3396 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3397 I915_ERROR_MEMORY_REFRESH
);
3399 I915_WRITE(EMR
, error_mask
);
3401 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3402 I915_WRITE(IER
, enable_mask
);
3405 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3406 POSTING_READ(PORT_HOTPLUG_EN
);
3408 i915_enable_asle_pipestat(dev
);
3413 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3415 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3416 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3417 struct intel_encoder
*intel_encoder
;
3420 assert_spin_locked(&dev_priv
->irq_lock
);
3422 if (I915_HAS_HOTPLUG(dev
)) {
3423 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3424 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3425 /* Note HDMI and DP share hotplug bits */
3426 /* enable bits are the same for all generations */
3427 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3428 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3429 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3430 /* Programming the CRT detection parameters tends
3431 to generate a spurious hotplug event about three
3432 seconds later. So just do it once.
3435 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3436 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3437 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3439 /* Ignore TV since it's buggy */
3440 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3444 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3446 struct drm_device
*dev
= (struct drm_device
*) arg
;
3447 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3449 u32 pipe_stats
[I915_MAX_PIPES
];
3450 unsigned long irqflags
;
3452 int ret
= IRQ_NONE
, pipe
;
3454 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3455 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3457 atomic_inc(&dev_priv
->irq_received
);
3459 iir
= I915_READ(IIR
);
3462 bool blc_event
= false;
3464 irq_received
= (iir
& ~flip_mask
) != 0;
3466 /* Can't rely on pipestat interrupt bit in iir as it might
3467 * have been cleared after the pipestat interrupt was received.
3468 * It doesn't set the bit in iir again, but it still produces
3469 * interrupts (for non-MSI).
3471 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3472 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3473 i915_handle_error(dev
, false);
3475 for_each_pipe(pipe
) {
3476 int reg
= PIPESTAT(pipe
);
3477 pipe_stats
[pipe
] = I915_READ(reg
);
3480 * Clear the PIPE*STAT regs before the IIR
3482 if (pipe_stats
[pipe
] & 0x8000ffff) {
3483 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3484 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3486 I915_WRITE(reg
, pipe_stats
[pipe
]);
3490 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3497 /* Consume port. Then clear IIR or we'll miss events */
3498 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3499 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3500 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3501 HOTPLUG_INT_STATUS_G4X
:
3502 HOTPLUG_INT_STATUS_I915
);
3504 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3507 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3508 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3510 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3511 I915_READ(PORT_HOTPLUG_STAT
);
3514 I915_WRITE(IIR
, iir
& ~flip_mask
);
3515 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3517 if (iir
& I915_USER_INTERRUPT
)
3518 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3519 if (iir
& I915_BSD_USER_INTERRUPT
)
3520 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3522 for_each_pipe(pipe
) {
3523 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3524 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3525 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3527 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3532 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3533 intel_opregion_asle_intr(dev
);
3535 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3536 gmbus_irq_handler(dev
);
3538 /* With MSI, interrupts are only generated when iir
3539 * transitions from zero to nonzero. If another bit got
3540 * set while we were handling the existing iir bits, then
3541 * we would never get another interrupt.
3543 * This is fine on non-MSI as well, as if we hit this path
3544 * we avoid exiting the interrupt handler only to generate
3547 * Note that for MSI this could cause a stray interrupt report
3548 * if an interrupt landed in the time between writing IIR and
3549 * the posting read. This should be rare enough to never
3550 * trigger the 99% of 100,000 interrupts test for disabling
3556 i915_update_dri1_breadcrumb(dev
);
3561 static void i965_irq_uninstall(struct drm_device
* dev
)
3563 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3569 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3571 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3572 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3574 I915_WRITE(HWSTAM
, 0xffffffff);
3576 I915_WRITE(PIPESTAT(pipe
), 0);
3577 I915_WRITE(IMR
, 0xffffffff);
3578 I915_WRITE(IER
, 0x0);
3581 I915_WRITE(PIPESTAT(pipe
),
3582 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3583 I915_WRITE(IIR
, I915_READ(IIR
));
3586 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3588 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3589 struct drm_device
*dev
= dev_priv
->dev
;
3590 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3591 unsigned long irqflags
;
3594 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3595 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3596 struct drm_connector
*connector
;
3598 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3601 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3603 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3604 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3606 if (intel_connector
->encoder
->hpd_pin
== i
) {
3607 if (connector
->polled
!= intel_connector
->polled
)
3608 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3609 drm_get_connector_name(connector
));
3610 connector
->polled
= intel_connector
->polled
;
3611 if (!connector
->polled
)
3612 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3616 if (dev_priv
->display
.hpd_irq_setup
)
3617 dev_priv
->display
.hpd_irq_setup(dev
);
3618 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3621 void intel_irq_init(struct drm_device
*dev
)
3623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3625 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3626 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3627 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3628 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3630 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3631 i915_hangcheck_elapsed
,
3632 (unsigned long) dev
);
3633 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3634 (unsigned long) dev_priv
);
3636 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3638 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3639 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3640 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3641 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3642 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3645 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3646 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3648 dev
->driver
->get_vblank_timestamp
= NULL
;
3649 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3651 if (IS_VALLEYVIEW(dev
)) {
3652 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3653 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3654 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3655 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3656 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3657 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3658 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3659 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3660 /* Share uninstall handlers with ILK/SNB */
3661 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
3662 dev
->driver
->irq_preinstall
= ivybridge_irq_preinstall
;
3663 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3664 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3665 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3666 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3667 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3668 } else if (HAS_PCH_SPLIT(dev
)) {
3669 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3670 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3671 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3672 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3673 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3674 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3675 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3677 if (INTEL_INFO(dev
)->gen
== 2) {
3678 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3679 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3680 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3681 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3682 } else if (INTEL_INFO(dev
)->gen
== 3) {
3683 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3684 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3685 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3686 dev
->driver
->irq_handler
= i915_irq_handler
;
3687 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3689 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3690 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3691 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3692 dev
->driver
->irq_handler
= i965_irq_handler
;
3693 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3695 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3696 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3700 void intel_hpd_init(struct drm_device
*dev
)
3702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3703 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3704 struct drm_connector
*connector
;
3705 unsigned long irqflags
;
3708 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3709 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3710 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3712 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3713 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3714 connector
->polled
= intel_connector
->polled
;
3715 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3716 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3719 /* Interrupt setup is already guaranteed to be single-threaded, this is
3720 * just to make the assert_spin_locked checks happy. */
3721 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3722 if (dev_priv
->display
.hpd_irq_setup
)
3723 dev_priv
->display
.hpd_irq_setup(dev
);
3724 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);