1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i965
[] = {
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I965
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I965
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
83 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
84 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
85 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
86 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
87 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
88 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
91 static void ibx_hpd_irq_setup(struct drm_device
*dev
);
92 static void i915_hpd_irq_setup(struct drm_device
*dev
);
94 /* For display hotplug interrupt */
96 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 if ((dev_priv
->irq_mask
& mask
) != 0) {
99 dev_priv
->irq_mask
&= ~mask
;
100 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
106 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
108 if ((dev_priv
->irq_mask
& mask
) != mask
) {
109 dev_priv
->irq_mask
|= mask
;
110 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
115 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct intel_crtc
*crtc
;
121 for_each_pipe(pipe
) {
122 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
124 if (crtc
->cpu_fifo_underrun_disabled
)
131 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 struct intel_crtc
*crtc
;
137 for_each_pipe(pipe
) {
138 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
140 if (crtc
->pch_fifo_underrun_disabled
)
147 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
148 enum pipe pipe
, bool enable
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
152 DE_PIPEB_FIFO_UNDERRUN
;
155 ironlake_enable_display_irq(dev_priv
, bit
);
157 ironlake_disable_display_irq(dev_priv
, bit
);
160 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
166 if (!ivb_can_enable_err_int(dev
))
169 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN_A
|
170 ERR_INT_FIFO_UNDERRUN_B
|
171 ERR_INT_FIFO_UNDERRUN_C
);
173 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
175 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
179 static void ibx_set_fifo_underrun_reporting(struct intel_crtc
*crtc
,
182 struct drm_device
*dev
= crtc
->base
.dev
;
183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
184 uint32_t bit
= (crtc
->pipe
== PIPE_A
) ? SDE_TRANSA_FIFO_UNDER
:
185 SDE_TRANSB_FIFO_UNDER
;
188 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) & ~bit
);
190 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) | bit
);
192 POSTING_READ(SDEIMR
);
195 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
196 enum transcoder pch_transcoder
,
199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
202 if (!cpt_can_enable_serr_int(dev
))
205 I915_WRITE(SERR_INT
, SERR_INT_TRANS_A_FIFO_UNDERRUN
|
206 SERR_INT_TRANS_B_FIFO_UNDERRUN
|
207 SERR_INT_TRANS_C_FIFO_UNDERRUN
);
209 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) & ~SDE_ERROR_CPT
);
211 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) | SDE_ERROR_CPT
);
214 POSTING_READ(SDEIMR
);
218 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
221 * @enable: true if we want to report FIFO underrun errors, false otherwise
223 * This function makes us disable or enable CPU fifo underruns for a specific
224 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
225 * reporting for one pipe may also disable all the other CPU error interruts for
226 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 * bit for all the pipes.
229 * Returns the previous state of underrun reporting.
231 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
232 enum pipe pipe
, bool enable
)
234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
235 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
240 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
242 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
247 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
249 if (IS_GEN5(dev
) || IS_GEN6(dev
))
250 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
251 else if (IS_GEN7(dev
))
252 ivybridge_set_fifo_underrun_reporting(dev
, enable
);
255 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
260 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
262 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
263 * @enable: true if we want to report FIFO underrun errors, false otherwise
265 * This function makes us disable or enable PCH fifo underruns for a specific
266 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
267 * underrun reporting for one transcoder may also disable all the other PCH
268 * error interruts for the other transcoders, due to the fact that there's just
269 * one interrupt mask/enable bit for all the transcoders.
271 * Returns the previous state of underrun reporting.
273 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
274 enum transcoder pch_transcoder
,
277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
279 struct drm_crtc
*crtc
;
280 struct intel_crtc
*intel_crtc
;
284 if (HAS_PCH_LPT(dev
)) {
287 struct drm_crtc
*c
= dev_priv
->pipe_to_crtc_mapping
[p
];
288 if (intel_pipe_has_type(c
, INTEL_OUTPUT_ANALOG
)) {
294 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
298 crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
300 intel_crtc
= to_intel_crtc(crtc
);
302 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
304 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
309 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
311 if (HAS_PCH_IBX(dev
))
312 ibx_set_fifo_underrun_reporting(intel_crtc
, enable
);
314 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
317 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
323 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
325 u32 reg
= PIPESTAT(pipe
);
326 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
328 if ((pipestat
& mask
) == mask
)
331 /* Enable the interrupt, clear any pending status */
332 pipestat
|= mask
| (mask
>> 16);
333 I915_WRITE(reg
, pipestat
);
338 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
340 u32 reg
= PIPESTAT(pipe
);
341 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
343 if ((pipestat
& mask
) == 0)
347 I915_WRITE(reg
, pipestat
);
352 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
354 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
356 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
357 unsigned long irqflags
;
359 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
362 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
364 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
365 if (INTEL_INFO(dev
)->gen
>= 4)
366 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
368 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
372 * i915_pipe_enabled - check if a pipe is enabled
374 * @pipe: pipe to check
376 * Reading certain registers when the pipe is disabled can hang the chip.
377 * Use this routine to make sure the PLL is running and the pipe is active
378 * before reading such registers if unsure.
381 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
383 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
384 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
387 if (!intel_display_power_enabled(dev
,
388 POWER_DOMAIN_TRANSCODER(cpu_transcoder
)))
391 return I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_ENABLE
;
394 /* Called from drm generic code, passed a 'crtc', which
395 * we use as a pipe index
397 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
399 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
400 unsigned long high_frame
;
401 unsigned long low_frame
;
402 u32 high1
, high2
, low
;
404 if (!i915_pipe_enabled(dev
, pipe
)) {
405 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
406 "pipe %c\n", pipe_name(pipe
));
410 high_frame
= PIPEFRAME(pipe
);
411 low_frame
= PIPEFRAMEPIXEL(pipe
);
414 * High & low register fields aren't synchronized, so make sure
415 * we get a low value that's stable across two reads of the high
419 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
420 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
421 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
422 } while (high1
!= high2
);
424 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
425 low
>>= PIPE_FRAME_LOW_SHIFT
;
426 return (high1
<< 8) | low
;
429 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
431 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
432 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
434 if (!i915_pipe_enabled(dev
, pipe
)) {
435 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
436 "pipe %c\n", pipe_name(pipe
));
440 return I915_READ(reg
);
443 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
444 int *vpos
, int *hpos
)
446 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
447 u32 vbl
= 0, position
= 0;
448 int vbl_start
, vbl_end
, htotal
, vtotal
;
451 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
454 if (!i915_pipe_enabled(dev
, pipe
)) {
455 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
456 "pipe %c\n", pipe_name(pipe
));
461 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
463 if (INTEL_INFO(dev
)->gen
>= 4) {
464 /* No obvious pixelcount register. Only query vertical
465 * scanout position from Display scan line register.
467 position
= I915_READ(PIPEDSL(pipe
));
469 /* Decode into vertical scanout position. Don't have
470 * horizontal scanout position.
472 *vpos
= position
& 0x1fff;
475 /* Have access to pixelcount since start of frame.
476 * We can split this into vertical and horizontal
479 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
481 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
482 *vpos
= position
/ htotal
;
483 *hpos
= position
- (*vpos
* htotal
);
486 /* Query vblank area. */
487 vbl
= I915_READ(VBLANK(cpu_transcoder
));
489 /* Test position against vblank region. */
490 vbl_start
= vbl
& 0x1fff;
491 vbl_end
= (vbl
>> 16) & 0x1fff;
493 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
496 /* Inside "upper part" of vblank area? Apply corrective offset: */
497 if (in_vbl
&& (*vpos
>= vbl_start
))
498 *vpos
= *vpos
- vtotal
;
500 /* Readouts valid? */
502 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
506 ret
|= DRM_SCANOUTPOS_INVBL
;
511 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
513 struct timeval
*vblank_time
,
516 struct drm_crtc
*crtc
;
518 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
519 DRM_ERROR("Invalid crtc %d\n", pipe
);
523 /* Get drm_crtc to timestamp: */
524 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
526 DRM_ERROR("Invalid crtc %d\n", pipe
);
530 if (!crtc
->enabled
) {
531 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
535 /* Helper routine in DRM core does all the work: */
536 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
541 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
543 enum drm_connector_status old_status
;
545 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
546 old_status
= connector
->status
;
548 connector
->status
= connector
->funcs
->detect(connector
, false);
549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
551 drm_get_connector_name(connector
),
552 old_status
, connector
->status
);
553 return (old_status
!= connector
->status
);
557 * Handle hotplug events outside the interrupt handler proper.
559 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
561 static void i915_hotplug_work_func(struct work_struct
*work
)
563 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
565 struct drm_device
*dev
= dev_priv
->dev
;
566 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
567 struct intel_connector
*intel_connector
;
568 struct intel_encoder
*intel_encoder
;
569 struct drm_connector
*connector
;
570 unsigned long irqflags
;
571 bool hpd_disabled
= false;
572 bool changed
= false;
575 /* HPD irq before everything is fully set up. */
576 if (!dev_priv
->enable_hotplug_processing
)
579 mutex_lock(&mode_config
->mutex
);
580 DRM_DEBUG_KMS("running encoder hotplug functions\n");
582 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
584 hpd_event_bits
= dev_priv
->hpd_event_bits
;
585 dev_priv
->hpd_event_bits
= 0;
586 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
587 intel_connector
= to_intel_connector(connector
);
588 intel_encoder
= intel_connector
->encoder
;
589 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
590 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
591 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
592 DRM_INFO("HPD interrupt storm detected on connector %s: "
593 "switching from hotplug detection to polling\n",
594 drm_get_connector_name(connector
));
595 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
596 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
597 | DRM_CONNECTOR_POLL_DISCONNECT
;
600 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
601 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
602 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
605 /* if there were no outputs to poll, poll was disabled,
606 * therefore make sure it's enabled when disabling HPD on
609 drm_kms_helper_poll_enable(dev
);
610 mod_timer(&dev_priv
->hotplug_reenable_timer
,
611 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
614 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
616 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
617 intel_connector
= to_intel_connector(connector
);
618 intel_encoder
= intel_connector
->encoder
;
619 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
620 if (intel_encoder
->hot_plug
)
621 intel_encoder
->hot_plug(intel_encoder
);
622 if (intel_hpd_irq_event(dev
, connector
))
626 mutex_unlock(&mode_config
->mutex
);
629 drm_kms_helper_hotplug_event(dev
);
632 static void ironlake_handle_rps_change(struct drm_device
*dev
)
634 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
635 u32 busy_up
, busy_down
, max_avg
, min_avg
;
639 spin_lock_irqsave(&mchdev_lock
, flags
);
641 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
643 new_delay
= dev_priv
->ips
.cur_delay
;
645 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
646 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
647 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
648 max_avg
= I915_READ(RCBMAXAVG
);
649 min_avg
= I915_READ(RCBMINAVG
);
651 /* Handle RCS change request from hw */
652 if (busy_up
> max_avg
) {
653 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
654 new_delay
= dev_priv
->ips
.cur_delay
- 1;
655 if (new_delay
< dev_priv
->ips
.max_delay
)
656 new_delay
= dev_priv
->ips
.max_delay
;
657 } else if (busy_down
< min_avg
) {
658 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
659 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
660 if (new_delay
> dev_priv
->ips
.min_delay
)
661 new_delay
= dev_priv
->ips
.min_delay
;
664 if (ironlake_set_drps(dev
, new_delay
))
665 dev_priv
->ips
.cur_delay
= new_delay
;
667 spin_unlock_irqrestore(&mchdev_lock
, flags
);
672 static void notify_ring(struct drm_device
*dev
,
673 struct intel_ring_buffer
*ring
)
675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 if (ring
->obj
== NULL
)
680 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
682 wake_up_all(&ring
->irq_queue
);
683 if (i915_enable_hangcheck
) {
684 dev_priv
->gpu_error
.hangcheck_count
= 0;
685 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
686 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
690 static void gen6_pm_rps_work(struct work_struct
*work
)
692 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
697 spin_lock_irq(&dev_priv
->rps
.lock
);
698 pm_iir
= dev_priv
->rps
.pm_iir
;
699 dev_priv
->rps
.pm_iir
= 0;
700 pm_imr
= I915_READ(GEN6_PMIMR
);
701 I915_WRITE(GEN6_PMIMR
, 0);
702 spin_unlock_irq(&dev_priv
->rps
.lock
);
704 if ((pm_iir
& GEN6_PM_DEFERRED_EVENTS
) == 0)
707 mutex_lock(&dev_priv
->rps
.hw_lock
);
709 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
)
710 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
712 new_delay
= dev_priv
->rps
.cur_delay
- 1;
714 /* sysfs frequency interfaces may have snuck in while servicing the
717 if (!(new_delay
> dev_priv
->rps
.max_delay
||
718 new_delay
< dev_priv
->rps
.min_delay
)) {
719 if (IS_VALLEYVIEW(dev_priv
->dev
))
720 valleyview_set_rps(dev_priv
->dev
, new_delay
);
722 gen6_set_rps(dev_priv
->dev
, new_delay
);
725 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
727 * On VLV, when we enter RC6 we may not be at the minimum
728 * voltage level, so arm a timer to check. It should only
729 * fire when there's activity or once after we've entered
730 * RC6, and then won't be re-armed until the next RPS interrupt.
732 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
733 msecs_to_jiffies(100));
736 mutex_unlock(&dev_priv
->rps
.hw_lock
);
741 * ivybridge_parity_work - Workqueue called when a parity error interrupt
743 * @work: workqueue struct
745 * Doesn't actually do anything except notify userspace. As a consequence of
746 * this event, userspace should try to remap the bad rows since statistically
747 * it is likely the same row is more likely to go bad again.
749 static void ivybridge_parity_work(struct work_struct
*work
)
751 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
752 l3_parity
.error_work
);
753 u32 error_status
, row
, bank
, subbank
;
754 char *parity_event
[5];
758 /* We must turn off DOP level clock gating to access the L3 registers.
759 * In order to prevent a get/put style interface, acquire struct mutex
760 * any time we access those registers.
762 mutex_lock(&dev_priv
->dev
->struct_mutex
);
764 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
765 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
766 POSTING_READ(GEN7_MISCCPCTL
);
768 error_status
= I915_READ(GEN7_L3CDERRST1
);
769 row
= GEN7_PARITY_ERROR_ROW(error_status
);
770 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
771 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
773 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
774 GEN7_L3CDERRST1_ENABLE
);
775 POSTING_READ(GEN7_L3CDERRST1
);
777 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
779 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
780 dev_priv
->gt_irq_mask
&= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
781 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
782 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
784 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
786 parity_event
[0] = "L3_PARITY_ERROR=1";
787 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
788 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
789 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
790 parity_event
[4] = NULL
;
792 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
793 KOBJ_CHANGE
, parity_event
);
795 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
798 kfree(parity_event
[3]);
799 kfree(parity_event
[2]);
800 kfree(parity_event
[1]);
803 static void ivybridge_handle_parity_error(struct drm_device
*dev
)
805 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
808 if (!HAS_L3_GPU_CACHE(dev
))
811 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
812 dev_priv
->gt_irq_mask
|= GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
813 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
814 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
816 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
819 static void snb_gt_irq_handler(struct drm_device
*dev
,
820 struct drm_i915_private
*dev_priv
,
824 if (gt_iir
& (GEN6_RENDER_USER_INTERRUPT
|
825 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT
))
826 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
827 if (gt_iir
& GEN6_BSD_USER_INTERRUPT
)
828 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
829 if (gt_iir
& GEN6_BLITTER_USER_INTERRUPT
)
830 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
832 if (gt_iir
& (GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
833 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
834 GT_RENDER_CS_ERROR_INTERRUPT
)) {
835 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
836 i915_handle_error(dev
, false);
839 if (gt_iir
& GT_GEN7_L3_PARITY_ERROR_INTERRUPT
)
840 ivybridge_handle_parity_error(dev
);
843 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
849 * IIR bits should never already be set because IMR should
850 * prevent an interrupt from being shown in IIR. The warning
851 * displays a case where we've unsafely cleared
852 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
853 * type is not a problem, it displays a problem in the logic.
855 * The mask bit in IMR is cleared by dev_priv->rps.work.
858 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
859 dev_priv
->rps
.pm_iir
|= pm_iir
;
860 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
861 POSTING_READ(GEN6_PMIMR
);
862 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
864 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
867 #define HPD_STORM_DETECT_PERIOD 1000
868 #define HPD_STORM_THRESHOLD 5
870 static inline bool hotplug_irq_storm_detect(struct drm_device
*dev
,
874 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
875 unsigned long irqflags
;
879 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
881 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
883 if (!(hpd
[i
] & hotplug_trigger
) ||
884 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
887 dev_priv
->hpd_event_bits
|= (1 << i
);
888 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
889 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
890 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
891 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
892 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
893 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
894 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
895 dev_priv
->hpd_event_bits
&= ~(1 << i
);
896 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
899 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
903 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
908 static void gmbus_irq_handler(struct drm_device
*dev
)
910 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
912 wake_up_all(&dev_priv
->gmbus_wait_queue
);
915 static void dp_aux_irq_handler(struct drm_device
*dev
)
917 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
919 wake_up_all(&dev_priv
->gmbus_wait_queue
);
922 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
924 struct drm_device
*dev
= (struct drm_device
*) arg
;
925 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
926 u32 iir
, gt_iir
, pm_iir
;
927 irqreturn_t ret
= IRQ_NONE
;
928 unsigned long irqflags
;
930 u32 pipe_stats
[I915_MAX_PIPES
];
932 atomic_inc(&dev_priv
->irq_received
);
935 iir
= I915_READ(VLV_IIR
);
936 gt_iir
= I915_READ(GTIIR
);
937 pm_iir
= I915_READ(GEN6_PMIIR
);
939 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
944 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
946 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
947 for_each_pipe(pipe
) {
948 int reg
= PIPESTAT(pipe
);
949 pipe_stats
[pipe
] = I915_READ(reg
);
952 * Clear the PIPE*STAT regs before the IIR
954 if (pipe_stats
[pipe
] & 0x8000ffff) {
955 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
956 DRM_DEBUG_DRIVER("pipe %c underrun\n",
958 I915_WRITE(reg
, pipe_stats
[pipe
]);
961 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
963 for_each_pipe(pipe
) {
964 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
965 drm_handle_vblank(dev
, pipe
);
967 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
968 intel_prepare_page_flip(dev
, pipe
);
969 intel_finish_page_flip(dev
, pipe
);
973 /* Consume port. Then clear IIR or we'll miss events */
974 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
975 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
976 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
978 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
980 if (hotplug_trigger
) {
981 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_status_i915
))
982 i915_hpd_irq_setup(dev
);
983 queue_work(dev_priv
->wq
,
984 &dev_priv
->hotplug_work
);
986 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
987 I915_READ(PORT_HOTPLUG_STAT
);
990 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
991 gmbus_irq_handler(dev
);
993 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
994 gen6_queue_rps_work(dev_priv
, pm_iir
);
996 I915_WRITE(GTIIR
, gt_iir
);
997 I915_WRITE(GEN6_PMIIR
, pm_iir
);
998 I915_WRITE(VLV_IIR
, iir
);
1005 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1007 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1009 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1011 if (hotplug_trigger
) {
1012 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_ibx
))
1013 ibx_hpd_irq_setup(dev
);
1014 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
1016 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1017 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1018 SDE_AUDIO_POWER_SHIFT
);
1019 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1023 if (pch_iir
& SDE_AUX_MASK
)
1024 dp_aux_irq_handler(dev
);
1026 if (pch_iir
& SDE_GMBUS
)
1027 gmbus_irq_handler(dev
);
1029 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1030 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1032 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1033 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1035 if (pch_iir
& SDE_POISON
)
1036 DRM_ERROR("PCH poison interrupt\n");
1038 if (pch_iir
& SDE_FDI_MASK
)
1040 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1042 I915_READ(FDI_RX_IIR(pipe
)));
1044 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1045 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1047 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1048 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1050 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1051 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1053 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1055 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1056 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1058 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1061 static void ivb_err_int_handler(struct drm_device
*dev
)
1063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1064 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1066 if (err_int
& ERR_INT_POISON
)
1067 DRM_ERROR("Poison interrupt\n");
1069 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1070 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1071 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1073 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1074 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1075 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1077 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1078 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1079 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1081 I915_WRITE(GEN7_ERR_INT
, err_int
);
1084 static void cpt_serr_int_handler(struct drm_device
*dev
)
1086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1087 u32 serr_int
= I915_READ(SERR_INT
);
1089 if (serr_int
& SERR_INT_POISON
)
1090 DRM_ERROR("PCH poison interrupt\n");
1092 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1093 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1095 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1097 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1098 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1100 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1102 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1103 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1105 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1107 I915_WRITE(SERR_INT
, serr_int
);
1110 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1112 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1114 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1116 if (hotplug_trigger
) {
1117 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_cpt
))
1118 ibx_hpd_irq_setup(dev
);
1119 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
1121 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1122 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1123 SDE_AUDIO_POWER_SHIFT_CPT
);
1124 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1128 if (pch_iir
& SDE_AUX_MASK_CPT
)
1129 dp_aux_irq_handler(dev
);
1131 if (pch_iir
& SDE_GMBUS_CPT
)
1132 gmbus_irq_handler(dev
);
1134 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1135 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1137 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1138 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1140 if (pch_iir
& SDE_FDI_MASK_CPT
)
1142 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1144 I915_READ(FDI_RX_IIR(pipe
)));
1146 if (pch_iir
& SDE_ERROR_CPT
)
1147 cpt_serr_int_handler(dev
);
1150 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
1152 struct drm_device
*dev
= (struct drm_device
*) arg
;
1153 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1154 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
= 0;
1155 irqreturn_t ret
= IRQ_NONE
;
1158 atomic_inc(&dev_priv
->irq_received
);
1160 /* We get interrupts on unclaimed registers, so check for this before we
1161 * do any I915_{READ,WRITE}. */
1162 if (IS_HASWELL(dev
) &&
1163 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1164 DRM_ERROR("Unclaimed register before interrupt\n");
1165 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1168 /* disable master interrupt before clearing iir */
1169 de_ier
= I915_READ(DEIER
);
1170 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1172 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1173 * interrupts will will be stored on its back queue, and then we'll be
1174 * able to process them after we restore SDEIER (as soon as we restore
1175 * it, we'll get an interrupt if SDEIIR still has something to process
1176 * due to its back queue). */
1177 if (!HAS_PCH_NOP(dev
)) {
1178 sde_ier
= I915_READ(SDEIER
);
1179 I915_WRITE(SDEIER
, 0);
1180 POSTING_READ(SDEIER
);
1183 /* On Haswell, also mask ERR_INT because we don't want to risk
1184 * generating "unclaimed register" interrupts from inside the interrupt
1186 if (IS_HASWELL(dev
))
1187 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1189 gt_iir
= I915_READ(GTIIR
);
1191 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1192 I915_WRITE(GTIIR
, gt_iir
);
1196 de_iir
= I915_READ(DEIIR
);
1198 if (de_iir
& DE_ERR_INT_IVB
)
1199 ivb_err_int_handler(dev
);
1201 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1202 dp_aux_irq_handler(dev
);
1204 if (de_iir
& DE_GSE_IVB
)
1205 intel_opregion_asle_intr(dev
);
1207 for (i
= 0; i
< 3; i
++) {
1208 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1209 drm_handle_vblank(dev
, i
);
1210 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1211 intel_prepare_page_flip(dev
, i
);
1212 intel_finish_page_flip_plane(dev
, i
);
1216 /* check event from PCH */
1217 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1218 u32 pch_iir
= I915_READ(SDEIIR
);
1220 cpt_irq_handler(dev
, pch_iir
);
1222 /* clear PCH hotplug event before clear CPU irq */
1223 I915_WRITE(SDEIIR
, pch_iir
);
1226 I915_WRITE(DEIIR
, de_iir
);
1230 pm_iir
= I915_READ(GEN6_PMIIR
);
1232 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
1233 gen6_queue_rps_work(dev_priv
, pm_iir
);
1234 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1238 if (IS_HASWELL(dev
) && ivb_can_enable_err_int(dev
))
1239 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1241 I915_WRITE(DEIER
, de_ier
);
1242 POSTING_READ(DEIER
);
1243 if (!HAS_PCH_NOP(dev
)) {
1244 I915_WRITE(SDEIER
, sde_ier
);
1245 POSTING_READ(SDEIER
);
1251 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1252 struct drm_i915_private
*dev_priv
,
1255 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
1256 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1257 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1258 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1261 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1263 struct drm_device
*dev
= (struct drm_device
*) arg
;
1264 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1266 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
1268 atomic_inc(&dev_priv
->irq_received
);
1270 /* disable master interrupt before clearing iir */
1271 de_ier
= I915_READ(DEIER
);
1272 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1273 POSTING_READ(DEIER
);
1275 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1276 * interrupts will will be stored on its back queue, and then we'll be
1277 * able to process them after we restore SDEIER (as soon as we restore
1278 * it, we'll get an interrupt if SDEIIR still has something to process
1279 * due to its back queue). */
1280 sde_ier
= I915_READ(SDEIER
);
1281 I915_WRITE(SDEIER
, 0);
1282 POSTING_READ(SDEIER
);
1284 de_iir
= I915_READ(DEIIR
);
1285 gt_iir
= I915_READ(GTIIR
);
1286 pm_iir
= I915_READ(GEN6_PMIIR
);
1288 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
1294 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1296 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1298 if (de_iir
& DE_AUX_CHANNEL_A
)
1299 dp_aux_irq_handler(dev
);
1301 if (de_iir
& DE_GSE
)
1302 intel_opregion_asle_intr(dev
);
1304 if (de_iir
& DE_PIPEA_VBLANK
)
1305 drm_handle_vblank(dev
, 0);
1307 if (de_iir
& DE_PIPEB_VBLANK
)
1308 drm_handle_vblank(dev
, 1);
1310 if (de_iir
& DE_POISON
)
1311 DRM_ERROR("Poison interrupt\n");
1313 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1314 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1315 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1317 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1318 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1319 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1321 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1322 intel_prepare_page_flip(dev
, 0);
1323 intel_finish_page_flip_plane(dev
, 0);
1326 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1327 intel_prepare_page_flip(dev
, 1);
1328 intel_finish_page_flip_plane(dev
, 1);
1331 /* check event from PCH */
1332 if (de_iir
& DE_PCH_EVENT
) {
1333 u32 pch_iir
= I915_READ(SDEIIR
);
1335 if (HAS_PCH_CPT(dev
))
1336 cpt_irq_handler(dev
, pch_iir
);
1338 ibx_irq_handler(dev
, pch_iir
);
1340 /* should clear PCH hotplug event before clear CPU irq */
1341 I915_WRITE(SDEIIR
, pch_iir
);
1344 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1345 ironlake_handle_rps_change(dev
);
1347 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
1348 gen6_queue_rps_work(dev_priv
, pm_iir
);
1350 I915_WRITE(GTIIR
, gt_iir
);
1351 I915_WRITE(DEIIR
, de_iir
);
1352 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1355 I915_WRITE(DEIER
, de_ier
);
1356 POSTING_READ(DEIER
);
1357 I915_WRITE(SDEIER
, sde_ier
);
1358 POSTING_READ(SDEIER
);
1364 * i915_error_work_func - do process context error handling work
1365 * @work: work struct
1367 * Fire an error uevent so userspace can see that a hang or error
1370 static void i915_error_work_func(struct work_struct
*work
)
1372 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1374 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1376 struct drm_device
*dev
= dev_priv
->dev
;
1377 struct intel_ring_buffer
*ring
;
1378 char *error_event
[] = { "ERROR=1", NULL
};
1379 char *reset_event
[] = { "RESET=1", NULL
};
1380 char *reset_done_event
[] = { "ERROR=0", NULL
};
1383 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1386 * Note that there's only one work item which does gpu resets, so we
1387 * need not worry about concurrent gpu resets potentially incrementing
1388 * error->reset_counter twice. We only need to take care of another
1389 * racing irq/hangcheck declaring the gpu dead for a second time. A
1390 * quick check for that is good enough: schedule_work ensures the
1391 * correct ordering between hang detection and this work item, and since
1392 * the reset in-progress bit is only ever set by code outside of this
1393 * work we don't need to worry about any other races.
1395 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1396 DRM_DEBUG_DRIVER("resetting chip\n");
1397 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1400 ret
= i915_reset(dev
);
1404 * After all the gem state is reset, increment the reset
1405 * counter and wake up everyone waiting for the reset to
1408 * Since unlock operations are a one-sided barrier only,
1409 * we need to insert a barrier here to order any seqno
1411 * the counter increment.
1413 smp_mb__before_atomic_inc();
1414 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1416 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1417 KOBJ_CHANGE
, reset_done_event
);
1419 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1422 for_each_ring(ring
, dev_priv
, i
)
1423 wake_up_all(&ring
->irq_queue
);
1425 intel_display_handle_reset(dev
);
1427 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1431 /* NB: please notice the memset */
1432 static void i915_get_extra_instdone(struct drm_device
*dev
,
1435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1436 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
1438 switch(INTEL_INFO(dev
)->gen
) {
1441 instdone
[0] = I915_READ(INSTDONE
);
1446 instdone
[0] = I915_READ(INSTDONE_I965
);
1447 instdone
[1] = I915_READ(INSTDONE1
);
1450 WARN_ONCE(1, "Unsupported platform\n");
1452 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
1453 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
1454 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
1455 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
1460 #ifdef CONFIG_DEBUG_FS
1461 static struct drm_i915_error_object
*
1462 i915_error_object_create_sized(struct drm_i915_private
*dev_priv
,
1463 struct drm_i915_gem_object
*src
,
1464 const int num_pages
)
1466 struct drm_i915_error_object
*dst
;
1470 if (src
== NULL
|| src
->pages
== NULL
)
1473 dst
= kmalloc(sizeof(*dst
) + num_pages
* sizeof(u32
*), GFP_ATOMIC
);
1477 reloc_offset
= src
->gtt_offset
;
1478 for (i
= 0; i
< num_pages
; i
++) {
1479 unsigned long flags
;
1482 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
1486 local_irq_save(flags
);
1487 if (reloc_offset
< dev_priv
->gtt
.mappable_end
&&
1488 src
->has_global_gtt_mapping
) {
1491 /* Simply ignore tiling or any overlapping fence.
1492 * It's part of the error state, and this hopefully
1493 * captures what the GPU read.
1496 s
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
1498 memcpy_fromio(d
, s
, PAGE_SIZE
);
1499 io_mapping_unmap_atomic(s
);
1500 } else if (src
->stolen
) {
1501 unsigned long offset
;
1503 offset
= dev_priv
->mm
.stolen_base
;
1504 offset
+= src
->stolen
->start
;
1505 offset
+= i
<< PAGE_SHIFT
;
1507 memcpy_fromio(d
, (void __iomem
*) offset
, PAGE_SIZE
);
1512 page
= i915_gem_object_get_page(src
, i
);
1514 drm_clflush_pages(&page
, 1);
1516 s
= kmap_atomic(page
);
1517 memcpy(d
, s
, PAGE_SIZE
);
1520 drm_clflush_pages(&page
, 1);
1522 local_irq_restore(flags
);
1526 reloc_offset
+= PAGE_SIZE
;
1528 dst
->page_count
= num_pages
;
1529 dst
->gtt_offset
= src
->gtt_offset
;
1535 kfree(dst
->pages
[i
]);
1539 #define i915_error_object_create(dev_priv, src) \
1540 i915_error_object_create_sized((dev_priv), (src), \
1541 (src)->base.size>>PAGE_SHIFT)
1544 i915_error_object_free(struct drm_i915_error_object
*obj
)
1551 for (page
= 0; page
< obj
->page_count
; page
++)
1552 kfree(obj
->pages
[page
]);
1558 i915_error_state_free(struct kref
*error_ref
)
1560 struct drm_i915_error_state
*error
= container_of(error_ref
,
1561 typeof(*error
), ref
);
1564 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
1565 i915_error_object_free(error
->ring
[i
].batchbuffer
);
1566 i915_error_object_free(error
->ring
[i
].ringbuffer
);
1567 kfree(error
->ring
[i
].requests
);
1570 kfree(error
->active_bo
);
1571 kfree(error
->overlay
);
1574 static void capture_bo(struct drm_i915_error_buffer
*err
,
1575 struct drm_i915_gem_object
*obj
)
1577 err
->size
= obj
->base
.size
;
1578 err
->name
= obj
->base
.name
;
1579 err
->rseqno
= obj
->last_read_seqno
;
1580 err
->wseqno
= obj
->last_write_seqno
;
1581 err
->gtt_offset
= obj
->gtt_offset
;
1582 err
->read_domains
= obj
->base
.read_domains
;
1583 err
->write_domain
= obj
->base
.write_domain
;
1584 err
->fence_reg
= obj
->fence_reg
;
1586 if (obj
->pin_count
> 0)
1588 if (obj
->user_pin_count
> 0)
1590 err
->tiling
= obj
->tiling_mode
;
1591 err
->dirty
= obj
->dirty
;
1592 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1593 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1594 err
->cache_level
= obj
->cache_level
;
1597 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1598 int count
, struct list_head
*head
)
1600 struct drm_i915_gem_object
*obj
;
1603 list_for_each_entry(obj
, head
, mm_list
) {
1604 capture_bo(err
++, obj
);
1612 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1613 int count
, struct list_head
*head
)
1615 struct drm_i915_gem_object
*obj
;
1618 list_for_each_entry(obj
, head
, gtt_list
) {
1619 if (obj
->pin_count
== 0)
1622 capture_bo(err
++, obj
);
1630 static void i915_gem_record_fences(struct drm_device
*dev
,
1631 struct drm_i915_error_state
*error
)
1633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1637 switch (INTEL_INFO(dev
)->gen
) {
1640 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++)
1641 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1645 for (i
= 0; i
< 16; i
++)
1646 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1649 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1650 for (i
= 0; i
< 8; i
++)
1651 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1653 for (i
= 0; i
< 8; i
++)
1654 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1662 static struct drm_i915_error_object
*
1663 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1664 struct intel_ring_buffer
*ring
)
1666 struct drm_i915_gem_object
*obj
;
1669 if (!ring
->get_seqno
)
1672 if (HAS_BROKEN_CS_TLB(dev_priv
->dev
)) {
1673 u32 acthd
= I915_READ(ACTHD
);
1675 if (WARN_ON(ring
->id
!= RCS
))
1678 obj
= ring
->private;
1679 if (acthd
>= obj
->gtt_offset
&&
1680 acthd
< obj
->gtt_offset
+ obj
->base
.size
)
1681 return i915_error_object_create(dev_priv
, obj
);
1684 seqno
= ring
->get_seqno(ring
, false);
1685 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1686 if (obj
->ring
!= ring
)
1689 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1692 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1695 /* We need to copy these to an anonymous buffer as the simplest
1696 * method to avoid being overwritten by userspace.
1698 return i915_error_object_create(dev_priv
, obj
);
1704 static void i915_record_ring_state(struct drm_device
*dev
,
1705 struct drm_i915_error_state
*error
,
1706 struct intel_ring_buffer
*ring
)
1708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1710 if (INTEL_INFO(dev
)->gen
>= 6) {
1711 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1712 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1713 error
->semaphore_mboxes
[ring
->id
][0]
1714 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1715 error
->semaphore_mboxes
[ring
->id
][1]
1716 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1717 error
->semaphore_seqno
[ring
->id
][0] = ring
->sync_seqno
[0];
1718 error
->semaphore_seqno
[ring
->id
][1] = ring
->sync_seqno
[1];
1721 if (INTEL_INFO(dev
)->gen
>= 4) {
1722 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1723 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1724 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1725 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1726 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1727 if (ring
->id
== RCS
)
1728 error
->bbaddr
= I915_READ64(BB_ADDR
);
1730 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1731 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1732 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1733 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1736 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1737 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1738 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1739 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1740 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1741 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1742 error
->ctl
[ring
->id
] = I915_READ_CTL(ring
);
1744 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1745 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1749 static void i915_gem_record_active_context(struct intel_ring_buffer
*ring
,
1750 struct drm_i915_error_state
*error
,
1751 struct drm_i915_error_ring
*ering
)
1753 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1754 struct drm_i915_gem_object
*obj
;
1756 /* Currently render ring is the only HW context user */
1757 if (ring
->id
!= RCS
|| !error
->ccid
)
1760 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
1761 if ((error
->ccid
& PAGE_MASK
) == obj
->gtt_offset
) {
1762 ering
->ctx
= i915_error_object_create_sized(dev_priv
,
1768 static void i915_gem_record_rings(struct drm_device
*dev
,
1769 struct drm_i915_error_state
*error
)
1771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1772 struct intel_ring_buffer
*ring
;
1773 struct drm_i915_gem_request
*request
;
1776 for_each_ring(ring
, dev_priv
, i
) {
1777 i915_record_ring_state(dev
, error
, ring
);
1779 error
->ring
[i
].batchbuffer
=
1780 i915_error_first_batchbuffer(dev_priv
, ring
);
1782 error
->ring
[i
].ringbuffer
=
1783 i915_error_object_create(dev_priv
, ring
->obj
);
1786 i915_gem_record_active_context(ring
, error
, &error
->ring
[i
]);
1789 list_for_each_entry(request
, &ring
->request_list
, list
)
1792 error
->ring
[i
].num_requests
= count
;
1793 error
->ring
[i
].requests
=
1794 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1796 if (error
->ring
[i
].requests
== NULL
) {
1797 error
->ring
[i
].num_requests
= 0;
1802 list_for_each_entry(request
, &ring
->request_list
, list
) {
1803 struct drm_i915_error_request
*erq
;
1805 erq
= &error
->ring
[i
].requests
[count
++];
1806 erq
->seqno
= request
->seqno
;
1807 erq
->jiffies
= request
->emitted_jiffies
;
1808 erq
->tail
= request
->tail
;
1814 * i915_capture_error_state - capture an error record for later analysis
1817 * Should be called when an error is detected (either a hang or an error
1818 * interrupt) to capture error state from the time of the error. Fills
1819 * out a structure which becomes available in debugfs for user level tools
1822 static void i915_capture_error_state(struct drm_device
*dev
)
1824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1825 struct drm_i915_gem_object
*obj
;
1826 struct drm_i915_error_state
*error
;
1827 unsigned long flags
;
1830 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1831 error
= dev_priv
->gpu_error
.first_error
;
1832 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1836 /* Account for pipe specific data like PIPE*STAT */
1837 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1839 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1843 DRM_INFO("capturing error event; look for more information in "
1844 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1845 dev
->primary
->index
);
1847 kref_init(&error
->ref
);
1848 error
->eir
= I915_READ(EIR
);
1849 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1850 if (HAS_HW_CONTEXTS(dev
))
1851 error
->ccid
= I915_READ(CCID
);
1853 if (HAS_PCH_SPLIT(dev
))
1854 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1855 else if (IS_VALLEYVIEW(dev
))
1856 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1857 else if (IS_GEN2(dev
))
1858 error
->ier
= I915_READ16(IER
);
1860 error
->ier
= I915_READ(IER
);
1862 if (INTEL_INFO(dev
)->gen
>= 6)
1863 error
->derrmr
= I915_READ(DERRMR
);
1865 if (IS_VALLEYVIEW(dev
))
1866 error
->forcewake
= I915_READ(FORCEWAKE_VLV
);
1867 else if (INTEL_INFO(dev
)->gen
>= 7)
1868 error
->forcewake
= I915_READ(FORCEWAKE_MT
);
1869 else if (INTEL_INFO(dev
)->gen
== 6)
1870 error
->forcewake
= I915_READ(FORCEWAKE
);
1872 if (!HAS_PCH_SPLIT(dev
))
1874 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1876 if (INTEL_INFO(dev
)->gen
>= 6) {
1877 error
->error
= I915_READ(ERROR_GEN6
);
1878 error
->done_reg
= I915_READ(DONE_REG
);
1881 if (INTEL_INFO(dev
)->gen
== 7)
1882 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1884 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1886 i915_gem_record_fences(dev
, error
);
1887 i915_gem_record_rings(dev
, error
);
1889 /* Record buffers on the active and pinned lists. */
1890 error
->active_bo
= NULL
;
1891 error
->pinned_bo
= NULL
;
1894 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1896 error
->active_bo_count
= i
;
1897 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
1900 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1902 error
->active_bo
= NULL
;
1903 error
->pinned_bo
= NULL
;
1905 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1907 if (error
->active_bo
)
1909 error
->active_bo
+ error
->active_bo_count
;
1912 if (error
->active_bo
)
1913 error
->active_bo_count
=
1914 capture_active_bo(error
->active_bo
,
1915 error
->active_bo_count
,
1916 &dev_priv
->mm
.active_list
);
1918 if (error
->pinned_bo
)
1919 error
->pinned_bo_count
=
1920 capture_pinned_bo(error
->pinned_bo
,
1921 error
->pinned_bo_count
,
1922 &dev_priv
->mm
.bound_list
);
1924 do_gettimeofday(&error
->time
);
1926 error
->overlay
= intel_overlay_capture_error_state(dev
);
1927 error
->display
= intel_display_capture_error_state(dev
);
1929 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1930 if (dev_priv
->gpu_error
.first_error
== NULL
) {
1931 dev_priv
->gpu_error
.first_error
= error
;
1934 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1937 i915_error_state_free(&error
->ref
);
1940 void i915_destroy_error_state(struct drm_device
*dev
)
1942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 struct drm_i915_error_state
*error
;
1944 unsigned long flags
;
1946 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1947 error
= dev_priv
->gpu_error
.first_error
;
1948 dev_priv
->gpu_error
.first_error
= NULL
;
1949 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1952 kref_put(&error
->ref
, i915_error_state_free
);
1955 #define i915_capture_error_state(x)
1958 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1961 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1962 u32 eir
= I915_READ(EIR
);
1968 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1970 i915_get_extra_instdone(dev
, instdone
);
1973 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1974 u32 ipeir
= I915_READ(IPEIR_I965
);
1976 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1977 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1978 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1979 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1980 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1981 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1982 I915_WRITE(IPEIR_I965
, ipeir
);
1983 POSTING_READ(IPEIR_I965
);
1985 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1986 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1987 pr_err("page table error\n");
1988 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1989 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1990 POSTING_READ(PGTBL_ER
);
1994 if (!IS_GEN2(dev
)) {
1995 if (eir
& I915_ERROR_PAGE_TABLE
) {
1996 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1997 pr_err("page table error\n");
1998 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1999 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2000 POSTING_READ(PGTBL_ER
);
2004 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2005 pr_err("memory refresh error:\n");
2007 pr_err("pipe %c stat: 0x%08x\n",
2008 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2009 /* pipestat has already been acked */
2011 if (eir
& I915_ERROR_INSTRUCTION
) {
2012 pr_err("instruction error\n");
2013 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2014 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2015 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2016 if (INTEL_INFO(dev
)->gen
< 4) {
2017 u32 ipeir
= I915_READ(IPEIR
);
2019 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2020 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2021 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2022 I915_WRITE(IPEIR
, ipeir
);
2023 POSTING_READ(IPEIR
);
2025 u32 ipeir
= I915_READ(IPEIR_I965
);
2027 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2028 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2029 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2030 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2031 I915_WRITE(IPEIR_I965
, ipeir
);
2032 POSTING_READ(IPEIR_I965
);
2036 I915_WRITE(EIR
, eir
);
2038 eir
= I915_READ(EIR
);
2041 * some errors might have become stuck,
2044 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2045 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2046 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2051 * i915_handle_error - handle an error interrupt
2054 * Do some basic checking of regsiter state at error interrupt time and
2055 * dump it to the syslog. Also call i915_capture_error_state() to make
2056 * sure we get a record and make it available in debugfs. Fire a uevent
2057 * so userspace knows something bad happened (should trigger collection
2058 * of a ring dump etc.).
2060 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
2062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2063 struct intel_ring_buffer
*ring
;
2066 i915_capture_error_state(dev
);
2067 i915_report_and_clear_eir(dev
);
2070 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2071 &dev_priv
->gpu_error
.reset_counter
);
2074 * Wakeup waiting processes so that the reset work item
2075 * doesn't deadlock trying to grab various locks.
2077 for_each_ring(ring
, dev_priv
, i
)
2078 wake_up_all(&ring
->irq_queue
);
2081 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
2084 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2086 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2087 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2089 struct drm_i915_gem_object
*obj
;
2090 struct intel_unpin_work
*work
;
2091 unsigned long flags
;
2092 bool stall_detected
;
2094 /* Ignore early vblank irqs */
2095 if (intel_crtc
== NULL
)
2098 spin_lock_irqsave(&dev
->event_lock
, flags
);
2099 work
= intel_crtc
->unpin_work
;
2102 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2103 !work
->enable_stall_check
) {
2104 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2105 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2109 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2110 obj
= work
->pending_flip_obj
;
2111 if (INTEL_INFO(dev
)->gen
>= 4) {
2112 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2113 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2116 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2117 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
2118 crtc
->y
* crtc
->fb
->pitches
[0] +
2119 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
2122 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2124 if (stall_detected
) {
2125 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2126 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2130 /* Called from drm generic code, passed 'crtc' which
2131 * we use as a pipe index
2133 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2135 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2136 unsigned long irqflags
;
2138 if (!i915_pipe_enabled(dev
, pipe
))
2141 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2142 if (INTEL_INFO(dev
)->gen
>= 4)
2143 i915_enable_pipestat(dev_priv
, pipe
,
2144 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2146 i915_enable_pipestat(dev_priv
, pipe
,
2147 PIPE_VBLANK_INTERRUPT_ENABLE
);
2149 /* maintain vblank delivery even in deep C-states */
2150 if (dev_priv
->info
->gen
== 3)
2151 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2152 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2157 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2159 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2160 unsigned long irqflags
;
2162 if (!i915_pipe_enabled(dev
, pipe
))
2165 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2166 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
2167 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2168 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2173 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
2175 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2176 unsigned long irqflags
;
2178 if (!i915_pipe_enabled(dev
, pipe
))
2181 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2182 ironlake_enable_display_irq(dev_priv
,
2183 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
2184 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2189 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2191 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2192 unsigned long irqflags
;
2195 if (!i915_pipe_enabled(dev
, pipe
))
2198 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2199 imr
= I915_READ(VLV_IMR
);
2201 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2203 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2204 I915_WRITE(VLV_IMR
, imr
);
2205 i915_enable_pipestat(dev_priv
, pipe
,
2206 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2207 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2212 /* Called from drm generic code, passed 'crtc' which
2213 * we use as a pipe index
2215 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2217 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2218 unsigned long irqflags
;
2220 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2221 if (dev_priv
->info
->gen
== 3)
2222 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2224 i915_disable_pipestat(dev_priv
, pipe
,
2225 PIPE_VBLANK_INTERRUPT_ENABLE
|
2226 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2227 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2230 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2232 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2233 unsigned long irqflags
;
2235 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2236 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
2237 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2238 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2241 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
2243 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2244 unsigned long irqflags
;
2246 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2247 ironlake_disable_display_irq(dev_priv
,
2248 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
2249 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2252 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2254 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2255 unsigned long irqflags
;
2258 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2259 i915_disable_pipestat(dev_priv
, pipe
,
2260 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2261 imr
= I915_READ(VLV_IMR
);
2263 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2265 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2266 I915_WRITE(VLV_IMR
, imr
);
2267 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2271 ring_last_seqno(struct intel_ring_buffer
*ring
)
2273 return list_entry(ring
->request_list
.prev
,
2274 struct drm_i915_gem_request
, list
)->seqno
;
2277 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer
*ring
, bool *err
)
2279 if (list_empty(&ring
->request_list
) ||
2280 i915_seqno_passed(ring
->get_seqno(ring
, false),
2281 ring_last_seqno(ring
))) {
2282 /* Issue a wake-up to catch stuck h/w. */
2283 if (waitqueue_active(&ring
->irq_queue
)) {
2284 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2286 wake_up_all(&ring
->irq_queue
);
2294 static bool semaphore_passed(struct intel_ring_buffer
*ring
)
2296 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2297 u32 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2298 struct intel_ring_buffer
*signaller
;
2299 u32 cmd
, ipehr
, acthd_min
;
2301 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2302 if ((ipehr
& ~(0x3 << 16)) !=
2303 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2306 /* ACTHD is likely pointing to the dword after the actual command,
2307 * so scan backwards until we find the MBOX.
2309 acthd_min
= max((int)acthd
- 3 * 4, 0);
2311 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2316 if (acthd
< acthd_min
)
2320 signaller
= &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2321 return i915_seqno_passed(signaller
->get_seqno(signaller
, false),
2322 ioread32(ring
->virtual_start
+acthd
+4)+1);
2325 static bool kick_ring(struct intel_ring_buffer
*ring
)
2327 struct drm_device
*dev
= ring
->dev
;
2328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2329 u32 tmp
= I915_READ_CTL(ring
);
2330 if (tmp
& RING_WAIT
) {
2331 DRM_ERROR("Kicking stuck wait on %s\n",
2333 I915_WRITE_CTL(ring
, tmp
);
2337 if (INTEL_INFO(dev
)->gen
>= 6 &&
2338 tmp
& RING_WAIT_SEMAPHORE
&&
2339 semaphore_passed(ring
)) {
2340 DRM_ERROR("Kicking stuck semaphore on %s\n",
2342 I915_WRITE_CTL(ring
, tmp
);
2348 static bool i915_hangcheck_hung(struct drm_device
*dev
)
2350 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2352 if (dev_priv
->gpu_error
.hangcheck_count
++ > 1) {
2355 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
2356 i915_handle_error(dev
, true);
2358 if (!IS_GEN2(dev
)) {
2359 struct intel_ring_buffer
*ring
;
2362 /* Is the chip hanging on a WAIT_FOR_EVENT?
2363 * If so we can simply poke the RB_WAIT bit
2364 * and break the hang. This should work on
2365 * all but the second generation chipsets.
2367 for_each_ring(ring
, dev_priv
, i
)
2368 hung
&= !kick_ring(ring
);
2378 * This is called when the chip hasn't reported back with completed
2379 * batchbuffers in a long time. The first time this is called we simply record
2380 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2381 * again, we assume the chip is wedged and try to fix it.
2383 void i915_hangcheck_elapsed(unsigned long data
)
2385 struct drm_device
*dev
= (struct drm_device
*)data
;
2386 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2387 uint32_t acthd
[I915_NUM_RINGS
], instdone
[I915_NUM_INSTDONE_REG
];
2388 struct intel_ring_buffer
*ring
;
2389 bool err
= false, idle
;
2392 if (!i915_enable_hangcheck
)
2395 memset(acthd
, 0, sizeof(acthd
));
2397 for_each_ring(ring
, dev_priv
, i
) {
2398 idle
&= i915_hangcheck_ring_idle(ring
, &err
);
2399 acthd
[i
] = intel_ring_get_active_head(ring
);
2402 /* If all work is done then ACTHD clearly hasn't advanced. */
2405 if (i915_hangcheck_hung(dev
))
2411 dev_priv
->gpu_error
.hangcheck_count
= 0;
2415 i915_get_extra_instdone(dev
, instdone
);
2416 if (memcmp(dev_priv
->gpu_error
.last_acthd
, acthd
,
2417 sizeof(acthd
)) == 0 &&
2418 memcmp(dev_priv
->gpu_error
.prev_instdone
, instdone
,
2419 sizeof(instdone
)) == 0) {
2420 if (i915_hangcheck_hung(dev
))
2423 dev_priv
->gpu_error
.hangcheck_count
= 0;
2425 memcpy(dev_priv
->gpu_error
.last_acthd
, acthd
,
2427 memcpy(dev_priv
->gpu_error
.prev_instdone
, instdone
,
2432 /* Reset timer case chip hangs without another request being added */
2433 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2434 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2439 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2441 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2443 atomic_set(&dev_priv
->irq_received
, 0);
2445 I915_WRITE(HWSTAM
, 0xeffe);
2447 /* XXX hotplug from PCH */
2449 I915_WRITE(DEIMR
, 0xffffffff);
2450 I915_WRITE(DEIER
, 0x0);
2451 POSTING_READ(DEIER
);
2454 I915_WRITE(GTIMR
, 0xffffffff);
2455 I915_WRITE(GTIER
, 0x0);
2456 POSTING_READ(GTIER
);
2458 if (HAS_PCH_NOP(dev
))
2461 /* south display irq */
2462 I915_WRITE(SDEIMR
, 0xffffffff);
2464 * SDEIER is also touched by the interrupt handler to work around missed
2465 * PCH interrupts. Hence we can't update it after the interrupt handler
2466 * is enabled - instead we unconditionally enable all PCH interrupt
2467 * sources here, but then only unmask them as needed with SDEIMR.
2469 I915_WRITE(SDEIER
, 0xffffffff);
2470 POSTING_READ(SDEIER
);
2473 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2475 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2478 atomic_set(&dev_priv
->irq_received
, 0);
2481 I915_WRITE(VLV_IMR
, 0);
2482 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2483 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2484 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2487 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2488 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2489 I915_WRITE(GTIMR
, 0xffffffff);
2490 I915_WRITE(GTIER
, 0x0);
2491 POSTING_READ(GTIER
);
2493 I915_WRITE(DPINVGTT
, 0xff);
2495 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2496 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2498 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2499 I915_WRITE(VLV_IIR
, 0xffffffff);
2500 I915_WRITE(VLV_IMR
, 0xffffffff);
2501 I915_WRITE(VLV_IER
, 0x0);
2502 POSTING_READ(VLV_IER
);
2505 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2507 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2508 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2509 struct intel_encoder
*intel_encoder
;
2510 u32 mask
= ~I915_READ(SDEIMR
);
2513 if (HAS_PCH_IBX(dev
)) {
2514 mask
&= ~SDE_HOTPLUG_MASK
;
2515 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2516 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2517 mask
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2519 mask
&= ~SDE_HOTPLUG_MASK_CPT
;
2520 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2521 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2522 mask
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2525 I915_WRITE(SDEIMR
, ~mask
);
2528 * Enable digital hotplug on the PCH, and configure the DP short pulse
2529 * duration to 2ms (which is the minimum in the Display Port spec)
2531 * This register is the same on all known PCH chips.
2533 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2534 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2535 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2536 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2537 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2538 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2541 static void ibx_irq_postinstall(struct drm_device
*dev
)
2543 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2546 if (HAS_PCH_IBX(dev
)) {
2547 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2548 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2550 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2552 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2555 if (HAS_PCH_NOP(dev
))
2558 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2559 I915_WRITE(SDEIMR
, ~mask
);
2562 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2564 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2565 /* enable kind of interrupts always enabled */
2566 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2567 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2568 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2569 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2572 dev_priv
->irq_mask
= ~display_mask
;
2574 /* should always can generate irq */
2575 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2576 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2577 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
2578 POSTING_READ(DEIER
);
2580 dev_priv
->gt_irq_mask
= ~0;
2582 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2583 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2588 GEN6_BSD_USER_INTERRUPT
|
2589 GEN6_BLITTER_USER_INTERRUPT
;
2594 GT_BSD_USER_INTERRUPT
;
2595 I915_WRITE(GTIER
, render_irqs
);
2596 POSTING_READ(GTIER
);
2598 ibx_irq_postinstall(dev
);
2600 if (IS_IRONLAKE_M(dev
)) {
2601 /* Clear & enable PCU event interrupts */
2602 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2603 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
2604 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2610 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2612 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2613 /* enable kind of interrupts always enabled */
2615 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2616 DE_PLANEC_FLIP_DONE_IVB
|
2617 DE_PLANEB_FLIP_DONE_IVB
|
2618 DE_PLANEA_FLIP_DONE_IVB
|
2619 DE_AUX_CHANNEL_A_IVB
|
2623 dev_priv
->irq_mask
= ~display_mask
;
2625 /* should always can generate irq */
2626 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2627 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2628 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2631 DE_PIPEC_VBLANK_IVB
|
2632 DE_PIPEB_VBLANK_IVB
|
2633 DE_PIPEA_VBLANK_IVB
);
2634 POSTING_READ(DEIER
);
2636 dev_priv
->gt_irq_mask
= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
2638 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2639 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2641 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
2642 GEN6_BLITTER_USER_INTERRUPT
| GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
2643 I915_WRITE(GTIER
, render_irqs
);
2644 POSTING_READ(GTIER
);
2646 ibx_irq_postinstall(dev
);
2651 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2653 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2655 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2658 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2659 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2660 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2661 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2662 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2665 *Leave vblank interrupts masked initially. enable/disable will
2666 * toggle them based on usage.
2668 dev_priv
->irq_mask
= (~enable_mask
) |
2669 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2670 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2672 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2673 POSTING_READ(PORT_HOTPLUG_EN
);
2675 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2676 I915_WRITE(VLV_IER
, enable_mask
);
2677 I915_WRITE(VLV_IIR
, 0xffffffff);
2678 I915_WRITE(PIPESTAT(0), 0xffff);
2679 I915_WRITE(PIPESTAT(1), 0xffff);
2680 POSTING_READ(VLV_IER
);
2682 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2683 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2684 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2686 I915_WRITE(VLV_IIR
, 0xffffffff);
2687 I915_WRITE(VLV_IIR
, 0xffffffff);
2689 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2690 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2692 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
2693 GEN6_BLITTER_USER_INTERRUPT
;
2694 I915_WRITE(GTIER
, render_irqs
);
2695 POSTING_READ(GTIER
);
2697 /* ack & enable invalid PTE error interrupts */
2698 #if 0 /* FIXME: add support to irq handler for checking these bits */
2699 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2700 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2703 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2708 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2710 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2716 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2719 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2721 I915_WRITE(HWSTAM
, 0xffffffff);
2722 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2723 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2725 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2726 I915_WRITE(VLV_IIR
, 0xffffffff);
2727 I915_WRITE(VLV_IMR
, 0xffffffff);
2728 I915_WRITE(VLV_IER
, 0x0);
2729 POSTING_READ(VLV_IER
);
2732 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2734 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2739 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2741 I915_WRITE(HWSTAM
, 0xffffffff);
2743 I915_WRITE(DEIMR
, 0xffffffff);
2744 I915_WRITE(DEIER
, 0x0);
2745 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2747 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2749 I915_WRITE(GTIMR
, 0xffffffff);
2750 I915_WRITE(GTIER
, 0x0);
2751 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2753 if (HAS_PCH_NOP(dev
))
2756 I915_WRITE(SDEIMR
, 0xffffffff);
2757 I915_WRITE(SDEIER
, 0x0);
2758 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2759 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2760 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2763 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2765 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2768 atomic_set(&dev_priv
->irq_received
, 0);
2771 I915_WRITE(PIPESTAT(pipe
), 0);
2772 I915_WRITE16(IMR
, 0xffff);
2773 I915_WRITE16(IER
, 0x0);
2774 POSTING_READ16(IER
);
2777 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2779 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2782 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2784 /* Unmask the interrupts that we always want on. */
2785 dev_priv
->irq_mask
=
2786 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2787 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2788 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2789 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2790 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2791 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2794 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2795 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2796 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2797 I915_USER_INTERRUPT
);
2798 POSTING_READ16(IER
);
2804 * Returns true when a page flip has completed.
2806 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2809 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2810 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2812 if (!drm_handle_vblank(dev
, pipe
))
2815 if ((iir
& flip_pending
) == 0)
2818 intel_prepare_page_flip(dev
, pipe
);
2820 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2821 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2822 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2823 * the flip is completed (no longer pending). Since this doesn't raise
2824 * an interrupt per se, we watch for the change at vblank.
2826 if (I915_READ16(ISR
) & flip_pending
)
2829 intel_finish_page_flip(dev
, pipe
);
2834 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2836 struct drm_device
*dev
= (struct drm_device
*) arg
;
2837 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2840 unsigned long irqflags
;
2844 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2845 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2847 atomic_inc(&dev_priv
->irq_received
);
2849 iir
= I915_READ16(IIR
);
2853 while (iir
& ~flip_mask
) {
2854 /* Can't rely on pipestat interrupt bit in iir as it might
2855 * have been cleared after the pipestat interrupt was received.
2856 * It doesn't set the bit in iir again, but it still produces
2857 * interrupts (for non-MSI).
2859 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2860 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2861 i915_handle_error(dev
, false);
2863 for_each_pipe(pipe
) {
2864 int reg
= PIPESTAT(pipe
);
2865 pipe_stats
[pipe
] = I915_READ(reg
);
2868 * Clear the PIPE*STAT regs before the IIR
2870 if (pipe_stats
[pipe
] & 0x8000ffff) {
2871 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2872 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2874 I915_WRITE(reg
, pipe_stats
[pipe
]);
2878 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2880 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2881 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2883 i915_update_dri1_breadcrumb(dev
);
2885 if (iir
& I915_USER_INTERRUPT
)
2886 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2888 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2889 i8xx_handle_vblank(dev
, 0, iir
))
2890 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2892 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2893 i8xx_handle_vblank(dev
, 1, iir
))
2894 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2902 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2904 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2907 for_each_pipe(pipe
) {
2908 /* Clear enable bits; then clear status bits */
2909 I915_WRITE(PIPESTAT(pipe
), 0);
2910 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2912 I915_WRITE16(IMR
, 0xffff);
2913 I915_WRITE16(IER
, 0x0);
2914 I915_WRITE16(IIR
, I915_READ16(IIR
));
2917 static void i915_irq_preinstall(struct drm_device
* dev
)
2919 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2922 atomic_set(&dev_priv
->irq_received
, 0);
2924 if (I915_HAS_HOTPLUG(dev
)) {
2925 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2926 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2929 I915_WRITE16(HWSTAM
, 0xeffe);
2931 I915_WRITE(PIPESTAT(pipe
), 0);
2932 I915_WRITE(IMR
, 0xffffffff);
2933 I915_WRITE(IER
, 0x0);
2937 static int i915_irq_postinstall(struct drm_device
*dev
)
2939 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2942 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2944 /* Unmask the interrupts that we always want on. */
2945 dev_priv
->irq_mask
=
2946 ~(I915_ASLE_INTERRUPT
|
2947 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2948 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2949 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2950 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2951 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2954 I915_ASLE_INTERRUPT
|
2955 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2956 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2957 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2958 I915_USER_INTERRUPT
;
2960 if (I915_HAS_HOTPLUG(dev
)) {
2961 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2962 POSTING_READ(PORT_HOTPLUG_EN
);
2964 /* Enable in IER... */
2965 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2966 /* and unmask in IMR */
2967 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2970 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2971 I915_WRITE(IER
, enable_mask
);
2974 i915_enable_asle_pipestat(dev
);
2980 * Returns true when a page flip has completed.
2982 static bool i915_handle_vblank(struct drm_device
*dev
,
2983 int plane
, int pipe
, u32 iir
)
2985 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2986 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2988 if (!drm_handle_vblank(dev
, pipe
))
2991 if ((iir
& flip_pending
) == 0)
2994 intel_prepare_page_flip(dev
, plane
);
2996 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2997 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2998 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2999 * the flip is completed (no longer pending). Since this doesn't raise
3000 * an interrupt per se, we watch for the change at vblank.
3002 if (I915_READ(ISR
) & flip_pending
)
3005 intel_finish_page_flip(dev
, pipe
);
3010 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3012 struct drm_device
*dev
= (struct drm_device
*) arg
;
3013 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3014 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3015 unsigned long irqflags
;
3017 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3018 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3019 int pipe
, ret
= IRQ_NONE
;
3021 atomic_inc(&dev_priv
->irq_received
);
3023 iir
= I915_READ(IIR
);
3025 bool irq_received
= (iir
& ~flip_mask
) != 0;
3026 bool blc_event
= false;
3028 /* Can't rely on pipestat interrupt bit in iir as it might
3029 * have been cleared after the pipestat interrupt was received.
3030 * It doesn't set the bit in iir again, but it still produces
3031 * interrupts (for non-MSI).
3033 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3034 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3035 i915_handle_error(dev
, false);
3037 for_each_pipe(pipe
) {
3038 int reg
= PIPESTAT(pipe
);
3039 pipe_stats
[pipe
] = I915_READ(reg
);
3041 /* Clear the PIPE*STAT regs before the IIR */
3042 if (pipe_stats
[pipe
] & 0x8000ffff) {
3043 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3044 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3046 I915_WRITE(reg
, pipe_stats
[pipe
]);
3047 irq_received
= true;
3050 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3055 /* Consume port. Then clear IIR or we'll miss events */
3056 if ((I915_HAS_HOTPLUG(dev
)) &&
3057 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
3058 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3059 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
3061 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3063 if (hotplug_trigger
) {
3064 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_status_i915
))
3065 i915_hpd_irq_setup(dev
);
3066 queue_work(dev_priv
->wq
,
3067 &dev_priv
->hotplug_work
);
3069 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3070 POSTING_READ(PORT_HOTPLUG_STAT
);
3073 I915_WRITE(IIR
, iir
& ~flip_mask
);
3074 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3076 if (iir
& I915_USER_INTERRUPT
)
3077 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3079 for_each_pipe(pipe
) {
3084 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3085 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3086 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3088 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3092 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3093 intel_opregion_asle_intr(dev
);
3095 /* With MSI, interrupts are only generated when iir
3096 * transitions from zero to nonzero. If another bit got
3097 * set while we were handling the existing iir bits, then
3098 * we would never get another interrupt.
3100 * This is fine on non-MSI as well, as if we hit this path
3101 * we avoid exiting the interrupt handler only to generate
3104 * Note that for MSI this could cause a stray interrupt report
3105 * if an interrupt landed in the time between writing IIR and
3106 * the posting read. This should be rare enough to never
3107 * trigger the 99% of 100,000 interrupts test for disabling
3112 } while (iir
& ~flip_mask
);
3114 i915_update_dri1_breadcrumb(dev
);
3119 static void i915_irq_uninstall(struct drm_device
* dev
)
3121 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3124 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3126 if (I915_HAS_HOTPLUG(dev
)) {
3127 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3128 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3131 I915_WRITE16(HWSTAM
, 0xffff);
3132 for_each_pipe(pipe
) {
3133 /* Clear enable bits; then clear status bits */
3134 I915_WRITE(PIPESTAT(pipe
), 0);
3135 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3137 I915_WRITE(IMR
, 0xffffffff);
3138 I915_WRITE(IER
, 0x0);
3140 I915_WRITE(IIR
, I915_READ(IIR
));
3143 static void i965_irq_preinstall(struct drm_device
* dev
)
3145 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3148 atomic_set(&dev_priv
->irq_received
, 0);
3150 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3151 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3153 I915_WRITE(HWSTAM
, 0xeffe);
3155 I915_WRITE(PIPESTAT(pipe
), 0);
3156 I915_WRITE(IMR
, 0xffffffff);
3157 I915_WRITE(IER
, 0x0);
3161 static int i965_irq_postinstall(struct drm_device
*dev
)
3163 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3167 /* Unmask the interrupts that we always want on. */
3168 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3169 I915_DISPLAY_PORT_INTERRUPT
|
3170 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3171 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3172 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3173 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3174 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3176 enable_mask
= ~dev_priv
->irq_mask
;
3177 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3178 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3179 enable_mask
|= I915_USER_INTERRUPT
;
3182 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3184 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
3187 * Enable some error detection, note the instruction error mask
3188 * bit is reserved, so we leave it masked.
3191 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3192 GM45_ERROR_MEM_PRIV
|
3193 GM45_ERROR_CP_PRIV
|
3194 I915_ERROR_MEMORY_REFRESH
);
3196 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3197 I915_ERROR_MEMORY_REFRESH
);
3199 I915_WRITE(EMR
, error_mask
);
3201 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3202 I915_WRITE(IER
, enable_mask
);
3205 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3206 POSTING_READ(PORT_HOTPLUG_EN
);
3208 i915_enable_asle_pipestat(dev
);
3213 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3215 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3216 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3217 struct intel_encoder
*intel_encoder
;
3220 if (I915_HAS_HOTPLUG(dev
)) {
3221 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3222 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3223 /* Note HDMI and DP share hotplug bits */
3224 /* enable bits are the same for all generations */
3225 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3226 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3227 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3228 /* Programming the CRT detection parameters tends
3229 to generate a spurious hotplug event about three
3230 seconds later. So just do it once.
3233 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3234 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3235 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3237 /* Ignore TV since it's buggy */
3238 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3242 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3244 struct drm_device
*dev
= (struct drm_device
*) arg
;
3245 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3247 u32 pipe_stats
[I915_MAX_PIPES
];
3248 unsigned long irqflags
;
3250 int ret
= IRQ_NONE
, pipe
;
3252 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3253 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3255 atomic_inc(&dev_priv
->irq_received
);
3257 iir
= I915_READ(IIR
);
3260 bool blc_event
= false;
3262 irq_received
= (iir
& ~flip_mask
) != 0;
3264 /* Can't rely on pipestat interrupt bit in iir as it might
3265 * have been cleared after the pipestat interrupt was received.
3266 * It doesn't set the bit in iir again, but it still produces
3267 * interrupts (for non-MSI).
3269 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3270 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3271 i915_handle_error(dev
, false);
3273 for_each_pipe(pipe
) {
3274 int reg
= PIPESTAT(pipe
);
3275 pipe_stats
[pipe
] = I915_READ(reg
);
3278 * Clear the PIPE*STAT regs before the IIR
3280 if (pipe_stats
[pipe
] & 0x8000ffff) {
3281 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3282 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3284 I915_WRITE(reg
, pipe_stats
[pipe
]);
3288 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3295 /* Consume port. Then clear IIR or we'll miss events */
3296 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3297 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3298 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3299 HOTPLUG_INT_STATUS_G4X
:
3300 HOTPLUG_INT_STATUS_I965
);
3302 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3304 if (hotplug_trigger
) {
3305 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
,
3306 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i965
))
3307 i915_hpd_irq_setup(dev
);
3308 queue_work(dev_priv
->wq
,
3309 &dev_priv
->hotplug_work
);
3311 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3312 I915_READ(PORT_HOTPLUG_STAT
);
3315 I915_WRITE(IIR
, iir
& ~flip_mask
);
3316 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3318 if (iir
& I915_USER_INTERRUPT
)
3319 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3320 if (iir
& I915_BSD_USER_INTERRUPT
)
3321 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3323 for_each_pipe(pipe
) {
3324 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3325 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3326 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3328 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3333 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3334 intel_opregion_asle_intr(dev
);
3336 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3337 gmbus_irq_handler(dev
);
3339 /* With MSI, interrupts are only generated when iir
3340 * transitions from zero to nonzero. If another bit got
3341 * set while we were handling the existing iir bits, then
3342 * we would never get another interrupt.
3344 * This is fine on non-MSI as well, as if we hit this path
3345 * we avoid exiting the interrupt handler only to generate
3348 * Note that for MSI this could cause a stray interrupt report
3349 * if an interrupt landed in the time between writing IIR and
3350 * the posting read. This should be rare enough to never
3351 * trigger the 99% of 100,000 interrupts test for disabling
3357 i915_update_dri1_breadcrumb(dev
);
3362 static void i965_irq_uninstall(struct drm_device
* dev
)
3364 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3370 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3372 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3373 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3375 I915_WRITE(HWSTAM
, 0xffffffff);
3377 I915_WRITE(PIPESTAT(pipe
), 0);
3378 I915_WRITE(IMR
, 0xffffffff);
3379 I915_WRITE(IER
, 0x0);
3382 I915_WRITE(PIPESTAT(pipe
),
3383 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3384 I915_WRITE(IIR
, I915_READ(IIR
));
3387 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3389 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3390 struct drm_device
*dev
= dev_priv
->dev
;
3391 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3392 unsigned long irqflags
;
3395 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3396 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3397 struct drm_connector
*connector
;
3399 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3402 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3404 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3405 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3407 if (intel_connector
->encoder
->hpd_pin
== i
) {
3408 if (connector
->polled
!= intel_connector
->polled
)
3409 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3410 drm_get_connector_name(connector
));
3411 connector
->polled
= intel_connector
->polled
;
3412 if (!connector
->polled
)
3413 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3417 if (dev_priv
->display
.hpd_irq_setup
)
3418 dev_priv
->display
.hpd_irq_setup(dev
);
3419 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3422 void intel_irq_init(struct drm_device
*dev
)
3424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3426 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3427 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3428 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3429 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3431 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3432 i915_hangcheck_elapsed
,
3433 (unsigned long) dev
);
3434 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3435 (unsigned long) dev_priv
);
3437 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3439 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3440 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3441 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3442 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3443 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3446 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3447 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3449 dev
->driver
->get_vblank_timestamp
= NULL
;
3450 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3452 if (IS_VALLEYVIEW(dev
)) {
3453 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3454 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3455 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3456 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3457 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3458 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3459 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3460 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3461 /* Share pre & uninstall handlers with ILK/SNB */
3462 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
3463 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3464 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3465 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3466 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3467 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3468 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3469 } else if (HAS_PCH_SPLIT(dev
)) {
3470 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3471 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3472 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3473 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3474 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3475 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3476 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3478 if (INTEL_INFO(dev
)->gen
== 2) {
3479 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3480 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3481 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3482 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3483 } else if (INTEL_INFO(dev
)->gen
== 3) {
3484 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3485 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3486 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3487 dev
->driver
->irq_handler
= i915_irq_handler
;
3488 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3490 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3491 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3492 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3493 dev
->driver
->irq_handler
= i965_irq_handler
;
3494 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3496 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3497 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3501 void intel_hpd_init(struct drm_device
*dev
)
3503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3504 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3505 struct drm_connector
*connector
;
3508 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3509 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3510 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3512 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3513 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3514 connector
->polled
= intel_connector
->polled
;
3515 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3516 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3518 if (dev_priv
->display
.hpd_irq_setup
)
3519 dev_priv
->display
.hpd_irq_setup(dev
);