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Merge tag 'v3.16-rc4' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92 } while (0)
93
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
102 } while (0)
103
104 /*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117 } while (0)
118
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124 } while (0)
125
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131 } while (0)
132
133 /* For display hotplug interrupt */
134 static void
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136 {
137 assert_spin_locked(&dev_priv->irq_lock);
138
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
140 return;
141
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
145 POSTING_READ(DEIMR);
146 }
147 }
148
149 static void
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151 {
152 assert_spin_locked(&dev_priv->irq_lock);
153
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
155 return;
156
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
160 POSTING_READ(DEIMR);
161 }
162 }
163
164 /**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173 {
174 assert_spin_locked(&dev_priv->irq_lock);
175
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
177 return;
178
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183 }
184
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186 {
187 ilk_update_gt_irq(dev_priv, mask, mask);
188 }
189
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 {
192 ilk_update_gt_irq(dev_priv, mask, 0);
193 }
194
195 /**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204 {
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221 }
222
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224 {
225 snb_update_pm_irq(dev_priv, mask, mask);
226 }
227
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229 {
230 snb_update_pm_irq(dev_priv, mask, 0);
231 }
232
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
234 {
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249 }
250
251 /**
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
256 *
257 * Copied from the snb function, updated with relevant register offsets
258 */
259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
262 {
263 uint32_t new_val;
264
265 assert_spin_locked(&dev_priv->irq_lock);
266
267 if (WARN_ON(dev_priv->pm.irqs_disabled))
268 return;
269
270 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask);
273
274 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2));
278 }
279 }
280
281 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
282 {
283 bdw_update_pm_irq(dev_priv, mask, mask);
284 }
285
286 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
287 {
288 bdw_update_pm_irq(dev_priv, mask, 0);
289 }
290
291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
292 {
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 enum pipe pipe;
295 struct intel_crtc *crtc;
296
297 assert_spin_locked(&dev_priv->irq_lock);
298
299 for_each_pipe(pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301
302 if (crtc->pch_fifo_underrun_disabled)
303 return false;
304 }
305
306 return true;
307 }
308
309 void i9xx_check_fifo_underruns(struct drm_device *dev)
310 {
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *crtc;
313 unsigned long flags;
314
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
316
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
319 u32 pipestat;
320
321 if (crtc->cpu_fifo_underrun_disabled)
322 continue;
323
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
326 continue;
327
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
329 POSTING_READ(reg);
330
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
332 }
333
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
335 }
336
337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
338 enum pipe pipe,
339 bool enable, bool old)
340 {
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 u32 reg = PIPESTAT(pipe);
343 u32 pipestat = I915_READ(reg) & 0xffff0000;
344
345 assert_spin_locked(&dev_priv->irq_lock);
346
347 if (enable) {
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
349 POSTING_READ(reg);
350 } else {
351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
353 }
354 }
355
356 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
357 enum pipe pipe, bool enable)
358 {
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
361 DE_PIPEB_FIFO_UNDERRUN;
362
363 if (enable)
364 ironlake_enable_display_irq(dev_priv, bit);
365 else
366 ironlake_disable_display_irq(dev_priv, bit);
367 }
368
369 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
370 enum pipe pipe,
371 bool enable, bool old)
372 {
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 if (enable) {
375 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
376
377 if (!ivb_can_enable_err_int(dev))
378 return;
379
380 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
381 } else {
382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
383
384 if (old &&
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
387 pipe_name(pipe));
388 }
389 }
390 }
391
392 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
393 enum pipe pipe, bool enable)
394 {
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 assert_spin_locked(&dev_priv->irq_lock);
398
399 if (enable)
400 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
401 else
402 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
403 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
404 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
405 }
406
407 /**
408 * ibx_display_interrupt_update - update SDEIMR
409 * @dev_priv: driver private
410 * @interrupt_mask: mask of interrupt bits to update
411 * @enabled_irq_mask: mask of interrupt bits to enable
412 */
413 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
414 uint32_t interrupt_mask,
415 uint32_t enabled_irq_mask)
416 {
417 uint32_t sdeimr = I915_READ(SDEIMR);
418 sdeimr &= ~interrupt_mask;
419 sdeimr |= (~enabled_irq_mask & interrupt_mask);
420
421 assert_spin_locked(&dev_priv->irq_lock);
422
423 if (WARN_ON(dev_priv->pm.irqs_disabled))
424 return;
425
426 I915_WRITE(SDEIMR, sdeimr);
427 POSTING_READ(SDEIMR);
428 }
429 #define ibx_enable_display_interrupt(dev_priv, bits) \
430 ibx_display_interrupt_update((dev_priv), (bits), (bits))
431 #define ibx_disable_display_interrupt(dev_priv, bits) \
432 ibx_display_interrupt_update((dev_priv), (bits), 0)
433
434 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
435 enum transcoder pch_transcoder,
436 bool enable)
437 {
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
440 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
441
442 if (enable)
443 ibx_enable_display_interrupt(dev_priv, bit);
444 else
445 ibx_disable_display_interrupt(dev_priv, bit);
446 }
447
448 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
449 enum transcoder pch_transcoder,
450 bool enable, bool old)
451 {
452 struct drm_i915_private *dev_priv = dev->dev_private;
453
454 if (enable) {
455 I915_WRITE(SERR_INT,
456 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
457
458 if (!cpt_can_enable_serr_int(dev))
459 return;
460
461 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
462 } else {
463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
464
465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
468 transcoder_name(pch_transcoder));
469 }
470 }
471 }
472
473 /**
474 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
475 * @dev: drm device
476 * @pipe: pipe
477 * @enable: true if we want to report FIFO underrun errors, false otherwise
478 *
479 * This function makes us disable or enable CPU fifo underruns for a specific
480 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
481 * reporting for one pipe may also disable all the other CPU error interruts for
482 * the other pipes, due to the fact that there's just one interrupt mask/enable
483 * bit for all the pipes.
484 *
485 * Returns the previous state of underrun reporting.
486 */
487 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
488 enum pipe pipe, bool enable)
489 {
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
493 bool old;
494
495 assert_spin_locked(&dev_priv->irq_lock);
496
497 old = !intel_crtc->cpu_fifo_underrun_disabled;
498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
508
509 return old;
510 }
511
512 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
513 enum pipe pipe, bool enable)
514 {
515 struct drm_i915_private *dev_priv = dev->dev_private;
516 unsigned long flags;
517 bool ret;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
520 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
521 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
522
523 return ret;
524 }
525
526 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
527 enum pipe pipe)
528 {
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
532
533 return !intel_crtc->cpu_fifo_underrun_disabled;
534 }
535
536 /**
537 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
538 * @dev: drm device
539 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
540 * @enable: true if we want to report FIFO underrun errors, false otherwise
541 *
542 * This function makes us disable or enable PCH fifo underruns for a specific
543 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
544 * underrun reporting for one transcoder may also disable all the other PCH
545 * error interruts for the other transcoders, due to the fact that there's just
546 * one interrupt mask/enable bit for all the transcoders.
547 *
548 * Returns the previous state of underrun reporting.
549 */
550 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
551 enum transcoder pch_transcoder,
552 bool enable)
553 {
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
557 unsigned long flags;
558 bool old;
559
560 /*
561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
562 * has only one pch transcoder A that all pipes can use. To avoid racy
563 * pch transcoder -> pipe lookups from interrupt code simply store the
564 * underrun statistics in crtc A. Since we never expose this anywhere
565 * nor use it outside of the fifo underrun code here using the "wrong"
566 * crtc on LPT won't cause issues.
567 */
568
569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
570
571 old = !intel_crtc->pch_fifo_underrun_disabled;
572 intel_crtc->pch_fifo_underrun_disabled = !enable;
573
574 if (HAS_PCH_IBX(dev))
575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
576 else
577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
578
579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
580 return old;
581 }
582
583
584 static void
585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
586 u32 enable_mask, u32 status_mask)
587 {
588 u32 reg = PIPESTAT(pipe);
589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
590
591 assert_spin_locked(&dev_priv->irq_lock);
592
593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
594 status_mask & ~PIPESTAT_INT_STATUS_MASK,
595 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
596 pipe_name(pipe), enable_mask, status_mask))
597 return;
598
599 if ((pipestat & enable_mask) == enable_mask)
600 return;
601
602 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
603
604 /* Enable the interrupt, clear any pending status */
605 pipestat |= enable_mask | status_mask;
606 I915_WRITE(reg, pipestat);
607 POSTING_READ(reg);
608 }
609
610 static void
611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
612 u32 enable_mask, u32 status_mask)
613 {
614 u32 reg = PIPESTAT(pipe);
615 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
616
617 assert_spin_locked(&dev_priv->irq_lock);
618
619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
620 status_mask & ~PIPESTAT_INT_STATUS_MASK,
621 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
622 pipe_name(pipe), enable_mask, status_mask))
623 return;
624
625 if ((pipestat & enable_mask) == 0)
626 return;
627
628 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
629
630 pipestat &= ~enable_mask;
631 I915_WRITE(reg, pipestat);
632 POSTING_READ(reg);
633 }
634
635 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
636 {
637 u32 enable_mask = status_mask << 16;
638
639 /*
640 * On pipe A we don't support the PSR interrupt yet,
641 * on pipe B and C the same bit MBZ.
642 */
643 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
644 return 0;
645 /*
646 * On pipe B and C we don't support the PSR interrupt yet, on pipe
647 * A the same bit is for perf counters which we don't use either.
648 */
649 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
650 return 0;
651
652 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
653 SPRITE0_FLIP_DONE_INT_EN_VLV |
654 SPRITE1_FLIP_DONE_INT_EN_VLV);
655 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
656 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
657 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
658 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
659
660 return enable_mask;
661 }
662
663 void
664 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
665 u32 status_mask)
666 {
667 u32 enable_mask;
668
669 if (IS_VALLEYVIEW(dev_priv->dev))
670 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
671 status_mask);
672 else
673 enable_mask = status_mask << 16;
674 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
675 }
676
677 void
678 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
679 u32 status_mask)
680 {
681 u32 enable_mask;
682
683 if (IS_VALLEYVIEW(dev_priv->dev))
684 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
685 status_mask);
686 else
687 enable_mask = status_mask << 16;
688 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
689 }
690
691 /**
692 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
693 */
694 static void i915_enable_asle_pipestat(struct drm_device *dev)
695 {
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 unsigned long irqflags;
698
699 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
700 return;
701
702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
703
704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
705 if (INTEL_INFO(dev)->gen >= 4)
706 i915_enable_pipestat(dev_priv, PIPE_A,
707 PIPE_LEGACY_BLC_EVENT_STATUS);
708
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
710 }
711
712 /**
713 * i915_pipe_enabled - check if a pipe is enabled
714 * @dev: DRM device
715 * @pipe: pipe to check
716 *
717 * Reading certain registers when the pipe is disabled can hang the chip.
718 * Use this routine to make sure the PLL is running and the pipe is active
719 * before reading such registers if unsure.
720 */
721 static int
722 i915_pipe_enabled(struct drm_device *dev, int pipe)
723 {
724 struct drm_i915_private *dev_priv = dev->dev_private;
725
726 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
727 /* Locking is horribly broken here, but whatever. */
728 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
730
731 return intel_crtc->active;
732 } else {
733 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
734 }
735 }
736
737 /*
738 * This timing diagram depicts the video signal in and
739 * around the vertical blanking period.
740 *
741 * Assumptions about the fictitious mode used in this example:
742 * vblank_start >= 3
743 * vsync_start = vblank_start + 1
744 * vsync_end = vblank_start + 2
745 * vtotal = vblank_start + 3
746 *
747 * start of vblank:
748 * latch double buffered registers
749 * increment frame counter (ctg+)
750 * generate start of vblank interrupt (gen4+)
751 * |
752 * | frame start:
753 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
754 * | may be shifted forward 1-3 extra lines via PIPECONF
755 * | |
756 * | | start of vsync:
757 * | | generate vsync interrupt
758 * | | |
759 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
760 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
761 * ----va---> <-----------------vb--------------------> <--------va-------------
762 * | | <----vs-----> |
763 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
764 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
765 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
766 * | | |
767 * last visible pixel first visible pixel
768 * | increment frame counter (gen3/4)
769 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
770 *
771 * x = horizontal active
772 * _ = horizontal blanking
773 * hs = horizontal sync
774 * va = vertical active
775 * vb = vertical blanking
776 * vs = vertical sync
777 * vbs = vblank_start (number)
778 *
779 * Summary:
780 * - most events happen at the start of horizontal sync
781 * - frame start happens at the start of horizontal blank, 1-4 lines
782 * (depending on PIPECONF settings) after the start of vblank
783 * - gen3/4 pixel and frame counter are synchronized with the start
784 * of horizontal active on the first line of vertical active
785 */
786
787 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
788 {
789 /* Gen2 doesn't have a hardware frame counter */
790 return 0;
791 }
792
793 /* Called from drm generic code, passed a 'crtc', which
794 * we use as a pipe index
795 */
796 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
797 {
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 unsigned long high_frame;
800 unsigned long low_frame;
801 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
802
803 if (!i915_pipe_enabled(dev, pipe)) {
804 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
805 "pipe %c\n", pipe_name(pipe));
806 return 0;
807 }
808
809 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
810 struct intel_crtc *intel_crtc =
811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
812 const struct drm_display_mode *mode =
813 &intel_crtc->config.adjusted_mode;
814
815 htotal = mode->crtc_htotal;
816 hsync_start = mode->crtc_hsync_start;
817 vbl_start = mode->crtc_vblank_start;
818 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
819 vbl_start = DIV_ROUND_UP(vbl_start, 2);
820 } else {
821 enum transcoder cpu_transcoder = (enum transcoder) pipe;
822
823 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
824 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
825 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
826 if ((I915_READ(PIPECONF(cpu_transcoder)) &
827 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
828 vbl_start = DIV_ROUND_UP(vbl_start, 2);
829 }
830
831 /* Convert to pixel count */
832 vbl_start *= htotal;
833
834 /* Start of vblank event occurs at start of hsync */
835 vbl_start -= htotal - hsync_start;
836
837 high_frame = PIPEFRAME(pipe);
838 low_frame = PIPEFRAMEPIXEL(pipe);
839
840 /*
841 * High & low register fields aren't synchronized, so make sure
842 * we get a low value that's stable across two reads of the high
843 * register.
844 */
845 do {
846 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
847 low = I915_READ(low_frame);
848 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
849 } while (high1 != high2);
850
851 high1 >>= PIPE_FRAME_HIGH_SHIFT;
852 pixel = low & PIPE_PIXEL_MASK;
853 low >>= PIPE_FRAME_LOW_SHIFT;
854
855 /*
856 * The frame counter increments at beginning of active.
857 * Cook up a vblank counter by also checking the pixel
858 * counter against vblank start.
859 */
860 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
861 }
862
863 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
864 {
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 int reg = PIPE_FRMCOUNT_GM45(pipe);
867
868 if (!i915_pipe_enabled(dev, pipe)) {
869 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
870 "pipe %c\n", pipe_name(pipe));
871 return 0;
872 }
873
874 return I915_READ(reg);
875 }
876
877 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
878 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
879
880 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
881 {
882 struct drm_device *dev = crtc->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
885 enum pipe pipe = crtc->pipe;
886 int position, vtotal;
887
888 vtotal = mode->crtc_vtotal;
889 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
890 vtotal /= 2;
891
892 if (IS_GEN2(dev))
893 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
894 else
895 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
896
897 /*
898 * See update_scanline_offset() for the details on the
899 * scanline_offset adjustment.
900 */
901 return (position + crtc->scanline_offset) % vtotal;
902 }
903
904 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
905 unsigned int flags, int *vpos, int *hpos,
906 ktime_t *stime, ktime_t *etime)
907 {
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
911 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
912 int position;
913 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
914 bool in_vbl = true;
915 int ret = 0;
916 unsigned long irqflags;
917
918 if (!intel_crtc->active) {
919 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
920 "pipe %c\n", pipe_name(pipe));
921 return 0;
922 }
923
924 htotal = mode->crtc_htotal;
925 hsync_start = mode->crtc_hsync_start;
926 vtotal = mode->crtc_vtotal;
927 vbl_start = mode->crtc_vblank_start;
928 vbl_end = mode->crtc_vblank_end;
929
930 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
931 vbl_start = DIV_ROUND_UP(vbl_start, 2);
932 vbl_end /= 2;
933 vtotal /= 2;
934 }
935
936 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
937
938 /*
939 * Lock uncore.lock, as we will do multiple timing critical raw
940 * register reads, potentially with preemption disabled, so the
941 * following code must not block on uncore.lock.
942 */
943 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
944
945 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
946
947 /* Get optional system timestamp before query. */
948 if (stime)
949 *stime = ktime_get();
950
951 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
952 /* No obvious pixelcount register. Only query vertical
953 * scanout position from Display scan line register.
954 */
955 position = __intel_get_crtc_scanline(intel_crtc);
956 } else {
957 /* Have access to pixelcount since start of frame.
958 * We can split this into vertical and horizontal
959 * scanout position.
960 */
961 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
962
963 /* convert to pixel counts */
964 vbl_start *= htotal;
965 vbl_end *= htotal;
966 vtotal *= htotal;
967
968 /*
969 * In interlaced modes, the pixel counter counts all pixels,
970 * so one field will have htotal more pixels. In order to avoid
971 * the reported position from jumping backwards when the pixel
972 * counter is beyond the length of the shorter field, just
973 * clamp the position the length of the shorter field. This
974 * matches how the scanline counter based position works since
975 * the scanline counter doesn't count the two half lines.
976 */
977 if (position >= vtotal)
978 position = vtotal - 1;
979
980 /*
981 * Start of vblank interrupt is triggered at start of hsync,
982 * just prior to the first active line of vblank. However we
983 * consider lines to start at the leading edge of horizontal
984 * active. So, should we get here before we've crossed into
985 * the horizontal active of the first line in vblank, we would
986 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
987 * always add htotal-hsync_start to the current pixel position.
988 */
989 position = (position + htotal - hsync_start) % vtotal;
990 }
991
992 /* Get optional system timestamp after query. */
993 if (etime)
994 *etime = ktime_get();
995
996 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
997
998 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
999
1000 in_vbl = position >= vbl_start && position < vbl_end;
1001
1002 /*
1003 * While in vblank, position will be negative
1004 * counting up towards 0 at vbl_end. And outside
1005 * vblank, position will be positive counting
1006 * up since vbl_end.
1007 */
1008 if (position >= vbl_start)
1009 position -= vbl_end;
1010 else
1011 position += vtotal - vbl_end;
1012
1013 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1014 *vpos = position;
1015 *hpos = 0;
1016 } else {
1017 *vpos = position / htotal;
1018 *hpos = position - (*vpos * htotal);
1019 }
1020
1021 /* In vblank? */
1022 if (in_vbl)
1023 ret |= DRM_SCANOUTPOS_INVBL;
1024
1025 return ret;
1026 }
1027
1028 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1029 {
1030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031 unsigned long irqflags;
1032 int position;
1033
1034 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035 position = __intel_get_crtc_scanline(crtc);
1036 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1037
1038 return position;
1039 }
1040
1041 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1042 int *max_error,
1043 struct timeval *vblank_time,
1044 unsigned flags)
1045 {
1046 struct drm_crtc *crtc;
1047
1048 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1049 DRM_ERROR("Invalid crtc %d\n", pipe);
1050 return -EINVAL;
1051 }
1052
1053 /* Get drm_crtc to timestamp: */
1054 crtc = intel_get_crtc_for_pipe(dev, pipe);
1055 if (crtc == NULL) {
1056 DRM_ERROR("Invalid crtc %d\n", pipe);
1057 return -EINVAL;
1058 }
1059
1060 if (!crtc->enabled) {
1061 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1062 return -EBUSY;
1063 }
1064
1065 /* Helper routine in DRM core does all the work: */
1066 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1067 vblank_time, flags,
1068 crtc,
1069 &to_intel_crtc(crtc)->config.adjusted_mode);
1070 }
1071
1072 static bool intel_hpd_irq_event(struct drm_device *dev,
1073 struct drm_connector *connector)
1074 {
1075 enum drm_connector_status old_status;
1076
1077 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078 old_status = connector->status;
1079
1080 connector->status = connector->funcs->detect(connector, false);
1081 if (old_status == connector->status)
1082 return false;
1083
1084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1085 connector->base.id,
1086 connector->name,
1087 drm_get_connector_status_name(old_status),
1088 drm_get_connector_status_name(connector->status));
1089
1090 return true;
1091 }
1092
1093 /*
1094 * Handle hotplug events outside the interrupt handler proper.
1095 */
1096 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1097
1098 static void i915_hotplug_work_func(struct work_struct *work)
1099 {
1100 struct drm_i915_private *dev_priv =
1101 container_of(work, struct drm_i915_private, hotplug_work);
1102 struct drm_device *dev = dev_priv->dev;
1103 struct drm_mode_config *mode_config = &dev->mode_config;
1104 struct intel_connector *intel_connector;
1105 struct intel_encoder *intel_encoder;
1106 struct drm_connector *connector;
1107 unsigned long irqflags;
1108 bool hpd_disabled = false;
1109 bool changed = false;
1110 u32 hpd_event_bits;
1111
1112 /* HPD irq before everything is fully set up. */
1113 if (!dev_priv->enable_hotplug_processing)
1114 return;
1115
1116 mutex_lock(&mode_config->mutex);
1117 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1118
1119 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1120
1121 hpd_event_bits = dev_priv->hpd_event_bits;
1122 dev_priv->hpd_event_bits = 0;
1123 list_for_each_entry(connector, &mode_config->connector_list, head) {
1124 intel_connector = to_intel_connector(connector);
1125 intel_encoder = intel_connector->encoder;
1126 if (intel_encoder->hpd_pin > HPD_NONE &&
1127 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1128 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1129 DRM_INFO("HPD interrupt storm detected on connector %s: "
1130 "switching from hotplug detection to polling\n",
1131 connector->name);
1132 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1133 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1134 | DRM_CONNECTOR_POLL_DISCONNECT;
1135 hpd_disabled = true;
1136 }
1137 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1138 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1139 connector->name, intel_encoder->hpd_pin);
1140 }
1141 }
1142 /* if there were no outputs to poll, poll was disabled,
1143 * therefore make sure it's enabled when disabling HPD on
1144 * some connectors */
1145 if (hpd_disabled) {
1146 drm_kms_helper_poll_enable(dev);
1147 mod_timer(&dev_priv->hotplug_reenable_timer,
1148 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1149 }
1150
1151 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1152
1153 list_for_each_entry(connector, &mode_config->connector_list, head) {
1154 intel_connector = to_intel_connector(connector);
1155 intel_encoder = intel_connector->encoder;
1156 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1157 if (intel_encoder->hot_plug)
1158 intel_encoder->hot_plug(intel_encoder);
1159 if (intel_hpd_irq_event(dev, connector))
1160 changed = true;
1161 }
1162 }
1163 mutex_unlock(&mode_config->mutex);
1164
1165 if (changed)
1166 drm_kms_helper_hotplug_event(dev);
1167 }
1168
1169 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1170 {
1171 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1172 }
1173
1174 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1175 {
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 u32 busy_up, busy_down, max_avg, min_avg;
1178 u8 new_delay;
1179
1180 spin_lock(&mchdev_lock);
1181
1182 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1183
1184 new_delay = dev_priv->ips.cur_delay;
1185
1186 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1187 busy_up = I915_READ(RCPREVBSYTUPAVG);
1188 busy_down = I915_READ(RCPREVBSYTDNAVG);
1189 max_avg = I915_READ(RCBMAXAVG);
1190 min_avg = I915_READ(RCBMINAVG);
1191
1192 /* Handle RCS change request from hw */
1193 if (busy_up > max_avg) {
1194 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1195 new_delay = dev_priv->ips.cur_delay - 1;
1196 if (new_delay < dev_priv->ips.max_delay)
1197 new_delay = dev_priv->ips.max_delay;
1198 } else if (busy_down < min_avg) {
1199 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1200 new_delay = dev_priv->ips.cur_delay + 1;
1201 if (new_delay > dev_priv->ips.min_delay)
1202 new_delay = dev_priv->ips.min_delay;
1203 }
1204
1205 if (ironlake_set_drps(dev, new_delay))
1206 dev_priv->ips.cur_delay = new_delay;
1207
1208 spin_unlock(&mchdev_lock);
1209
1210 return;
1211 }
1212
1213 static void notify_ring(struct drm_device *dev,
1214 struct intel_engine_cs *ring)
1215 {
1216 if (!intel_ring_initialized(ring))
1217 return;
1218
1219 trace_i915_gem_request_complete(ring);
1220
1221 if (drm_core_check_feature(dev, DRIVER_MODESET))
1222 intel_notify_mmio_flip(ring);
1223
1224 wake_up_all(&ring->irq_queue);
1225 i915_queue_hangcheck(dev);
1226 }
1227
1228 static void gen6_pm_rps_work(struct work_struct *work)
1229 {
1230 struct drm_i915_private *dev_priv =
1231 container_of(work, struct drm_i915_private, rps.work);
1232 u32 pm_iir;
1233 int new_delay, adj;
1234
1235 spin_lock_irq(&dev_priv->irq_lock);
1236 pm_iir = dev_priv->rps.pm_iir;
1237 dev_priv->rps.pm_iir = 0;
1238 if (IS_BROADWELL(dev_priv->dev))
1239 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1240 else {
1241 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1242 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1243 }
1244 spin_unlock_irq(&dev_priv->irq_lock);
1245
1246 /* Make sure we didn't queue anything we're not going to process. */
1247 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1248
1249 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1250 return;
1251
1252 mutex_lock(&dev_priv->rps.hw_lock);
1253
1254 adj = dev_priv->rps.last_adj;
1255 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1256 if (adj > 0)
1257 adj *= 2;
1258 else {
1259 /* CHV needs even encode values */
1260 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1261 }
1262 new_delay = dev_priv->rps.cur_freq + adj;
1263
1264 /*
1265 * For better performance, jump directly
1266 * to RPe if we're below it.
1267 */
1268 if (new_delay < dev_priv->rps.efficient_freq)
1269 new_delay = dev_priv->rps.efficient_freq;
1270 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1271 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1272 new_delay = dev_priv->rps.efficient_freq;
1273 else
1274 new_delay = dev_priv->rps.min_freq_softlimit;
1275 adj = 0;
1276 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1277 if (adj < 0)
1278 adj *= 2;
1279 else {
1280 /* CHV needs even encode values */
1281 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1282 }
1283 new_delay = dev_priv->rps.cur_freq + adj;
1284 } else { /* unknown event */
1285 new_delay = dev_priv->rps.cur_freq;
1286 }
1287
1288 /* sysfs frequency interfaces may have snuck in while servicing the
1289 * interrupt
1290 */
1291 new_delay = clamp_t(int, new_delay,
1292 dev_priv->rps.min_freq_softlimit,
1293 dev_priv->rps.max_freq_softlimit);
1294
1295 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1296
1297 if (IS_VALLEYVIEW(dev_priv->dev))
1298 valleyview_set_rps(dev_priv->dev, new_delay);
1299 else
1300 gen6_set_rps(dev_priv->dev, new_delay);
1301
1302 mutex_unlock(&dev_priv->rps.hw_lock);
1303 }
1304
1305
1306 /**
1307 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1308 * occurred.
1309 * @work: workqueue struct
1310 *
1311 * Doesn't actually do anything except notify userspace. As a consequence of
1312 * this event, userspace should try to remap the bad rows since statistically
1313 * it is likely the same row is more likely to go bad again.
1314 */
1315 static void ivybridge_parity_work(struct work_struct *work)
1316 {
1317 struct drm_i915_private *dev_priv =
1318 container_of(work, struct drm_i915_private, l3_parity.error_work);
1319 u32 error_status, row, bank, subbank;
1320 char *parity_event[6];
1321 uint32_t misccpctl;
1322 unsigned long flags;
1323 uint8_t slice = 0;
1324
1325 /* We must turn off DOP level clock gating to access the L3 registers.
1326 * In order to prevent a get/put style interface, acquire struct mutex
1327 * any time we access those registers.
1328 */
1329 mutex_lock(&dev_priv->dev->struct_mutex);
1330
1331 /* If we've screwed up tracking, just let the interrupt fire again */
1332 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1333 goto out;
1334
1335 misccpctl = I915_READ(GEN7_MISCCPCTL);
1336 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1337 POSTING_READ(GEN7_MISCCPCTL);
1338
1339 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1340 u32 reg;
1341
1342 slice--;
1343 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1344 break;
1345
1346 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1347
1348 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1349
1350 error_status = I915_READ(reg);
1351 row = GEN7_PARITY_ERROR_ROW(error_status);
1352 bank = GEN7_PARITY_ERROR_BANK(error_status);
1353 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1354
1355 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1356 POSTING_READ(reg);
1357
1358 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1359 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1360 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1361 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1362 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1363 parity_event[5] = NULL;
1364
1365 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1366 KOBJ_CHANGE, parity_event);
1367
1368 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1369 slice, row, bank, subbank);
1370
1371 kfree(parity_event[4]);
1372 kfree(parity_event[3]);
1373 kfree(parity_event[2]);
1374 kfree(parity_event[1]);
1375 }
1376
1377 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1378
1379 out:
1380 WARN_ON(dev_priv->l3_parity.which_slice);
1381 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1382 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1383 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1384
1385 mutex_unlock(&dev_priv->dev->struct_mutex);
1386 }
1387
1388 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1389 {
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391
1392 if (!HAS_L3_DPF(dev))
1393 return;
1394
1395 spin_lock(&dev_priv->irq_lock);
1396 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1397 spin_unlock(&dev_priv->irq_lock);
1398
1399 iir &= GT_PARITY_ERROR(dev);
1400 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1401 dev_priv->l3_parity.which_slice |= 1 << 1;
1402
1403 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1404 dev_priv->l3_parity.which_slice |= 1 << 0;
1405
1406 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1407 }
1408
1409 static void ilk_gt_irq_handler(struct drm_device *dev,
1410 struct drm_i915_private *dev_priv,
1411 u32 gt_iir)
1412 {
1413 if (gt_iir &
1414 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1415 notify_ring(dev, &dev_priv->ring[RCS]);
1416 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1417 notify_ring(dev, &dev_priv->ring[VCS]);
1418 }
1419
1420 static void snb_gt_irq_handler(struct drm_device *dev,
1421 struct drm_i915_private *dev_priv,
1422 u32 gt_iir)
1423 {
1424
1425 if (gt_iir &
1426 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1427 notify_ring(dev, &dev_priv->ring[RCS]);
1428 if (gt_iir & GT_BSD_USER_INTERRUPT)
1429 notify_ring(dev, &dev_priv->ring[VCS]);
1430 if (gt_iir & GT_BLT_USER_INTERRUPT)
1431 notify_ring(dev, &dev_priv->ring[BCS]);
1432
1433 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1434 GT_BSD_CS_ERROR_INTERRUPT |
1435 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1436 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1437 gt_iir);
1438 }
1439
1440 if (gt_iir & GT_PARITY_ERROR(dev))
1441 ivybridge_parity_error_irq_handler(dev, gt_iir);
1442 }
1443
1444 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1445 {
1446 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1447 return;
1448
1449 spin_lock(&dev_priv->irq_lock);
1450 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1451 bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1452 spin_unlock(&dev_priv->irq_lock);
1453
1454 queue_work(dev_priv->wq, &dev_priv->rps.work);
1455 }
1456
1457 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1458 struct drm_i915_private *dev_priv,
1459 u32 master_ctl)
1460 {
1461 u32 rcs, bcs, vcs;
1462 uint32_t tmp = 0;
1463 irqreturn_t ret = IRQ_NONE;
1464
1465 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1466 tmp = I915_READ(GEN8_GT_IIR(0));
1467 if (tmp) {
1468 I915_WRITE(GEN8_GT_IIR(0), tmp);
1469 ret = IRQ_HANDLED;
1470 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1471 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1472 if (rcs & GT_RENDER_USER_INTERRUPT)
1473 notify_ring(dev, &dev_priv->ring[RCS]);
1474 if (bcs & GT_RENDER_USER_INTERRUPT)
1475 notify_ring(dev, &dev_priv->ring[BCS]);
1476 } else
1477 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1478 }
1479
1480 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1481 tmp = I915_READ(GEN8_GT_IIR(1));
1482 if (tmp) {
1483 I915_WRITE(GEN8_GT_IIR(1), tmp);
1484 ret = IRQ_HANDLED;
1485 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1486 if (vcs & GT_RENDER_USER_INTERRUPT)
1487 notify_ring(dev, &dev_priv->ring[VCS]);
1488 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1489 if (vcs & GT_RENDER_USER_INTERRUPT)
1490 notify_ring(dev, &dev_priv->ring[VCS2]);
1491 } else
1492 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1493 }
1494
1495 if (master_ctl & GEN8_GT_PM_IRQ) {
1496 tmp = I915_READ(GEN8_GT_IIR(2));
1497 if (tmp & dev_priv->pm_rps_events) {
1498 I915_WRITE(GEN8_GT_IIR(2),
1499 tmp & dev_priv->pm_rps_events);
1500 ret = IRQ_HANDLED;
1501 gen8_rps_irq_handler(dev_priv, tmp);
1502 } else
1503 DRM_ERROR("The master control interrupt lied (PM)!\n");
1504 }
1505
1506 if (master_ctl & GEN8_GT_VECS_IRQ) {
1507 tmp = I915_READ(GEN8_GT_IIR(3));
1508 if (tmp) {
1509 I915_WRITE(GEN8_GT_IIR(3), tmp);
1510 ret = IRQ_HANDLED;
1511 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1512 if (vcs & GT_RENDER_USER_INTERRUPT)
1513 notify_ring(dev, &dev_priv->ring[VECS]);
1514 } else
1515 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1516 }
1517
1518 return ret;
1519 }
1520
1521 #define HPD_STORM_DETECT_PERIOD 1000
1522 #define HPD_STORM_THRESHOLD 5
1523
1524 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1525 u32 hotplug_trigger,
1526 const u32 *hpd)
1527 {
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 int i;
1530 bool storm_detected = false;
1531
1532 if (!hotplug_trigger)
1533 return;
1534
1535 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1536 hotplug_trigger);
1537
1538 spin_lock(&dev_priv->irq_lock);
1539 for (i = 1; i < HPD_NUM_PINS; i++) {
1540
1541 if (hpd[i] & hotplug_trigger &&
1542 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1543 /*
1544 * On GMCH platforms the interrupt mask bits only
1545 * prevent irq generation, not the setting of the
1546 * hotplug bits itself. So only WARN about unexpected
1547 * interrupts on saner platforms.
1548 */
1549 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1550 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1551 hotplug_trigger, i, hpd[i]);
1552
1553 continue;
1554 }
1555
1556 if (!(hpd[i] & hotplug_trigger) ||
1557 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1558 continue;
1559
1560 dev_priv->hpd_event_bits |= (1 << i);
1561 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1562 dev_priv->hpd_stats[i].hpd_last_jiffies
1563 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1564 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1565 dev_priv->hpd_stats[i].hpd_cnt = 0;
1566 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1567 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1568 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1569 dev_priv->hpd_event_bits &= ~(1 << i);
1570 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1571 storm_detected = true;
1572 } else {
1573 dev_priv->hpd_stats[i].hpd_cnt++;
1574 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1575 dev_priv->hpd_stats[i].hpd_cnt);
1576 }
1577 }
1578
1579 if (storm_detected)
1580 dev_priv->display.hpd_irq_setup(dev);
1581 spin_unlock(&dev_priv->irq_lock);
1582
1583 /*
1584 * Our hotplug handler can grab modeset locks (by calling down into the
1585 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1586 * queue for otherwise the flush_work in the pageflip code will
1587 * deadlock.
1588 */
1589 schedule_work(&dev_priv->hotplug_work);
1590 }
1591
1592 static void gmbus_irq_handler(struct drm_device *dev)
1593 {
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 wake_up_all(&dev_priv->gmbus_wait_queue);
1597 }
1598
1599 static void dp_aux_irq_handler(struct drm_device *dev)
1600 {
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602
1603 wake_up_all(&dev_priv->gmbus_wait_queue);
1604 }
1605
1606 #if defined(CONFIG_DEBUG_FS)
1607 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1608 uint32_t crc0, uint32_t crc1,
1609 uint32_t crc2, uint32_t crc3,
1610 uint32_t crc4)
1611 {
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1614 struct intel_pipe_crc_entry *entry;
1615 int head, tail;
1616
1617 spin_lock(&pipe_crc->lock);
1618
1619 if (!pipe_crc->entries) {
1620 spin_unlock(&pipe_crc->lock);
1621 DRM_ERROR("spurious interrupt\n");
1622 return;
1623 }
1624
1625 head = pipe_crc->head;
1626 tail = pipe_crc->tail;
1627
1628 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1629 spin_unlock(&pipe_crc->lock);
1630 DRM_ERROR("CRC buffer overflowing\n");
1631 return;
1632 }
1633
1634 entry = &pipe_crc->entries[head];
1635
1636 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1637 entry->crc[0] = crc0;
1638 entry->crc[1] = crc1;
1639 entry->crc[2] = crc2;
1640 entry->crc[3] = crc3;
1641 entry->crc[4] = crc4;
1642
1643 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1644 pipe_crc->head = head;
1645
1646 spin_unlock(&pipe_crc->lock);
1647
1648 wake_up_interruptible(&pipe_crc->wq);
1649 }
1650 #else
1651 static inline void
1652 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1653 uint32_t crc0, uint32_t crc1,
1654 uint32_t crc2, uint32_t crc3,
1655 uint32_t crc4) {}
1656 #endif
1657
1658
1659 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1660 {
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662
1663 display_pipe_crc_irq_handler(dev, pipe,
1664 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1665 0, 0, 0, 0);
1666 }
1667
1668 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1669 {
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671
1672 display_pipe_crc_irq_handler(dev, pipe,
1673 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1674 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1675 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1676 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1677 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1678 }
1679
1680 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1681 {
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 uint32_t res1, res2;
1684
1685 if (INTEL_INFO(dev)->gen >= 3)
1686 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1687 else
1688 res1 = 0;
1689
1690 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1691 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1692 else
1693 res2 = 0;
1694
1695 display_pipe_crc_irq_handler(dev, pipe,
1696 I915_READ(PIPE_CRC_RES_RED(pipe)),
1697 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1698 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1699 res1, res2);
1700 }
1701
1702 /* The RPS events need forcewake, so we add them to a work queue and mask their
1703 * IMR bits until the work is done. Other interrupts can be processed without
1704 * the work queue. */
1705 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1706 {
1707 if (pm_iir & dev_priv->pm_rps_events) {
1708 spin_lock(&dev_priv->irq_lock);
1709 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1710 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1711 spin_unlock(&dev_priv->irq_lock);
1712
1713 queue_work(dev_priv->wq, &dev_priv->rps.work);
1714 }
1715
1716 if (HAS_VEBOX(dev_priv->dev)) {
1717 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1718 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1719
1720 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1721 i915_handle_error(dev_priv->dev, false,
1722 "VEBOX CS error interrupt 0x%08x",
1723 pm_iir);
1724 }
1725 }
1726 }
1727
1728 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1729 {
1730 struct intel_crtc *crtc;
1731
1732 if (!drm_handle_vblank(dev, pipe))
1733 return false;
1734
1735 crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1736 wake_up(&crtc->vbl_wait);
1737
1738 return true;
1739 }
1740
1741 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1742 {
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 u32 pipe_stats[I915_MAX_PIPES] = { };
1745 int pipe;
1746
1747 spin_lock(&dev_priv->irq_lock);
1748 for_each_pipe(pipe) {
1749 int reg;
1750 u32 mask, iir_bit = 0;
1751
1752 /*
1753 * PIPESTAT bits get signalled even when the interrupt is
1754 * disabled with the mask bits, and some of the status bits do
1755 * not generate interrupts at all (like the underrun bit). Hence
1756 * we need to be careful that we only handle what we want to
1757 * handle.
1758 */
1759 mask = 0;
1760 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1761 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1762
1763 switch (pipe) {
1764 case PIPE_A:
1765 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1766 break;
1767 case PIPE_B:
1768 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1769 break;
1770 case PIPE_C:
1771 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1772 break;
1773 }
1774 if (iir & iir_bit)
1775 mask |= dev_priv->pipestat_irq_mask[pipe];
1776
1777 if (!mask)
1778 continue;
1779
1780 reg = PIPESTAT(pipe);
1781 mask |= PIPESTAT_INT_ENABLE_MASK;
1782 pipe_stats[pipe] = I915_READ(reg) & mask;
1783
1784 /*
1785 * Clear the PIPE*STAT regs before the IIR
1786 */
1787 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1788 PIPESTAT_INT_STATUS_MASK))
1789 I915_WRITE(reg, pipe_stats[pipe]);
1790 }
1791 spin_unlock(&dev_priv->irq_lock);
1792
1793 for_each_pipe(pipe) {
1794 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1795 intel_pipe_handle_vblank(dev, pipe);
1796
1797 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1798 intel_prepare_page_flip(dev, pipe);
1799 intel_finish_page_flip(dev, pipe);
1800 }
1801
1802 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1803 i9xx_pipe_crc_irq_handler(dev, pipe);
1804
1805 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1806 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1807 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1808 }
1809
1810 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1811 gmbus_irq_handler(dev);
1812 }
1813
1814 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1815 {
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1818
1819 if (hotplug_status) {
1820 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1821 /*
1822 * Make sure hotplug status is cleared before we clear IIR, or else we
1823 * may miss hotplug events.
1824 */
1825 POSTING_READ(PORT_HOTPLUG_STAT);
1826
1827 if (IS_G4X(dev)) {
1828 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1829
1830 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1831 } else {
1832 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1833
1834 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1835 }
1836
1837 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1838 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1839 dp_aux_irq_handler(dev);
1840 }
1841 }
1842
1843 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1844 {
1845 struct drm_device *dev = arg;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847 u32 iir, gt_iir, pm_iir;
1848 irqreturn_t ret = IRQ_NONE;
1849
1850 while (true) {
1851 /* Find, clear, then process each source of interrupt */
1852
1853 gt_iir = I915_READ(GTIIR);
1854 if (gt_iir)
1855 I915_WRITE(GTIIR, gt_iir);
1856
1857 pm_iir = I915_READ(GEN6_PMIIR);
1858 if (pm_iir)
1859 I915_WRITE(GEN6_PMIIR, pm_iir);
1860
1861 iir = I915_READ(VLV_IIR);
1862 if (iir) {
1863 /* Consume port before clearing IIR or we'll miss events */
1864 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1865 i9xx_hpd_irq_handler(dev);
1866 I915_WRITE(VLV_IIR, iir);
1867 }
1868
1869 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1870 goto out;
1871
1872 ret = IRQ_HANDLED;
1873
1874 if (gt_iir)
1875 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1876 if (pm_iir)
1877 gen6_rps_irq_handler(dev_priv, pm_iir);
1878 /* Call regardless, as some status bits might not be
1879 * signalled in iir */
1880 valleyview_pipestat_irq_handler(dev, iir);
1881 }
1882
1883 out:
1884 return ret;
1885 }
1886
1887 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1888 {
1889 struct drm_device *dev = arg;
1890 struct drm_i915_private *dev_priv = dev->dev_private;
1891 u32 master_ctl, iir;
1892 irqreturn_t ret = IRQ_NONE;
1893
1894 for (;;) {
1895 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1896 iir = I915_READ(VLV_IIR);
1897
1898 if (master_ctl == 0 && iir == 0)
1899 break;
1900
1901 ret = IRQ_HANDLED;
1902
1903 I915_WRITE(GEN8_MASTER_IRQ, 0);
1904
1905 /* Find, clear, then process each source of interrupt */
1906
1907 if (iir) {
1908 /* Consume port before clearing IIR or we'll miss events */
1909 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1910 i9xx_hpd_irq_handler(dev);
1911 I915_WRITE(VLV_IIR, iir);
1912 }
1913
1914 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1915
1916 /* Call regardless, as some status bits might not be
1917 * signalled in iir */
1918 valleyview_pipestat_irq_handler(dev, iir);
1919
1920 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1921 POSTING_READ(GEN8_MASTER_IRQ);
1922 }
1923
1924 return ret;
1925 }
1926
1927 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1928 {
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 int pipe;
1931 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1932
1933 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1934
1935 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1936 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1937 SDE_AUDIO_POWER_SHIFT);
1938 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1939 port_name(port));
1940 }
1941
1942 if (pch_iir & SDE_AUX_MASK)
1943 dp_aux_irq_handler(dev);
1944
1945 if (pch_iir & SDE_GMBUS)
1946 gmbus_irq_handler(dev);
1947
1948 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1949 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1950
1951 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1952 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1953
1954 if (pch_iir & SDE_POISON)
1955 DRM_ERROR("PCH poison interrupt\n");
1956
1957 if (pch_iir & SDE_FDI_MASK)
1958 for_each_pipe(pipe)
1959 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1960 pipe_name(pipe),
1961 I915_READ(FDI_RX_IIR(pipe)));
1962
1963 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1964 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1965
1966 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1967 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1968
1969 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1970 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1971 false))
1972 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1973
1974 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1975 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1976 false))
1977 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1978 }
1979
1980 static void ivb_err_int_handler(struct drm_device *dev)
1981 {
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 u32 err_int = I915_READ(GEN7_ERR_INT);
1984 enum pipe pipe;
1985
1986 if (err_int & ERR_INT_POISON)
1987 DRM_ERROR("Poison interrupt\n");
1988
1989 for_each_pipe(pipe) {
1990 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1991 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1992 false))
1993 DRM_ERROR("Pipe %c FIFO underrun\n",
1994 pipe_name(pipe));
1995 }
1996
1997 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1998 if (IS_IVYBRIDGE(dev))
1999 ivb_pipe_crc_irq_handler(dev, pipe);
2000 else
2001 hsw_pipe_crc_irq_handler(dev, pipe);
2002 }
2003 }
2004
2005 I915_WRITE(GEN7_ERR_INT, err_int);
2006 }
2007
2008 static void cpt_serr_int_handler(struct drm_device *dev)
2009 {
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 u32 serr_int = I915_READ(SERR_INT);
2012
2013 if (serr_int & SERR_INT_POISON)
2014 DRM_ERROR("PCH poison interrupt\n");
2015
2016 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2017 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2018 false))
2019 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2020
2021 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2022 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2023 false))
2024 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2025
2026 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2027 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2028 false))
2029 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2030
2031 I915_WRITE(SERR_INT, serr_int);
2032 }
2033
2034 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2035 {
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037 int pipe;
2038 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2039
2040 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
2041
2042 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2043 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2044 SDE_AUDIO_POWER_SHIFT_CPT);
2045 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2046 port_name(port));
2047 }
2048
2049 if (pch_iir & SDE_AUX_MASK_CPT)
2050 dp_aux_irq_handler(dev);
2051
2052 if (pch_iir & SDE_GMBUS_CPT)
2053 gmbus_irq_handler(dev);
2054
2055 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2056 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2057
2058 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2059 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2060
2061 if (pch_iir & SDE_FDI_MASK_CPT)
2062 for_each_pipe(pipe)
2063 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2064 pipe_name(pipe),
2065 I915_READ(FDI_RX_IIR(pipe)));
2066
2067 if (pch_iir & SDE_ERROR_CPT)
2068 cpt_serr_int_handler(dev);
2069 }
2070
2071 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2072 {
2073 struct drm_i915_private *dev_priv = dev->dev_private;
2074 enum pipe pipe;
2075
2076 if (de_iir & DE_AUX_CHANNEL_A)
2077 dp_aux_irq_handler(dev);
2078
2079 if (de_iir & DE_GSE)
2080 intel_opregion_asle_intr(dev);
2081
2082 if (de_iir & DE_POISON)
2083 DRM_ERROR("Poison interrupt\n");
2084
2085 for_each_pipe(pipe) {
2086 if (de_iir & DE_PIPE_VBLANK(pipe))
2087 intel_pipe_handle_vblank(dev, pipe);
2088
2089 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2090 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2091 DRM_ERROR("Pipe %c FIFO underrun\n",
2092 pipe_name(pipe));
2093
2094 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2095 i9xx_pipe_crc_irq_handler(dev, pipe);
2096
2097 /* plane/pipes map 1:1 on ilk+ */
2098 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2099 intel_prepare_page_flip(dev, pipe);
2100 intel_finish_page_flip_plane(dev, pipe);
2101 }
2102 }
2103
2104 /* check event from PCH */
2105 if (de_iir & DE_PCH_EVENT) {
2106 u32 pch_iir = I915_READ(SDEIIR);
2107
2108 if (HAS_PCH_CPT(dev))
2109 cpt_irq_handler(dev, pch_iir);
2110 else
2111 ibx_irq_handler(dev, pch_iir);
2112
2113 /* should clear PCH hotplug event before clear CPU irq */
2114 I915_WRITE(SDEIIR, pch_iir);
2115 }
2116
2117 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2118 ironlake_rps_change_irq_handler(dev);
2119 }
2120
2121 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2122 {
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 enum pipe pipe;
2125
2126 if (de_iir & DE_ERR_INT_IVB)
2127 ivb_err_int_handler(dev);
2128
2129 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2130 dp_aux_irq_handler(dev);
2131
2132 if (de_iir & DE_GSE_IVB)
2133 intel_opregion_asle_intr(dev);
2134
2135 for_each_pipe(pipe) {
2136 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2137 intel_pipe_handle_vblank(dev, pipe);
2138
2139 /* plane/pipes map 1:1 on ilk+ */
2140 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2141 intel_prepare_page_flip(dev, pipe);
2142 intel_finish_page_flip_plane(dev, pipe);
2143 }
2144 }
2145
2146 /* check event from PCH */
2147 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2148 u32 pch_iir = I915_READ(SDEIIR);
2149
2150 cpt_irq_handler(dev, pch_iir);
2151
2152 /* clear PCH hotplug event before clear CPU irq */
2153 I915_WRITE(SDEIIR, pch_iir);
2154 }
2155 }
2156
2157 /*
2158 * To handle irqs with the minimum potential races with fresh interrupts, we:
2159 * 1 - Disable Master Interrupt Control.
2160 * 2 - Find the source(s) of the interrupt.
2161 * 3 - Clear the Interrupt Identity bits (IIR).
2162 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2163 * 5 - Re-enable Master Interrupt Control.
2164 */
2165 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2166 {
2167 struct drm_device *dev = arg;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2170 irqreturn_t ret = IRQ_NONE;
2171
2172 /* We get interrupts on unclaimed registers, so check for this before we
2173 * do any I915_{READ,WRITE}. */
2174 intel_uncore_check_errors(dev);
2175
2176 /* disable master interrupt before clearing iir */
2177 de_ier = I915_READ(DEIER);
2178 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2179 POSTING_READ(DEIER);
2180
2181 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2182 * interrupts will will be stored on its back queue, and then we'll be
2183 * able to process them after we restore SDEIER (as soon as we restore
2184 * it, we'll get an interrupt if SDEIIR still has something to process
2185 * due to its back queue). */
2186 if (!HAS_PCH_NOP(dev)) {
2187 sde_ier = I915_READ(SDEIER);
2188 I915_WRITE(SDEIER, 0);
2189 POSTING_READ(SDEIER);
2190 }
2191
2192 /* Find, clear, then process each source of interrupt */
2193
2194 gt_iir = I915_READ(GTIIR);
2195 if (gt_iir) {
2196 I915_WRITE(GTIIR, gt_iir);
2197 ret = IRQ_HANDLED;
2198 if (INTEL_INFO(dev)->gen >= 6)
2199 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2200 else
2201 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2202 }
2203
2204 de_iir = I915_READ(DEIIR);
2205 if (de_iir) {
2206 I915_WRITE(DEIIR, de_iir);
2207 ret = IRQ_HANDLED;
2208 if (INTEL_INFO(dev)->gen >= 7)
2209 ivb_display_irq_handler(dev, de_iir);
2210 else
2211 ilk_display_irq_handler(dev, de_iir);
2212 }
2213
2214 if (INTEL_INFO(dev)->gen >= 6) {
2215 u32 pm_iir = I915_READ(GEN6_PMIIR);
2216 if (pm_iir) {
2217 I915_WRITE(GEN6_PMIIR, pm_iir);
2218 ret = IRQ_HANDLED;
2219 gen6_rps_irq_handler(dev_priv, pm_iir);
2220 }
2221 }
2222
2223 I915_WRITE(DEIER, de_ier);
2224 POSTING_READ(DEIER);
2225 if (!HAS_PCH_NOP(dev)) {
2226 I915_WRITE(SDEIER, sde_ier);
2227 POSTING_READ(SDEIER);
2228 }
2229
2230 return ret;
2231 }
2232
2233 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2234 {
2235 struct drm_device *dev = arg;
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237 u32 master_ctl;
2238 irqreturn_t ret = IRQ_NONE;
2239 uint32_t tmp = 0;
2240 enum pipe pipe;
2241
2242 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2243 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2244 if (!master_ctl)
2245 return IRQ_NONE;
2246
2247 I915_WRITE(GEN8_MASTER_IRQ, 0);
2248 POSTING_READ(GEN8_MASTER_IRQ);
2249
2250 /* Find, clear, then process each source of interrupt */
2251
2252 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2253
2254 if (master_ctl & GEN8_DE_MISC_IRQ) {
2255 tmp = I915_READ(GEN8_DE_MISC_IIR);
2256 if (tmp) {
2257 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2258 ret = IRQ_HANDLED;
2259 if (tmp & GEN8_DE_MISC_GSE)
2260 intel_opregion_asle_intr(dev);
2261 else
2262 DRM_ERROR("Unexpected DE Misc interrupt\n");
2263 }
2264 else
2265 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2266 }
2267
2268 if (master_ctl & GEN8_DE_PORT_IRQ) {
2269 tmp = I915_READ(GEN8_DE_PORT_IIR);
2270 if (tmp) {
2271 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2272 ret = IRQ_HANDLED;
2273 if (tmp & GEN8_AUX_CHANNEL_A)
2274 dp_aux_irq_handler(dev);
2275 else
2276 DRM_ERROR("Unexpected DE Port interrupt\n");
2277 }
2278 else
2279 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2280 }
2281
2282 for_each_pipe(pipe) {
2283 uint32_t pipe_iir;
2284
2285 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2286 continue;
2287
2288 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2289 if (pipe_iir) {
2290 ret = IRQ_HANDLED;
2291 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2292 if (pipe_iir & GEN8_PIPE_VBLANK)
2293 intel_pipe_handle_vblank(dev, pipe);
2294
2295 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2296 intel_prepare_page_flip(dev, pipe);
2297 intel_finish_page_flip_plane(dev, pipe);
2298 }
2299
2300 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2301 hsw_pipe_crc_irq_handler(dev, pipe);
2302
2303 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2304 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2305 false))
2306 DRM_ERROR("Pipe %c FIFO underrun\n",
2307 pipe_name(pipe));
2308 }
2309
2310 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2311 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2312 pipe_name(pipe),
2313 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2314 }
2315 } else
2316 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2317 }
2318
2319 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2320 /*
2321 * FIXME(BDW): Assume for now that the new interrupt handling
2322 * scheme also closed the SDE interrupt handling race we've seen
2323 * on older pch-split platforms. But this needs testing.
2324 */
2325 u32 pch_iir = I915_READ(SDEIIR);
2326 if (pch_iir) {
2327 I915_WRITE(SDEIIR, pch_iir);
2328 ret = IRQ_HANDLED;
2329 cpt_irq_handler(dev, pch_iir);
2330 } else
2331 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2332
2333 }
2334
2335 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2336 POSTING_READ(GEN8_MASTER_IRQ);
2337
2338 return ret;
2339 }
2340
2341 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2342 bool reset_completed)
2343 {
2344 struct intel_engine_cs *ring;
2345 int i;
2346
2347 /*
2348 * Notify all waiters for GPU completion events that reset state has
2349 * been changed, and that they need to restart their wait after
2350 * checking for potential errors (and bail out to drop locks if there is
2351 * a gpu reset pending so that i915_error_work_func can acquire them).
2352 */
2353
2354 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2355 for_each_ring(ring, dev_priv, i)
2356 wake_up_all(&ring->irq_queue);
2357
2358 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2359 wake_up_all(&dev_priv->pending_flip_queue);
2360
2361 /*
2362 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2363 * reset state is cleared.
2364 */
2365 if (reset_completed)
2366 wake_up_all(&dev_priv->gpu_error.reset_queue);
2367 }
2368
2369 /**
2370 * i915_error_work_func - do process context error handling work
2371 * @work: work struct
2372 *
2373 * Fire an error uevent so userspace can see that a hang or error
2374 * was detected.
2375 */
2376 static void i915_error_work_func(struct work_struct *work)
2377 {
2378 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2379 work);
2380 struct drm_i915_private *dev_priv =
2381 container_of(error, struct drm_i915_private, gpu_error);
2382 struct drm_device *dev = dev_priv->dev;
2383 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2384 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2385 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2386 int ret;
2387
2388 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2389
2390 /*
2391 * Note that there's only one work item which does gpu resets, so we
2392 * need not worry about concurrent gpu resets potentially incrementing
2393 * error->reset_counter twice. We only need to take care of another
2394 * racing irq/hangcheck declaring the gpu dead for a second time. A
2395 * quick check for that is good enough: schedule_work ensures the
2396 * correct ordering between hang detection and this work item, and since
2397 * the reset in-progress bit is only ever set by code outside of this
2398 * work we don't need to worry about any other races.
2399 */
2400 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2401 DRM_DEBUG_DRIVER("resetting chip\n");
2402 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2403 reset_event);
2404
2405 /*
2406 * In most cases it's guaranteed that we get here with an RPM
2407 * reference held, for example because there is a pending GPU
2408 * request that won't finish until the reset is done. This
2409 * isn't the case at least when we get here by doing a
2410 * simulated reset via debugs, so get an RPM reference.
2411 */
2412 intel_runtime_pm_get(dev_priv);
2413 /*
2414 * All state reset _must_ be completed before we update the
2415 * reset counter, for otherwise waiters might miss the reset
2416 * pending state and not properly drop locks, resulting in
2417 * deadlocks with the reset work.
2418 */
2419 ret = i915_reset(dev);
2420
2421 intel_display_handle_reset(dev);
2422
2423 intel_runtime_pm_put(dev_priv);
2424
2425 if (ret == 0) {
2426 /*
2427 * After all the gem state is reset, increment the reset
2428 * counter and wake up everyone waiting for the reset to
2429 * complete.
2430 *
2431 * Since unlock operations are a one-sided barrier only,
2432 * we need to insert a barrier here to order any seqno
2433 * updates before
2434 * the counter increment.
2435 */
2436 smp_mb__before_atomic();
2437 atomic_inc(&dev_priv->gpu_error.reset_counter);
2438
2439 kobject_uevent_env(&dev->primary->kdev->kobj,
2440 KOBJ_CHANGE, reset_done_event);
2441 } else {
2442 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2443 }
2444
2445 /*
2446 * Note: The wake_up also serves as a memory barrier so that
2447 * waiters see the update value of the reset counter atomic_t.
2448 */
2449 i915_error_wake_up(dev_priv, true);
2450 }
2451 }
2452
2453 static void i915_report_and_clear_eir(struct drm_device *dev)
2454 {
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 uint32_t instdone[I915_NUM_INSTDONE_REG];
2457 u32 eir = I915_READ(EIR);
2458 int pipe, i;
2459
2460 if (!eir)
2461 return;
2462
2463 pr_err("render error detected, EIR: 0x%08x\n", eir);
2464
2465 i915_get_extra_instdone(dev, instdone);
2466
2467 if (IS_G4X(dev)) {
2468 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2469 u32 ipeir = I915_READ(IPEIR_I965);
2470
2471 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2472 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2473 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2474 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2475 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2476 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2477 I915_WRITE(IPEIR_I965, ipeir);
2478 POSTING_READ(IPEIR_I965);
2479 }
2480 if (eir & GM45_ERROR_PAGE_TABLE) {
2481 u32 pgtbl_err = I915_READ(PGTBL_ER);
2482 pr_err("page table error\n");
2483 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2484 I915_WRITE(PGTBL_ER, pgtbl_err);
2485 POSTING_READ(PGTBL_ER);
2486 }
2487 }
2488
2489 if (!IS_GEN2(dev)) {
2490 if (eir & I915_ERROR_PAGE_TABLE) {
2491 u32 pgtbl_err = I915_READ(PGTBL_ER);
2492 pr_err("page table error\n");
2493 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2494 I915_WRITE(PGTBL_ER, pgtbl_err);
2495 POSTING_READ(PGTBL_ER);
2496 }
2497 }
2498
2499 if (eir & I915_ERROR_MEMORY_REFRESH) {
2500 pr_err("memory refresh error:\n");
2501 for_each_pipe(pipe)
2502 pr_err("pipe %c stat: 0x%08x\n",
2503 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2504 /* pipestat has already been acked */
2505 }
2506 if (eir & I915_ERROR_INSTRUCTION) {
2507 pr_err("instruction error\n");
2508 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2509 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2510 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2511 if (INTEL_INFO(dev)->gen < 4) {
2512 u32 ipeir = I915_READ(IPEIR);
2513
2514 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2515 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2516 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2517 I915_WRITE(IPEIR, ipeir);
2518 POSTING_READ(IPEIR);
2519 } else {
2520 u32 ipeir = I915_READ(IPEIR_I965);
2521
2522 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2523 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2524 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2525 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2526 I915_WRITE(IPEIR_I965, ipeir);
2527 POSTING_READ(IPEIR_I965);
2528 }
2529 }
2530
2531 I915_WRITE(EIR, eir);
2532 POSTING_READ(EIR);
2533 eir = I915_READ(EIR);
2534 if (eir) {
2535 /*
2536 * some errors might have become stuck,
2537 * mask them.
2538 */
2539 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2540 I915_WRITE(EMR, I915_READ(EMR) | eir);
2541 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2542 }
2543 }
2544
2545 /**
2546 * i915_handle_error - handle an error interrupt
2547 * @dev: drm device
2548 *
2549 * Do some basic checking of regsiter state at error interrupt time and
2550 * dump it to the syslog. Also call i915_capture_error_state() to make
2551 * sure we get a record and make it available in debugfs. Fire a uevent
2552 * so userspace knows something bad happened (should trigger collection
2553 * of a ring dump etc.).
2554 */
2555 void i915_handle_error(struct drm_device *dev, bool wedged,
2556 const char *fmt, ...)
2557 {
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 va_list args;
2560 char error_msg[80];
2561
2562 va_start(args, fmt);
2563 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2564 va_end(args);
2565
2566 i915_capture_error_state(dev, wedged, error_msg);
2567 i915_report_and_clear_eir(dev);
2568
2569 if (wedged) {
2570 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2571 &dev_priv->gpu_error.reset_counter);
2572
2573 /*
2574 * Wakeup waiting processes so that the reset work function
2575 * i915_error_work_func doesn't deadlock trying to grab various
2576 * locks. By bumping the reset counter first, the woken
2577 * processes will see a reset in progress and back off,
2578 * releasing their locks and then wait for the reset completion.
2579 * We must do this for _all_ gpu waiters that might hold locks
2580 * that the reset work needs to acquire.
2581 *
2582 * Note: The wake_up serves as the required memory barrier to
2583 * ensure that the waiters see the updated value of the reset
2584 * counter atomic_t.
2585 */
2586 i915_error_wake_up(dev_priv, false);
2587 }
2588
2589 /*
2590 * Our reset work can grab modeset locks (since it needs to reset the
2591 * state of outstanding pagelips). Hence it must not be run on our own
2592 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2593 * code will deadlock.
2594 */
2595 schedule_work(&dev_priv->gpu_error.work);
2596 }
2597
2598 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2599 {
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2603 struct drm_i915_gem_object *obj;
2604 struct intel_unpin_work *work;
2605 unsigned long flags;
2606 bool stall_detected;
2607
2608 /* Ignore early vblank irqs */
2609 if (intel_crtc == NULL)
2610 return;
2611
2612 spin_lock_irqsave(&dev->event_lock, flags);
2613 work = intel_crtc->unpin_work;
2614
2615 if (work == NULL ||
2616 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2617 !work->enable_stall_check) {
2618 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2619 spin_unlock_irqrestore(&dev->event_lock, flags);
2620 return;
2621 }
2622
2623 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2624 obj = work->pending_flip_obj;
2625 if (INTEL_INFO(dev)->gen >= 4) {
2626 int dspsurf = DSPSURF(intel_crtc->plane);
2627 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2628 i915_gem_obj_ggtt_offset(obj);
2629 } else {
2630 int dspaddr = DSPADDR(intel_crtc->plane);
2631 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2632 crtc->y * crtc->primary->fb->pitches[0] +
2633 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2634 }
2635
2636 spin_unlock_irqrestore(&dev->event_lock, flags);
2637
2638 if (stall_detected) {
2639 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2640 intel_prepare_page_flip(dev, intel_crtc->plane);
2641 }
2642 }
2643
2644 /* Called from drm generic code, passed 'crtc' which
2645 * we use as a pipe index
2646 */
2647 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2648 {
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 unsigned long irqflags;
2651
2652 if (!i915_pipe_enabled(dev, pipe))
2653 return -EINVAL;
2654
2655 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2656 if (INTEL_INFO(dev)->gen >= 4)
2657 i915_enable_pipestat(dev_priv, pipe,
2658 PIPE_START_VBLANK_INTERRUPT_STATUS);
2659 else
2660 i915_enable_pipestat(dev_priv, pipe,
2661 PIPE_VBLANK_INTERRUPT_STATUS);
2662 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2663
2664 return 0;
2665 }
2666
2667 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2668 {
2669 struct drm_i915_private *dev_priv = dev->dev_private;
2670 unsigned long irqflags;
2671 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2672 DE_PIPE_VBLANK(pipe);
2673
2674 if (!i915_pipe_enabled(dev, pipe))
2675 return -EINVAL;
2676
2677 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2678 ironlake_enable_display_irq(dev_priv, bit);
2679 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2680
2681 return 0;
2682 }
2683
2684 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2685 {
2686 struct drm_i915_private *dev_priv = dev->dev_private;
2687 unsigned long irqflags;
2688
2689 if (!i915_pipe_enabled(dev, pipe))
2690 return -EINVAL;
2691
2692 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2693 i915_enable_pipestat(dev_priv, pipe,
2694 PIPE_START_VBLANK_INTERRUPT_STATUS);
2695 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2696
2697 return 0;
2698 }
2699
2700 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2701 {
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 unsigned long irqflags;
2704
2705 if (!i915_pipe_enabled(dev, pipe))
2706 return -EINVAL;
2707
2708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2709 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2710 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2711 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2712 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2713 return 0;
2714 }
2715
2716 /* Called from drm generic code, passed 'crtc' which
2717 * we use as a pipe index
2718 */
2719 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2720 {
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 unsigned long irqflags;
2723
2724 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2725 i915_disable_pipestat(dev_priv, pipe,
2726 PIPE_VBLANK_INTERRUPT_STATUS |
2727 PIPE_START_VBLANK_INTERRUPT_STATUS);
2728 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2729 }
2730
2731 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2732 {
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 unsigned long irqflags;
2735 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2736 DE_PIPE_VBLANK(pipe);
2737
2738 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2739 ironlake_disable_display_irq(dev_priv, bit);
2740 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2741 }
2742
2743 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2744 {
2745 struct drm_i915_private *dev_priv = dev->dev_private;
2746 unsigned long irqflags;
2747
2748 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2749 i915_disable_pipestat(dev_priv, pipe,
2750 PIPE_START_VBLANK_INTERRUPT_STATUS);
2751 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2752 }
2753
2754 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2755 {
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 unsigned long irqflags;
2758
2759 if (!i915_pipe_enabled(dev, pipe))
2760 return;
2761
2762 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2763 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2764 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2765 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2766 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2767 }
2768
2769 static u32
2770 ring_last_seqno(struct intel_engine_cs *ring)
2771 {
2772 return list_entry(ring->request_list.prev,
2773 struct drm_i915_gem_request, list)->seqno;
2774 }
2775
2776 static bool
2777 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2778 {
2779 return (list_empty(&ring->request_list) ||
2780 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2781 }
2782
2783 static bool
2784 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2785 {
2786 if (INTEL_INFO(dev)->gen >= 8) {
2787 /*
2788 * FIXME: gen8 semaphore support - currently we don't emit
2789 * semaphores on bdw anyway, but this needs to be addressed when
2790 * we merge that code.
2791 */
2792 return false;
2793 } else {
2794 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2795 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2796 MI_SEMAPHORE_REGISTER);
2797 }
2798 }
2799
2800 static struct intel_engine_cs *
2801 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
2802 {
2803 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2804 struct intel_engine_cs *signaller;
2805 int i;
2806
2807 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2808 /*
2809 * FIXME: gen8 semaphore support - currently we don't emit
2810 * semaphores on bdw anyway, but this needs to be addressed when
2811 * we merge that code.
2812 */
2813 return NULL;
2814 } else {
2815 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2816
2817 for_each_ring(signaller, dev_priv, i) {
2818 if(ring == signaller)
2819 continue;
2820
2821 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2822 return signaller;
2823 }
2824 }
2825
2826 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2827 ring->id, ipehr);
2828
2829 return NULL;
2830 }
2831
2832 static struct intel_engine_cs *
2833 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2834 {
2835 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2836 u32 cmd, ipehr, head;
2837 int i;
2838
2839 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2840 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2841 return NULL;
2842
2843 /*
2844 * HEAD is likely pointing to the dword after the actual command,
2845 * so scan backwards until we find the MBOX. But limit it to just 3
2846 * dwords. Note that we don't care about ACTHD here since that might
2847 * point at at batch, and semaphores are always emitted into the
2848 * ringbuffer itself.
2849 */
2850 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2851
2852 for (i = 4; i; --i) {
2853 /*
2854 * Be paranoid and presume the hw has gone off into the wild -
2855 * our ring is smaller than what the hardware (and hence
2856 * HEAD_ADDR) allows. Also handles wrap-around.
2857 */
2858 head &= ring->buffer->size - 1;
2859
2860 /* This here seems to blow up */
2861 cmd = ioread32(ring->buffer->virtual_start + head);
2862 if (cmd == ipehr)
2863 break;
2864
2865 head -= 4;
2866 }
2867
2868 if (!i)
2869 return NULL;
2870
2871 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2872 return semaphore_wait_to_signaller_ring(ring, ipehr);
2873 }
2874
2875 static int semaphore_passed(struct intel_engine_cs *ring)
2876 {
2877 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2878 struct intel_engine_cs *signaller;
2879 u32 seqno, ctl;
2880
2881 ring->hangcheck.deadlock++;
2882
2883 signaller = semaphore_waits_for(ring, &seqno);
2884 if (signaller == NULL)
2885 return -1;
2886
2887 /* Prevent pathological recursion due to driver bugs */
2888 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2889 return -1;
2890
2891 /* cursory check for an unkickable deadlock */
2892 ctl = I915_READ_CTL(signaller);
2893 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2894 return -1;
2895
2896 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2897 return 1;
2898
2899 if (signaller->hangcheck.deadlock)
2900 return -1;
2901
2902 return 0;
2903 }
2904
2905 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2906 {
2907 struct intel_engine_cs *ring;
2908 int i;
2909
2910 for_each_ring(ring, dev_priv, i)
2911 ring->hangcheck.deadlock = 0;
2912 }
2913
2914 static enum intel_ring_hangcheck_action
2915 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2916 {
2917 struct drm_device *dev = ring->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 u32 tmp;
2920
2921 if (ring->hangcheck.acthd != acthd)
2922 return HANGCHECK_ACTIVE;
2923
2924 if (IS_GEN2(dev))
2925 return HANGCHECK_HUNG;
2926
2927 /* Is the chip hanging on a WAIT_FOR_EVENT?
2928 * If so we can simply poke the RB_WAIT bit
2929 * and break the hang. This should work on
2930 * all but the second generation chipsets.
2931 */
2932 tmp = I915_READ_CTL(ring);
2933 if (tmp & RING_WAIT) {
2934 i915_handle_error(dev, false,
2935 "Kicking stuck wait on %s",
2936 ring->name);
2937 I915_WRITE_CTL(ring, tmp);
2938 return HANGCHECK_KICK;
2939 }
2940
2941 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2942 switch (semaphore_passed(ring)) {
2943 default:
2944 return HANGCHECK_HUNG;
2945 case 1:
2946 i915_handle_error(dev, false,
2947 "Kicking stuck semaphore on %s",
2948 ring->name);
2949 I915_WRITE_CTL(ring, tmp);
2950 return HANGCHECK_KICK;
2951 case 0:
2952 return HANGCHECK_WAIT;
2953 }
2954 }
2955
2956 return HANGCHECK_HUNG;
2957 }
2958
2959 /**
2960 * This is called when the chip hasn't reported back with completed
2961 * batchbuffers in a long time. We keep track per ring seqno progress and
2962 * if there are no progress, hangcheck score for that ring is increased.
2963 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2964 * we kick the ring. If we see no progress on three subsequent calls
2965 * we assume chip is wedged and try to fix it by resetting the chip.
2966 */
2967 static void i915_hangcheck_elapsed(unsigned long data)
2968 {
2969 struct drm_device *dev = (struct drm_device *)data;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_engine_cs *ring;
2972 int i;
2973 int busy_count = 0, rings_hung = 0;
2974 bool stuck[I915_NUM_RINGS] = { 0 };
2975 #define BUSY 1
2976 #define KICK 5
2977 #define HUNG 20
2978
2979 if (!i915.enable_hangcheck)
2980 return;
2981
2982 for_each_ring(ring, dev_priv, i) {
2983 u64 acthd;
2984 u32 seqno;
2985 bool busy = true;
2986
2987 semaphore_clear_deadlocks(dev_priv);
2988
2989 seqno = ring->get_seqno(ring, false);
2990 acthd = intel_ring_get_active_head(ring);
2991
2992 if (ring->hangcheck.seqno == seqno) {
2993 if (ring_idle(ring, seqno)) {
2994 ring->hangcheck.action = HANGCHECK_IDLE;
2995
2996 if (waitqueue_active(&ring->irq_queue)) {
2997 /* Issue a wake-up to catch stuck h/w. */
2998 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2999 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3000 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3001 ring->name);
3002 else
3003 DRM_INFO("Fake missed irq on %s\n",
3004 ring->name);
3005 wake_up_all(&ring->irq_queue);
3006 }
3007 /* Safeguard against driver failure */
3008 ring->hangcheck.score += BUSY;
3009 } else
3010 busy = false;
3011 } else {
3012 /* We always increment the hangcheck score
3013 * if the ring is busy and still processing
3014 * the same request, so that no single request
3015 * can run indefinitely (such as a chain of
3016 * batches). The only time we do not increment
3017 * the hangcheck score on this ring, if this
3018 * ring is in a legitimate wait for another
3019 * ring. In that case the waiting ring is a
3020 * victim and we want to be sure we catch the
3021 * right culprit. Then every time we do kick
3022 * the ring, add a small increment to the
3023 * score so that we can catch a batch that is
3024 * being repeatedly kicked and so responsible
3025 * for stalling the machine.
3026 */
3027 ring->hangcheck.action = ring_stuck(ring,
3028 acthd);
3029
3030 switch (ring->hangcheck.action) {
3031 case HANGCHECK_IDLE:
3032 case HANGCHECK_WAIT:
3033 break;
3034 case HANGCHECK_ACTIVE:
3035 ring->hangcheck.score += BUSY;
3036 break;
3037 case HANGCHECK_KICK:
3038 ring->hangcheck.score += KICK;
3039 break;
3040 case HANGCHECK_HUNG:
3041 ring->hangcheck.score += HUNG;
3042 stuck[i] = true;
3043 break;
3044 }
3045 }
3046 } else {
3047 ring->hangcheck.action = HANGCHECK_ACTIVE;
3048
3049 /* Gradually reduce the count so that we catch DoS
3050 * attempts across multiple batches.
3051 */
3052 if (ring->hangcheck.score > 0)
3053 ring->hangcheck.score--;
3054 }
3055
3056 ring->hangcheck.seqno = seqno;
3057 ring->hangcheck.acthd = acthd;
3058 busy_count += busy;
3059 }
3060
3061 for_each_ring(ring, dev_priv, i) {
3062 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3063 DRM_INFO("%s on %s\n",
3064 stuck[i] ? "stuck" : "no progress",
3065 ring->name);
3066 rings_hung++;
3067 }
3068 }
3069
3070 if (rings_hung)
3071 return i915_handle_error(dev, true, "Ring hung");
3072
3073 if (busy_count)
3074 /* Reset timer case chip hangs without another request
3075 * being added */
3076 i915_queue_hangcheck(dev);
3077 }
3078
3079 void i915_queue_hangcheck(struct drm_device *dev)
3080 {
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 if (!i915.enable_hangcheck)
3083 return;
3084
3085 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3086 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3087 }
3088
3089 static void ibx_irq_reset(struct drm_device *dev)
3090 {
3091 struct drm_i915_private *dev_priv = dev->dev_private;
3092
3093 if (HAS_PCH_NOP(dev))
3094 return;
3095
3096 GEN5_IRQ_RESET(SDE);
3097
3098 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3099 I915_WRITE(SERR_INT, 0xffffffff);
3100 }
3101
3102 /*
3103 * SDEIER is also touched by the interrupt handler to work around missed PCH
3104 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3105 * instead we unconditionally enable all PCH interrupt sources here, but then
3106 * only unmask them as needed with SDEIMR.
3107 *
3108 * This function needs to be called before interrupts are enabled.
3109 */
3110 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3111 {
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113
3114 if (HAS_PCH_NOP(dev))
3115 return;
3116
3117 WARN_ON(I915_READ(SDEIER) != 0);
3118 I915_WRITE(SDEIER, 0xffffffff);
3119 POSTING_READ(SDEIER);
3120 }
3121
3122 static void gen5_gt_irq_reset(struct drm_device *dev)
3123 {
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125
3126 GEN5_IRQ_RESET(GT);
3127 if (INTEL_INFO(dev)->gen >= 6)
3128 GEN5_IRQ_RESET(GEN6_PM);
3129 }
3130
3131 /* drm_dma.h hooks
3132 */
3133 static void ironlake_irq_reset(struct drm_device *dev)
3134 {
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3136
3137 I915_WRITE(HWSTAM, 0xffffffff);
3138
3139 GEN5_IRQ_RESET(DE);
3140 if (IS_GEN7(dev))
3141 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3142
3143 gen5_gt_irq_reset(dev);
3144
3145 ibx_irq_reset(dev);
3146 }
3147
3148 static void valleyview_irq_preinstall(struct drm_device *dev)
3149 {
3150 struct drm_i915_private *dev_priv = dev->dev_private;
3151 int pipe;
3152
3153 /* VLV magic */
3154 I915_WRITE(VLV_IMR, 0);
3155 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3156 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3157 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3158
3159 /* and GT */
3160 I915_WRITE(GTIIR, I915_READ(GTIIR));
3161 I915_WRITE(GTIIR, I915_READ(GTIIR));
3162
3163 gen5_gt_irq_reset(dev);
3164
3165 I915_WRITE(DPINVGTT, 0xff);
3166
3167 I915_WRITE(PORT_HOTPLUG_EN, 0);
3168 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3169 for_each_pipe(pipe)
3170 I915_WRITE(PIPESTAT(pipe), 0xffff);
3171 I915_WRITE(VLV_IIR, 0xffffffff);
3172 I915_WRITE(VLV_IMR, 0xffffffff);
3173 I915_WRITE(VLV_IER, 0x0);
3174 POSTING_READ(VLV_IER);
3175 }
3176
3177 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3178 {
3179 GEN8_IRQ_RESET_NDX(GT, 0);
3180 GEN8_IRQ_RESET_NDX(GT, 1);
3181 GEN8_IRQ_RESET_NDX(GT, 2);
3182 GEN8_IRQ_RESET_NDX(GT, 3);
3183 }
3184
3185 static void gen8_irq_reset(struct drm_device *dev)
3186 {
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 int pipe;
3189
3190 I915_WRITE(GEN8_MASTER_IRQ, 0);
3191 POSTING_READ(GEN8_MASTER_IRQ);
3192
3193 gen8_gt_irq_reset(dev_priv);
3194
3195 for_each_pipe(pipe)
3196 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3197
3198 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3199 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3200 GEN5_IRQ_RESET(GEN8_PCU_);
3201
3202 ibx_irq_reset(dev);
3203 }
3204
3205 static void cherryview_irq_preinstall(struct drm_device *dev)
3206 {
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 int pipe;
3209
3210 I915_WRITE(GEN8_MASTER_IRQ, 0);
3211 POSTING_READ(GEN8_MASTER_IRQ);
3212
3213 gen8_gt_irq_reset(dev_priv);
3214
3215 GEN5_IRQ_RESET(GEN8_PCU_);
3216
3217 POSTING_READ(GEN8_PCU_IIR);
3218
3219 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3220
3221 I915_WRITE(PORT_HOTPLUG_EN, 0);
3222 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3223
3224 for_each_pipe(pipe)
3225 I915_WRITE(PIPESTAT(pipe), 0xffff);
3226
3227 I915_WRITE(VLV_IMR, 0xffffffff);
3228 I915_WRITE(VLV_IER, 0x0);
3229 I915_WRITE(VLV_IIR, 0xffffffff);
3230 POSTING_READ(VLV_IIR);
3231 }
3232
3233 static void ibx_hpd_irq_setup(struct drm_device *dev)
3234 {
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236 struct drm_mode_config *mode_config = &dev->mode_config;
3237 struct intel_encoder *intel_encoder;
3238 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3239
3240 if (HAS_PCH_IBX(dev)) {
3241 hotplug_irqs = SDE_HOTPLUG_MASK;
3242 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3243 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3244 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3245 } else {
3246 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3247 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3248 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3249 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3250 }
3251
3252 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3253
3254 /*
3255 * Enable digital hotplug on the PCH, and configure the DP short pulse
3256 * duration to 2ms (which is the minimum in the Display Port spec)
3257 *
3258 * This register is the same on all known PCH chips.
3259 */
3260 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3261 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3262 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3263 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3264 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3265 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3266 }
3267
3268 static void ibx_irq_postinstall(struct drm_device *dev)
3269 {
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 u32 mask;
3272
3273 if (HAS_PCH_NOP(dev))
3274 return;
3275
3276 if (HAS_PCH_IBX(dev))
3277 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3278 else
3279 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3280
3281 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3282 I915_WRITE(SDEIMR, ~mask);
3283 }
3284
3285 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3286 {
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 u32 pm_irqs, gt_irqs;
3289
3290 pm_irqs = gt_irqs = 0;
3291
3292 dev_priv->gt_irq_mask = ~0;
3293 if (HAS_L3_DPF(dev)) {
3294 /* L3 parity interrupt is always unmasked. */
3295 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3296 gt_irqs |= GT_PARITY_ERROR(dev);
3297 }
3298
3299 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3300 if (IS_GEN5(dev)) {
3301 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3302 ILK_BSD_USER_INTERRUPT;
3303 } else {
3304 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3305 }
3306
3307 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3308
3309 if (INTEL_INFO(dev)->gen >= 6) {
3310 pm_irqs |= dev_priv->pm_rps_events;
3311
3312 if (HAS_VEBOX(dev))
3313 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3314
3315 dev_priv->pm_irq_mask = 0xffffffff;
3316 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3317 }
3318 }
3319
3320 static int ironlake_irq_postinstall(struct drm_device *dev)
3321 {
3322 unsigned long irqflags;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 u32 display_mask, extra_mask;
3325
3326 if (INTEL_INFO(dev)->gen >= 7) {
3327 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3328 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3329 DE_PLANEB_FLIP_DONE_IVB |
3330 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3331 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3332 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3333 } else {
3334 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3335 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3336 DE_AUX_CHANNEL_A |
3337 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3338 DE_POISON);
3339 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3340 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3341 }
3342
3343 dev_priv->irq_mask = ~display_mask;
3344
3345 I915_WRITE(HWSTAM, 0xeffe);
3346
3347 ibx_irq_pre_postinstall(dev);
3348
3349 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3350
3351 gen5_gt_irq_postinstall(dev);
3352
3353 ibx_irq_postinstall(dev);
3354
3355 if (IS_IRONLAKE_M(dev)) {
3356 /* Enable PCU event interrupts
3357 *
3358 * spinlocking not required here for correctness since interrupt
3359 * setup is guaranteed to run in single-threaded context. But we
3360 * need it to make the assert_spin_locked happy. */
3361 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3362 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3363 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3364 }
3365
3366 return 0;
3367 }
3368
3369 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3370 {
3371 u32 pipestat_mask;
3372 u32 iir_mask;
3373
3374 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3375 PIPE_FIFO_UNDERRUN_STATUS;
3376
3377 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3378 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3379 POSTING_READ(PIPESTAT(PIPE_A));
3380
3381 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3382 PIPE_CRC_DONE_INTERRUPT_STATUS;
3383
3384 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3385 PIPE_GMBUS_INTERRUPT_STATUS);
3386 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3387
3388 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3389 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3390 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3391 dev_priv->irq_mask &= ~iir_mask;
3392
3393 I915_WRITE(VLV_IIR, iir_mask);
3394 I915_WRITE(VLV_IIR, iir_mask);
3395 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3396 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3397 POSTING_READ(VLV_IER);
3398 }
3399
3400 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3401 {
3402 u32 pipestat_mask;
3403 u32 iir_mask;
3404
3405 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3406 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3407 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3408
3409 dev_priv->irq_mask |= iir_mask;
3410 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3411 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3412 I915_WRITE(VLV_IIR, iir_mask);
3413 I915_WRITE(VLV_IIR, iir_mask);
3414 POSTING_READ(VLV_IIR);
3415
3416 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3417 PIPE_CRC_DONE_INTERRUPT_STATUS;
3418
3419 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3420 PIPE_GMBUS_INTERRUPT_STATUS);
3421 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3422
3423 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3424 PIPE_FIFO_UNDERRUN_STATUS;
3425 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3426 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3427 POSTING_READ(PIPESTAT(PIPE_A));
3428 }
3429
3430 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3431 {
3432 assert_spin_locked(&dev_priv->irq_lock);
3433
3434 if (dev_priv->display_irqs_enabled)
3435 return;
3436
3437 dev_priv->display_irqs_enabled = true;
3438
3439 if (dev_priv->dev->irq_enabled)
3440 valleyview_display_irqs_install(dev_priv);
3441 }
3442
3443 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3444 {
3445 assert_spin_locked(&dev_priv->irq_lock);
3446
3447 if (!dev_priv->display_irqs_enabled)
3448 return;
3449
3450 dev_priv->display_irqs_enabled = false;
3451
3452 if (dev_priv->dev->irq_enabled)
3453 valleyview_display_irqs_uninstall(dev_priv);
3454 }
3455
3456 static int valleyview_irq_postinstall(struct drm_device *dev)
3457 {
3458 struct drm_i915_private *dev_priv = dev->dev_private;
3459 unsigned long irqflags;
3460
3461 dev_priv->irq_mask = ~0;
3462
3463 I915_WRITE(PORT_HOTPLUG_EN, 0);
3464 POSTING_READ(PORT_HOTPLUG_EN);
3465
3466 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3467 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3468 I915_WRITE(VLV_IIR, 0xffffffff);
3469 POSTING_READ(VLV_IER);
3470
3471 /* Interrupt setup is already guaranteed to be single-threaded, this is
3472 * just to make the assert_spin_locked check happy. */
3473 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3474 if (dev_priv->display_irqs_enabled)
3475 valleyview_display_irqs_install(dev_priv);
3476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3477
3478 I915_WRITE(VLV_IIR, 0xffffffff);
3479 I915_WRITE(VLV_IIR, 0xffffffff);
3480
3481 gen5_gt_irq_postinstall(dev);
3482
3483 /* ack & enable invalid PTE error interrupts */
3484 #if 0 /* FIXME: add support to irq handler for checking these bits */
3485 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3486 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3487 #endif
3488
3489 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3490
3491 return 0;
3492 }
3493
3494 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3495 {
3496 int i;
3497
3498 /* These are interrupts we'll toggle with the ring mask register */
3499 uint32_t gt_interrupts[] = {
3500 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3501 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3502 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3503 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3504 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3505 0,
3506 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3507 };
3508
3509 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3510 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3511
3512 dev_priv->pm_irq_mask = 0xffffffff;
3513 }
3514
3515 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3516 {
3517 struct drm_device *dev = dev_priv->dev;
3518 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3519 GEN8_PIPE_CDCLK_CRC_DONE |
3520 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3521 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3522 GEN8_PIPE_FIFO_UNDERRUN;
3523 int pipe;
3524 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3525 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3526 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3527
3528 for_each_pipe(pipe)
3529 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3530 de_pipe_enables);
3531
3532 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3533 }
3534
3535 static int gen8_irq_postinstall(struct drm_device *dev)
3536 {
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538
3539 ibx_irq_pre_postinstall(dev);
3540
3541 gen8_gt_irq_postinstall(dev_priv);
3542 gen8_de_irq_postinstall(dev_priv);
3543
3544 ibx_irq_postinstall(dev);
3545
3546 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3547 POSTING_READ(GEN8_MASTER_IRQ);
3548
3549 return 0;
3550 }
3551
3552 static int cherryview_irq_postinstall(struct drm_device *dev)
3553 {
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3556 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3557 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3558 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3559 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3560 PIPE_CRC_DONE_INTERRUPT_STATUS;
3561 unsigned long irqflags;
3562 int pipe;
3563
3564 /*
3565 * Leave vblank interrupts masked initially. enable/disable will
3566 * toggle them based on usage.
3567 */
3568 dev_priv->irq_mask = ~enable_mask;
3569
3570 for_each_pipe(pipe)
3571 I915_WRITE(PIPESTAT(pipe), 0xffff);
3572
3573 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3574 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3575 for_each_pipe(pipe)
3576 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3577 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3578
3579 I915_WRITE(VLV_IIR, 0xffffffff);
3580 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3581 I915_WRITE(VLV_IER, enable_mask);
3582
3583 gen8_gt_irq_postinstall(dev_priv);
3584
3585 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3586 POSTING_READ(GEN8_MASTER_IRQ);
3587
3588 return 0;
3589 }
3590
3591 static void gen8_irq_uninstall(struct drm_device *dev)
3592 {
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595 if (!dev_priv)
3596 return;
3597
3598 intel_hpd_irq_uninstall(dev_priv);
3599
3600 gen8_irq_reset(dev);
3601 }
3602
3603 static void valleyview_irq_uninstall(struct drm_device *dev)
3604 {
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 unsigned long irqflags;
3607 int pipe;
3608
3609 if (!dev_priv)
3610 return;
3611
3612 I915_WRITE(VLV_MASTER_IER, 0);
3613
3614 intel_hpd_irq_uninstall(dev_priv);
3615
3616 for_each_pipe(pipe)
3617 I915_WRITE(PIPESTAT(pipe), 0xffff);
3618
3619 I915_WRITE(HWSTAM, 0xffffffff);
3620 I915_WRITE(PORT_HOTPLUG_EN, 0);
3621 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3622
3623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3624 if (dev_priv->display_irqs_enabled)
3625 valleyview_display_irqs_uninstall(dev_priv);
3626 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3627
3628 dev_priv->irq_mask = 0;
3629
3630 I915_WRITE(VLV_IIR, 0xffffffff);
3631 I915_WRITE(VLV_IMR, 0xffffffff);
3632 I915_WRITE(VLV_IER, 0x0);
3633 POSTING_READ(VLV_IER);
3634 }
3635
3636 static void cherryview_irq_uninstall(struct drm_device *dev)
3637 {
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 int pipe;
3640
3641 if (!dev_priv)
3642 return;
3643
3644 I915_WRITE(GEN8_MASTER_IRQ, 0);
3645 POSTING_READ(GEN8_MASTER_IRQ);
3646
3647 #define GEN8_IRQ_FINI_NDX(type, which) \
3648 do { \
3649 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3650 I915_WRITE(GEN8_##type##_IER(which), 0); \
3651 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3652 POSTING_READ(GEN8_##type##_IIR(which)); \
3653 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3654 } while (0)
3655
3656 #define GEN8_IRQ_FINI(type) \
3657 do { \
3658 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3659 I915_WRITE(GEN8_##type##_IER, 0); \
3660 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3661 POSTING_READ(GEN8_##type##_IIR); \
3662 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3663 } while (0)
3664
3665 GEN8_IRQ_FINI_NDX(GT, 0);
3666 GEN8_IRQ_FINI_NDX(GT, 1);
3667 GEN8_IRQ_FINI_NDX(GT, 2);
3668 GEN8_IRQ_FINI_NDX(GT, 3);
3669
3670 GEN8_IRQ_FINI(PCU);
3671
3672 #undef GEN8_IRQ_FINI
3673 #undef GEN8_IRQ_FINI_NDX
3674
3675 I915_WRITE(PORT_HOTPLUG_EN, 0);
3676 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3677
3678 for_each_pipe(pipe)
3679 I915_WRITE(PIPESTAT(pipe), 0xffff);
3680
3681 I915_WRITE(VLV_IMR, 0xffffffff);
3682 I915_WRITE(VLV_IER, 0x0);
3683 I915_WRITE(VLV_IIR, 0xffffffff);
3684 POSTING_READ(VLV_IIR);
3685 }
3686
3687 static void ironlake_irq_uninstall(struct drm_device *dev)
3688 {
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690
3691 if (!dev_priv)
3692 return;
3693
3694 intel_hpd_irq_uninstall(dev_priv);
3695
3696 ironlake_irq_reset(dev);
3697 }
3698
3699 static void i8xx_irq_preinstall(struct drm_device * dev)
3700 {
3701 struct drm_i915_private *dev_priv = dev->dev_private;
3702 int pipe;
3703
3704 for_each_pipe(pipe)
3705 I915_WRITE(PIPESTAT(pipe), 0);
3706 I915_WRITE16(IMR, 0xffff);
3707 I915_WRITE16(IER, 0x0);
3708 POSTING_READ16(IER);
3709 }
3710
3711 static int i8xx_irq_postinstall(struct drm_device *dev)
3712 {
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714 unsigned long irqflags;
3715
3716 I915_WRITE16(EMR,
3717 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3718
3719 /* Unmask the interrupts that we always want on. */
3720 dev_priv->irq_mask =
3721 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3722 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3723 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3724 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3725 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3726 I915_WRITE16(IMR, dev_priv->irq_mask);
3727
3728 I915_WRITE16(IER,
3729 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3730 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3731 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3732 I915_USER_INTERRUPT);
3733 POSTING_READ16(IER);
3734
3735 /* Interrupt setup is already guaranteed to be single-threaded, this is
3736 * just to make the assert_spin_locked check happy. */
3737 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3738 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3739 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3740 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3741
3742 return 0;
3743 }
3744
3745 /*
3746 * Returns true when a page flip has completed.
3747 */
3748 static bool i8xx_handle_vblank(struct drm_device *dev,
3749 int plane, int pipe, u32 iir)
3750 {
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3753
3754 if (!intel_pipe_handle_vblank(dev, pipe))
3755 return false;
3756
3757 if ((iir & flip_pending) == 0)
3758 return false;
3759
3760 intel_prepare_page_flip(dev, plane);
3761
3762 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3763 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3764 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3765 * the flip is completed (no longer pending). Since this doesn't raise
3766 * an interrupt per se, we watch for the change at vblank.
3767 */
3768 if (I915_READ16(ISR) & flip_pending)
3769 return false;
3770
3771 intel_finish_page_flip(dev, pipe);
3772
3773 return true;
3774 }
3775
3776 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3777 {
3778 struct drm_device *dev = arg;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780 u16 iir, new_iir;
3781 u32 pipe_stats[2];
3782 unsigned long irqflags;
3783 int pipe;
3784 u16 flip_mask =
3785 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3786 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3787
3788 iir = I915_READ16(IIR);
3789 if (iir == 0)
3790 return IRQ_NONE;
3791
3792 while (iir & ~flip_mask) {
3793 /* Can't rely on pipestat interrupt bit in iir as it might
3794 * have been cleared after the pipestat interrupt was received.
3795 * It doesn't set the bit in iir again, but it still produces
3796 * interrupts (for non-MSI).
3797 */
3798 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3799 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3800 i915_handle_error(dev, false,
3801 "Command parser error, iir 0x%08x",
3802 iir);
3803
3804 for_each_pipe(pipe) {
3805 int reg = PIPESTAT(pipe);
3806 pipe_stats[pipe] = I915_READ(reg);
3807
3808 /*
3809 * Clear the PIPE*STAT regs before the IIR
3810 */
3811 if (pipe_stats[pipe] & 0x8000ffff)
3812 I915_WRITE(reg, pipe_stats[pipe]);
3813 }
3814 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3815
3816 I915_WRITE16(IIR, iir & ~flip_mask);
3817 new_iir = I915_READ16(IIR); /* Flush posted writes */
3818
3819 i915_update_dri1_breadcrumb(dev);
3820
3821 if (iir & I915_USER_INTERRUPT)
3822 notify_ring(dev, &dev_priv->ring[RCS]);
3823
3824 for_each_pipe(pipe) {
3825 int plane = pipe;
3826 if (HAS_FBC(dev))
3827 plane = !plane;
3828
3829 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3830 i8xx_handle_vblank(dev, plane, pipe, iir))
3831 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3832
3833 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3834 i9xx_pipe_crc_irq_handler(dev, pipe);
3835
3836 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3837 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3838 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3839 }
3840
3841 iir = new_iir;
3842 }
3843
3844 return IRQ_HANDLED;
3845 }
3846
3847 static void i8xx_irq_uninstall(struct drm_device * dev)
3848 {
3849 struct drm_i915_private *dev_priv = dev->dev_private;
3850 int pipe;
3851
3852 for_each_pipe(pipe) {
3853 /* Clear enable bits; then clear status bits */
3854 I915_WRITE(PIPESTAT(pipe), 0);
3855 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3856 }
3857 I915_WRITE16(IMR, 0xffff);
3858 I915_WRITE16(IER, 0x0);
3859 I915_WRITE16(IIR, I915_READ16(IIR));
3860 }
3861
3862 static void i915_irq_preinstall(struct drm_device * dev)
3863 {
3864 struct drm_i915_private *dev_priv = dev->dev_private;
3865 int pipe;
3866
3867 if (I915_HAS_HOTPLUG(dev)) {
3868 I915_WRITE(PORT_HOTPLUG_EN, 0);
3869 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3870 }
3871
3872 I915_WRITE16(HWSTAM, 0xeffe);
3873 for_each_pipe(pipe)
3874 I915_WRITE(PIPESTAT(pipe), 0);
3875 I915_WRITE(IMR, 0xffffffff);
3876 I915_WRITE(IER, 0x0);
3877 POSTING_READ(IER);
3878 }
3879
3880 static int i915_irq_postinstall(struct drm_device *dev)
3881 {
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 u32 enable_mask;
3884 unsigned long irqflags;
3885
3886 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3887
3888 /* Unmask the interrupts that we always want on. */
3889 dev_priv->irq_mask =
3890 ~(I915_ASLE_INTERRUPT |
3891 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3892 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3893 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3894 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3895 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3896
3897 enable_mask =
3898 I915_ASLE_INTERRUPT |
3899 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3900 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3901 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3902 I915_USER_INTERRUPT;
3903
3904 if (I915_HAS_HOTPLUG(dev)) {
3905 I915_WRITE(PORT_HOTPLUG_EN, 0);
3906 POSTING_READ(PORT_HOTPLUG_EN);
3907
3908 /* Enable in IER... */
3909 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3910 /* and unmask in IMR */
3911 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3912 }
3913
3914 I915_WRITE(IMR, dev_priv->irq_mask);
3915 I915_WRITE(IER, enable_mask);
3916 POSTING_READ(IER);
3917
3918 i915_enable_asle_pipestat(dev);
3919
3920 /* Interrupt setup is already guaranteed to be single-threaded, this is
3921 * just to make the assert_spin_locked check happy. */
3922 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3923 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3924 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3925 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3926
3927 return 0;
3928 }
3929
3930 /*
3931 * Returns true when a page flip has completed.
3932 */
3933 static bool i915_handle_vblank(struct drm_device *dev,
3934 int plane, int pipe, u32 iir)
3935 {
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3938
3939 if (!intel_pipe_handle_vblank(dev, pipe))
3940 return false;
3941
3942 if ((iir & flip_pending) == 0)
3943 return false;
3944
3945 intel_prepare_page_flip(dev, plane);
3946
3947 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3948 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3949 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3950 * the flip is completed (no longer pending). Since this doesn't raise
3951 * an interrupt per se, we watch for the change at vblank.
3952 */
3953 if (I915_READ(ISR) & flip_pending)
3954 return false;
3955
3956 intel_finish_page_flip(dev, pipe);
3957
3958 return true;
3959 }
3960
3961 static irqreturn_t i915_irq_handler(int irq, void *arg)
3962 {
3963 struct drm_device *dev = arg;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
3965 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3966 unsigned long irqflags;
3967 u32 flip_mask =
3968 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3969 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3970 int pipe, ret = IRQ_NONE;
3971
3972 iir = I915_READ(IIR);
3973 do {
3974 bool irq_received = (iir & ~flip_mask) != 0;
3975 bool blc_event = false;
3976
3977 /* Can't rely on pipestat interrupt bit in iir as it might
3978 * have been cleared after the pipestat interrupt was received.
3979 * It doesn't set the bit in iir again, but it still produces
3980 * interrupts (for non-MSI).
3981 */
3982 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3983 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3984 i915_handle_error(dev, false,
3985 "Command parser error, iir 0x%08x",
3986 iir);
3987
3988 for_each_pipe(pipe) {
3989 int reg = PIPESTAT(pipe);
3990 pipe_stats[pipe] = I915_READ(reg);
3991
3992 /* Clear the PIPE*STAT regs before the IIR */
3993 if (pipe_stats[pipe] & 0x8000ffff) {
3994 I915_WRITE(reg, pipe_stats[pipe]);
3995 irq_received = true;
3996 }
3997 }
3998 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3999
4000 if (!irq_received)
4001 break;
4002
4003 /* Consume port. Then clear IIR or we'll miss events */
4004 if (I915_HAS_HOTPLUG(dev) &&
4005 iir & I915_DISPLAY_PORT_INTERRUPT)
4006 i9xx_hpd_irq_handler(dev);
4007
4008 I915_WRITE(IIR, iir & ~flip_mask);
4009 new_iir = I915_READ(IIR); /* Flush posted writes */
4010
4011 if (iir & I915_USER_INTERRUPT)
4012 notify_ring(dev, &dev_priv->ring[RCS]);
4013
4014 for_each_pipe(pipe) {
4015 int plane = pipe;
4016 if (HAS_FBC(dev))
4017 plane = !plane;
4018
4019 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4020 i915_handle_vblank(dev, plane, pipe, iir))
4021 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4022
4023 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4024 blc_event = true;
4025
4026 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4027 i9xx_pipe_crc_irq_handler(dev, pipe);
4028
4029 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4030 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4031 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4032 }
4033
4034 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4035 intel_opregion_asle_intr(dev);
4036
4037 /* With MSI, interrupts are only generated when iir
4038 * transitions from zero to nonzero. If another bit got
4039 * set while we were handling the existing iir bits, then
4040 * we would never get another interrupt.
4041 *
4042 * This is fine on non-MSI as well, as if we hit this path
4043 * we avoid exiting the interrupt handler only to generate
4044 * another one.
4045 *
4046 * Note that for MSI this could cause a stray interrupt report
4047 * if an interrupt landed in the time between writing IIR and
4048 * the posting read. This should be rare enough to never
4049 * trigger the 99% of 100,000 interrupts test for disabling
4050 * stray interrupts.
4051 */
4052 ret = IRQ_HANDLED;
4053 iir = new_iir;
4054 } while (iir & ~flip_mask);
4055
4056 i915_update_dri1_breadcrumb(dev);
4057
4058 return ret;
4059 }
4060
4061 static void i915_irq_uninstall(struct drm_device * dev)
4062 {
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4064 int pipe;
4065
4066 intel_hpd_irq_uninstall(dev_priv);
4067
4068 if (I915_HAS_HOTPLUG(dev)) {
4069 I915_WRITE(PORT_HOTPLUG_EN, 0);
4070 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4071 }
4072
4073 I915_WRITE16(HWSTAM, 0xffff);
4074 for_each_pipe(pipe) {
4075 /* Clear enable bits; then clear status bits */
4076 I915_WRITE(PIPESTAT(pipe), 0);
4077 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4078 }
4079 I915_WRITE(IMR, 0xffffffff);
4080 I915_WRITE(IER, 0x0);
4081
4082 I915_WRITE(IIR, I915_READ(IIR));
4083 }
4084
4085 static void i965_irq_preinstall(struct drm_device * dev)
4086 {
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 int pipe;
4089
4090 I915_WRITE(PORT_HOTPLUG_EN, 0);
4091 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4092
4093 I915_WRITE(HWSTAM, 0xeffe);
4094 for_each_pipe(pipe)
4095 I915_WRITE(PIPESTAT(pipe), 0);
4096 I915_WRITE(IMR, 0xffffffff);
4097 I915_WRITE(IER, 0x0);
4098 POSTING_READ(IER);
4099 }
4100
4101 static int i965_irq_postinstall(struct drm_device *dev)
4102 {
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 u32 enable_mask;
4105 u32 error_mask;
4106 unsigned long irqflags;
4107
4108 /* Unmask the interrupts that we always want on. */
4109 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4110 I915_DISPLAY_PORT_INTERRUPT |
4111 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4112 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4113 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4114 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4115 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4116
4117 enable_mask = ~dev_priv->irq_mask;
4118 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4119 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4120 enable_mask |= I915_USER_INTERRUPT;
4121
4122 if (IS_G4X(dev))
4123 enable_mask |= I915_BSD_USER_INTERRUPT;
4124
4125 /* Interrupt setup is already guaranteed to be single-threaded, this is
4126 * just to make the assert_spin_locked check happy. */
4127 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4128 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4129 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4130 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4131 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4132
4133 /*
4134 * Enable some error detection, note the instruction error mask
4135 * bit is reserved, so we leave it masked.
4136 */
4137 if (IS_G4X(dev)) {
4138 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4139 GM45_ERROR_MEM_PRIV |
4140 GM45_ERROR_CP_PRIV |
4141 I915_ERROR_MEMORY_REFRESH);
4142 } else {
4143 error_mask = ~(I915_ERROR_PAGE_TABLE |
4144 I915_ERROR_MEMORY_REFRESH);
4145 }
4146 I915_WRITE(EMR, error_mask);
4147
4148 I915_WRITE(IMR, dev_priv->irq_mask);
4149 I915_WRITE(IER, enable_mask);
4150 POSTING_READ(IER);
4151
4152 I915_WRITE(PORT_HOTPLUG_EN, 0);
4153 POSTING_READ(PORT_HOTPLUG_EN);
4154
4155 i915_enable_asle_pipestat(dev);
4156
4157 return 0;
4158 }
4159
4160 static void i915_hpd_irq_setup(struct drm_device *dev)
4161 {
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct drm_mode_config *mode_config = &dev->mode_config;
4164 struct intel_encoder *intel_encoder;
4165 u32 hotplug_en;
4166
4167 assert_spin_locked(&dev_priv->irq_lock);
4168
4169 if (I915_HAS_HOTPLUG(dev)) {
4170 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4171 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4172 /* Note HDMI and DP share hotplug bits */
4173 /* enable bits are the same for all generations */
4174 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
4175 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4176 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4177 /* Programming the CRT detection parameters tends
4178 to generate a spurious hotplug event about three
4179 seconds later. So just do it once.
4180 */
4181 if (IS_G4X(dev))
4182 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4183 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4184 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4185
4186 /* Ignore TV since it's buggy */
4187 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4188 }
4189 }
4190
4191 static irqreturn_t i965_irq_handler(int irq, void *arg)
4192 {
4193 struct drm_device *dev = arg;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 u32 iir, new_iir;
4196 u32 pipe_stats[I915_MAX_PIPES];
4197 unsigned long irqflags;
4198 int ret = IRQ_NONE, pipe;
4199 u32 flip_mask =
4200 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4201 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4202
4203 iir = I915_READ(IIR);
4204
4205 for (;;) {
4206 bool irq_received = (iir & ~flip_mask) != 0;
4207 bool blc_event = false;
4208
4209 /* Can't rely on pipestat interrupt bit in iir as it might
4210 * have been cleared after the pipestat interrupt was received.
4211 * It doesn't set the bit in iir again, but it still produces
4212 * interrupts (for non-MSI).
4213 */
4214 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4215 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4216 i915_handle_error(dev, false,
4217 "Command parser error, iir 0x%08x",
4218 iir);
4219
4220 for_each_pipe(pipe) {
4221 int reg = PIPESTAT(pipe);
4222 pipe_stats[pipe] = I915_READ(reg);
4223
4224 /*
4225 * Clear the PIPE*STAT regs before the IIR
4226 */
4227 if (pipe_stats[pipe] & 0x8000ffff) {
4228 I915_WRITE(reg, pipe_stats[pipe]);
4229 irq_received = true;
4230 }
4231 }
4232 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4233
4234 if (!irq_received)
4235 break;
4236
4237 ret = IRQ_HANDLED;
4238
4239 /* Consume port. Then clear IIR or we'll miss events */
4240 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4241 i9xx_hpd_irq_handler(dev);
4242
4243 I915_WRITE(IIR, iir & ~flip_mask);
4244 new_iir = I915_READ(IIR); /* Flush posted writes */
4245
4246 if (iir & I915_USER_INTERRUPT)
4247 notify_ring(dev, &dev_priv->ring[RCS]);
4248 if (iir & I915_BSD_USER_INTERRUPT)
4249 notify_ring(dev, &dev_priv->ring[VCS]);
4250
4251 for_each_pipe(pipe) {
4252 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4253 i915_handle_vblank(dev, pipe, pipe, iir))
4254 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4255
4256 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4257 blc_event = true;
4258
4259 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4260 i9xx_pipe_crc_irq_handler(dev, pipe);
4261
4262 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4263 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4264 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4265 }
4266
4267 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4268 intel_opregion_asle_intr(dev);
4269
4270 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4271 gmbus_irq_handler(dev);
4272
4273 /* With MSI, interrupts are only generated when iir
4274 * transitions from zero to nonzero. If another bit got
4275 * set while we were handling the existing iir bits, then
4276 * we would never get another interrupt.
4277 *
4278 * This is fine on non-MSI as well, as if we hit this path
4279 * we avoid exiting the interrupt handler only to generate
4280 * another one.
4281 *
4282 * Note that for MSI this could cause a stray interrupt report
4283 * if an interrupt landed in the time between writing IIR and
4284 * the posting read. This should be rare enough to never
4285 * trigger the 99% of 100,000 interrupts test for disabling
4286 * stray interrupts.
4287 */
4288 iir = new_iir;
4289 }
4290
4291 i915_update_dri1_breadcrumb(dev);
4292
4293 return ret;
4294 }
4295
4296 static void i965_irq_uninstall(struct drm_device * dev)
4297 {
4298 struct drm_i915_private *dev_priv = dev->dev_private;
4299 int pipe;
4300
4301 if (!dev_priv)
4302 return;
4303
4304 intel_hpd_irq_uninstall(dev_priv);
4305
4306 I915_WRITE(PORT_HOTPLUG_EN, 0);
4307 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4308
4309 I915_WRITE(HWSTAM, 0xffffffff);
4310 for_each_pipe(pipe)
4311 I915_WRITE(PIPESTAT(pipe), 0);
4312 I915_WRITE(IMR, 0xffffffff);
4313 I915_WRITE(IER, 0x0);
4314
4315 for_each_pipe(pipe)
4316 I915_WRITE(PIPESTAT(pipe),
4317 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4318 I915_WRITE(IIR, I915_READ(IIR));
4319 }
4320
4321 static void intel_hpd_irq_reenable(unsigned long data)
4322 {
4323 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4324 struct drm_device *dev = dev_priv->dev;
4325 struct drm_mode_config *mode_config = &dev->mode_config;
4326 unsigned long irqflags;
4327 int i;
4328
4329 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4330 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4331 struct drm_connector *connector;
4332
4333 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4334 continue;
4335
4336 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4337
4338 list_for_each_entry(connector, &mode_config->connector_list, head) {
4339 struct intel_connector *intel_connector = to_intel_connector(connector);
4340
4341 if (intel_connector->encoder->hpd_pin == i) {
4342 if (connector->polled != intel_connector->polled)
4343 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4344 connector->name);
4345 connector->polled = intel_connector->polled;
4346 if (!connector->polled)
4347 connector->polled = DRM_CONNECTOR_POLL_HPD;
4348 }
4349 }
4350 }
4351 if (dev_priv->display.hpd_irq_setup)
4352 dev_priv->display.hpd_irq_setup(dev);
4353 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4354 }
4355
4356 void intel_irq_init(struct drm_device *dev)
4357 {
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359
4360 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4361 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4362 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4363 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4364
4365 /* Let's track the enabled rps events */
4366 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4367
4368 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4369 i915_hangcheck_elapsed,
4370 (unsigned long) dev);
4371 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4372 (unsigned long) dev_priv);
4373
4374 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4375
4376 if (IS_GEN2(dev)) {
4377 dev->max_vblank_count = 0;
4378 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4379 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4380 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4381 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4382 } else {
4383 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4384 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4385 }
4386
4387 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4388 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4389 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4390 }
4391
4392 if (IS_CHERRYVIEW(dev)) {
4393 dev->driver->irq_handler = cherryview_irq_handler;
4394 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4395 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4396 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4397 dev->driver->enable_vblank = valleyview_enable_vblank;
4398 dev->driver->disable_vblank = valleyview_disable_vblank;
4399 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4400 } else if (IS_VALLEYVIEW(dev)) {
4401 dev->driver->irq_handler = valleyview_irq_handler;
4402 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4403 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4404 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4405 dev->driver->enable_vblank = valleyview_enable_vblank;
4406 dev->driver->disable_vblank = valleyview_disable_vblank;
4407 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4408 } else if (IS_GEN8(dev)) {
4409 dev->driver->irq_handler = gen8_irq_handler;
4410 dev->driver->irq_preinstall = gen8_irq_reset;
4411 dev->driver->irq_postinstall = gen8_irq_postinstall;
4412 dev->driver->irq_uninstall = gen8_irq_uninstall;
4413 dev->driver->enable_vblank = gen8_enable_vblank;
4414 dev->driver->disable_vblank = gen8_disable_vblank;
4415 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4416 } else if (HAS_PCH_SPLIT(dev)) {
4417 dev->driver->irq_handler = ironlake_irq_handler;
4418 dev->driver->irq_preinstall = ironlake_irq_reset;
4419 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4420 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4421 dev->driver->enable_vblank = ironlake_enable_vblank;
4422 dev->driver->disable_vblank = ironlake_disable_vblank;
4423 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4424 } else {
4425 if (INTEL_INFO(dev)->gen == 2) {
4426 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4427 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4428 dev->driver->irq_handler = i8xx_irq_handler;
4429 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4430 } else if (INTEL_INFO(dev)->gen == 3) {
4431 dev->driver->irq_preinstall = i915_irq_preinstall;
4432 dev->driver->irq_postinstall = i915_irq_postinstall;
4433 dev->driver->irq_uninstall = i915_irq_uninstall;
4434 dev->driver->irq_handler = i915_irq_handler;
4435 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4436 } else {
4437 dev->driver->irq_preinstall = i965_irq_preinstall;
4438 dev->driver->irq_postinstall = i965_irq_postinstall;
4439 dev->driver->irq_uninstall = i965_irq_uninstall;
4440 dev->driver->irq_handler = i965_irq_handler;
4441 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4442 }
4443 dev->driver->enable_vblank = i915_enable_vblank;
4444 dev->driver->disable_vblank = i915_disable_vblank;
4445 }
4446 }
4447
4448 void intel_hpd_init(struct drm_device *dev)
4449 {
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451 struct drm_mode_config *mode_config = &dev->mode_config;
4452 struct drm_connector *connector;
4453 unsigned long irqflags;
4454 int i;
4455
4456 for (i = 1; i < HPD_NUM_PINS; i++) {
4457 dev_priv->hpd_stats[i].hpd_cnt = 0;
4458 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4459 }
4460 list_for_each_entry(connector, &mode_config->connector_list, head) {
4461 struct intel_connector *intel_connector = to_intel_connector(connector);
4462 connector->polled = intel_connector->polled;
4463 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4464 connector->polled = DRM_CONNECTOR_POLL_HPD;
4465 }
4466
4467 /* Interrupt setup is already guaranteed to be single-threaded, this is
4468 * just to make the assert_spin_locked checks happy. */
4469 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4470 if (dev_priv->display.hpd_irq_setup)
4471 dev_priv->display.hpd_irq_setup(dev);
4472 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4473 }
4474
4475 /* Disable interrupts so we can allow runtime PM. */
4476 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4477 {
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479
4480 dev->driver->irq_uninstall(dev);
4481 dev_priv->pm.irqs_disabled = true;
4482 }
4483
4484 /* Restore interrupts so we can recover from runtime PM. */
4485 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4486 {
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488
4489 dev_priv->pm.irqs_disabled = false;
4490 dev->driver->irq_preinstall(dev);
4491 dev->driver->irq_postinstall(dev);
4492 }
Linux kernel - Deliverables
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