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drm/i915: Capture ERROR register on Sandybridge hangs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67 void
68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
69 {
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75 }
76
77 void
78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
79 {
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85 }
86
87 /* For display hotplug interrupt */
88 static void
89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
90 {
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96 }
97
98 static inline void
99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
100 {
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106 }
107
108 void
109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110 {
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116 }
117
118 void
119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120 {
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126 }
127
128 static inline u32
129 i915_pipestat(int pipe)
130 {
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
135 BUG();
136 }
137
138 void
139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140 {
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149 }
150
151 void
152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153 {
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161 }
162
163 /**
164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166 void intel_enable_asle (struct drm_device *dev)
167 {
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
170 if (HAS_PCH_SPLIT(dev))
171 ironlake_enable_display_irq(dev_priv, DE_GSE);
172 else {
173 i915_enable_pipestat(dev_priv, 1,
174 PIPE_LEGACY_BLC_EVENT_ENABLE);
175 if (INTEL_INFO(dev)->gen >= 4)
176 i915_enable_pipestat(dev_priv, 0,
177 PIPE_LEGACY_BLC_EVENT_ENABLE);
178 }
179 }
180
181 /**
182 * i915_pipe_enabled - check if a pipe is enabled
183 * @dev: DRM device
184 * @pipe: pipe to check
185 *
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
189 */
190 static int
191 i915_pipe_enabled(struct drm_device *dev, int pipe)
192 {
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
195 }
196
197 /* Called from drm generic code, passed a 'crtc', which
198 * we use as a pipe index
199 */
200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
201 {
202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
203 unsigned long high_frame;
204 unsigned long low_frame;
205 u32 high1, high2, low;
206
207 if (!i915_pipe_enabled(dev, pipe)) {
208 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
209 "pipe %d\n", pipe);
210 return 0;
211 }
212
213 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
214 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
215
216 /*
217 * High & low register fields aren't synchronized, so make sure
218 * we get a low value that's stable across two reads of the high
219 * register.
220 */
221 do {
222 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
223 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
224 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
225 } while (high1 != high2);
226
227 high1 >>= PIPE_FRAME_HIGH_SHIFT;
228 low >>= PIPE_FRAME_LOW_SHIFT;
229 return (high1 << 8) | low;
230 }
231
232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
233 {
234 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
235 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
236
237 if (!i915_pipe_enabled(dev, pipe)) {
238 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
239 "pipe %d\n", pipe);
240 return 0;
241 }
242
243 return I915_READ(reg);
244 }
245
246 /*
247 * Handle hotplug events outside the interrupt handler proper.
248 */
249 static void i915_hotplug_work_func(struct work_struct *work)
250 {
251 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
252 hotplug_work);
253 struct drm_device *dev = dev_priv->dev;
254 struct drm_mode_config *mode_config = &dev->mode_config;
255 struct intel_encoder *encoder;
256
257 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
258 if (encoder->hot_plug)
259 encoder->hot_plug(encoder);
260
261 /* Just fire off a uevent and let userspace tell us what to do */
262 drm_helper_hpd_irq_event(dev);
263 }
264
265 static void i915_handle_rps_change(struct drm_device *dev)
266 {
267 drm_i915_private_t *dev_priv = dev->dev_private;
268 u32 busy_up, busy_down, max_avg, min_avg;
269 u8 new_delay = dev_priv->cur_delay;
270
271 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
272 busy_up = I915_READ(RCPREVBSYTUPAVG);
273 busy_down = I915_READ(RCPREVBSYTDNAVG);
274 max_avg = I915_READ(RCBMAXAVG);
275 min_avg = I915_READ(RCBMINAVG);
276
277 /* Handle RCS change request from hw */
278 if (busy_up > max_avg) {
279 if (dev_priv->cur_delay != dev_priv->max_delay)
280 new_delay = dev_priv->cur_delay - 1;
281 if (new_delay < dev_priv->max_delay)
282 new_delay = dev_priv->max_delay;
283 } else if (busy_down < min_avg) {
284 if (dev_priv->cur_delay != dev_priv->min_delay)
285 new_delay = dev_priv->cur_delay + 1;
286 if (new_delay > dev_priv->min_delay)
287 new_delay = dev_priv->min_delay;
288 }
289
290 if (ironlake_set_drps(dev, new_delay))
291 dev_priv->cur_delay = new_delay;
292
293 return;
294 }
295
296 static void notify_ring(struct drm_device *dev,
297 struct intel_ring_buffer *ring)
298 {
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 u32 seqno = ring->get_seqno(ring);
301 ring->irq_seqno = seqno;
302 trace_i915_gem_request_complete(dev, seqno);
303 wake_up_all(&ring->irq_queue);
304 dev_priv->hangcheck_count = 0;
305 mod_timer(&dev_priv->hangcheck_timer,
306 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
307 }
308
309 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
310 {
311 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
312 int ret = IRQ_NONE;
313 u32 de_iir, gt_iir, de_ier, pch_iir;
314 u32 hotplug_mask;
315 struct drm_i915_master_private *master_priv;
316 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
317
318 if (IS_GEN6(dev))
319 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
320
321 /* disable master interrupt before clearing iir */
322 de_ier = I915_READ(DEIER);
323 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
324 (void)I915_READ(DEIER);
325
326 de_iir = I915_READ(DEIIR);
327 gt_iir = I915_READ(GTIIR);
328 pch_iir = I915_READ(SDEIIR);
329
330 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
331 goto done;
332
333 if (HAS_PCH_CPT(dev))
334 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
335 else
336 hotplug_mask = SDE_HOTPLUG_MASK;
337
338 ret = IRQ_HANDLED;
339
340 if (dev->primary->master) {
341 master_priv = dev->primary->master->driver_priv;
342 if (master_priv->sarea_priv)
343 master_priv->sarea_priv->last_dispatch =
344 READ_BREADCRUMB(dev_priv);
345 }
346
347 if (gt_iir & GT_PIPE_NOTIFY)
348 notify_ring(dev, &dev_priv->render_ring);
349 if (gt_iir & bsd_usr_interrupt)
350 notify_ring(dev, &dev_priv->bsd_ring);
351 if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
352 notify_ring(dev, &dev_priv->blt_ring);
353
354 if (de_iir & DE_GSE)
355 intel_opregion_gse_intr(dev);
356
357 if (de_iir & DE_PLANEA_FLIP_DONE) {
358 intel_prepare_page_flip(dev, 0);
359 intel_finish_page_flip_plane(dev, 0);
360 }
361
362 if (de_iir & DE_PLANEB_FLIP_DONE) {
363 intel_prepare_page_flip(dev, 1);
364 intel_finish_page_flip_plane(dev, 1);
365 }
366
367 if (de_iir & DE_PIPEA_VBLANK)
368 drm_handle_vblank(dev, 0);
369
370 if (de_iir & DE_PIPEB_VBLANK)
371 drm_handle_vblank(dev, 1);
372
373 /* check event from PCH */
374 if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
375 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
376
377 if (de_iir & DE_PCU_EVENT) {
378 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
379 i915_handle_rps_change(dev);
380 }
381
382 /* should clear PCH hotplug event before clear CPU irq */
383 I915_WRITE(SDEIIR, pch_iir);
384 I915_WRITE(GTIIR, gt_iir);
385 I915_WRITE(DEIIR, de_iir);
386
387 done:
388 I915_WRITE(DEIER, de_ier);
389 (void)I915_READ(DEIER);
390
391 return ret;
392 }
393
394 /**
395 * i915_error_work_func - do process context error handling work
396 * @work: work struct
397 *
398 * Fire an error uevent so userspace can see that a hang or error
399 * was detected.
400 */
401 static void i915_error_work_func(struct work_struct *work)
402 {
403 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
404 error_work);
405 struct drm_device *dev = dev_priv->dev;
406 char *error_event[] = { "ERROR=1", NULL };
407 char *reset_event[] = { "RESET=1", NULL };
408 char *reset_done_event[] = { "ERROR=0", NULL };
409
410 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
411
412 if (atomic_read(&dev_priv->mm.wedged)) {
413 DRM_DEBUG_DRIVER("resetting chip\n");
414 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
415 if (!i915_reset(dev, GRDOM_RENDER)) {
416 atomic_set(&dev_priv->mm.wedged, 0);
417 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
418 }
419 complete_all(&dev_priv->error_completion);
420 }
421 }
422
423 #ifdef CONFIG_DEBUG_FS
424 static struct drm_i915_error_object *
425 i915_error_object_create(struct drm_device *dev,
426 struct drm_gem_object *src)
427 {
428 drm_i915_private_t *dev_priv = dev->dev_private;
429 struct drm_i915_error_object *dst;
430 struct drm_i915_gem_object *src_priv;
431 int page, page_count;
432 u32 reloc_offset;
433
434 if (src == NULL)
435 return NULL;
436
437 src_priv = to_intel_bo(src);
438 if (src_priv->pages == NULL)
439 return NULL;
440
441 page_count = src->size / PAGE_SIZE;
442
443 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
444 if (dst == NULL)
445 return NULL;
446
447 reloc_offset = src_priv->gtt_offset;
448 for (page = 0; page < page_count; page++) {
449 unsigned long flags;
450 void __iomem *s;
451 void *d;
452
453 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
454 if (d == NULL)
455 goto unwind;
456
457 local_irq_save(flags);
458 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
459 reloc_offset);
460 memcpy_fromio(d, s, PAGE_SIZE);
461 io_mapping_unmap_atomic(s);
462 local_irq_restore(flags);
463
464 dst->pages[page] = d;
465
466 reloc_offset += PAGE_SIZE;
467 }
468 dst->page_count = page_count;
469 dst->gtt_offset = src_priv->gtt_offset;
470
471 return dst;
472
473 unwind:
474 while (page--)
475 kfree(dst->pages[page]);
476 kfree(dst);
477 return NULL;
478 }
479
480 static void
481 i915_error_object_free(struct drm_i915_error_object *obj)
482 {
483 int page;
484
485 if (obj == NULL)
486 return;
487
488 for (page = 0; page < obj->page_count; page++)
489 kfree(obj->pages[page]);
490
491 kfree(obj);
492 }
493
494 static void
495 i915_error_state_free(struct drm_device *dev,
496 struct drm_i915_error_state *error)
497 {
498 i915_error_object_free(error->batchbuffer[0]);
499 i915_error_object_free(error->batchbuffer[1]);
500 i915_error_object_free(error->ringbuffer);
501 kfree(error->active_bo);
502 kfree(error->overlay);
503 kfree(error);
504 }
505
506 static u32
507 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
508 {
509 u32 cmd;
510
511 if (IS_I830(dev) || IS_845G(dev))
512 cmd = MI_BATCH_BUFFER;
513 else if (INTEL_INFO(dev)->gen >= 4)
514 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
515 MI_BATCH_NON_SECURE_I965);
516 else
517 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
518
519 return ring[0] == cmd ? ring[1] : 0;
520 }
521
522 static u32
523 i915_ringbuffer_last_batch(struct drm_device *dev)
524 {
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 u32 head, bbaddr;
527 u32 *ring;
528
529 /* Locate the current position in the ringbuffer and walk back
530 * to find the most recently dispatched batch buffer.
531 */
532 bbaddr = 0;
533 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
534 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
535
536 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
537 bbaddr = i915_get_bbaddr(dev, ring);
538 if (bbaddr)
539 break;
540 }
541
542 if (bbaddr == 0) {
543 ring = (u32 *)(dev_priv->render_ring.virtual_start
544 + dev_priv->render_ring.size);
545 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
546 bbaddr = i915_get_bbaddr(dev, ring);
547 if (bbaddr)
548 break;
549 }
550 }
551
552 return bbaddr;
553 }
554
555 /**
556 * i915_capture_error_state - capture an error record for later analysis
557 * @dev: drm device
558 *
559 * Should be called when an error is detected (either a hang or an error
560 * interrupt) to capture error state from the time of the error. Fills
561 * out a structure which becomes available in debugfs for user level tools
562 * to pick up.
563 */
564 static void i915_capture_error_state(struct drm_device *dev)
565 {
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct drm_i915_gem_object *obj_priv;
568 struct drm_i915_error_state *error;
569 struct drm_gem_object *batchbuffer[2];
570 unsigned long flags;
571 u32 bbaddr;
572 int count;
573
574 spin_lock_irqsave(&dev_priv->error_lock, flags);
575 error = dev_priv->first_error;
576 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
577 if (error)
578 return;
579
580 error = kmalloc(sizeof(*error), GFP_ATOMIC);
581 if (!error) {
582 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
583 return;
584 }
585
586 DRM_DEBUG_DRIVER("generating error event\n");
587
588 error->seqno =
589 dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
590 error->eir = I915_READ(EIR);
591 error->pgtbl_er = I915_READ(PGTBL_ER);
592 error->pipeastat = I915_READ(PIPEASTAT);
593 error->pipebstat = I915_READ(PIPEBSTAT);
594 error->instpm = I915_READ(INSTPM);
595 error->error = 0;
596 if (INTEL_INFO(dev)->gen >= 6) {
597 error->error = I915_READ(ERROR_GEN6);
598 }
599 if (INTEL_INFO(dev)->gen >= 4) {
600 error->ipeir = I915_READ(IPEIR_I965);
601 error->ipehr = I915_READ(IPEHR_I965);
602 error->instdone = I915_READ(INSTDONE_I965);
603 error->instps = I915_READ(INSTPS);
604 error->instdone1 = I915_READ(INSTDONE1);
605 error->acthd = I915_READ(ACTHD_I965);
606 error->bbaddr = I915_READ64(BB_ADDR);
607 } else {
608 error->ipeir = I915_READ(IPEIR);
609 error->ipehr = I915_READ(IPEHR);
610 error->instdone = I915_READ(INSTDONE);
611 error->acthd = I915_READ(ACTHD);
612 error->bbaddr = 0;
613 }
614
615 bbaddr = i915_ringbuffer_last_batch(dev);
616
617 /* Grab the current batchbuffer, most likely to have crashed. */
618 batchbuffer[0] = NULL;
619 batchbuffer[1] = NULL;
620 count = 0;
621 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
622 struct drm_gem_object *obj = &obj_priv->base;
623
624 if (batchbuffer[0] == NULL &&
625 bbaddr >= obj_priv->gtt_offset &&
626 bbaddr < obj_priv->gtt_offset + obj->size)
627 batchbuffer[0] = obj;
628
629 if (batchbuffer[1] == NULL &&
630 error->acthd >= obj_priv->gtt_offset &&
631 error->acthd < obj_priv->gtt_offset + obj->size)
632 batchbuffer[1] = obj;
633
634 count++;
635 }
636 /* Scan the other lists for completeness for those bizarre errors. */
637 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
638 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) {
639 struct drm_gem_object *obj = &obj_priv->base;
640
641 if (batchbuffer[0] == NULL &&
642 bbaddr >= obj_priv->gtt_offset &&
643 bbaddr < obj_priv->gtt_offset + obj->size)
644 batchbuffer[0] = obj;
645
646 if (batchbuffer[1] == NULL &&
647 error->acthd >= obj_priv->gtt_offset &&
648 error->acthd < obj_priv->gtt_offset + obj->size)
649 batchbuffer[1] = obj;
650
651 if (batchbuffer[0] && batchbuffer[1])
652 break;
653 }
654 }
655 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
656 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) {
657 struct drm_gem_object *obj = &obj_priv->base;
658
659 if (batchbuffer[0] == NULL &&
660 bbaddr >= obj_priv->gtt_offset &&
661 bbaddr < obj_priv->gtt_offset + obj->size)
662 batchbuffer[0] = obj;
663
664 if (batchbuffer[1] == NULL &&
665 error->acthd >= obj_priv->gtt_offset &&
666 error->acthd < obj_priv->gtt_offset + obj->size)
667 batchbuffer[1] = obj;
668
669 if (batchbuffer[0] && batchbuffer[1])
670 break;
671 }
672 }
673
674 /* We need to copy these to an anonymous buffer as the simplest
675 * method to avoid being overwritten by userspace.
676 */
677 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
678 if (batchbuffer[1] != batchbuffer[0])
679 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
680 else
681 error->batchbuffer[1] = NULL;
682
683 /* Record the ringbuffer */
684 error->ringbuffer = i915_error_object_create(dev,
685 dev_priv->render_ring.gem_object);
686
687 /* Record buffers on the active list. */
688 error->active_bo = NULL;
689 error->active_bo_count = 0;
690
691 if (count)
692 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
693 GFP_ATOMIC);
694
695 if (error->active_bo) {
696 int i = 0;
697 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
698 struct drm_gem_object *obj = &obj_priv->base;
699
700 error->active_bo[i].size = obj->size;
701 error->active_bo[i].name = obj->name;
702 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
703 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
704 error->active_bo[i].read_domains = obj->read_domains;
705 error->active_bo[i].write_domain = obj->write_domain;
706 error->active_bo[i].fence_reg = obj_priv->fence_reg;
707 error->active_bo[i].pinned = 0;
708 if (obj_priv->pin_count > 0)
709 error->active_bo[i].pinned = 1;
710 if (obj_priv->user_pin_count > 0)
711 error->active_bo[i].pinned = -1;
712 error->active_bo[i].tiling = obj_priv->tiling_mode;
713 error->active_bo[i].dirty = obj_priv->dirty;
714 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
715
716 if (++i == count)
717 break;
718 }
719 error->active_bo_count = i;
720 }
721
722 do_gettimeofday(&error->time);
723
724 error->overlay = intel_overlay_capture_error_state(dev);
725
726 spin_lock_irqsave(&dev_priv->error_lock, flags);
727 if (dev_priv->first_error == NULL) {
728 dev_priv->first_error = error;
729 error = NULL;
730 }
731 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
732
733 if (error)
734 i915_error_state_free(dev, error);
735 }
736
737 void i915_destroy_error_state(struct drm_device *dev)
738 {
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 struct drm_i915_error_state *error;
741
742 spin_lock(&dev_priv->error_lock);
743 error = dev_priv->first_error;
744 dev_priv->first_error = NULL;
745 spin_unlock(&dev_priv->error_lock);
746
747 if (error)
748 i915_error_state_free(dev, error);
749 }
750 #else
751 #define i915_capture_error_state(x)
752 #endif
753
754 static void i915_report_and_clear_eir(struct drm_device *dev)
755 {
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 u32 eir = I915_READ(EIR);
758
759 if (!eir)
760 return;
761
762 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
763 eir);
764
765 if (IS_G4X(dev)) {
766 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
767 u32 ipeir = I915_READ(IPEIR_I965);
768
769 printk(KERN_ERR " IPEIR: 0x%08x\n",
770 I915_READ(IPEIR_I965));
771 printk(KERN_ERR " IPEHR: 0x%08x\n",
772 I915_READ(IPEHR_I965));
773 printk(KERN_ERR " INSTDONE: 0x%08x\n",
774 I915_READ(INSTDONE_I965));
775 printk(KERN_ERR " INSTPS: 0x%08x\n",
776 I915_READ(INSTPS));
777 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
778 I915_READ(INSTDONE1));
779 printk(KERN_ERR " ACTHD: 0x%08x\n",
780 I915_READ(ACTHD_I965));
781 I915_WRITE(IPEIR_I965, ipeir);
782 (void)I915_READ(IPEIR_I965);
783 }
784 if (eir & GM45_ERROR_PAGE_TABLE) {
785 u32 pgtbl_err = I915_READ(PGTBL_ER);
786 printk(KERN_ERR "page table error\n");
787 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
788 pgtbl_err);
789 I915_WRITE(PGTBL_ER, pgtbl_err);
790 (void)I915_READ(PGTBL_ER);
791 }
792 }
793
794 if (!IS_GEN2(dev)) {
795 if (eir & I915_ERROR_PAGE_TABLE) {
796 u32 pgtbl_err = I915_READ(PGTBL_ER);
797 printk(KERN_ERR "page table error\n");
798 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
799 pgtbl_err);
800 I915_WRITE(PGTBL_ER, pgtbl_err);
801 (void)I915_READ(PGTBL_ER);
802 }
803 }
804
805 if (eir & I915_ERROR_MEMORY_REFRESH) {
806 u32 pipea_stats = I915_READ(PIPEASTAT);
807 u32 pipeb_stats = I915_READ(PIPEBSTAT);
808
809 printk(KERN_ERR "memory refresh error\n");
810 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
811 pipea_stats);
812 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
813 pipeb_stats);
814 /* pipestat has already been acked */
815 }
816 if (eir & I915_ERROR_INSTRUCTION) {
817 printk(KERN_ERR "instruction error\n");
818 printk(KERN_ERR " INSTPM: 0x%08x\n",
819 I915_READ(INSTPM));
820 if (INTEL_INFO(dev)->gen < 4) {
821 u32 ipeir = I915_READ(IPEIR);
822
823 printk(KERN_ERR " IPEIR: 0x%08x\n",
824 I915_READ(IPEIR));
825 printk(KERN_ERR " IPEHR: 0x%08x\n",
826 I915_READ(IPEHR));
827 printk(KERN_ERR " INSTDONE: 0x%08x\n",
828 I915_READ(INSTDONE));
829 printk(KERN_ERR " ACTHD: 0x%08x\n",
830 I915_READ(ACTHD));
831 I915_WRITE(IPEIR, ipeir);
832 (void)I915_READ(IPEIR);
833 } else {
834 u32 ipeir = I915_READ(IPEIR_I965);
835
836 printk(KERN_ERR " IPEIR: 0x%08x\n",
837 I915_READ(IPEIR_I965));
838 printk(KERN_ERR " IPEHR: 0x%08x\n",
839 I915_READ(IPEHR_I965));
840 printk(KERN_ERR " INSTDONE: 0x%08x\n",
841 I915_READ(INSTDONE_I965));
842 printk(KERN_ERR " INSTPS: 0x%08x\n",
843 I915_READ(INSTPS));
844 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
845 I915_READ(INSTDONE1));
846 printk(KERN_ERR " ACTHD: 0x%08x\n",
847 I915_READ(ACTHD_I965));
848 I915_WRITE(IPEIR_I965, ipeir);
849 (void)I915_READ(IPEIR_I965);
850 }
851 }
852
853 I915_WRITE(EIR, eir);
854 (void)I915_READ(EIR);
855 eir = I915_READ(EIR);
856 if (eir) {
857 /*
858 * some errors might have become stuck,
859 * mask them.
860 */
861 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
862 I915_WRITE(EMR, I915_READ(EMR) | eir);
863 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
864 }
865 }
866
867 /**
868 * i915_handle_error - handle an error interrupt
869 * @dev: drm device
870 *
871 * Do some basic checking of regsiter state at error interrupt time and
872 * dump it to the syslog. Also call i915_capture_error_state() to make
873 * sure we get a record and make it available in debugfs. Fire a uevent
874 * so userspace knows something bad happened (should trigger collection
875 * of a ring dump etc.).
876 */
877 static void i915_handle_error(struct drm_device *dev, bool wedged)
878 {
879 struct drm_i915_private *dev_priv = dev->dev_private;
880
881 i915_capture_error_state(dev);
882 i915_report_and_clear_eir(dev);
883
884 if (wedged) {
885 INIT_COMPLETION(dev_priv->error_completion);
886 atomic_set(&dev_priv->mm.wedged, 1);
887
888 /*
889 * Wakeup waiting processes so they don't hang
890 */
891 wake_up_all(&dev_priv->render_ring.irq_queue);
892 if (HAS_BSD(dev))
893 wake_up_all(&dev_priv->bsd_ring.irq_queue);
894 if (HAS_BLT(dev))
895 wake_up_all(&dev_priv->blt_ring.irq_queue);
896 }
897
898 queue_work(dev_priv->wq, &dev_priv->error_work);
899 }
900
901 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
902 {
903 drm_i915_private_t *dev_priv = dev->dev_private;
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906 struct drm_i915_gem_object *obj_priv;
907 struct intel_unpin_work *work;
908 unsigned long flags;
909 bool stall_detected;
910
911 /* Ignore early vblank irqs */
912 if (intel_crtc == NULL)
913 return;
914
915 spin_lock_irqsave(&dev->event_lock, flags);
916 work = intel_crtc->unpin_work;
917
918 if (work == NULL || work->pending || !work->enable_stall_check) {
919 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
920 spin_unlock_irqrestore(&dev->event_lock, flags);
921 return;
922 }
923
924 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
925 obj_priv = to_intel_bo(work->pending_flip_obj);
926 if (INTEL_INFO(dev)->gen >= 4) {
927 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
928 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
929 } else {
930 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
931 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
932 crtc->y * crtc->fb->pitch +
933 crtc->x * crtc->fb->bits_per_pixel/8);
934 }
935
936 spin_unlock_irqrestore(&dev->event_lock, flags);
937
938 if (stall_detected) {
939 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
940 intel_prepare_page_flip(dev, intel_crtc->plane);
941 }
942 }
943
944 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
945 {
946 struct drm_device *dev = (struct drm_device *) arg;
947 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
948 struct drm_i915_master_private *master_priv;
949 u32 iir, new_iir;
950 u32 pipea_stats, pipeb_stats;
951 u32 vblank_status;
952 int vblank = 0;
953 unsigned long irqflags;
954 int irq_received;
955 int ret = IRQ_NONE;
956
957 atomic_inc(&dev_priv->irq_received);
958
959 if (HAS_PCH_SPLIT(dev))
960 return ironlake_irq_handler(dev);
961
962 iir = I915_READ(IIR);
963
964 if (INTEL_INFO(dev)->gen >= 4)
965 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
966 else
967 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
968
969 for (;;) {
970 irq_received = iir != 0;
971
972 /* Can't rely on pipestat interrupt bit in iir as it might
973 * have been cleared after the pipestat interrupt was received.
974 * It doesn't set the bit in iir again, but it still produces
975 * interrupts (for non-MSI).
976 */
977 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
978 pipea_stats = I915_READ(PIPEASTAT);
979 pipeb_stats = I915_READ(PIPEBSTAT);
980
981 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
982 i915_handle_error(dev, false);
983
984 /*
985 * Clear the PIPE(A|B)STAT regs before the IIR
986 */
987 if (pipea_stats & 0x8000ffff) {
988 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
989 DRM_DEBUG_DRIVER("pipe a underrun\n");
990 I915_WRITE(PIPEASTAT, pipea_stats);
991 irq_received = 1;
992 }
993
994 if (pipeb_stats & 0x8000ffff) {
995 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
996 DRM_DEBUG_DRIVER("pipe b underrun\n");
997 I915_WRITE(PIPEBSTAT, pipeb_stats);
998 irq_received = 1;
999 }
1000 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1001
1002 if (!irq_received)
1003 break;
1004
1005 ret = IRQ_HANDLED;
1006
1007 /* Consume port. Then clear IIR or we'll miss events */
1008 if ((I915_HAS_HOTPLUG(dev)) &&
1009 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1010 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1011
1012 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1013 hotplug_status);
1014 if (hotplug_status & dev_priv->hotplug_supported_mask)
1015 queue_work(dev_priv->wq,
1016 &dev_priv->hotplug_work);
1017
1018 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1019 I915_READ(PORT_HOTPLUG_STAT);
1020 }
1021
1022 I915_WRITE(IIR, iir);
1023 new_iir = I915_READ(IIR); /* Flush posted writes */
1024
1025 if (dev->primary->master) {
1026 master_priv = dev->primary->master->driver_priv;
1027 if (master_priv->sarea_priv)
1028 master_priv->sarea_priv->last_dispatch =
1029 READ_BREADCRUMB(dev_priv);
1030 }
1031
1032 if (iir & I915_USER_INTERRUPT)
1033 notify_ring(dev, &dev_priv->render_ring);
1034 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1035 notify_ring(dev, &dev_priv->bsd_ring);
1036
1037 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1038 intel_prepare_page_flip(dev, 0);
1039 if (dev_priv->flip_pending_is_done)
1040 intel_finish_page_flip_plane(dev, 0);
1041 }
1042
1043 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1044 intel_prepare_page_flip(dev, 1);
1045 if (dev_priv->flip_pending_is_done)
1046 intel_finish_page_flip_plane(dev, 1);
1047 }
1048
1049 if (pipea_stats & vblank_status) {
1050 vblank++;
1051 drm_handle_vblank(dev, 0);
1052 if (!dev_priv->flip_pending_is_done) {
1053 i915_pageflip_stall_check(dev, 0);
1054 intel_finish_page_flip(dev, 0);
1055 }
1056 }
1057
1058 if (pipeb_stats & vblank_status) {
1059 vblank++;
1060 drm_handle_vblank(dev, 1);
1061 if (!dev_priv->flip_pending_is_done) {
1062 i915_pageflip_stall_check(dev, 1);
1063 intel_finish_page_flip(dev, 1);
1064 }
1065 }
1066
1067 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1068 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1069 (iir & I915_ASLE_INTERRUPT))
1070 intel_opregion_asle_intr(dev);
1071
1072 /* With MSI, interrupts are only generated when iir
1073 * transitions from zero to nonzero. If another bit got
1074 * set while we were handling the existing iir bits, then
1075 * we would never get another interrupt.
1076 *
1077 * This is fine on non-MSI as well, as if we hit this path
1078 * we avoid exiting the interrupt handler only to generate
1079 * another one.
1080 *
1081 * Note that for MSI this could cause a stray interrupt report
1082 * if an interrupt landed in the time between writing IIR and
1083 * the posting read. This should be rare enough to never
1084 * trigger the 99% of 100,000 interrupts test for disabling
1085 * stray interrupts.
1086 */
1087 iir = new_iir;
1088 }
1089
1090 return ret;
1091 }
1092
1093 static int i915_emit_irq(struct drm_device * dev)
1094 {
1095 drm_i915_private_t *dev_priv = dev->dev_private;
1096 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1097
1098 i915_kernel_lost_context(dev);
1099
1100 DRM_DEBUG_DRIVER("\n");
1101
1102 dev_priv->counter++;
1103 if (dev_priv->counter > 0x7FFFFFFFUL)
1104 dev_priv->counter = 1;
1105 if (master_priv->sarea_priv)
1106 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1107
1108 if (BEGIN_LP_RING(4) == 0) {
1109 OUT_RING(MI_STORE_DWORD_INDEX);
1110 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1111 OUT_RING(dev_priv->counter);
1112 OUT_RING(MI_USER_INTERRUPT);
1113 ADVANCE_LP_RING();
1114 }
1115
1116 return dev_priv->counter;
1117 }
1118
1119 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1120 {
1121 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1122 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1123
1124 if (dev_priv->trace_irq_seqno == 0)
1125 render_ring->user_irq_get(render_ring);
1126
1127 dev_priv->trace_irq_seqno = seqno;
1128 }
1129
1130 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1131 {
1132 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1133 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1134 int ret = 0;
1135 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1136
1137 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1138 READ_BREADCRUMB(dev_priv));
1139
1140 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1141 if (master_priv->sarea_priv)
1142 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1143 return 0;
1144 }
1145
1146 if (master_priv->sarea_priv)
1147 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1148
1149 render_ring->user_irq_get(render_ring);
1150 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1151 READ_BREADCRUMB(dev_priv) >= irq_nr);
1152 render_ring->user_irq_put(render_ring);
1153
1154 if (ret == -EBUSY) {
1155 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1156 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1157 }
1158
1159 return ret;
1160 }
1161
1162 /* Needs the lock as it touches the ring.
1163 */
1164 int i915_irq_emit(struct drm_device *dev, void *data,
1165 struct drm_file *file_priv)
1166 {
1167 drm_i915_private_t *dev_priv = dev->dev_private;
1168 drm_i915_irq_emit_t *emit = data;
1169 int result;
1170
1171 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1172 DRM_ERROR("called with no initialization\n");
1173 return -EINVAL;
1174 }
1175
1176 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1177
1178 mutex_lock(&dev->struct_mutex);
1179 result = i915_emit_irq(dev);
1180 mutex_unlock(&dev->struct_mutex);
1181
1182 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1183 DRM_ERROR("copy_to_user\n");
1184 return -EFAULT;
1185 }
1186
1187 return 0;
1188 }
1189
1190 /* Doesn't need the hardware lock.
1191 */
1192 int i915_irq_wait(struct drm_device *dev, void *data,
1193 struct drm_file *file_priv)
1194 {
1195 drm_i915_private_t *dev_priv = dev->dev_private;
1196 drm_i915_irq_wait_t *irqwait = data;
1197
1198 if (!dev_priv) {
1199 DRM_ERROR("called with no initialization\n");
1200 return -EINVAL;
1201 }
1202
1203 return i915_wait_irq(dev, irqwait->irq_seq);
1204 }
1205
1206 /* Called from drm generic code, passed 'crtc' which
1207 * we use as a pipe index
1208 */
1209 int i915_enable_vblank(struct drm_device *dev, int pipe)
1210 {
1211 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1212 unsigned long irqflags;
1213
1214 if (!i915_pipe_enabled(dev, pipe))
1215 return -EINVAL;
1216
1217 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1218 if (HAS_PCH_SPLIT(dev))
1219 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1220 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1221 else if (INTEL_INFO(dev)->gen >= 4)
1222 i915_enable_pipestat(dev_priv, pipe,
1223 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1224 else
1225 i915_enable_pipestat(dev_priv, pipe,
1226 PIPE_VBLANK_INTERRUPT_ENABLE);
1227 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1228 return 0;
1229 }
1230
1231 /* Called from drm generic code, passed 'crtc' which
1232 * we use as a pipe index
1233 */
1234 void i915_disable_vblank(struct drm_device *dev, int pipe)
1235 {
1236 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1237 unsigned long irqflags;
1238
1239 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1240 if (HAS_PCH_SPLIT(dev))
1241 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1242 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1243 else
1244 i915_disable_pipestat(dev_priv, pipe,
1245 PIPE_VBLANK_INTERRUPT_ENABLE |
1246 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1247 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1248 }
1249
1250 void i915_enable_interrupt (struct drm_device *dev)
1251 {
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253
1254 if (!HAS_PCH_SPLIT(dev))
1255 intel_opregion_enable_asle(dev);
1256 dev_priv->irq_enabled = 1;
1257 }
1258
1259
1260 /* Set the vblank monitor pipe
1261 */
1262 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1263 struct drm_file *file_priv)
1264 {
1265 drm_i915_private_t *dev_priv = dev->dev_private;
1266
1267 if (!dev_priv) {
1268 DRM_ERROR("called with no initialization\n");
1269 return -EINVAL;
1270 }
1271
1272 return 0;
1273 }
1274
1275 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1276 struct drm_file *file_priv)
1277 {
1278 drm_i915_private_t *dev_priv = dev->dev_private;
1279 drm_i915_vblank_pipe_t *pipe = data;
1280
1281 if (!dev_priv) {
1282 DRM_ERROR("called with no initialization\n");
1283 return -EINVAL;
1284 }
1285
1286 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1287
1288 return 0;
1289 }
1290
1291 /**
1292 * Schedule buffer swap at given vertical blank.
1293 */
1294 int i915_vblank_swap(struct drm_device *dev, void *data,
1295 struct drm_file *file_priv)
1296 {
1297 /* The delayed swap mechanism was fundamentally racy, and has been
1298 * removed. The model was that the client requested a delayed flip/swap
1299 * from the kernel, then waited for vblank before continuing to perform
1300 * rendering. The problem was that the kernel might wake the client
1301 * up before it dispatched the vblank swap (since the lock has to be
1302 * held while touching the ringbuffer), in which case the client would
1303 * clear and start the next frame before the swap occurred, and
1304 * flicker would occur in addition to likely missing the vblank.
1305 *
1306 * In the absence of this ioctl, userland falls back to a correct path
1307 * of waiting for a vblank, then dispatching the swap on its own.
1308 * Context switching to userland and back is plenty fast enough for
1309 * meeting the requirements of vblank swapping.
1310 */
1311 return -EINVAL;
1312 }
1313
1314 static u32
1315 ring_last_seqno(struct intel_ring_buffer *ring)
1316 {
1317 return list_entry(ring->request_list.prev,
1318 struct drm_i915_gem_request, list)->seqno;
1319 }
1320
1321 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1322 {
1323 if (list_empty(&ring->request_list) ||
1324 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1325 /* Issue a wake-up to catch stuck h/w. */
1326 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1327 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1328 ring->name,
1329 ring->waiting_seqno,
1330 ring->get_seqno(ring));
1331 wake_up_all(&ring->irq_queue);
1332 *err = true;
1333 }
1334 return true;
1335 }
1336 return false;
1337 }
1338
1339 /**
1340 * This is called when the chip hasn't reported back with completed
1341 * batchbuffers in a long time. The first time this is called we simply record
1342 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1343 * again, we assume the chip is wedged and try to fix it.
1344 */
1345 void i915_hangcheck_elapsed(unsigned long data)
1346 {
1347 struct drm_device *dev = (struct drm_device *)data;
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 uint32_t acthd, instdone, instdone1;
1350 bool err = false;
1351
1352 /* If all work is done then ACTHD clearly hasn't advanced. */
1353 if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) &&
1354 i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) &&
1355 i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) {
1356 dev_priv->hangcheck_count = 0;
1357 if (err)
1358 goto repeat;
1359 return;
1360 }
1361
1362 if (INTEL_INFO(dev)->gen < 4) {
1363 acthd = I915_READ(ACTHD);
1364 instdone = I915_READ(INSTDONE);
1365 instdone1 = 0;
1366 } else {
1367 acthd = I915_READ(ACTHD_I965);
1368 instdone = I915_READ(INSTDONE_I965);
1369 instdone1 = I915_READ(INSTDONE1);
1370 }
1371
1372 if (dev_priv->last_acthd == acthd &&
1373 dev_priv->last_instdone == instdone &&
1374 dev_priv->last_instdone1 == instdone1) {
1375 if (dev_priv->hangcheck_count++ > 1) {
1376 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1377
1378 if (!IS_GEN2(dev)) {
1379 /* Is the chip hanging on a WAIT_FOR_EVENT?
1380 * If so we can simply poke the RB_WAIT bit
1381 * and break the hang. This should work on
1382 * all but the second generation chipsets.
1383 */
1384 u32 tmp = I915_READ(PRB0_CTL);
1385 if (tmp & RING_WAIT) {
1386 I915_WRITE(PRB0_CTL, tmp);
1387 POSTING_READ(PRB0_CTL);
1388 goto repeat;
1389 }
1390 }
1391
1392 i915_handle_error(dev, true);
1393 return;
1394 }
1395 } else {
1396 dev_priv->hangcheck_count = 0;
1397
1398 dev_priv->last_acthd = acthd;
1399 dev_priv->last_instdone = instdone;
1400 dev_priv->last_instdone1 = instdone1;
1401 }
1402
1403 repeat:
1404 /* Reset timer case chip hangs without another request being added */
1405 mod_timer(&dev_priv->hangcheck_timer,
1406 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1407 }
1408
1409 /* drm_dma.h hooks
1410 */
1411 static void ironlake_irq_preinstall(struct drm_device *dev)
1412 {
1413 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1414
1415 I915_WRITE(HWSTAM, 0xeffe);
1416
1417 /* XXX hotplug from PCH */
1418
1419 I915_WRITE(DEIMR, 0xffffffff);
1420 I915_WRITE(DEIER, 0x0);
1421 (void) I915_READ(DEIER);
1422
1423 /* and GT */
1424 I915_WRITE(GTIMR, 0xffffffff);
1425 I915_WRITE(GTIER, 0x0);
1426 (void) I915_READ(GTIER);
1427
1428 /* south display irq */
1429 I915_WRITE(SDEIMR, 0xffffffff);
1430 I915_WRITE(SDEIER, 0x0);
1431 (void) I915_READ(SDEIER);
1432 }
1433
1434 static int ironlake_irq_postinstall(struct drm_device *dev)
1435 {
1436 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1437 /* enable kind of interrupts always enabled */
1438 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1439 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1440 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1441 u32 hotplug_mask;
1442
1443 dev_priv->irq_mask_reg = ~display_mask;
1444 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1445
1446 /* should always can generate irq */
1447 I915_WRITE(DEIIR, I915_READ(DEIIR));
1448 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1449 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1450 (void) I915_READ(DEIER);
1451
1452 if (IS_GEN6(dev)) {
1453 render_mask =
1454 GT_PIPE_NOTIFY |
1455 GT_GEN6_BSD_USER_INTERRUPT |
1456 GT_BLT_USER_INTERRUPT;
1457 }
1458
1459 dev_priv->gt_irq_mask_reg = ~render_mask;
1460 dev_priv->gt_irq_enable_reg = render_mask;
1461
1462 I915_WRITE(GTIIR, I915_READ(GTIIR));
1463 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1464 if (IS_GEN6(dev)) {
1465 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1466 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1467 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1468 }
1469
1470 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1471 (void) I915_READ(GTIER);
1472
1473 if (HAS_PCH_CPT(dev)) {
1474 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
1475 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1476 } else {
1477 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1478 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1479 }
1480
1481 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1482 dev_priv->pch_irq_enable_reg = hotplug_mask;
1483
1484 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1485 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1486 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1487 (void) I915_READ(SDEIER);
1488
1489 if (IS_IRONLAKE_M(dev)) {
1490 /* Clear & enable PCU event interrupts */
1491 I915_WRITE(DEIIR, DE_PCU_EVENT);
1492 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1493 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1494 }
1495
1496 return 0;
1497 }
1498
1499 void i915_driver_irq_preinstall(struct drm_device * dev)
1500 {
1501 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1502
1503 atomic_set(&dev_priv->irq_received, 0);
1504
1505 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1506 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1507
1508 if (HAS_PCH_SPLIT(dev)) {
1509 ironlake_irq_preinstall(dev);
1510 return;
1511 }
1512
1513 if (I915_HAS_HOTPLUG(dev)) {
1514 I915_WRITE(PORT_HOTPLUG_EN, 0);
1515 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1516 }
1517
1518 I915_WRITE(HWSTAM, 0xeffe);
1519 I915_WRITE(PIPEASTAT, 0);
1520 I915_WRITE(PIPEBSTAT, 0);
1521 I915_WRITE(IMR, 0xffffffff);
1522 I915_WRITE(IER, 0x0);
1523 (void) I915_READ(IER);
1524 }
1525
1526 /*
1527 * Must be called after intel_modeset_init or hotplug interrupts won't be
1528 * enabled correctly.
1529 */
1530 int i915_driver_irq_postinstall(struct drm_device *dev)
1531 {
1532 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1533 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1534 u32 error_mask;
1535
1536 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1537 if (HAS_BSD(dev))
1538 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1539 if (HAS_BLT(dev))
1540 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1541
1542 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1543
1544 if (HAS_PCH_SPLIT(dev))
1545 return ironlake_irq_postinstall(dev);
1546
1547 /* Unmask the interrupts that we always want on. */
1548 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1549
1550 dev_priv->pipestat[0] = 0;
1551 dev_priv->pipestat[1] = 0;
1552
1553 if (I915_HAS_HOTPLUG(dev)) {
1554 /* Enable in IER... */
1555 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1556 /* and unmask in IMR */
1557 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1558 }
1559
1560 /*
1561 * Enable some error detection, note the instruction error mask
1562 * bit is reserved, so we leave it masked.
1563 */
1564 if (IS_G4X(dev)) {
1565 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1566 GM45_ERROR_MEM_PRIV |
1567 GM45_ERROR_CP_PRIV |
1568 I915_ERROR_MEMORY_REFRESH);
1569 } else {
1570 error_mask = ~(I915_ERROR_PAGE_TABLE |
1571 I915_ERROR_MEMORY_REFRESH);
1572 }
1573 I915_WRITE(EMR, error_mask);
1574
1575 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1576 I915_WRITE(IER, enable_mask);
1577 (void) I915_READ(IER);
1578
1579 if (I915_HAS_HOTPLUG(dev)) {
1580 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1581
1582 /* Note HDMI and DP share bits */
1583 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1584 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1585 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1586 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1587 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1588 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1589 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1590 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1591 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1592 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1593 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1594 hotplug_en |= CRT_HOTPLUG_INT_EN;
1595
1596 /* Programming the CRT detection parameters tends
1597 to generate a spurious hotplug event about three
1598 seconds later. So just do it once.
1599 */
1600 if (IS_G4X(dev))
1601 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1602 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1603 }
1604
1605 /* Ignore TV since it's buggy */
1606
1607 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1608 }
1609
1610 intel_opregion_enable_asle(dev);
1611
1612 return 0;
1613 }
1614
1615 static void ironlake_irq_uninstall(struct drm_device *dev)
1616 {
1617 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1618 I915_WRITE(HWSTAM, 0xffffffff);
1619
1620 I915_WRITE(DEIMR, 0xffffffff);
1621 I915_WRITE(DEIER, 0x0);
1622 I915_WRITE(DEIIR, I915_READ(DEIIR));
1623
1624 I915_WRITE(GTIMR, 0xffffffff);
1625 I915_WRITE(GTIER, 0x0);
1626 I915_WRITE(GTIIR, I915_READ(GTIIR));
1627 }
1628
1629 void i915_driver_irq_uninstall(struct drm_device * dev)
1630 {
1631 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1632
1633 if (!dev_priv)
1634 return;
1635
1636 dev_priv->vblank_pipe = 0;
1637
1638 if (HAS_PCH_SPLIT(dev)) {
1639 ironlake_irq_uninstall(dev);
1640 return;
1641 }
1642
1643 if (I915_HAS_HOTPLUG(dev)) {
1644 I915_WRITE(PORT_HOTPLUG_EN, 0);
1645 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1646 }
1647
1648 I915_WRITE(HWSTAM, 0xffffffff);
1649 I915_WRITE(PIPEASTAT, 0);
1650 I915_WRITE(PIPEBSTAT, 0);
1651 I915_WRITE(IMR, 0xffffffff);
1652 I915_WRITE(IER, 0x0);
1653
1654 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1655 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1656 I915_WRITE(IIR, I915_READ(IIR));
1657 }
Linux kernel - Deliverables
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