2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
31 #define GEN_DEFAULT_PIPEOFFSETS \
32 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
33 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
34 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
35 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
36 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
38 #define GEN_CHV_PIPEOFFSETS \
39 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
40 CHV_PIPE_C_OFFSET }, \
41 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
42 CHV_TRANSCODER_C_OFFSET, }, \
43 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
44 CHV_PALETTE_C_OFFSET }
46 #define CURSOR_OFFSETS \
47 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
49 #define IVB_CURSOR_OFFSETS \
50 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
53 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
55 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
57 static const struct intel_device_info intel_i830_info
= {
58 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
59 .has_overlay
= 1, .overlay_needs_physical
= 1,
60 .ring_mask
= RENDER_RING
,
61 GEN_DEFAULT_PIPEOFFSETS
,
65 static const struct intel_device_info intel_845g_info
= {
66 .gen
= 2, .num_pipes
= 1,
67 .has_overlay
= 1, .overlay_needs_physical
= 1,
68 .ring_mask
= RENDER_RING
,
69 GEN_DEFAULT_PIPEOFFSETS
,
73 static const struct intel_device_info intel_i85x_info
= {
74 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
75 .cursor_needs_physical
= 1,
76 .has_overlay
= 1, .overlay_needs_physical
= 1,
78 .ring_mask
= RENDER_RING
,
79 GEN_DEFAULT_PIPEOFFSETS
,
83 static const struct intel_device_info intel_i865g_info
= {
84 .gen
= 2, .num_pipes
= 1,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
86 .ring_mask
= RENDER_RING
,
87 GEN_DEFAULT_PIPEOFFSETS
,
91 static const struct intel_device_info intel_i915g_info
= {
92 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
93 .has_overlay
= 1, .overlay_needs_physical
= 1,
94 .ring_mask
= RENDER_RING
,
95 GEN_DEFAULT_PIPEOFFSETS
,
98 static const struct intel_device_info intel_i915gm_info
= {
99 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
100 .cursor_needs_physical
= 1,
101 .has_overlay
= 1, .overlay_needs_physical
= 1,
104 .ring_mask
= RENDER_RING
,
105 GEN_DEFAULT_PIPEOFFSETS
,
108 static const struct intel_device_info intel_i945g_info
= {
109 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
110 .has_overlay
= 1, .overlay_needs_physical
= 1,
111 .ring_mask
= RENDER_RING
,
112 GEN_DEFAULT_PIPEOFFSETS
,
115 static const struct intel_device_info intel_i945gm_info
= {
116 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
117 .has_hotplug
= 1, .cursor_needs_physical
= 1,
118 .has_overlay
= 1, .overlay_needs_physical
= 1,
121 .ring_mask
= RENDER_RING
,
122 GEN_DEFAULT_PIPEOFFSETS
,
126 static const struct intel_device_info intel_i965g_info
= {
127 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
130 .ring_mask
= RENDER_RING
,
131 GEN_DEFAULT_PIPEOFFSETS
,
135 static const struct intel_device_info intel_i965gm_info
= {
136 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
137 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
140 .ring_mask
= RENDER_RING
,
141 GEN_DEFAULT_PIPEOFFSETS
,
145 static const struct intel_device_info intel_g33_info
= {
146 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
147 .need_gfx_hws
= 1, .has_hotplug
= 1,
149 .ring_mask
= RENDER_RING
,
150 GEN_DEFAULT_PIPEOFFSETS
,
154 static const struct intel_device_info intel_g45_info
= {
155 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
156 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
157 .ring_mask
= RENDER_RING
| BSD_RING
,
158 GEN_DEFAULT_PIPEOFFSETS
,
162 static const struct intel_device_info intel_gm45_info
= {
163 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
164 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
165 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
167 .ring_mask
= RENDER_RING
| BSD_RING
,
168 GEN_DEFAULT_PIPEOFFSETS
,
172 static const struct intel_device_info intel_pineview_info
= {
173 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
174 .need_gfx_hws
= 1, .has_hotplug
= 1,
176 GEN_DEFAULT_PIPEOFFSETS
,
180 static const struct intel_device_info intel_ironlake_d_info
= {
181 .gen
= 5, .num_pipes
= 2,
182 .need_gfx_hws
= 1, .has_hotplug
= 1,
183 .ring_mask
= RENDER_RING
| BSD_RING
,
184 GEN_DEFAULT_PIPEOFFSETS
,
188 static const struct intel_device_info intel_ironlake_m_info
= {
189 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
190 .need_gfx_hws
= 1, .has_hotplug
= 1,
192 .ring_mask
= RENDER_RING
| BSD_RING
,
193 GEN_DEFAULT_PIPEOFFSETS
,
197 static const struct intel_device_info intel_sandybridge_d_info
= {
198 .gen
= 6, .num_pipes
= 2,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
203 GEN_DEFAULT_PIPEOFFSETS
,
207 static const struct intel_device_info intel_sandybridge_m_info
= {
208 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
209 .need_gfx_hws
= 1, .has_hotplug
= 1,
211 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
213 GEN_DEFAULT_PIPEOFFSETS
,
217 #define GEN7_FEATURES \
218 .gen = 7, .num_pipes = 3, \
219 .need_gfx_hws = 1, .has_hotplug = 1, \
221 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
223 GEN_DEFAULT_PIPEOFFSETS, \
226 static const struct intel_device_info intel_ivybridge_d_info
= {
231 static const struct intel_device_info intel_ivybridge_m_info
= {
237 static const struct intel_device_info intel_ivybridge_q_info
= {
240 .num_pipes
= 0, /* legal, last one wins */
243 #define VLV_FEATURES \
244 .gen = 7, .num_pipes = 2, \
245 .need_gfx_hws = 1, .has_hotplug = 1, \
246 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
247 .display_mmio_offset = VLV_DISPLAY_BASE, \
248 GEN_DEFAULT_PIPEOFFSETS, \
251 static const struct intel_device_info intel_valleyview_m_info
= {
257 static const struct intel_device_info intel_valleyview_d_info
= {
262 #define HSW_FEATURES \
264 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
268 static const struct intel_device_info intel_haswell_d_info
= {
273 static const struct intel_device_info intel_haswell_m_info
= {
279 #define BDW_FEATURES \
283 static const struct intel_device_info intel_broadwell_d_info
= {
289 static const struct intel_device_info intel_broadwell_m_info
= {
291 .gen
= 8, .is_mobile
= 1,
295 static const struct intel_device_info intel_broadwell_gt3d_info
= {
299 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
302 static const struct intel_device_info intel_broadwell_gt3m_info
= {
304 .gen
= 8, .is_mobile
= 1,
306 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
309 static const struct intel_device_info intel_cherryview_info
= {
310 .gen
= 8, .num_pipes
= 3,
311 .need_gfx_hws
= 1, .has_hotplug
= 1,
312 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
314 .display_mmio_offset
= VLV_DISPLAY_BASE
,
320 static const struct intel_device_info intel_skylake_info
= {
326 static const struct intel_device_info intel_skylake_gt3_info
= {
330 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
333 static const struct intel_device_info intel_broxton_info
= {
336 .need_gfx_hws
= 1, .has_hotplug
= 1,
337 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
343 GEN_DEFAULT_PIPEOFFSETS
,
348 static const struct intel_device_info intel_kabylake_info
= {
354 static const struct intel_device_info intel_kabylake_gt3_info
= {
358 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
362 * Make sure any device matches here are from most specific to most
363 * general. For example, since the Quanta match is based on the subsystem
364 * and subvendor IDs, we need it to come before the more general IVB
365 * PCI ID matches, otherwise we'll use the wrong info struct above.
367 static const struct pci_device_id pciidlist
[] = {
368 INTEL_I830_IDS(&intel_i830_info
),
369 INTEL_I845G_IDS(&intel_845g_info
),
370 INTEL_I85X_IDS(&intel_i85x_info
),
371 INTEL_I865G_IDS(&intel_i865g_info
),
372 INTEL_I915G_IDS(&intel_i915g_info
),
373 INTEL_I915GM_IDS(&intel_i915gm_info
),
374 INTEL_I945G_IDS(&intel_i945g_info
),
375 INTEL_I945GM_IDS(&intel_i945gm_info
),
376 INTEL_I965G_IDS(&intel_i965g_info
),
377 INTEL_G33_IDS(&intel_g33_info
),
378 INTEL_I965GM_IDS(&intel_i965gm_info
),
379 INTEL_GM45_IDS(&intel_gm45_info
),
380 INTEL_G45_IDS(&intel_g45_info
),
381 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
382 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
383 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
384 INTEL_SNB_D_IDS(&intel_sandybridge_d_info
),
385 INTEL_SNB_M_IDS(&intel_sandybridge_m_info
),
386 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
387 INTEL_IVB_M_IDS(&intel_ivybridge_m_info
),
388 INTEL_IVB_D_IDS(&intel_ivybridge_d_info
),
389 INTEL_HSW_D_IDS(&intel_haswell_d_info
),
390 INTEL_HSW_M_IDS(&intel_haswell_m_info
),
391 INTEL_VLV_M_IDS(&intel_valleyview_m_info
),
392 INTEL_VLV_D_IDS(&intel_valleyview_d_info
),
393 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info
),
394 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info
),
395 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info
),
396 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info
),
397 INTEL_CHV_IDS(&intel_cherryview_info
),
398 INTEL_SKL_GT1_IDS(&intel_skylake_info
),
399 INTEL_SKL_GT2_IDS(&intel_skylake_info
),
400 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
401 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info
),
402 INTEL_BXT_IDS(&intel_broxton_info
),
403 INTEL_KBL_GT1_IDS(&intel_kabylake_info
),
404 INTEL_KBL_GT2_IDS(&intel_kabylake_info
),
405 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
406 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
409 MODULE_DEVICE_TABLE(pci
, pciidlist
);
411 extern int i915_driver_load(struct pci_dev
*pdev
,
412 const struct pci_device_id
*ent
);
414 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
416 struct intel_device_info
*intel_info
=
417 (struct intel_device_info
*) ent
->driver_data
;
419 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
420 DRM_INFO("This hardware requires preliminary hardware support.\n"
421 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
425 /* Only bind to function 0 of the device. Early generations
426 * used function 1 as a placeholder for multi-head. This causes
427 * us confusion instead, especially on the systems where both
428 * functions have the same PCI-ID!
430 if (PCI_FUNC(pdev
->devfn
))
434 * apple-gmux is needed on dual GPU MacBook Pro
435 * to probe the panel if we're the inactive GPU.
437 if (vga_switcheroo_client_probe_defer(pdev
))
438 return -EPROBE_DEFER
;
440 return i915_driver_load(pdev
, ent
);
443 extern void i915_driver_unload(struct drm_device
*dev
);
445 static void i915_pci_remove(struct pci_dev
*pdev
)
447 struct drm_device
*dev
= pci_get_drvdata(pdev
);
449 i915_driver_unload(dev
);
453 extern const struct dev_pm_ops i915_pm_ops
;
455 static struct pci_driver i915_pci_driver
= {
457 .id_table
= pciidlist
,
458 .probe
= i915_pci_probe
,
459 .remove
= i915_pci_remove
,
460 .driver
.pm
= &i915_pm_ops
,
463 static int __init
i915_init(void)
468 * Enable KMS by default, unless explicitly overriden by
469 * either the i915.modeset prarameter or by the
470 * vga_text_mode_force boot option.
473 if (i915
.modeset
== 0)
476 if (vgacon_text_force() && i915
.modeset
== -1)
480 /* Silently fail loading to not upset userspace. */
481 DRM_DEBUG_DRIVER("KMS disabled.\n");
485 return pci_register_driver(&i915_pci_driver
);
488 static void __exit
i915_exit(void)
490 if (!i915_pci_driver
.driver
.owner
)
493 pci_unregister_driver(&i915_pci_driver
);
496 module_init(i915_init
);
497 module_exit(i915_exit
);
499 MODULE_AUTHOR("Tungsten Graphics, Inc.");
500 MODULE_AUTHOR("Intel Corporation");
502 MODULE_DESCRIPTION(DRIVER_DESC
);
503 MODULE_LICENSE("GPL and additional rights");