1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
33 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
36 /* PCI config space */
38 #define HPLLCC 0xc0 /* 855 only */
39 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
40 #define GC_CLOCK_133_200 (0 << 0)
41 #define GC_CLOCK_100_200 (1 << 0)
42 #define GC_CLOCK_100_133 (2 << 0)
43 #define GC_CLOCK_166_250 (3 << 0)
45 #define GCFGC 0xf0 /* 915+ only */
46 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
47 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
48 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
49 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
50 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
51 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
52 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
53 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
54 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
55 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
56 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
57 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
58 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
59 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
60 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
61 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
62 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
63 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
64 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
65 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
66 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
67 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
68 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
69 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
70 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
71 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
72 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
73 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
74 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
75 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
78 /* Graphics reset regs */
79 #define I965_GDRST 0xc0 /* PCI config register */
80 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
81 #define GRDOM_FULL (0<<2)
82 #define GRDOM_RENDER (1<<2)
83 #define GRDOM_MEDIA (3<<2)
84 #define GRDOM_MASK (3<<2)
85 #define GRDOM_RESET_ENABLE (1<<0)
87 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
88 #define GEN6_MBC_SNPCR_SHIFT 21
89 #define GEN6_MBC_SNPCR_MASK (3<<21)
90 #define GEN6_MBC_SNPCR_MAX (0<<21)
91 #define GEN6_MBC_SNPCR_MED (1<<21)
92 #define GEN6_MBC_SNPCR_LOW (2<<21)
93 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
95 #define GEN6_MBCTL 0x0907c
96 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
97 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
98 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
99 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
100 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
102 #define GEN6_GDRST 0x941c
103 #define GEN6_GRDOM_FULL (1 << 0)
104 #define GEN6_GRDOM_RENDER (1 << 1)
105 #define GEN6_GRDOM_MEDIA (1 << 2)
106 #define GEN6_GRDOM_BLT (1 << 3)
108 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
109 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
110 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
111 #define PP_DIR_DCLV_2G 0xffffffff
113 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
114 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
116 #define GAM_ECOCHK 0x4090
117 #define ECOCHK_SNB_BIT (1<<10)
118 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
119 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
120 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
121 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
122 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
123 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
124 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
125 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
127 #define GAC_ECO_BITS 0x14090
128 #define ECOBITS_SNB_BIT (1<<13)
129 #define ECOBITS_PPGTT_CACHE64B (3<<8)
130 #define ECOBITS_PPGTT_CACHE4B (0<<8)
132 #define GAB_CTL 0x24000
133 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
137 #define VGA_ST01_MDA 0x3ba
138 #define VGA_ST01_CGA 0x3da
140 #define VGA_MSR_WRITE 0x3c2
141 #define VGA_MSR_READ 0x3cc
142 #define VGA_MSR_MEM_EN (1<<1)
143 #define VGA_MSR_CGA_MODE (1<<0)
145 #define VGA_SR_INDEX 0x3c4
147 #define VGA_SR_DATA 0x3c5
149 #define VGA_AR_INDEX 0x3c0
150 #define VGA_AR_VID_EN (1<<5)
151 #define VGA_AR_DATA_WRITE 0x3c0
152 #define VGA_AR_DATA_READ 0x3c1
154 #define VGA_GR_INDEX 0x3ce
155 #define VGA_GR_DATA 0x3cf
157 #define VGA_GR_MEM_READ_MODE_SHIFT 3
158 #define VGA_GR_MEM_READ_MODE_PLANE 1
160 #define VGA_GR_MEM_MODE_MASK 0xc
161 #define VGA_GR_MEM_MODE_SHIFT 2
162 #define VGA_GR_MEM_A0000_AFFFF 0
163 #define VGA_GR_MEM_A0000_BFFFF 1
164 #define VGA_GR_MEM_B0000_B7FFF 2
165 #define VGA_GR_MEM_B0000_BFFFF 3
167 #define VGA_DACMASK 0x3c6
168 #define VGA_DACRX 0x3c7
169 #define VGA_DACWX 0x3c8
170 #define VGA_DACDATA 0x3c9
172 #define VGA_CR_INDEX_MDA 0x3b4
173 #define VGA_CR_DATA_MDA 0x3b5
174 #define VGA_CR_INDEX_CGA 0x3d4
175 #define VGA_CR_DATA_CGA 0x3d5
178 * Instruction field definitions used by the command parser
180 #define INSTR_CLIENT_SHIFT 29
181 #define INSTR_CLIENT_MASK 0xE0000000
182 #define INSTR_MI_CLIENT 0x0
183 #define INSTR_BC_CLIENT 0x2
184 #define INSTR_RC_CLIENT 0x3
185 #define INSTR_SUBCLIENT_SHIFT 27
186 #define INSTR_SUBCLIENT_MASK 0x18000000
187 #define INSTR_MEDIA_SUBCLIENT 0x2
190 * Memory interface instructions used by the kernel
192 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
194 #define MI_NOOP MI_INSTR(0, 0)
195 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
196 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
197 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
198 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
199 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
200 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
201 #define MI_FLUSH MI_INSTR(0x04, 0)
202 #define MI_READ_FLUSH (1 << 0)
203 #define MI_EXE_FLUSH (1 << 1)
204 #define MI_NO_WRITE_FLUSH (1 << 2)
205 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
206 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
207 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
208 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
209 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
210 #define MI_ARB_ENABLE (1<<0)
211 #define MI_ARB_DISABLE (0<<0)
212 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
213 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
214 #define MI_SUSPEND_FLUSH_EN (1<<0)
215 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
216 #define MI_OVERLAY_CONTINUE (0x0<<21)
217 #define MI_OVERLAY_ON (0x1<<21)
218 #define MI_OVERLAY_OFF (0x2<<21)
219 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
220 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
221 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
222 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
223 /* IVB has funny definitions for which plane to flip. */
224 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
225 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
226 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
227 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
228 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
229 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
230 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
231 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
232 #define MI_SEMAPHORE_UPDATE (1<<21)
233 #define MI_SEMAPHORE_COMPARE (1<<20)
234 #define MI_SEMAPHORE_REGISTER (1<<18)
235 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
236 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
237 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
238 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
239 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
240 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
241 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
242 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
243 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
244 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
245 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
246 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
247 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
248 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
249 #define MI_MM_SPACE_GTT (1<<8)
250 #define MI_MM_SPACE_PHYSICAL (0<<8)
251 #define MI_SAVE_EXT_STATE_EN (1<<3)
252 #define MI_RESTORE_EXT_STATE_EN (1<<2)
253 #define MI_FORCE_RESTORE (1<<1)
254 #define MI_RESTORE_INHIBIT (1<<0)
255 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
256 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
257 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
258 #define MI_STORE_DWORD_INDEX_SHIFT 2
259 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
260 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
261 * simply ignores the register load under certain conditions.
262 * - One can actually load arbitrary many arbitrary registers: Simply issue x
263 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
265 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
266 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
267 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
268 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
269 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
270 #define MI_INVALIDATE_TLB (1<<18)
271 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
272 #define MI_INVALIDATE_BSD (1<<7)
273 #define MI_FLUSH_DW_USE_GTT (1<<2)
274 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
275 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
276 #define MI_BATCH_NON_SECURE (1)
277 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
278 #define MI_BATCH_NON_SECURE_I965 (1<<8)
279 #define MI_BATCH_PPGTT_HSW (1<<8)
280 #define MI_BATCH_NON_SECURE_HSW (1<<13)
281 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
282 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
283 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
286 #define MI_PREDICATE_RESULT_2 (0x2214)
287 #define LOWER_SLICE_ENABLED (1<<0)
288 #define LOWER_SLICE_DISABLED (0<<0)
291 * 3D instructions used by the kernel
293 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
295 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
296 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
297 #define SC_UPDATE_SCISSOR (0x1<<1)
298 #define SC_ENABLE_MASK (0x1<<0)
299 #define SC_ENABLE (0x1<<0)
300 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
301 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
302 #define SCI_YMIN_MASK (0xffff<<16)
303 #define SCI_XMIN_MASK (0xffff<<0)
304 #define SCI_YMAX_MASK (0xffff<<16)
305 #define SCI_XMAX_MASK (0xffff<<0)
306 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
307 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
308 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
309 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
310 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
311 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
312 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
313 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
314 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
315 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
316 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
317 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
318 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
319 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
320 #define BLT_DEPTH_8 (0<<24)
321 #define BLT_DEPTH_16_565 (1<<24)
322 #define BLT_DEPTH_16_1555 (2<<24)
323 #define BLT_DEPTH_32 (3<<24)
324 #define BLT_ROP_GXCOPY (0xcc<<16)
325 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
326 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
327 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
328 #define ASYNC_FLIP (1<<22)
329 #define DISPLAY_PLANE_A (0<<20)
330 #define DISPLAY_PLANE_B (1<<20)
331 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
332 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
333 #define PIPE_CONTROL_CS_STALL (1<<20)
334 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
335 #define PIPE_CONTROL_QW_WRITE (1<<14)
336 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
337 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
338 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
339 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
340 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
341 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
342 #define PIPE_CONTROL_NOTIFY (1<<8)
343 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
344 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
345 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
346 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
347 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
348 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
354 #define DEBUG_RESET_I830 0x6070
355 #define DEBUG_RESET_FULL (1<<7)
356 #define DEBUG_RESET_RENDER (1<<8)
357 #define DEBUG_RESET_DISPLAY (1<<9)
362 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
363 #define IOSF_DEVFN_SHIFT 24
364 #define IOSF_OPCODE_SHIFT 16
365 #define IOSF_PORT_SHIFT 8
366 #define IOSF_BYTE_ENABLES_SHIFT 4
367 #define IOSF_BAR_SHIFT 1
368 #define IOSF_SB_BUSY (1<<0)
369 #define IOSF_PORT_BUNIT 0x3
370 #define IOSF_PORT_PUNIT 0x4
371 #define IOSF_PORT_NC 0x11
372 #define IOSF_PORT_DPIO 0x12
373 #define IOSF_PORT_GPIO_NC 0x13
374 #define IOSF_PORT_CCK 0x14
375 #define IOSF_PORT_CCU 0xA9
376 #define IOSF_PORT_GPS_CORE 0x48
377 #define IOSF_PORT_FLISDSI 0x1B
378 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
379 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
381 /* See configdb bunit SB addr map */
382 #define BUNIT_REG_BISOC 0x11
384 #define PUNIT_OPCODE_REG_READ 6
385 #define PUNIT_OPCODE_REG_WRITE 7
387 #define PUNIT_REG_DSPFREQ 0x36
388 #define DSPFREQSTAT_SHIFT 30
389 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
390 #define DSPFREQGUAR_SHIFT 14
391 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
393 /* See the PUNIT HAS v0.8 for the below bits */
394 enum punit_power_well
{
395 PUNIT_POWER_WELL_RENDER
= 0,
396 PUNIT_POWER_WELL_MEDIA
= 1,
397 PUNIT_POWER_WELL_DISP2D
= 3,
398 PUNIT_POWER_WELL_DPIO_CMN_BC
= 5,
399 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
= 6,
400 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
= 7,
401 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
= 8,
402 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
= 9,
403 PUNIT_POWER_WELL_DPIO_RX0
= 10,
404 PUNIT_POWER_WELL_DPIO_RX1
= 11,
406 PUNIT_POWER_WELL_NUM
,
409 #define PUNIT_REG_PWRGT_CTRL 0x60
410 #define PUNIT_REG_PWRGT_STATUS 0x61
411 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
412 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
413 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
414 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
415 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
417 #define PUNIT_REG_GPU_LFM 0xd3
418 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
419 #define PUNIT_REG_GPU_FREQ_STS 0xd8
420 #define GENFREQSTATUS (1<<0)
421 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
423 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
424 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
426 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
427 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
428 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
429 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
430 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
431 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
432 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
433 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
434 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
435 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
437 /* vlv2 north clock has */
438 #define CCK_FUSE_REG 0x8
439 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
440 #define CCK_REG_DSI_PLL_FUSE 0x44
441 #define CCK_REG_DSI_PLL_CONTROL 0x48
442 #define DSI_PLL_VCO_EN (1 << 31)
443 #define DSI_PLL_LDO_GATE (1 << 30)
444 #define DSI_PLL_P1_POST_DIV_SHIFT 17
445 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
446 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
447 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
448 #define DSI_PLL_MUX_MASK (3 << 9)
449 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
450 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
451 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
452 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
453 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
454 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
455 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
456 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
457 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
458 #define DSI_PLL_LOCK (1 << 0)
459 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
460 #define DSI_PLL_LFSR (1 << 31)
461 #define DSI_PLL_FRACTION_EN (1 << 30)
462 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
463 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
464 #define DSI_PLL_USYNC_CNT_SHIFT 18
465 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
466 #define DSI_PLL_N1_DIV_SHIFT 16
467 #define DSI_PLL_N1_DIV_MASK (3 << 16)
468 #define DSI_PLL_M1_DIV_SHIFT 0
469 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
470 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
473 * DPIO - a special bus for various display related registers to hide behind
477 * Note: digital port B is DDI0, digital pot C is DDI1
480 #define DPIO_OPCODE_REG_WRITE 1
481 #define DPIO_OPCODE_REG_READ 0
483 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
484 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
485 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
486 #define DPIO_SFR_BYPASS (1<<1)
487 #define DPIO_CMNRST (1<<0)
489 #define DPIO_PHY(pipe) ((pipe) >> 1)
490 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
493 * Per pipe/PLL DPIO regs
495 #define _VLV_PLL_DW3_CH0 0x800c
496 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
497 #define DPIO_POST_DIV_DAC 0
498 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
499 #define DPIO_POST_DIV_LVDS1 2
500 #define DPIO_POST_DIV_LVDS2 3
501 #define DPIO_K_SHIFT (24) /* 4 bits */
502 #define DPIO_P1_SHIFT (21) /* 3 bits */
503 #define DPIO_P2_SHIFT (16) /* 5 bits */
504 #define DPIO_N_SHIFT (12) /* 4 bits */
505 #define DPIO_ENABLE_CALIBRATION (1<<11)
506 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
507 #define DPIO_M2DIV_MASK 0xff
508 #define _VLV_PLL_DW3_CH1 0x802c
509 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
511 #define _VLV_PLL_DW5_CH0 0x8014
512 #define DPIO_REFSEL_OVERRIDE 27
513 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
514 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
515 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
516 #define DPIO_PLL_REFCLK_SEL_MASK 3
517 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
518 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
519 #define _VLV_PLL_DW5_CH1 0x8034
520 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
522 #define _VLV_PLL_DW7_CH0 0x801c
523 #define _VLV_PLL_DW7_CH1 0x803c
524 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
526 #define _VLV_PLL_DW8_CH0 0x8040
527 #define _VLV_PLL_DW8_CH1 0x8060
528 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
530 #define VLV_PLL_DW9_BCAST 0xc044
531 #define _VLV_PLL_DW9_CH0 0x8044
532 #define _VLV_PLL_DW9_CH1 0x8064
533 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
535 #define _VLV_PLL_DW10_CH0 0x8048
536 #define _VLV_PLL_DW10_CH1 0x8068
537 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
539 #define _VLV_PLL_DW11_CH0 0x804c
540 #define _VLV_PLL_DW11_CH1 0x806c
541 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
543 /* Spec for ref block start counts at DW10 */
544 #define VLV_REF_DW13 0x80ac
546 #define VLV_CMN_DW0 0x8100
549 * Per DDI channel DPIO regs
552 #define _VLV_PCS_DW0_CH0 0x8200
553 #define _VLV_PCS_DW0_CH1 0x8400
554 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
555 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
556 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
558 #define _VLV_PCS_DW1_CH0 0x8204
559 #define _VLV_PCS_DW1_CH1 0x8404
560 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
561 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
562 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
563 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
564 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
566 #define _VLV_PCS_DW8_CH0 0x8220
567 #define _VLV_PCS_DW8_CH1 0x8420
568 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
570 #define _VLV_PCS01_DW8_CH0 0x0220
571 #define _VLV_PCS23_DW8_CH0 0x0420
572 #define _VLV_PCS01_DW8_CH1 0x2620
573 #define _VLV_PCS23_DW8_CH1 0x2820
574 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
575 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
577 #define _VLV_PCS_DW9_CH0 0x8224
578 #define _VLV_PCS_DW9_CH1 0x8424
579 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
581 #define _VLV_PCS_DW11_CH0 0x822c
582 #define _VLV_PCS_DW11_CH1 0x842c
583 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
585 #define _VLV_PCS_DW12_CH0 0x8230
586 #define _VLV_PCS_DW12_CH1 0x8430
587 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
589 #define _VLV_PCS_DW14_CH0 0x8238
590 #define _VLV_PCS_DW14_CH1 0x8438
591 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
593 #define _VLV_PCS_DW23_CH0 0x825c
594 #define _VLV_PCS_DW23_CH1 0x845c
595 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
597 #define _VLV_TX_DW2_CH0 0x8288
598 #define _VLV_TX_DW2_CH1 0x8488
599 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
601 #define _VLV_TX_DW3_CH0 0x828c
602 #define _VLV_TX_DW3_CH1 0x848c
603 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
605 #define _VLV_TX_DW4_CH0 0x8290
606 #define _VLV_TX_DW4_CH1 0x8490
607 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
609 #define _VLV_TX3_DW4_CH0 0x690
610 #define _VLV_TX3_DW4_CH1 0x2a90
611 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
613 #define _VLV_TX_DW5_CH0 0x8294
614 #define _VLV_TX_DW5_CH1 0x8494
615 #define DPIO_TX_OCALINIT_EN (1<<31)
616 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
618 #define _VLV_TX_DW11_CH0 0x82ac
619 #define _VLV_TX_DW11_CH1 0x84ac
620 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
622 #define _VLV_TX_DW14_CH0 0x82b8
623 #define _VLV_TX_DW14_CH1 0x84b8
624 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
629 #define FENCE_REG_830_0 0x2000
630 #define FENCE_REG_945_8 0x3000
631 #define I830_FENCE_START_MASK 0x07f80000
632 #define I830_FENCE_TILING_Y_SHIFT 12
633 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
634 #define I830_FENCE_PITCH_SHIFT 4
635 #define I830_FENCE_REG_VALID (1<<0)
636 #define I915_FENCE_MAX_PITCH_VAL 4
637 #define I830_FENCE_MAX_PITCH_VAL 6
638 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
640 #define I915_FENCE_START_MASK 0x0ff00000
641 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
643 #define FENCE_REG_965_0 0x03000
644 #define I965_FENCE_PITCH_SHIFT 2
645 #define I965_FENCE_TILING_Y_SHIFT 1
646 #define I965_FENCE_REG_VALID (1<<0)
647 #define I965_FENCE_MAX_PITCH_VAL 0x0400
649 #define FENCE_REG_SANDYBRIDGE_0 0x100000
650 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
651 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
653 /* control register for cpu gtt access */
654 #define TILECTL 0x101000
655 #define TILECTL_SWZCTL (1 << 0)
656 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
657 #define TILECTL_BACKSNOOP_DIS (1 << 3)
660 * Instruction and interrupt control regs
662 #define PGTBL_ER 0x02024
663 #define RENDER_RING_BASE 0x02000
664 #define BSD_RING_BASE 0x04000
665 #define GEN6_BSD_RING_BASE 0x12000
666 #define VEBOX_RING_BASE 0x1a000
667 #define BLT_RING_BASE 0x22000
668 #define RING_TAIL(base) ((base)+0x30)
669 #define RING_HEAD(base) ((base)+0x34)
670 #define RING_START(base) ((base)+0x38)
671 #define RING_CTL(base) ((base)+0x3c)
672 #define RING_SYNC_0(base) ((base)+0x40)
673 #define RING_SYNC_1(base) ((base)+0x44)
674 #define RING_SYNC_2(base) ((base)+0x48)
675 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
676 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
677 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
678 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
679 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
680 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
681 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
682 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
683 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
684 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
685 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
686 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
687 #define GEN6_NOSYNC 0
688 #define RING_MAX_IDLE(base) ((base)+0x54)
689 #define RING_HWS_PGA(base) ((base)+0x80)
690 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
691 #define ARB_MODE 0x04030
692 #define ARB_MODE_SWIZZLE_SNB (1<<4)
693 #define ARB_MODE_SWIZZLE_IVB (1<<5)
694 #define GAMTARBMODE 0x04a08
695 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
696 #define ARB_MODE_SWIZZLE_BDW (1<<1)
697 #define RENDER_HWS_PGA_GEN7 (0x04080)
698 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
699 #define RING_FAULT_GTTSEL_MASK (1<<11)
700 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
701 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
702 #define RING_FAULT_VALID (1<<0)
703 #define DONE_REG 0x40b0
704 #define GEN8_PRIVATE_PAT 0x40e0
705 #define BSD_HWS_PGA_GEN7 (0x04180)
706 #define BLT_HWS_PGA_GEN7 (0x04280)
707 #define VEBOX_HWS_PGA_GEN7 (0x04380)
708 #define RING_ACTHD(base) ((base)+0x74)
709 #define RING_NOPID(base) ((base)+0x94)
710 #define RING_IMR(base) ((base)+0xa8)
711 #define RING_TIMESTAMP(base) ((base)+0x358)
712 #define TAIL_ADDR 0x001FFFF8
713 #define HEAD_WRAP_COUNT 0xFFE00000
714 #define HEAD_WRAP_ONE 0x00200000
715 #define HEAD_ADDR 0x001FFFFC
716 #define RING_NR_PAGES 0x001FF000
717 #define RING_REPORT_MASK 0x00000006
718 #define RING_REPORT_64K 0x00000002
719 #define RING_REPORT_128K 0x00000004
720 #define RING_NO_REPORT 0x00000000
721 #define RING_VALID_MASK 0x00000001
722 #define RING_VALID 0x00000001
723 #define RING_INVALID 0x00000000
724 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
725 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
726 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
728 #define PRB0_TAIL 0x02030
729 #define PRB0_HEAD 0x02034
730 #define PRB0_START 0x02038
731 #define PRB0_CTL 0x0203c
732 #define PRB1_TAIL 0x02040 /* 915+ only */
733 #define PRB1_HEAD 0x02044 /* 915+ only */
734 #define PRB1_START 0x02048 /* 915+ only */
735 #define PRB1_CTL 0x0204c /* 915+ only */
737 #define IPEIR_I965 0x02064
738 #define IPEHR_I965 0x02068
739 #define INSTDONE_I965 0x0206c
740 #define GEN7_INSTDONE_1 0x0206c
741 #define GEN7_SC_INSTDONE 0x07100
742 #define GEN7_SAMPLER_INSTDONE 0x0e160
743 #define GEN7_ROW_INSTDONE 0x0e164
744 #define I915_NUM_INSTDONE_REG 4
745 #define RING_IPEIR(base) ((base)+0x64)
746 #define RING_IPEHR(base) ((base)+0x68)
747 #define RING_INSTDONE(base) ((base)+0x6c)
748 #define RING_INSTPS(base) ((base)+0x70)
749 #define RING_DMA_FADD(base) ((base)+0x78)
750 #define RING_INSTPM(base) ((base)+0xc0)
751 #define INSTPS 0x02070 /* 965+ only */
752 #define INSTDONE1 0x0207c /* 965+ only */
753 #define ACTHD_I965 0x02074
754 #define HWS_PGA 0x02080
755 #define HWS_ADDRESS_MASK 0xfffff000
756 #define HWS_START_ADDRESS_SHIFT 4
757 #define PWRCTXA 0x2088 /* 965GM+ only */
758 #define PWRCTX_EN (1<<0)
759 #define IPEIR 0x02088
760 #define IPEHR 0x0208c
761 #define INSTDONE 0x02090
762 #define NOPID 0x02094
763 #define HWSTAM 0x02098
764 #define DMA_FADD_I8XX 0x020d0
765 #define RING_BBSTATE(base) ((base)+0x110)
766 #define RING_BBADDR(base) ((base)+0x140)
767 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
769 #define ERROR_GEN6 0x040a0
770 #define GEN7_ERR_INT 0x44040
771 #define ERR_INT_POISON (1<<31)
772 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
773 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
774 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
775 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
776 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
777 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
778 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
779 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
780 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
782 #define FPGA_DBG 0x42300
783 #define FPGA_DBG_RM_NOCLAIM (1<<31)
785 #define DERRMR 0x44050
786 /* Note that HBLANK events are reserved on bdw+ */
787 #define DERRMR_PIPEA_SCANLINE (1<<0)
788 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
789 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
790 #define DERRMR_PIPEA_VBLANK (1<<3)
791 #define DERRMR_PIPEA_HBLANK (1<<5)
792 #define DERRMR_PIPEB_SCANLINE (1<<8)
793 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
794 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
795 #define DERRMR_PIPEB_VBLANK (1<<11)
796 #define DERRMR_PIPEB_HBLANK (1<<13)
797 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
798 #define DERRMR_PIPEC_SCANLINE (1<<14)
799 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
800 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
801 #define DERRMR_PIPEC_VBLANK (1<<21)
802 #define DERRMR_PIPEC_HBLANK (1<<22)
805 /* GM45+ chicken bits -- debug workaround bits that may be required
806 * for various sorts of correct behavior. The top 16 bits of each are
807 * the enables for writing to the corresponding low bit.
809 #define _3D_CHICKEN 0x02084
810 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
811 #define _3D_CHICKEN2 0x0208c
812 /* Disables pipelining of read flushes past the SF-WIZ interface.
813 * Required on all Ironlake steppings according to the B-Spec, but the
814 * particular danger of not doing so is not specified.
816 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
817 #define _3D_CHICKEN3 0x02090
818 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
819 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
820 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
821 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
823 #define MI_MODE 0x0209c
824 # define VS_TIMER_DISPATCH (1 << 6)
825 # define MI_FLUSH_ENABLE (1 << 12)
826 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
828 #define GEN6_GT_MODE 0x20d0
829 #define GEN7_GT_MODE 0x7008
830 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
831 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
832 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
833 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
834 #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16)
835 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
837 #define GFX_MODE 0x02520
838 #define GFX_MODE_GEN7 0x0229c
839 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
840 #define GFX_RUN_LIST_ENABLE (1<<15)
841 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
842 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
843 #define GFX_REPLAY_MODE (1<<11)
844 #define GFX_PSMI_GRANULARITY (1<<10)
845 #define GFX_PPGTT_ENABLE (1<<9)
847 #define VLV_DISPLAY_BASE 0x180000
849 #define SCPD0 0x0209c /* 915+ only */
854 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
855 #define GCFG_DIS (1<<8)
856 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
857 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
858 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
859 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
860 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
861 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
862 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
866 #define GM45_ERROR_PAGE_TABLE (1<<5)
867 #define GM45_ERROR_MEM_PRIV (1<<4)
868 #define I915_ERROR_PAGE_TABLE (1<<4)
869 #define GM45_ERROR_CP_PRIV (1<<3)
870 #define I915_ERROR_MEMORY_REFRESH (1<<1)
871 #define I915_ERROR_INSTRUCTION (1<<0)
872 #define INSTPM 0x020c0
873 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
874 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
875 will not assert AGPBUSY# and will only
876 be delivered when out of C3. */
877 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
878 #define INSTPM_TLB_INVALIDATE (1<<9)
879 #define INSTPM_SYNC_FLUSH (1<<5)
880 #define ACTHD 0x020c8
881 #define FW_BLC 0x020d8
882 #define FW_BLC2 0x020dc
883 #define FW_BLC_SELF 0x020e0 /* 915+ only */
884 #define FW_BLC_SELF_EN_MASK (1<<31)
885 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
886 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
887 #define MM_BURST_LENGTH 0x00700000
888 #define MM_FIFO_WATERMARK 0x0001F000
889 #define LM_BURST_LENGTH 0x00000700
890 #define LM_FIFO_WATERMARK 0x0000001F
891 #define MI_ARB_STATE 0x020e4 /* 915+ only */
893 /* Make render/texture TLB fetches lower priorty than associated data
894 * fetches. This is not turned on by default
896 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
898 /* Isoch request wait on GTT enable (Display A/B/C streams).
899 * Make isoch requests stall on the TLB update. May cause
900 * display underruns (test mode only)
902 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
904 /* Block grant count for isoch requests when block count is
905 * set to a finite value.
907 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
908 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
909 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
910 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
911 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
913 /* Enable render writes to complete in C2/C3/C4 power states.
914 * If this isn't enabled, render writes are prevented in low
915 * power states. That seems bad to me.
917 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
919 /* This acknowledges an async flip immediately instead
920 * of waiting for 2TLB fetches.
922 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
924 /* Enables non-sequential data reads through arbiter
926 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
928 /* Disable FSB snooping of cacheable write cycles from binner/render
931 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
933 /* Arbiter time slice for non-isoch streams */
934 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
935 #define MI_ARB_TIME_SLICE_1 (0 << 5)
936 #define MI_ARB_TIME_SLICE_2 (1 << 5)
937 #define MI_ARB_TIME_SLICE_4 (2 << 5)
938 #define MI_ARB_TIME_SLICE_6 (3 << 5)
939 #define MI_ARB_TIME_SLICE_8 (4 << 5)
940 #define MI_ARB_TIME_SLICE_10 (5 << 5)
941 #define MI_ARB_TIME_SLICE_14 (6 << 5)
942 #define MI_ARB_TIME_SLICE_16 (7 << 5)
944 /* Low priority grace period page size */
945 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
946 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
948 /* Disable display A/B trickle feed */
949 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
951 /* Set display plane priority */
952 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
953 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
955 #define CACHE_MODE_0 0x02120 /* 915+ only */
956 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
957 #define CM0_IZ_OPT_DISABLE (1<<6)
958 #define CM0_ZR_OPT_DISABLE (1<<5)
959 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
960 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
961 #define CM0_COLOR_EVICT_DISABLE (1<<3)
962 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
963 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
964 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
965 #define GFX_FLSH_CNTL_GEN6 0x101008
966 #define GFX_FLSH_CNTL_EN (1<<0)
967 #define ECOSKPD 0x021d0
968 #define ECO_GATING_CX_ONLY (1<<3)
969 #define ECO_FLIP_DONE (1<<0)
971 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
972 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
973 #define CACHE_MODE_1 0x7004 /* IVB+ */
974 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
976 #define GEN6_BLITTER_ECOSKPD 0x221d0
977 #define GEN6_BLITTER_LOCK_SHIFT 16
978 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
980 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
981 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
983 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
984 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
985 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
986 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
987 #define GEN6_BSD_GO_INDICATOR (1 << 4)
989 /* On modern GEN architectures interrupt control consists of two sets
990 * of registers. The first set pertains to the ring generating the
991 * interrupt. The second control is for the functional block generating the
992 * interrupt. These are PM, GT, DE, etc.
994 * Luckily *knocks on wood* all the ring interrupt bits match up with the
995 * GT interrupt bits, so we don't need to duplicate the defines.
997 * These defines should cover us well from SNB->HSW with minor exceptions
998 * it can also work on ILK.
1000 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1001 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1002 #define GT_BLT_USER_INTERRUPT (1 << 22)
1003 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1004 #define GT_BSD_USER_INTERRUPT (1 << 12)
1005 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1006 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1007 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1008 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1009 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1010 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1011 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1013 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1014 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1016 #define GT_PARITY_ERROR(dev) \
1017 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1018 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1020 /* These are all the "old" interrupts */
1021 #define ILK_BSD_USER_INTERRUPT (1<<5)
1022 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1023 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1024 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1025 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
1026 #define I915_HWB_OOM_INTERRUPT (1<<13)
1027 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
1028 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1029 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1030 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1031 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1032 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1033 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1034 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1035 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1036 #define I915_DEBUG_INTERRUPT (1<<2)
1037 #define I915_USER_INTERRUPT (1<<1)
1038 #define I915_ASLE_INTERRUPT (1<<0)
1039 #define I915_BSD_USER_INTERRUPT (1 << 25)
1041 #define GEN6_BSD_RNCID 0x12198
1043 #define GEN7_FF_THREAD_MODE 0x20a0
1044 #define GEN7_FF_SCHED_MASK 0x0077070
1045 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1046 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1047 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1048 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1049 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
1050 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1051 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1052 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1053 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1054 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
1055 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1056 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1057 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1058 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
1061 * Framebuffer compression (915+ only)
1064 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1065 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
1066 #define FBC_CONTROL 0x03208
1067 #define FBC_CTL_EN (1<<31)
1068 #define FBC_CTL_PERIODIC (1<<30)
1069 #define FBC_CTL_INTERVAL_SHIFT (16)
1070 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1071 #define FBC_CTL_C3_IDLE (1<<13)
1072 #define FBC_CTL_STRIDE_SHIFT (5)
1073 #define FBC_CTL_FENCENO_SHIFT (0)
1074 #define FBC_COMMAND 0x0320c
1075 #define FBC_CMD_COMPRESS (1<<0)
1076 #define FBC_STATUS 0x03210
1077 #define FBC_STAT_COMPRESSING (1<<31)
1078 #define FBC_STAT_COMPRESSED (1<<30)
1079 #define FBC_STAT_MODIFIED (1<<29)
1080 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
1081 #define FBC_CONTROL2 0x03214
1082 #define FBC_CTL_FENCE_DBL (0<<4)
1083 #define FBC_CTL_IDLE_IMM (0<<2)
1084 #define FBC_CTL_IDLE_FULL (1<<2)
1085 #define FBC_CTL_IDLE_LINE (2<<2)
1086 #define FBC_CTL_IDLE_DEBUG (3<<2)
1087 #define FBC_CTL_CPU_FENCE (1<<1)
1088 #define FBC_CTL_PLANE(plane) ((plane)<<0)
1089 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
1090 #define FBC_TAG 0x03300
1092 #define FBC_LL_SIZE (1536)
1094 /* Framebuffer compression for GM45+ */
1095 #define DPFC_CB_BASE 0x3200
1096 #define DPFC_CONTROL 0x3208
1097 #define DPFC_CTL_EN (1<<31)
1098 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
1099 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
1100 #define DPFC_CTL_FENCE_EN (1<<29)
1101 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
1102 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
1103 #define DPFC_SR_EN (1<<10)
1104 #define DPFC_CTL_LIMIT_1X (0<<6)
1105 #define DPFC_CTL_LIMIT_2X (1<<6)
1106 #define DPFC_CTL_LIMIT_4X (2<<6)
1107 #define DPFC_RECOMP_CTL 0x320c
1108 #define DPFC_RECOMP_STALL_EN (1<<27)
1109 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
1110 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1111 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1112 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1113 #define DPFC_STATUS 0x3210
1114 #define DPFC_INVAL_SEG_SHIFT (16)
1115 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
1116 #define DPFC_COMP_SEG_SHIFT (0)
1117 #define DPFC_COMP_SEG_MASK (0x000003ff)
1118 #define DPFC_STATUS2 0x3214
1119 #define DPFC_FENCE_YOFF 0x3218
1120 #define DPFC_CHICKEN 0x3224
1121 #define DPFC_HT_MODIFY (1<<31)
1123 /* Framebuffer compression for Ironlake */
1124 #define ILK_DPFC_CB_BASE 0x43200
1125 #define ILK_DPFC_CONTROL 0x43208
1126 /* The bit 28-8 is reserved */
1127 #define DPFC_RESERVED (0x1FFFFF00)
1128 #define ILK_DPFC_RECOMP_CTL 0x4320c
1129 #define ILK_DPFC_STATUS 0x43210
1130 #define ILK_DPFC_FENCE_YOFF 0x43218
1131 #define ILK_DPFC_CHICKEN 0x43224
1132 #define ILK_FBC_RT_BASE 0x2128
1133 #define ILK_FBC_RT_VALID (1<<0)
1134 #define SNB_FBC_FRONT_BUFFER (1<<1)
1136 #define ILK_DISPLAY_CHICKEN1 0x42000
1137 #define ILK_FBCQ_DIS (1<<22)
1138 #define ILK_PABSTRETCH_DIS (1<<21)
1142 * Framebuffer compression for Sandybridge
1144 * The following two registers are of type GTTMMADR
1146 #define SNB_DPFC_CTL_SA 0x100100
1147 #define SNB_CPU_FENCE_ENABLE (1<<29)
1148 #define DPFC_CPU_FENCE_OFFSET 0x100104
1150 /* Framebuffer compression for Ivybridge */
1151 #define IVB_FBC_RT_BASE 0x7020
1153 #define IPS_CTL 0x43408
1154 #define IPS_ENABLE (1 << 31)
1156 #define MSG_FBC_REND_STATE 0x50380
1157 #define FBC_REND_NUKE (1<<2)
1158 #define FBC_REND_CACHE_CLEAN (1<<1)
1163 #define GPIOA 0x5010
1164 #define GPIOB 0x5014
1165 #define GPIOC 0x5018
1166 #define GPIOD 0x501c
1167 #define GPIOE 0x5020
1168 #define GPIOF 0x5024
1169 #define GPIOG 0x5028
1170 #define GPIOH 0x502c
1171 # define GPIO_CLOCK_DIR_MASK (1 << 0)
1172 # define GPIO_CLOCK_DIR_IN (0 << 1)
1173 # define GPIO_CLOCK_DIR_OUT (1 << 1)
1174 # define GPIO_CLOCK_VAL_MASK (1 << 2)
1175 # define GPIO_CLOCK_VAL_OUT (1 << 3)
1176 # define GPIO_CLOCK_VAL_IN (1 << 4)
1177 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1178 # define GPIO_DATA_DIR_MASK (1 << 8)
1179 # define GPIO_DATA_DIR_IN (0 << 9)
1180 # define GPIO_DATA_DIR_OUT (1 << 9)
1181 # define GPIO_DATA_VAL_MASK (1 << 10)
1182 # define GPIO_DATA_VAL_OUT (1 << 11)
1183 # define GPIO_DATA_VAL_IN (1 << 12)
1184 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1186 #define GMBUS0 0x5100 /* clock/port select */
1187 #define GMBUS_RATE_100KHZ (0<<8)
1188 #define GMBUS_RATE_50KHZ (1<<8)
1189 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1190 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1191 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1192 #define GMBUS_PORT_DISABLED 0
1193 #define GMBUS_PORT_SSC 1
1194 #define GMBUS_PORT_VGADDC 2
1195 #define GMBUS_PORT_PANEL 3
1196 #define GMBUS_PORT_DPC 4 /* HDMIC */
1197 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
1198 #define GMBUS_PORT_DPD 6 /* HDMID */
1199 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
1200 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1201 #define GMBUS1 0x5104 /* command/status */
1202 #define GMBUS_SW_CLR_INT (1<<31)
1203 #define GMBUS_SW_RDY (1<<30)
1204 #define GMBUS_ENT (1<<29) /* enable timeout */
1205 #define GMBUS_CYCLE_NONE (0<<25)
1206 #define GMBUS_CYCLE_WAIT (1<<25)
1207 #define GMBUS_CYCLE_INDEX (2<<25)
1208 #define GMBUS_CYCLE_STOP (4<<25)
1209 #define GMBUS_BYTE_COUNT_SHIFT 16
1210 #define GMBUS_SLAVE_INDEX_SHIFT 8
1211 #define GMBUS_SLAVE_ADDR_SHIFT 1
1212 #define GMBUS_SLAVE_READ (1<<0)
1213 #define GMBUS_SLAVE_WRITE (0<<0)
1214 #define GMBUS2 0x5108 /* status */
1215 #define GMBUS_INUSE (1<<15)
1216 #define GMBUS_HW_WAIT_PHASE (1<<14)
1217 #define GMBUS_STALL_TIMEOUT (1<<13)
1218 #define GMBUS_INT (1<<12)
1219 #define GMBUS_HW_RDY (1<<11)
1220 #define GMBUS_SATOER (1<<10)
1221 #define GMBUS_ACTIVE (1<<9)
1222 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
1223 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1224 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1225 #define GMBUS_NAK_EN (1<<3)
1226 #define GMBUS_IDLE_EN (1<<2)
1227 #define GMBUS_HW_WAIT_EN (1<<1)
1228 #define GMBUS_HW_RDY_EN (1<<0)
1229 #define GMBUS5 0x5120 /* byte index */
1230 #define GMBUS_2BYTE_INDEX_EN (1<<31)
1233 * Clock control & power management
1235 #define DPLL_A_OFFSET 0x6014
1236 #define DPLL_B_OFFSET 0x6018
1237 #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
1238 dev_priv->info.display_mmio_offset)
1242 #define VGA_PD 0x6010
1243 #define VGA0_PD_P2_DIV_4 (1 << 7)
1244 #define VGA0_PD_P1_DIV_2 (1 << 5)
1245 #define VGA0_PD_P1_SHIFT 0
1246 #define VGA0_PD_P1_MASK (0x1f << 0)
1247 #define VGA1_PD_P2_DIV_4 (1 << 15)
1248 #define VGA1_PD_P1_DIV_2 (1 << 13)
1249 #define VGA1_PD_P1_SHIFT 8
1250 #define VGA1_PD_P1_MASK (0x1f << 8)
1251 #define DPLL_VCO_ENABLE (1 << 31)
1252 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1253 #define DPLL_DVO_2X_MODE (1 << 30)
1254 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1255 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1256 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
1257 #define DPLL_VGA_MODE_DIS (1 << 28)
1258 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1259 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1260 #define DPLL_MODE_MASK (3 << 26)
1261 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1262 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1263 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1264 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1265 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1266 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1267 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1268 #define DPLL_LOCK_VLV (1<<15)
1269 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
1270 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
1271 #define DPLL_PORTC_READY_MASK (0xf << 4)
1272 #define DPLL_PORTB_READY_MASK (0xf)
1274 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1276 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1277 * this field (only one bit may be set).
1279 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1280 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1281 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1282 /* i830, required in DVO non-gang */
1283 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1284 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1285 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1286 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1287 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1288 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1289 #define PLL_REF_INPUT_MASK (3 << 13)
1290 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1292 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1293 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1294 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1295 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1296 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1299 * Parallel to Serial Load Pulse phase selection.
1300 * Selects the phase for the 10X DPLL clock for the PCIe
1301 * digital display port. The range is 4 to 13; 10 or more
1302 * is just a flip delay. The default is 6
1304 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1305 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1307 * SDVO multiplier for 945G/GM. Not used on 965.
1309 #define SDVO_MULTIPLIER_MASK 0x000000ff
1310 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1311 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1313 #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
1314 #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
1315 #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
1316 dev_priv->info.display_mmio_offset)
1319 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1321 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1323 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1324 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1325 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1326 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1327 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1329 * SDVO/UDI pixel multiplier.
1331 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1332 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1333 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1334 * dummy bytes in the datastream at an increased clock rate, with both sides of
1335 * the link knowing how many bytes are fill.
1337 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1338 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1339 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1340 * through an SDVO command.
1342 * This register field has values of multiplication factor minus 1, with
1343 * a maximum multiplier of 5 for SDVO.
1345 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1346 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1348 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1349 * This best be set to the default value (3) or the CRT won't work. No,
1350 * I don't entirely understand what this does...
1352 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1353 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1355 #define _FPA0 0x06040
1356 #define _FPA1 0x06044
1357 #define _FPB0 0x06048
1358 #define _FPB1 0x0604c
1359 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1360 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1361 #define FP_N_DIV_MASK 0x003f0000
1362 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1363 #define FP_N_DIV_SHIFT 16
1364 #define FP_M1_DIV_MASK 0x00003f00
1365 #define FP_M1_DIV_SHIFT 8
1366 #define FP_M2_DIV_MASK 0x0000003f
1367 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1368 #define FP_M2_DIV_SHIFT 0
1369 #define DPLL_TEST 0x606c
1370 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1371 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1372 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1373 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1374 #define DPLLB_TEST_N_BYPASS (1 << 19)
1375 #define DPLLB_TEST_M_BYPASS (1 << 18)
1376 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1377 #define DPLLA_TEST_N_BYPASS (1 << 3)
1378 #define DPLLA_TEST_M_BYPASS (1 << 2)
1379 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1380 #define D_STATE 0x6104
1381 #define DSTATE_GFX_RESET_I830 (1<<6)
1382 #define DSTATE_PLL_D3_OFF (1<<3)
1383 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1384 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1385 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
1386 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1387 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1388 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1389 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1390 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1391 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1392 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1393 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1394 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1395 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1396 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1397 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1398 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1399 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1400 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1401 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1402 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1403 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1404 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1405 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1406 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1407 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1408 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1409 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1410 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1411 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1412 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1413 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1415 * This bit must be set on the 830 to prevent hangs when turning off the
1418 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1419 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1420 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1421 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1422 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1424 #define RENCLK_GATE_D1 0x6204
1425 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1426 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1427 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1428 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1429 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1430 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1431 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1432 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1433 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1434 /** This bit must be unset on 855,865 */
1435 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1436 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1437 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1438 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1439 /** This bit must be set on 855,865. */
1440 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1441 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1442 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1443 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1444 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1445 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1446 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1447 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1448 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1449 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1450 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1451 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1452 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1453 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1454 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1455 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1456 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1457 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1459 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1460 /** This bit must always be set on 965G/965GM */
1461 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1462 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1463 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1464 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1465 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1466 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1467 /** This bit must always be set on 965G */
1468 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1469 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1470 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1471 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1472 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1473 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1474 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1475 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1476 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1477 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1478 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1479 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1480 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1481 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1482 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1483 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1484 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1485 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1486 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1488 #define RENCLK_GATE_D2 0x6208
1489 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1490 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1491 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1492 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1493 #define DEUC 0x6214 /* CRL only */
1495 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
1496 #define FW_CSPWRDWNEN (1<<15)
1498 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1500 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1501 #define CDCLK_FREQ_SHIFT 4
1502 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1503 #define CZCLK_FREQ_MASK 0xf
1504 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1509 #define PALETTE_A_OFFSET 0xa000
1510 #define PALETTE_B_OFFSET 0xa800
1511 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
1512 dev_priv->info.display_mmio_offset)
1514 /* MCH MMIO space */
1519 * This mirrors the MCHBAR MMIO space whose location is determined by
1520 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1521 * every way. It is not accessible from the CP register read instructions.
1523 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
1526 #define MCHBAR_MIRROR_BASE 0x10000
1528 #define MCHBAR_MIRROR_BASE_SNB 0x140000
1530 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
1531 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
1533 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1535 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1536 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1537 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1538 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
1539 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1540 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1542 /** Pineview MCH register contains DDR3 setting */
1543 #define CSHRDDR3CTL 0x101a8
1544 #define CSHRDDR3CTL_DDR3 (1 << 2)
1546 /** 965 MCH register controlling DRAM channel configuration */
1547 #define C0DRB3 0x10206
1548 #define C1DRB3 0x10606
1550 /** snb MCH registers for reading the DRAM channel configuration */
1551 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1552 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1553 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1554 #define MAD_DIMM_ECC_MASK (0x3 << 24)
1555 #define MAD_DIMM_ECC_OFF (0x0 << 24)
1556 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1557 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1558 #define MAD_DIMM_ECC_ON (0x3 << 24)
1559 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1560 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1561 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1562 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1563 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1564 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1565 #define MAD_DIMM_A_SELECT (0x1 << 16)
1566 /* DIMM sizes are in multiples of 256mb. */
1567 #define MAD_DIMM_B_SIZE_SHIFT 8
1568 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1569 #define MAD_DIMM_A_SIZE_SHIFT 0
1570 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1572 /** snb MCH registers for priority tuning */
1573 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1574 #define MCH_SSKPD_WM0_MASK 0x3f
1575 #define MCH_SSKPD_WM0_VAL 0xc
1577 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
1579 /* Clocking configuration register */
1580 #define CLKCFG 0x10c00
1581 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1582 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1583 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1584 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1585 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1586 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1587 /* Note, below two are guess */
1588 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1589 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1590 #define CLKCFG_FSB_MASK (7 << 0)
1591 #define CLKCFG_MEM_533 (1 << 4)
1592 #define CLKCFG_MEM_667 (2 << 4)
1593 #define CLKCFG_MEM_800 (3 << 4)
1594 #define CLKCFG_MEM_MASK (7 << 4)
1596 #define TSC1 0x11001
1599 #define TSFS 0x11020
1600 #define TSFS_SLOPE_MASK 0x0000ff00
1601 #define TSFS_SLOPE_SHIFT 8
1602 #define TSFS_INTR_MASK 0x000000ff
1604 #define CRSTANDVID 0x11100
1605 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1606 #define PXVFREQ_PX_MASK 0x7f000000
1607 #define PXVFREQ_PX_SHIFT 24
1608 #define VIDFREQ_BASE 0x11110
1609 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1610 #define VIDFREQ2 0x11114
1611 #define VIDFREQ3 0x11118
1612 #define VIDFREQ4 0x1111c
1613 #define VIDFREQ_P0_MASK 0x1f000000
1614 #define VIDFREQ_P0_SHIFT 24
1615 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1616 #define VIDFREQ_P0_CSCLK_SHIFT 20
1617 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1618 #define VIDFREQ_P0_CRCLK_SHIFT 16
1619 #define VIDFREQ_P1_MASK 0x00001f00
1620 #define VIDFREQ_P1_SHIFT 8
1621 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1622 #define VIDFREQ_P1_CSCLK_SHIFT 4
1623 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1624 #define INTTOEXT_BASE_ILK 0x11300
1625 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1626 #define INTTOEXT_MAP3_SHIFT 24
1627 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1628 #define INTTOEXT_MAP2_SHIFT 16
1629 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1630 #define INTTOEXT_MAP1_SHIFT 8
1631 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1632 #define INTTOEXT_MAP0_SHIFT 0
1633 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1634 #define MEMSWCTL 0x11170 /* Ironlake only */
1635 #define MEMCTL_CMD_MASK 0xe000
1636 #define MEMCTL_CMD_SHIFT 13
1637 #define MEMCTL_CMD_RCLK_OFF 0
1638 #define MEMCTL_CMD_RCLK_ON 1
1639 #define MEMCTL_CMD_CHFREQ 2
1640 #define MEMCTL_CMD_CHVID 3
1641 #define MEMCTL_CMD_VMMOFF 4
1642 #define MEMCTL_CMD_VMMON 5
1643 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1644 when command complete */
1645 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1646 #define MEMCTL_FREQ_SHIFT 8
1647 #define MEMCTL_SFCAVM (1<<7)
1648 #define MEMCTL_TGT_VID_MASK 0x007f
1649 #define MEMIHYST 0x1117c
1650 #define MEMINTREN 0x11180 /* 16 bits */
1651 #define MEMINT_RSEXIT_EN (1<<8)
1652 #define MEMINT_CX_SUPR_EN (1<<7)
1653 #define MEMINT_CONT_BUSY_EN (1<<6)
1654 #define MEMINT_AVG_BUSY_EN (1<<5)
1655 #define MEMINT_EVAL_CHG_EN (1<<4)
1656 #define MEMINT_MON_IDLE_EN (1<<3)
1657 #define MEMINT_UP_EVAL_EN (1<<2)
1658 #define MEMINT_DOWN_EVAL_EN (1<<1)
1659 #define MEMINT_SW_CMD_EN (1<<0)
1660 #define MEMINTRSTR 0x11182 /* 16 bits */
1661 #define MEM_RSEXIT_MASK 0xc000
1662 #define MEM_RSEXIT_SHIFT 14
1663 #define MEM_CONT_BUSY_MASK 0x3000
1664 #define MEM_CONT_BUSY_SHIFT 12
1665 #define MEM_AVG_BUSY_MASK 0x0c00
1666 #define MEM_AVG_BUSY_SHIFT 10
1667 #define MEM_EVAL_CHG_MASK 0x0300
1668 #define MEM_EVAL_BUSY_SHIFT 8
1669 #define MEM_MON_IDLE_MASK 0x00c0
1670 #define MEM_MON_IDLE_SHIFT 6
1671 #define MEM_UP_EVAL_MASK 0x0030
1672 #define MEM_UP_EVAL_SHIFT 4
1673 #define MEM_DOWN_EVAL_MASK 0x000c
1674 #define MEM_DOWN_EVAL_SHIFT 2
1675 #define MEM_SW_CMD_MASK 0x0003
1676 #define MEM_INT_STEER_GFX 0
1677 #define MEM_INT_STEER_CMR 1
1678 #define MEM_INT_STEER_SMI 2
1679 #define MEM_INT_STEER_SCI 3
1680 #define MEMINTRSTS 0x11184
1681 #define MEMINT_RSEXIT (1<<7)
1682 #define MEMINT_CONT_BUSY (1<<6)
1683 #define MEMINT_AVG_BUSY (1<<5)
1684 #define MEMINT_EVAL_CHG (1<<4)
1685 #define MEMINT_MON_IDLE (1<<3)
1686 #define MEMINT_UP_EVAL (1<<2)
1687 #define MEMINT_DOWN_EVAL (1<<1)
1688 #define MEMINT_SW_CMD (1<<0)
1689 #define MEMMODECTL 0x11190
1690 #define MEMMODE_BOOST_EN (1<<31)
1691 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1692 #define MEMMODE_BOOST_FREQ_SHIFT 24
1693 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1694 #define MEMMODE_IDLE_MODE_SHIFT 16
1695 #define MEMMODE_IDLE_MODE_EVAL 0
1696 #define MEMMODE_IDLE_MODE_CONT 1
1697 #define MEMMODE_HWIDLE_EN (1<<15)
1698 #define MEMMODE_SWMODE_EN (1<<14)
1699 #define MEMMODE_RCLK_GATE (1<<13)
1700 #define MEMMODE_HW_UPDATE (1<<12)
1701 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1702 #define MEMMODE_FSTART_SHIFT 8
1703 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1704 #define MEMMODE_FMAX_SHIFT 4
1705 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1706 #define RCBMAXAVG 0x1119c
1707 #define MEMSWCTL2 0x1119e /* Cantiga only */
1708 #define SWMEMCMD_RENDER_OFF (0 << 13)
1709 #define SWMEMCMD_RENDER_ON (1 << 13)
1710 #define SWMEMCMD_SWFREQ (2 << 13)
1711 #define SWMEMCMD_TARVID (3 << 13)
1712 #define SWMEMCMD_VRM_OFF (4 << 13)
1713 #define SWMEMCMD_VRM_ON (5 << 13)
1714 #define CMDSTS (1<<12)
1715 #define SFCAVM (1<<11)
1716 #define SWFREQ_MASK 0x0380 /* P0-7 */
1717 #define SWFREQ_SHIFT 7
1718 #define TARVID_MASK 0x001f
1719 #define MEMSTAT_CTG 0x111a0
1720 #define RCBMINAVG 0x111a0
1721 #define RCUPEI 0x111b0
1722 #define RCDNEI 0x111b4
1723 #define RSTDBYCTL 0x111b8
1724 #define RS1EN (1<<31)
1725 #define RS2EN (1<<30)
1726 #define RS3EN (1<<29)
1727 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1728 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1729 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1730 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1731 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1732 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1733 #define RSX_STATUS_MASK (7<<20)
1734 #define RSX_STATUS_ON (0<<20)
1735 #define RSX_STATUS_RC1 (1<<20)
1736 #define RSX_STATUS_RC1E (2<<20)
1737 #define RSX_STATUS_RS1 (3<<20)
1738 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1739 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1740 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1741 #define RSX_STATUS_RSVD2 (7<<20)
1742 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1743 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1744 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1745 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1746 #define RS1CONTSAV_MASK (3<<14)
1747 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1748 #define RS1CONTSAV_RSVD (1<<14)
1749 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1750 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1751 #define NORMSLEXLAT_MASK (3<<12)
1752 #define SLOW_RS123 (0<<12)
1753 #define SLOW_RS23 (1<<12)
1754 #define SLOW_RS3 (2<<12)
1755 #define NORMAL_RS123 (3<<12)
1756 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1757 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1758 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1759 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1760 #define RS_CSTATE_MASK (3<<4)
1761 #define RS_CSTATE_C367_RS1 (0<<4)
1762 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1763 #define RS_CSTATE_RSVD (2<<4)
1764 #define RS_CSTATE_C367_RS2 (3<<4)
1765 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1766 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1767 #define VIDCTL 0x111c0
1768 #define VIDSTS 0x111c8
1769 #define VIDSTART 0x111cc /* 8 bits */
1770 #define MEMSTAT_ILK 0x111f8
1771 #define MEMSTAT_VID_MASK 0x7f00
1772 #define MEMSTAT_VID_SHIFT 8
1773 #define MEMSTAT_PSTATE_MASK 0x00f8
1774 #define MEMSTAT_PSTATE_SHIFT 3
1775 #define MEMSTAT_MON_ACTV (1<<2)
1776 #define MEMSTAT_SRC_CTL_MASK 0x0003
1777 #define MEMSTAT_SRC_CTL_CORE 0
1778 #define MEMSTAT_SRC_CTL_TRB 1
1779 #define MEMSTAT_SRC_CTL_THM 2
1780 #define MEMSTAT_SRC_CTL_STDBY 3
1781 #define RCPREVBSYTUPAVG 0x113b8
1782 #define RCPREVBSYTDNAVG 0x113bc
1783 #define PMMISC 0x11214
1784 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1785 #define SDEW 0x1124c
1786 #define CSIEW0 0x11250
1787 #define CSIEW1 0x11254
1788 #define CSIEW2 0x11258
1791 #define MCHAFE 0x112c0
1792 #define CSIEC 0x112e0
1793 #define DMIEC 0x112e4
1794 #define DDREC 0x112e8
1795 #define PEG0EC 0x112ec
1796 #define PEG1EC 0x112f0
1797 #define GFXEC 0x112f4
1798 #define RPPREVBSYTUPAVG 0x113b8
1799 #define RPPREVBSYTDNAVG 0x113bc
1801 #define ECR_GPFE (1<<31)
1802 #define ECR_IMONE (1<<30)
1803 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1804 #define OGW0 0x11608
1805 #define OGW1 0x1160c
1815 #define PXWL 0x11680
1816 #define LCFUSE02 0x116c0
1817 #define LCFUSE_HIV_MASK 0x000000ff
1818 #define CSIPLL0 0x12c10
1819 #define DDRMPLL1 0X12c20
1820 #define PEG_BAND_GAP_DATA 0x14d68
1822 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1823 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1824 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1826 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
1827 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
1828 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
1831 * Logical Context regs
1834 #define CCID_EN (1<<0)
1836 * Notes on SNB/IVB/VLV context size:
1837 * - Power context is saved elsewhere (LLC or stolen)
1838 * - Ring/execlist context is saved on SNB, not on IVB
1839 * - Extended context size already includes render context size
1840 * - We always need to follow the extended context size.
1841 * SNB BSpec has comments indicating that we should use the
1842 * render context size instead if execlists are disabled, but
1843 * based on empirical testing that's just nonsense.
1844 * - Pipelined/VF state is saved on SNB/IVB respectively
1845 * - GT1 size just indicates how much of render context
1846 * doesn't need saving on GT1
1848 #define CXT_SIZE 0x21a0
1849 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1850 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1851 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1852 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1853 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1854 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
1855 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1856 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1857 #define GEN7_CXT_SIZE 0x21a8
1858 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1859 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1860 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1861 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1862 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1863 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1864 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1865 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1866 /* Haswell does have the CXT_SIZE register however it does not appear to be
1867 * valid. Now, docs explain in dwords what is in the context object. The full
1868 * size is 70720 bytes, however, the power context and execlist context will
1869 * never be saved (power context is stored elsewhere, and execlists don't work
1870 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1872 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
1873 /* Same as Haswell, but 72064 bytes now. */
1874 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
1877 #define VLV_CLK_CTL2 0x101104
1878 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1884 #define OVADD 0x30000
1885 #define DOVSTA 0x30008
1886 #define OC_BUF (0x3<<20)
1887 #define OGAMC5 0x30010
1888 #define OGAMC4 0x30014
1889 #define OGAMC3 0x30018
1890 #define OGAMC2 0x3001c
1891 #define OGAMC1 0x30020
1892 #define OGAMC0 0x30024
1895 * Display engine regs
1898 /* Pipe A CRC regs */
1899 #define _PIPE_CRC_CTL_A 0x60050
1900 #define PIPE_CRC_ENABLE (1 << 31)
1901 /* ivb+ source selection */
1902 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
1903 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
1904 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
1905 /* ilk+ source selection */
1906 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
1907 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
1908 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
1909 /* embedded DP port on the north display block, reserved on ivb */
1910 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
1911 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
1912 /* vlv source selection */
1913 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
1914 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
1915 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
1916 /* with DP port the pipe source is invalid */
1917 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
1918 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
1919 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
1920 /* gen3+ source selection */
1921 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
1922 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
1923 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
1924 /* with DP/TV port the pipe source is invalid */
1925 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
1926 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
1927 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
1928 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
1929 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
1930 /* gen2 doesn't have source selection bits */
1931 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
1933 #define _PIPE_CRC_RES_1_A_IVB 0x60064
1934 #define _PIPE_CRC_RES_2_A_IVB 0x60068
1935 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
1936 #define _PIPE_CRC_RES_4_A_IVB 0x60070
1937 #define _PIPE_CRC_RES_5_A_IVB 0x60074
1939 #define _PIPE_CRC_RES_RED_A 0x60060
1940 #define _PIPE_CRC_RES_GREEN_A 0x60064
1941 #define _PIPE_CRC_RES_BLUE_A 0x60068
1942 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1943 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1945 /* Pipe B CRC regs */
1946 #define _PIPE_CRC_RES_1_B_IVB 0x61064
1947 #define _PIPE_CRC_RES_2_B_IVB 0x61068
1948 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
1949 #define _PIPE_CRC_RES_4_B_IVB 0x61070
1950 #define _PIPE_CRC_RES_5_B_IVB 0x61074
1952 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
1953 #define PIPE_CRC_RES_1_IVB(pipe) \
1954 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
1955 #define PIPE_CRC_RES_2_IVB(pipe) \
1956 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
1957 #define PIPE_CRC_RES_3_IVB(pipe) \
1958 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
1959 #define PIPE_CRC_RES_4_IVB(pipe) \
1960 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
1961 #define PIPE_CRC_RES_5_IVB(pipe) \
1962 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
1964 #define PIPE_CRC_RES_RED(pipe) \
1965 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
1966 #define PIPE_CRC_RES_GREEN(pipe) \
1967 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
1968 #define PIPE_CRC_RES_BLUE(pipe) \
1969 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
1970 #define PIPE_CRC_RES_RES1_I915(pipe) \
1971 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1972 #define PIPE_CRC_RES_RES2_G4X(pipe) \
1973 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1975 /* Pipe A timing regs */
1976 #define _HTOTAL_A 0x60000
1977 #define _HBLANK_A 0x60004
1978 #define _HSYNC_A 0x60008
1979 #define _VTOTAL_A 0x6000c
1980 #define _VBLANK_A 0x60010
1981 #define _VSYNC_A 0x60014
1982 #define _PIPEASRC 0x6001c
1983 #define _BCLRPAT_A 0x60020
1984 #define _VSYNCSHIFT_A 0x60028
1986 /* Pipe B timing regs */
1987 #define _HTOTAL_B 0x61000
1988 #define _HBLANK_B 0x61004
1989 #define _HSYNC_B 0x61008
1990 #define _VTOTAL_B 0x6100c
1991 #define _VBLANK_B 0x61010
1992 #define _VSYNC_B 0x61014
1993 #define _PIPEBSRC 0x6101c
1994 #define _BCLRPAT_B 0x61020
1995 #define _VSYNCSHIFT_B 0x61028
1997 #define TRANSCODER_A_OFFSET 0x60000
1998 #define TRANSCODER_B_OFFSET 0x61000
1999 #define TRANSCODER_C_OFFSET 0x62000
2000 #define TRANSCODER_EDP_OFFSET 0x6f000
2002 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2003 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2004 dev_priv->info.display_mmio_offset)
2006 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2007 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2008 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2009 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2010 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2011 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2012 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2013 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2014 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
2016 /* HSW+ eDP PSR registers */
2017 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2018 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
2019 #define EDP_PSR_ENABLE (1<<31)
2020 #define EDP_PSR_LINK_DISABLE (0<<27)
2021 #define EDP_PSR_LINK_STANDBY (1<<27)
2022 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2023 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2024 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2025 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2026 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2027 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2028 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2029 #define EDP_PSR_TP1_TP2_SEL (0<<11)
2030 #define EDP_PSR_TP1_TP3_SEL (1<<11)
2031 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2032 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2033 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2034 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2035 #define EDP_PSR_TP1_TIME_500us (0<<4)
2036 #define EDP_PSR_TP1_TIME_100us (1<<4)
2037 #define EDP_PSR_TP1_TIME_2500us (2<<4)
2038 #define EDP_PSR_TP1_TIME_0us (3<<4)
2039 #define EDP_PSR_IDLE_FRAME_SHIFT 0
2041 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2042 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
2043 #define EDP_PSR_DPCD_COMMAND 0x80060000
2044 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
2045 #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
2046 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2047 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2048 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
2050 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
2051 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
2052 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2053 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2054 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2055 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2056 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2057 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2058 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2059 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
2060 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2061 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2062 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2063 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2064 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2065 #define EDP_PSR_STATUS_COUNT_SHIFT 16
2066 #define EDP_PSR_STATUS_COUNT_MASK 0xf
2067 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2068 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2069 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2070 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2071 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2072 #define EDP_PSR_STATUS_IDLE_MASK 0xf
2074 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
2075 #define EDP_PSR_PERF_CNT_MASK 0xffffff
2077 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
2078 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2079 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2080 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2082 /* VGA port control */
2083 #define ADPA 0x61100
2084 #define PCH_ADPA 0xe1100
2085 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
2087 #define ADPA_DAC_ENABLE (1<<31)
2088 #define ADPA_DAC_DISABLE 0
2089 #define ADPA_PIPE_SELECT_MASK (1<<30)
2090 #define ADPA_PIPE_A_SELECT 0
2091 #define ADPA_PIPE_B_SELECT (1<<30)
2092 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
2093 /* CPT uses bits 29:30 for pch transcoder select */
2094 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2095 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2096 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2097 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2098 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2099 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2100 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2101 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2102 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2103 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2104 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2105 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2106 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2107 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2108 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2109 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2110 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2111 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2112 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2113 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
2114 #define ADPA_SETS_HVPOLARITY 0
2115 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
2116 #define ADPA_VSYNC_CNTL_ENABLE 0
2117 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
2118 #define ADPA_HSYNC_CNTL_ENABLE 0
2119 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2120 #define ADPA_VSYNC_ACTIVE_LOW 0
2121 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2122 #define ADPA_HSYNC_ACTIVE_LOW 0
2123 #define ADPA_DPMS_MASK (~(3<<10))
2124 #define ADPA_DPMS_ON (0<<10)
2125 #define ADPA_DPMS_SUSPEND (1<<10)
2126 #define ADPA_DPMS_STANDBY (2<<10)
2127 #define ADPA_DPMS_OFF (3<<10)
2130 /* Hotplug control (945+ only) */
2131 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
2132 #define PORTB_HOTPLUG_INT_EN (1 << 29)
2133 #define PORTC_HOTPLUG_INT_EN (1 << 28)
2134 #define PORTD_HOTPLUG_INT_EN (1 << 27)
2135 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
2136 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
2137 #define TV_HOTPLUG_INT_EN (1 << 18)
2138 #define CRT_HOTPLUG_INT_EN (1 << 9)
2139 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2140 PORTC_HOTPLUG_INT_EN | \
2141 PORTD_HOTPLUG_INT_EN | \
2142 SDVOC_HOTPLUG_INT_EN | \
2143 SDVOB_HOTPLUG_INT_EN | \
2145 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2146 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2147 /* must use period 64 on GM45 according to docs */
2148 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2149 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2150 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2151 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2152 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2153 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2154 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2155 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2156 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2157 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2158 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2159 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2161 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
2163 * HDMI/DP bits are gen4+
2165 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2166 * Please check the detailed lore in the commit message for for experimental
2169 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2170 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2171 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2172 /* VLV DP/HDMI bits again match Bspec */
2173 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2174 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2175 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
2176 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2177 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2178 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2179 /* CRT/TV common between gen3+ */
2180 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
2181 #define TV_HOTPLUG_INT_STATUS (1 << 10)
2182 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2183 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2184 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2185 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2186 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2187 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2188 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2189 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2191 /* SDVO is different across gen3/4 */
2192 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2193 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2195 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2196 * since reality corrobates that they're the same as on gen3. But keep these
2197 * bits here (and the comment!) to help any other lost wanderers back onto the
2200 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2201 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2202 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2203 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2204 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2205 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2206 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2207 PORTB_HOTPLUG_INT_STATUS | \
2208 PORTC_HOTPLUG_INT_STATUS | \
2209 PORTD_HOTPLUG_INT_STATUS)
2211 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2212 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2213 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2214 PORTB_HOTPLUG_INT_STATUS | \
2215 PORTC_HOTPLUG_INT_STATUS | \
2216 PORTD_HOTPLUG_INT_STATUS)
2218 /* SDVO and HDMI port control.
2219 * The same register may be used for SDVO or HDMI */
2220 #define GEN3_SDVOB 0x61140
2221 #define GEN3_SDVOC 0x61160
2222 #define GEN4_HDMIB GEN3_SDVOB
2223 #define GEN4_HDMIC GEN3_SDVOC
2224 #define PCH_SDVOB 0xe1140
2225 #define PCH_HDMIB PCH_SDVOB
2226 #define PCH_HDMIC 0xe1150
2227 #define PCH_HDMID 0xe1160
2229 #define PORT_DFT_I9XX 0x61150
2230 #define DC_BALANCE_RESET (1 << 25)
2231 #define PORT_DFT2_G4X 0x61154
2232 #define DC_BALANCE_RESET_VLV (1 << 31)
2233 #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2234 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
2235 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
2237 /* Gen 3 SDVO bits: */
2238 #define SDVO_ENABLE (1 << 31)
2239 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2240 #define SDVO_PIPE_SEL_MASK (1 << 30)
2241 #define SDVO_PIPE_B_SELECT (1 << 30)
2242 #define SDVO_STALL_SELECT (1 << 29)
2243 #define SDVO_INTERRUPT_ENABLE (1 << 26)
2245 * 915G/GM SDVO pixel multiplier.
2246 * Programmed value is multiplier - 1, up to 5x.
2247 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2249 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2250 #define SDVO_PORT_MULTIPLY_SHIFT 23
2251 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2252 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2253 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2254 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2255 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2256 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2257 #define SDVO_DETECTED (1 << 2)
2258 /* Bits to be preserved when writing */
2259 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2260 SDVO_INTERRUPT_ENABLE)
2261 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2263 /* Gen 4 SDVO/HDMI bits: */
2264 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2265 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
2266 #define SDVO_ENCODING_SDVO (0 << 10)
2267 #define SDVO_ENCODING_HDMI (2 << 10)
2268 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2269 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2270 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2271 #define SDVO_AUDIO_ENABLE (1 << 6)
2272 /* VSYNC/HSYNC bits new with 965, default is to be set */
2273 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2274 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2276 /* Gen 5 (IBX) SDVO/HDMI bits: */
2277 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2278 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2280 /* Gen 6 (CPT) SDVO/HDMI bits: */
2281 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2282 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2285 /* DVO port control */
2286 #define DVOA 0x61120
2287 #define DVOB 0x61140
2288 #define DVOC 0x61160
2289 #define DVO_ENABLE (1 << 31)
2290 #define DVO_PIPE_B_SELECT (1 << 30)
2291 #define DVO_PIPE_STALL_UNUSED (0 << 28)
2292 #define DVO_PIPE_STALL (1 << 28)
2293 #define DVO_PIPE_STALL_TV (2 << 28)
2294 #define DVO_PIPE_STALL_MASK (3 << 28)
2295 #define DVO_USE_VGA_SYNC (1 << 15)
2296 #define DVO_DATA_ORDER_I740 (0 << 14)
2297 #define DVO_DATA_ORDER_FP (1 << 14)
2298 #define DVO_VSYNC_DISABLE (1 << 11)
2299 #define DVO_HSYNC_DISABLE (1 << 10)
2300 #define DVO_VSYNC_TRISTATE (1 << 9)
2301 #define DVO_HSYNC_TRISTATE (1 << 8)
2302 #define DVO_BORDER_ENABLE (1 << 7)
2303 #define DVO_DATA_ORDER_GBRG (1 << 6)
2304 #define DVO_DATA_ORDER_RGGB (0 << 6)
2305 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2306 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2307 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2308 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2309 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2310 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2311 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2312 #define DVO_PRESERVE_MASK (0x7<<24)
2313 #define DVOA_SRCDIM 0x61124
2314 #define DVOB_SRCDIM 0x61144
2315 #define DVOC_SRCDIM 0x61164
2316 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2317 #define DVO_SRCDIM_VERTICAL_SHIFT 0
2319 /* LVDS port control */
2320 #define LVDS 0x61180
2322 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2323 * the DPLL semantics change when the LVDS is assigned to that pipe.
2325 #define LVDS_PORT_EN (1 << 31)
2326 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2327 #define LVDS_PIPEB_SELECT (1 << 30)
2328 #define LVDS_PIPE_MASK (1 << 30)
2329 #define LVDS_PIPE(pipe) ((pipe) << 30)
2330 /* LVDS dithering flag on 965/g4x platform */
2331 #define LVDS_ENABLE_DITHER (1 << 25)
2332 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2333 #define LVDS_VSYNC_POLARITY (1 << 21)
2334 #define LVDS_HSYNC_POLARITY (1 << 20)
2336 /* Enable border for unscaled (or aspect-scaled) display */
2337 #define LVDS_BORDER_ENABLE (1 << 15)
2339 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2342 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2343 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2344 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2346 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2347 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2350 #define LVDS_A3_POWER_MASK (3 << 6)
2351 #define LVDS_A3_POWER_DOWN (0 << 6)
2352 #define LVDS_A3_POWER_UP (3 << 6)
2354 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2357 #define LVDS_CLKB_POWER_MASK (3 << 4)
2358 #define LVDS_CLKB_POWER_DOWN (0 << 4)
2359 #define LVDS_CLKB_POWER_UP (3 << 4)
2361 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2362 * setting for whether we are in dual-channel mode. The B3 pair will
2363 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2365 #define LVDS_B0B3_POWER_MASK (3 << 2)
2366 #define LVDS_B0B3_POWER_DOWN (0 << 2)
2367 #define LVDS_B0B3_POWER_UP (3 << 2)
2369 /* Video Data Island Packet control */
2370 #define VIDEO_DIP_DATA 0x61178
2371 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2372 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2373 * of the infoframe structure specified by CEA-861. */
2374 #define VIDEO_DIP_DATA_SIZE 32
2375 #define VIDEO_DIP_VSC_DATA_SIZE 36
2376 #define VIDEO_DIP_CTL 0x61170
2378 #define VIDEO_DIP_ENABLE (1 << 31)
2379 #define VIDEO_DIP_PORT(port) ((port) << 29)
2380 #define VIDEO_DIP_PORT_MASK (3 << 29)
2381 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
2382 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2383 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2384 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
2385 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2386 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2387 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2388 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2389 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2390 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2391 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2392 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2393 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2394 /* HSW and later: */
2395 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2396 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2397 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2398 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2399 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2400 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2402 /* Panel power sequencing */
2403 #define PP_STATUS 0x61200
2404 #define PP_ON (1 << 31)
2406 * Indicates that all dependencies of the panel are on:
2410 * - LVDS/DVOB/DVOC on
2412 #define PP_READY (1 << 30)
2413 #define PP_SEQUENCE_NONE (0 << 28)
2414 #define PP_SEQUENCE_POWER_UP (1 << 28)
2415 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
2416 #define PP_SEQUENCE_MASK (3 << 28)
2417 #define PP_SEQUENCE_SHIFT 28
2418 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
2419 #define PP_SEQUENCE_STATE_MASK 0x0000000f
2420 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2421 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2422 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2423 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2424 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2425 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2426 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2427 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2428 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
2429 #define PP_CONTROL 0x61204
2430 #define POWER_TARGET_ON (1 << 0)
2431 #define PP_ON_DELAYS 0x61208
2432 #define PP_OFF_DELAYS 0x6120c
2433 #define PP_DIVISOR 0x61210
2436 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
2437 #define PFIT_ENABLE (1 << 31)
2438 #define PFIT_PIPE_MASK (3 << 29)
2439 #define PFIT_PIPE_SHIFT 29
2440 #define VERT_INTERP_DISABLE (0 << 10)
2441 #define VERT_INTERP_BILINEAR (1 << 10)
2442 #define VERT_INTERP_MASK (3 << 10)
2443 #define VERT_AUTO_SCALE (1 << 9)
2444 #define HORIZ_INTERP_DISABLE (0 << 6)
2445 #define HORIZ_INTERP_BILINEAR (1 << 6)
2446 #define HORIZ_INTERP_MASK (3 << 6)
2447 #define HORIZ_AUTO_SCALE (1 << 5)
2448 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2449 #define PFIT_FILTER_FUZZY (0 << 24)
2450 #define PFIT_SCALING_AUTO (0 << 26)
2451 #define PFIT_SCALING_PROGRAMMED (1 << 26)
2452 #define PFIT_SCALING_PILLAR (2 << 26)
2453 #define PFIT_SCALING_LETTER (3 << 26)
2454 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
2456 #define PFIT_VERT_SCALE_SHIFT 20
2457 #define PFIT_VERT_SCALE_MASK 0xfff00000
2458 #define PFIT_HORIZ_SCALE_SHIFT 4
2459 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2461 #define PFIT_VERT_SCALE_SHIFT_965 16
2462 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2463 #define PFIT_HORIZ_SCALE_SHIFT_965 0
2464 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2466 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
2468 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2469 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
2470 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2471 _VLV_BLC_PWM_CTL2_B)
2473 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2474 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
2475 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2478 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
2479 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
2480 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2481 _VLV_BLC_HIST_CTL_B)
2483 /* Backlight control */
2484 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
2485 #define BLM_PWM_ENABLE (1 << 31)
2486 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2487 #define BLM_PIPE_SELECT (1 << 29)
2488 #define BLM_PIPE_SELECT_IVB (3 << 29)
2489 #define BLM_PIPE_A (0 << 29)
2490 #define BLM_PIPE_B (1 << 29)
2491 #define BLM_PIPE_C (2 << 29) /* ivb + */
2492 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2493 #define BLM_TRANSCODER_B BLM_PIPE_B
2494 #define BLM_TRANSCODER_C BLM_PIPE_C
2495 #define BLM_TRANSCODER_EDP (3 << 29)
2496 #define BLM_PIPE(pipe) ((pipe) << 29)
2497 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2498 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2499 #define BLM_PHASE_IN_ENABLE (1 << 25)
2500 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2501 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2502 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2503 #define BLM_PHASE_IN_COUNT_SHIFT (8)
2504 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2505 #define BLM_PHASE_IN_INCR_SHIFT (0)
2506 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
2507 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
2509 * This is the most significant 15 bits of the number of backlight cycles in a
2510 * complete cycle of the modulated backlight control.
2512 * The actual value is this field multiplied by two.
2514 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2515 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2516 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
2518 * This is the number of cycles out of the backlight modulation cycle for which
2519 * the backlight is on.
2521 * This field must be no greater than the number of cycles in the complete
2522 * backlight modulation cycle.
2524 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2525 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
2526 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2527 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
2529 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
2531 /* New registers for PCH-split platforms. Safe where new bits show up, the
2532 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2533 #define BLC_PWM_CPU_CTL2 0x48250
2534 #define BLC_PWM_CPU_CTL 0x48254
2536 #define HSW_BLC_PWM2_CTL 0x48350
2538 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2539 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2540 #define BLC_PWM_PCH_CTL1 0xc8250
2541 #define BLM_PCH_PWM_ENABLE (1 << 31)
2542 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2543 #define BLM_PCH_POLARITY (1 << 29)
2544 #define BLC_PWM_PCH_CTL2 0xc8254
2546 #define UTIL_PIN_CTL 0x48400
2547 #define UTIL_PIN_ENABLE (1 << 31)
2549 #define PCH_GTC_CTL 0xe7000
2550 #define PCH_GTC_ENABLE (1 << 31)
2552 /* TV port control */
2553 #define TV_CTL 0x68000
2554 /** Enables the TV encoder */
2555 # define TV_ENC_ENABLE (1 << 31)
2556 /** Sources the TV encoder input from pipe B instead of A. */
2557 # define TV_ENC_PIPEB_SELECT (1 << 30)
2558 /** Outputs composite video (DAC A only) */
2559 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2560 /** Outputs SVideo video (DAC B/C) */
2561 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2562 /** Outputs Component video (DAC A/B/C) */
2563 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2564 /** Outputs Composite and SVideo (DAC A/B/C) */
2565 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2566 # define TV_TRILEVEL_SYNC (1 << 21)
2567 /** Enables slow sync generation (945GM only) */
2568 # define TV_SLOW_SYNC (1 << 20)
2569 /** Selects 4x oversampling for 480i and 576p */
2570 # define TV_OVERSAMPLE_4X (0 << 18)
2571 /** Selects 2x oversampling for 720p and 1080i */
2572 # define TV_OVERSAMPLE_2X (1 << 18)
2573 /** Selects no oversampling for 1080p */
2574 # define TV_OVERSAMPLE_NONE (2 << 18)
2575 /** Selects 8x oversampling */
2576 # define TV_OVERSAMPLE_8X (3 << 18)
2577 /** Selects progressive mode rather than interlaced */
2578 # define TV_PROGRESSIVE (1 << 17)
2579 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2580 # define TV_PAL_BURST (1 << 16)
2581 /** Field for setting delay of Y compared to C */
2582 # define TV_YC_SKEW_MASK (7 << 12)
2583 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2584 # define TV_ENC_SDP_FIX (1 << 11)
2586 * Enables a fix for the 915GM only.
2588 * Not sure what it does.
2590 # define TV_ENC_C0_FIX (1 << 10)
2591 /** Bits that must be preserved by software */
2592 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2593 # define TV_FUSE_STATE_MASK (3 << 4)
2594 /** Read-only state that reports all features enabled */
2595 # define TV_FUSE_STATE_ENABLED (0 << 4)
2596 /** Read-only state that reports that Macrovision is disabled in hardware*/
2597 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2598 /** Read-only state that reports that TV-out is disabled in hardware. */
2599 # define TV_FUSE_STATE_DISABLED (2 << 4)
2600 /** Normal operation */
2601 # define TV_TEST_MODE_NORMAL (0 << 0)
2602 /** Encoder test pattern 1 - combo pattern */
2603 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2604 /** Encoder test pattern 2 - full screen vertical 75% color bars */
2605 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2606 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
2607 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2608 /** Encoder test pattern 4 - random noise */
2609 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2610 /** Encoder test pattern 5 - linear color ramps */
2611 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2613 * This test mode forces the DACs to 50% of full output.
2615 * This is used for load detection in combination with TVDAC_SENSE_MASK
2617 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2618 # define TV_TEST_MODE_MASK (7 << 0)
2620 #define TV_DAC 0x68004
2621 # define TV_DAC_SAVE 0x00ffff00
2623 * Reports that DAC state change logic has reported change (RO).
2625 * This gets cleared when TV_DAC_STATE_EN is cleared
2627 # define TVDAC_STATE_CHG (1 << 31)
2628 # define TVDAC_SENSE_MASK (7 << 28)
2629 /** Reports that DAC A voltage is above the detect threshold */
2630 # define TVDAC_A_SENSE (1 << 30)
2631 /** Reports that DAC B voltage is above the detect threshold */
2632 # define TVDAC_B_SENSE (1 << 29)
2633 /** Reports that DAC C voltage is above the detect threshold */
2634 # define TVDAC_C_SENSE (1 << 28)
2636 * Enables DAC state detection logic, for load-based TV detection.
2638 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2639 * to off, for load detection to work.
2641 # define TVDAC_STATE_CHG_EN (1 << 27)
2642 /** Sets the DAC A sense value to high */
2643 # define TVDAC_A_SENSE_CTL (1 << 26)
2644 /** Sets the DAC B sense value to high */
2645 # define TVDAC_B_SENSE_CTL (1 << 25)
2646 /** Sets the DAC C sense value to high */
2647 # define TVDAC_C_SENSE_CTL (1 << 24)
2648 /** Overrides the ENC_ENABLE and DAC voltage levels */
2649 # define DAC_CTL_OVERRIDE (1 << 7)
2650 /** Sets the slew rate. Must be preserved in software */
2651 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2652 # define DAC_A_1_3_V (0 << 4)
2653 # define DAC_A_1_1_V (1 << 4)
2654 # define DAC_A_0_7_V (2 << 4)
2655 # define DAC_A_MASK (3 << 4)
2656 # define DAC_B_1_3_V (0 << 2)
2657 # define DAC_B_1_1_V (1 << 2)
2658 # define DAC_B_0_7_V (2 << 2)
2659 # define DAC_B_MASK (3 << 2)
2660 # define DAC_C_1_3_V (0 << 0)
2661 # define DAC_C_1_1_V (1 << 0)
2662 # define DAC_C_0_7_V (2 << 0)
2663 # define DAC_C_MASK (3 << 0)
2666 * CSC coefficients are stored in a floating point format with 9 bits of
2667 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2668 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2669 * -1 (0x3) being the only legal negative value.
2671 #define TV_CSC_Y 0x68010
2672 # define TV_RY_MASK 0x07ff0000
2673 # define TV_RY_SHIFT 16
2674 # define TV_GY_MASK 0x00000fff
2675 # define TV_GY_SHIFT 0
2677 #define TV_CSC_Y2 0x68014
2678 # define TV_BY_MASK 0x07ff0000
2679 # define TV_BY_SHIFT 16
2681 * Y attenuation for component video.
2683 * Stored in 1.9 fixed point.
2685 # define TV_AY_MASK 0x000003ff
2686 # define TV_AY_SHIFT 0
2688 #define TV_CSC_U 0x68018
2689 # define TV_RU_MASK 0x07ff0000
2690 # define TV_RU_SHIFT 16
2691 # define TV_GU_MASK 0x000007ff
2692 # define TV_GU_SHIFT 0
2694 #define TV_CSC_U2 0x6801c
2695 # define TV_BU_MASK 0x07ff0000
2696 # define TV_BU_SHIFT 16
2698 * U attenuation for component video.
2700 * Stored in 1.9 fixed point.
2702 # define TV_AU_MASK 0x000003ff
2703 # define TV_AU_SHIFT 0
2705 #define TV_CSC_V 0x68020
2706 # define TV_RV_MASK 0x0fff0000
2707 # define TV_RV_SHIFT 16
2708 # define TV_GV_MASK 0x000007ff
2709 # define TV_GV_SHIFT 0
2711 #define TV_CSC_V2 0x68024
2712 # define TV_BV_MASK 0x07ff0000
2713 # define TV_BV_SHIFT 16
2715 * V attenuation for component video.
2717 * Stored in 1.9 fixed point.
2719 # define TV_AV_MASK 0x000007ff
2720 # define TV_AV_SHIFT 0
2722 #define TV_CLR_KNOBS 0x68028
2723 /** 2s-complement brightness adjustment */
2724 # define TV_BRIGHTNESS_MASK 0xff000000
2725 # define TV_BRIGHTNESS_SHIFT 24
2726 /** Contrast adjustment, as a 2.6 unsigned floating point number */
2727 # define TV_CONTRAST_MASK 0x00ff0000
2728 # define TV_CONTRAST_SHIFT 16
2729 /** Saturation adjustment, as a 2.6 unsigned floating point number */
2730 # define TV_SATURATION_MASK 0x0000ff00
2731 # define TV_SATURATION_SHIFT 8
2732 /** Hue adjustment, as an integer phase angle in degrees */
2733 # define TV_HUE_MASK 0x000000ff
2734 # define TV_HUE_SHIFT 0
2736 #define TV_CLR_LEVEL 0x6802c
2737 /** Controls the DAC level for black */
2738 # define TV_BLACK_LEVEL_MASK 0x01ff0000
2739 # define TV_BLACK_LEVEL_SHIFT 16
2740 /** Controls the DAC level for blanking */
2741 # define TV_BLANK_LEVEL_MASK 0x000001ff
2742 # define TV_BLANK_LEVEL_SHIFT 0
2744 #define TV_H_CTL_1 0x68030
2745 /** Number of pixels in the hsync. */
2746 # define TV_HSYNC_END_MASK 0x1fff0000
2747 # define TV_HSYNC_END_SHIFT 16
2748 /** Total number of pixels minus one in the line (display and blanking). */
2749 # define TV_HTOTAL_MASK 0x00001fff
2750 # define TV_HTOTAL_SHIFT 0
2752 #define TV_H_CTL_2 0x68034
2753 /** Enables the colorburst (needed for non-component color) */
2754 # define TV_BURST_ENA (1 << 31)
2755 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2756 # define TV_HBURST_START_SHIFT 16
2757 # define TV_HBURST_START_MASK 0x1fff0000
2758 /** Length of the colorburst */
2759 # define TV_HBURST_LEN_SHIFT 0
2760 # define TV_HBURST_LEN_MASK 0x0001fff
2762 #define TV_H_CTL_3 0x68038
2763 /** End of hblank, measured in pixels minus one from start of hsync */
2764 # define TV_HBLANK_END_SHIFT 16
2765 # define TV_HBLANK_END_MASK 0x1fff0000
2766 /** Start of hblank, measured in pixels minus one from start of hsync */
2767 # define TV_HBLANK_START_SHIFT 0
2768 # define TV_HBLANK_START_MASK 0x0001fff
2770 #define TV_V_CTL_1 0x6803c
2772 # define TV_NBR_END_SHIFT 16
2773 # define TV_NBR_END_MASK 0x07ff0000
2775 # define TV_VI_END_F1_SHIFT 8
2776 # define TV_VI_END_F1_MASK 0x00003f00
2778 # define TV_VI_END_F2_SHIFT 0
2779 # define TV_VI_END_F2_MASK 0x0000003f
2781 #define TV_V_CTL_2 0x68040
2782 /** Length of vsync, in half lines */
2783 # define TV_VSYNC_LEN_MASK 0x07ff0000
2784 # define TV_VSYNC_LEN_SHIFT 16
2785 /** Offset of the start of vsync in field 1, measured in one less than the
2786 * number of half lines.
2788 # define TV_VSYNC_START_F1_MASK 0x00007f00
2789 # define TV_VSYNC_START_F1_SHIFT 8
2791 * Offset of the start of vsync in field 2, measured in one less than the
2792 * number of half lines.
2794 # define TV_VSYNC_START_F2_MASK 0x0000007f
2795 # define TV_VSYNC_START_F2_SHIFT 0
2797 #define TV_V_CTL_3 0x68044
2798 /** Enables generation of the equalization signal */
2799 # define TV_EQUAL_ENA (1 << 31)
2800 /** Length of vsync, in half lines */
2801 # define TV_VEQ_LEN_MASK 0x007f0000
2802 # define TV_VEQ_LEN_SHIFT 16
2803 /** Offset of the start of equalization in field 1, measured in one less than
2804 * the number of half lines.
2806 # define TV_VEQ_START_F1_MASK 0x0007f00
2807 # define TV_VEQ_START_F1_SHIFT 8
2809 * Offset of the start of equalization in field 2, measured in one less than
2810 * the number of half lines.
2812 # define TV_VEQ_START_F2_MASK 0x000007f
2813 # define TV_VEQ_START_F2_SHIFT 0
2815 #define TV_V_CTL_4 0x68048
2817 * Offset to start of vertical colorburst, measured in one less than the
2818 * number of lines from vertical start.
2820 # define TV_VBURST_START_F1_MASK 0x003f0000
2821 # define TV_VBURST_START_F1_SHIFT 16
2823 * Offset to the end of vertical colorburst, measured in one less than the
2824 * number of lines from the start of NBR.
2826 # define TV_VBURST_END_F1_MASK 0x000000ff
2827 # define TV_VBURST_END_F1_SHIFT 0
2829 #define TV_V_CTL_5 0x6804c
2831 * Offset to start of vertical colorburst, measured in one less than the
2832 * number of lines from vertical start.
2834 # define TV_VBURST_START_F2_MASK 0x003f0000
2835 # define TV_VBURST_START_F2_SHIFT 16
2837 * Offset to the end of vertical colorburst, measured in one less than the
2838 * number of lines from the start of NBR.
2840 # define TV_VBURST_END_F2_MASK 0x000000ff
2841 # define TV_VBURST_END_F2_SHIFT 0
2843 #define TV_V_CTL_6 0x68050
2845 * Offset to start of vertical colorburst, measured in one less than the
2846 * number of lines from vertical start.
2848 # define TV_VBURST_START_F3_MASK 0x003f0000
2849 # define TV_VBURST_START_F3_SHIFT 16
2851 * Offset to the end of vertical colorburst, measured in one less than the
2852 * number of lines from the start of NBR.
2854 # define TV_VBURST_END_F3_MASK 0x000000ff
2855 # define TV_VBURST_END_F3_SHIFT 0
2857 #define TV_V_CTL_7 0x68054
2859 * Offset to start of vertical colorburst, measured in one less than the
2860 * number of lines from vertical start.
2862 # define TV_VBURST_START_F4_MASK 0x003f0000
2863 # define TV_VBURST_START_F4_SHIFT 16
2865 * Offset to the end of vertical colorburst, measured in one less than the
2866 * number of lines from the start of NBR.
2868 # define TV_VBURST_END_F4_MASK 0x000000ff
2869 # define TV_VBURST_END_F4_SHIFT 0
2871 #define TV_SC_CTL_1 0x68060
2872 /** Turns on the first subcarrier phase generation DDA */
2873 # define TV_SC_DDA1_EN (1 << 31)
2874 /** Turns on the first subcarrier phase generation DDA */
2875 # define TV_SC_DDA2_EN (1 << 30)
2876 /** Turns on the first subcarrier phase generation DDA */
2877 # define TV_SC_DDA3_EN (1 << 29)
2878 /** Sets the subcarrier DDA to reset frequency every other field */
2879 # define TV_SC_RESET_EVERY_2 (0 << 24)
2880 /** Sets the subcarrier DDA to reset frequency every fourth field */
2881 # define TV_SC_RESET_EVERY_4 (1 << 24)
2882 /** Sets the subcarrier DDA to reset frequency every eighth field */
2883 # define TV_SC_RESET_EVERY_8 (2 << 24)
2884 /** Sets the subcarrier DDA to never reset the frequency */
2885 # define TV_SC_RESET_NEVER (3 << 24)
2886 /** Sets the peak amplitude of the colorburst.*/
2887 # define TV_BURST_LEVEL_MASK 0x00ff0000
2888 # define TV_BURST_LEVEL_SHIFT 16
2889 /** Sets the increment of the first subcarrier phase generation DDA */
2890 # define TV_SCDDA1_INC_MASK 0x00000fff
2891 # define TV_SCDDA1_INC_SHIFT 0
2893 #define TV_SC_CTL_2 0x68064
2894 /** Sets the rollover for the second subcarrier phase generation DDA */
2895 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2896 # define TV_SCDDA2_SIZE_SHIFT 16
2897 /** Sets the increent of the second subcarrier phase generation DDA */
2898 # define TV_SCDDA2_INC_MASK 0x00007fff
2899 # define TV_SCDDA2_INC_SHIFT 0
2901 #define TV_SC_CTL_3 0x68068
2902 /** Sets the rollover for the third subcarrier phase generation DDA */
2903 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2904 # define TV_SCDDA3_SIZE_SHIFT 16
2905 /** Sets the increent of the third subcarrier phase generation DDA */
2906 # define TV_SCDDA3_INC_MASK 0x00007fff
2907 # define TV_SCDDA3_INC_SHIFT 0
2909 #define TV_WIN_POS 0x68070
2910 /** X coordinate of the display from the start of horizontal active */
2911 # define TV_XPOS_MASK 0x1fff0000
2912 # define TV_XPOS_SHIFT 16
2913 /** Y coordinate of the display from the start of vertical active (NBR) */
2914 # define TV_YPOS_MASK 0x00000fff
2915 # define TV_YPOS_SHIFT 0
2917 #define TV_WIN_SIZE 0x68074
2918 /** Horizontal size of the display window, measured in pixels*/
2919 # define TV_XSIZE_MASK 0x1fff0000
2920 # define TV_XSIZE_SHIFT 16
2922 * Vertical size of the display window, measured in pixels.
2924 * Must be even for interlaced modes.
2926 # define TV_YSIZE_MASK 0x00000fff
2927 # define TV_YSIZE_SHIFT 0
2929 #define TV_FILTER_CTL_1 0x68080
2931 * Enables automatic scaling calculation.
2933 * If set, the rest of the registers are ignored, and the calculated values can
2934 * be read back from the register.
2936 # define TV_AUTO_SCALE (1 << 31)
2938 * Disables the vertical filter.
2940 * This is required on modes more than 1024 pixels wide */
2941 # define TV_V_FILTER_BYPASS (1 << 29)
2942 /** Enables adaptive vertical filtering */
2943 # define TV_VADAPT (1 << 28)
2944 # define TV_VADAPT_MODE_MASK (3 << 26)
2945 /** Selects the least adaptive vertical filtering mode */
2946 # define TV_VADAPT_MODE_LEAST (0 << 26)
2947 /** Selects the moderately adaptive vertical filtering mode */
2948 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2949 /** Selects the most adaptive vertical filtering mode */
2950 # define TV_VADAPT_MODE_MOST (3 << 26)
2952 * Sets the horizontal scaling factor.
2954 * This should be the fractional part of the horizontal scaling factor divided
2955 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2957 * (src width - 1) / ((oversample * dest width) - 1)
2959 # define TV_HSCALE_FRAC_MASK 0x00003fff
2960 # define TV_HSCALE_FRAC_SHIFT 0
2962 #define TV_FILTER_CTL_2 0x68084
2964 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2966 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2968 # define TV_VSCALE_INT_MASK 0x00038000
2969 # define TV_VSCALE_INT_SHIFT 15
2971 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2973 * \sa TV_VSCALE_INT_MASK
2975 # define TV_VSCALE_FRAC_MASK 0x00007fff
2976 # define TV_VSCALE_FRAC_SHIFT 0
2978 #define TV_FILTER_CTL_3 0x68088
2980 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2982 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2984 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2986 # define TV_VSCALE_IP_INT_MASK 0x00038000
2987 # define TV_VSCALE_IP_INT_SHIFT 15
2989 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2991 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2993 * \sa TV_VSCALE_IP_INT_MASK
2995 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2996 # define TV_VSCALE_IP_FRAC_SHIFT 0
2998 #define TV_CC_CONTROL 0x68090
2999 # define TV_CC_ENABLE (1 << 31)
3001 * Specifies which field to send the CC data in.
3003 * CC data is usually sent in field 0.
3005 # define TV_CC_FID_MASK (1 << 27)
3006 # define TV_CC_FID_SHIFT 27
3007 /** Sets the horizontal position of the CC data. Usually 135. */
3008 # define TV_CC_HOFF_MASK 0x03ff0000
3009 # define TV_CC_HOFF_SHIFT 16
3010 /** Sets the vertical position of the CC data. Usually 21 */
3011 # define TV_CC_LINE_MASK 0x0000003f
3012 # define TV_CC_LINE_SHIFT 0
3014 #define TV_CC_DATA 0x68094
3015 # define TV_CC_RDY (1 << 31)
3016 /** Second word of CC data to be transmitted. */
3017 # define TV_CC_DATA_2_MASK 0x007f0000
3018 # define TV_CC_DATA_2_SHIFT 16
3019 /** First word of CC data to be transmitted. */
3020 # define TV_CC_DATA_1_MASK 0x0000007f
3021 # define TV_CC_DATA_1_SHIFT 0
3023 #define TV_H_LUMA_0 0x68100
3024 #define TV_H_LUMA_59 0x681ec
3025 #define TV_H_CHROMA_0 0x68200
3026 #define TV_H_CHROMA_59 0x682ec
3027 #define TV_V_LUMA_0 0x68300
3028 #define TV_V_LUMA_42 0x683a8
3029 #define TV_V_CHROMA_0 0x68400
3030 #define TV_V_CHROMA_42 0x684a8
3033 #define DP_A 0x64000 /* eDP */
3034 #define DP_B 0x64100
3035 #define DP_C 0x64200
3036 #define DP_D 0x64300
3038 #define DP_PORT_EN (1 << 31)
3039 #define DP_PIPEB_SELECT (1 << 30)
3040 #define DP_PIPE_MASK (1 << 30)
3042 /* Link training mode - select a suitable mode for each stage */
3043 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
3044 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
3045 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3046 #define DP_LINK_TRAIN_OFF (3 << 28)
3047 #define DP_LINK_TRAIN_MASK (3 << 28)
3048 #define DP_LINK_TRAIN_SHIFT 28
3050 /* CPT Link training mode */
3051 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3052 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3053 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3054 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3055 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3056 #define DP_LINK_TRAIN_SHIFT_CPT 8
3058 /* Signal voltages. These are mostly controlled by the other end */
3059 #define DP_VOLTAGE_0_4 (0 << 25)
3060 #define DP_VOLTAGE_0_6 (1 << 25)
3061 #define DP_VOLTAGE_0_8 (2 << 25)
3062 #define DP_VOLTAGE_1_2 (3 << 25)
3063 #define DP_VOLTAGE_MASK (7 << 25)
3064 #define DP_VOLTAGE_SHIFT 25
3066 /* Signal pre-emphasis levels, like voltages, the other end tells us what
3069 #define DP_PRE_EMPHASIS_0 (0 << 22)
3070 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
3071 #define DP_PRE_EMPHASIS_6 (2 << 22)
3072 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
3073 #define DP_PRE_EMPHASIS_MASK (7 << 22)
3074 #define DP_PRE_EMPHASIS_SHIFT 22
3076 /* How many wires to use. I guess 3 was too hard */
3077 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3078 #define DP_PORT_WIDTH_MASK (7 << 19)
3080 /* Mystic DPCD version 1.1 special mode */
3081 #define DP_ENHANCED_FRAMING (1 << 18)
3084 #define DP_PLL_FREQ_270MHZ (0 << 16)
3085 #define DP_PLL_FREQ_160MHZ (1 << 16)
3086 #define DP_PLL_FREQ_MASK (3 << 16)
3088 /** locked once port is enabled */
3089 #define DP_PORT_REVERSAL (1 << 15)
3092 #define DP_PLL_ENABLE (1 << 14)
3094 /** sends the clock on lane 15 of the PEG for debug */
3095 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3097 #define DP_SCRAMBLING_DISABLE (1 << 12)
3098 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3100 /** limit RGB values to avoid confusing TVs */
3101 #define DP_COLOR_RANGE_16_235 (1 << 8)
3103 /** Turn on the audio link */
3104 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3106 /** vs and hs sync polarity */
3107 #define DP_SYNC_VS_HIGH (1 << 4)
3108 #define DP_SYNC_HS_HIGH (1 << 3)
3111 #define DP_DETECTED (1 << 2)
3113 /** The aux channel provides a way to talk to the
3114 * signal sink for DDC etc. Max packet size supported
3115 * is 20 bytes in each direction, hence the 5 fixed
3118 #define DPA_AUX_CH_CTL 0x64010
3119 #define DPA_AUX_CH_DATA1 0x64014
3120 #define DPA_AUX_CH_DATA2 0x64018
3121 #define DPA_AUX_CH_DATA3 0x6401c
3122 #define DPA_AUX_CH_DATA4 0x64020
3123 #define DPA_AUX_CH_DATA5 0x64024
3125 #define DPB_AUX_CH_CTL 0x64110
3126 #define DPB_AUX_CH_DATA1 0x64114
3127 #define DPB_AUX_CH_DATA2 0x64118
3128 #define DPB_AUX_CH_DATA3 0x6411c
3129 #define DPB_AUX_CH_DATA4 0x64120
3130 #define DPB_AUX_CH_DATA5 0x64124
3132 #define DPC_AUX_CH_CTL 0x64210
3133 #define DPC_AUX_CH_DATA1 0x64214
3134 #define DPC_AUX_CH_DATA2 0x64218
3135 #define DPC_AUX_CH_DATA3 0x6421c
3136 #define DPC_AUX_CH_DATA4 0x64220
3137 #define DPC_AUX_CH_DATA5 0x64224
3139 #define DPD_AUX_CH_CTL 0x64310
3140 #define DPD_AUX_CH_DATA1 0x64314
3141 #define DPD_AUX_CH_DATA2 0x64318
3142 #define DPD_AUX_CH_DATA3 0x6431c
3143 #define DPD_AUX_CH_DATA4 0x64320
3144 #define DPD_AUX_CH_DATA5 0x64324
3146 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3147 #define DP_AUX_CH_CTL_DONE (1 << 30)
3148 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3149 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3150 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3151 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3152 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3153 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3154 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3155 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3156 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3157 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3158 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3159 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3160 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3161 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3162 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3163 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3164 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3165 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3166 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3169 * Computing GMCH M and N values for the Display Port link
3171 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3173 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3175 * The GMCH value is used internally
3177 * bytes_per_pixel is the number of bytes coming out of the plane,
3178 * which is after the LUTs, so we want the bytes for our color format.
3179 * For our current usage, this is always 3, one byte for R, G and B.
3181 #define _PIPEA_DATA_M_G4X 0x70050
3182 #define _PIPEB_DATA_M_G4X 0x71050
3184 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3185 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3186 #define TU_SIZE_SHIFT 25
3187 #define TU_SIZE_MASK (0x3f << 25)
3189 #define DATA_LINK_M_N_MASK (0xffffff)
3190 #define DATA_LINK_N_MAX (0x800000)
3192 #define _PIPEA_DATA_N_G4X 0x70054
3193 #define _PIPEB_DATA_N_G4X 0x71054
3194 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
3197 * Computing Link M and N values for the Display Port link
3199 * Link M / N = pixel_clock / ls_clk
3201 * (the DP spec calls pixel_clock the 'strm_clk')
3203 * The Link value is transmitted in the Main Stream
3204 * Attributes and VB-ID.
3207 #define _PIPEA_LINK_M_G4X 0x70060
3208 #define _PIPEB_LINK_M_G4X 0x71060
3209 #define PIPEA_DP_LINK_M_MASK (0xffffff)
3211 #define _PIPEA_LINK_N_G4X 0x70064
3212 #define _PIPEB_LINK_N_G4X 0x71064
3213 #define PIPEA_DP_LINK_N_MASK (0xffffff)
3215 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3216 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3217 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3218 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3220 /* Display & cursor control */
3223 #define _PIPEADSL 0x70000
3224 #define DSL_LINEMASK_GEN2 0x00000fff
3225 #define DSL_LINEMASK_GEN3 0x00001fff
3226 #define _PIPEACONF 0x70008
3227 #define PIPECONF_ENABLE (1<<31)
3228 #define PIPECONF_DISABLE 0
3229 #define PIPECONF_DOUBLE_WIDE (1<<30)
3230 #define I965_PIPECONF_ACTIVE (1<<30)
3231 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
3232 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
3233 #define PIPECONF_SINGLE_WIDE 0
3234 #define PIPECONF_PIPE_UNLOCKED 0
3235 #define PIPECONF_PIPE_LOCKED (1<<25)
3236 #define PIPECONF_PALETTE 0
3237 #define PIPECONF_GAMMA (1<<24)
3238 #define PIPECONF_FORCE_BORDER (1<<25)
3239 #define PIPECONF_INTERLACE_MASK (7 << 21)
3240 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
3241 /* Note that pre-gen3 does not support interlaced display directly. Panel
3242 * fitting must be disabled on pre-ilk for interlaced. */
3243 #define PIPECONF_PROGRESSIVE (0 << 21)
3244 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3245 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3246 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3247 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3248 /* Ironlake and later have a complete new set of values for interlaced. PFIT
3249 * means panel fitter required, PF means progressive fetch, DBL means power
3250 * saving pixel doubling. */
3251 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3252 #define PIPECONF_INTERLACED_ILK (3 << 21)
3253 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3254 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
3255 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
3256 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
3257 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
3258 #define PIPECONF_BPC_MASK (0x7 << 5)
3259 #define PIPECONF_8BPC (0<<5)
3260 #define PIPECONF_10BPC (1<<5)
3261 #define PIPECONF_6BPC (2<<5)
3262 #define PIPECONF_12BPC (3<<5)
3263 #define PIPECONF_DITHER_EN (1<<4)
3264 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3265 #define PIPECONF_DITHER_TYPE_SP (0<<2)
3266 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3267 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3268 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3269 #define _PIPEASTAT 0x70024
3270 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3271 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
3272 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3273 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
3274 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
3275 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
3276 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3277 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3278 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3279 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
3280 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
3281 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3282 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3283 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3284 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
3285 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3286 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3287 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
3288 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
3289 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
3290 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3291 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
3292 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3293 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3294 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
3295 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
3296 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3297 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3298 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3299 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
3300 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3301 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
3302 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3303 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3304 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
3305 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3306 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3307 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3308 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3310 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3311 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3313 #define PIPE_A_OFFSET 0x70000
3314 #define PIPE_B_OFFSET 0x71000
3315 #define PIPE_C_OFFSET 0x72000
3317 * There's actually no pipe EDP. Some pipe registers have
3318 * simply shifted from the pipe to the transcoder, while
3319 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3320 * to access such registers in transcoder EDP.
3322 #define PIPE_EDP_OFFSET 0x7f000
3324 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3325 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3326 dev_priv->info.display_mmio_offset)
3328 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3329 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3330 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3331 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3332 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
3334 #define _PIPE_MISC_A 0x70030
3335 #define _PIPE_MISC_B 0x71030
3336 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
3337 #define PIPEMISC_DITHER_8_BPC (0<<5)
3338 #define PIPEMISC_DITHER_10_BPC (1<<5)
3339 #define PIPEMISC_DITHER_6_BPC (2<<5)
3340 #define PIPEMISC_DITHER_12_BPC (3<<5)
3341 #define PIPEMISC_DITHER_ENABLE (1<<4)
3342 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3343 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
3344 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
3346 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3347 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
3348 #define PIPEB_HLINE_INT_EN (1<<28)
3349 #define PIPEB_VBLANK_INT_EN (1<<27)
3350 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
3351 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3352 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
3353 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
3354 #define PIPEA_HLINE_INT_EN (1<<20)
3355 #define PIPEA_VBLANK_INT_EN (1<<19)
3356 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3357 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
3358 #define PLANEA_FLIPDONE_INT_EN (1<<16)
3360 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3361 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
3362 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
3363 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
3364 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3365 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
3366 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3367 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3368 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
3369 #define DPINVGTT_EN_MASK 0xff0000
3370 #define CURSORB_INVALID_GTT_STATUS (1<<7)
3371 #define CURSORA_INVALID_GTT_STATUS (1<<6)
3372 #define SPRITED_INVALID_GTT_STATUS (1<<5)
3373 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
3374 #define PLANEB_INVALID_GTT_STATUS (1<<3)
3375 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
3376 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
3377 #define PLANEA_INVALID_GTT_STATUS (1<<0)
3378 #define DPINVGTT_STATUS_MASK 0xff
3380 #define DSPARB 0x70030
3381 #define DSPARB_CSTART_MASK (0x7f << 7)
3382 #define DSPARB_CSTART_SHIFT 7
3383 #define DSPARB_BSTART_MASK (0x7f)
3384 #define DSPARB_BSTART_SHIFT 0
3385 #define DSPARB_BEND_SHIFT 9 /* on 855 */
3386 #define DSPARB_AEND_SHIFT 0
3388 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
3389 #define DSPFW_SR_SHIFT 23
3390 #define DSPFW_SR_MASK (0x1ff<<23)
3391 #define DSPFW_CURSORB_SHIFT 16
3392 #define DSPFW_CURSORB_MASK (0x3f<<16)
3393 #define DSPFW_PLANEB_SHIFT 8
3394 #define DSPFW_PLANEB_MASK (0x7f<<8)
3395 #define DSPFW_PLANEA_MASK (0x7f)
3396 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
3397 #define DSPFW_CURSORA_MASK 0x00003f00
3398 #define DSPFW_CURSORA_SHIFT 8
3399 #define DSPFW_PLANEC_MASK (0x7f)
3400 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
3401 #define DSPFW_HPLL_SR_EN (1<<31)
3402 #define DSPFW_CURSOR_SR_SHIFT 24
3403 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
3404 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3405 #define DSPFW_HPLL_CURSOR_SHIFT 16
3406 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3407 #define DSPFW_HPLL_SR_MASK (0x1ff)
3408 #define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
3409 #define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
3411 /* drain latency register values*/
3412 #define DRAIN_LATENCY_PRECISION_32 32
3413 #define DRAIN_LATENCY_PRECISION_16 16
3414 #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
3415 #define DDL_CURSORA_PRECISION_32 (1<<31)
3416 #define DDL_CURSORA_PRECISION_16 (0<<31)
3417 #define DDL_CURSORA_SHIFT 24
3418 #define DDL_PLANEA_PRECISION_32 (1<<7)
3419 #define DDL_PLANEA_PRECISION_16 (0<<7)
3420 #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
3421 #define DDL_CURSORB_PRECISION_32 (1<<31)
3422 #define DDL_CURSORB_PRECISION_16 (0<<31)
3423 #define DDL_CURSORB_SHIFT 24
3424 #define DDL_PLANEB_PRECISION_32 (1<<7)
3425 #define DDL_PLANEB_PRECISION_16 (0<<7)
3427 /* FIFO watermark sizes etc */
3428 #define G4X_FIFO_LINE_SIZE 64
3429 #define I915_FIFO_LINE_SIZE 64
3430 #define I830_FIFO_LINE_SIZE 32
3432 #define VALLEYVIEW_FIFO_SIZE 255
3433 #define G4X_FIFO_SIZE 127
3434 #define I965_FIFO_SIZE 512
3435 #define I945_FIFO_SIZE 127
3436 #define I915_FIFO_SIZE 95
3437 #define I855GM_FIFO_SIZE 127 /* In cachelines */
3438 #define I830_FIFO_SIZE 95
3440 #define VALLEYVIEW_MAX_WM 0xff
3441 #define G4X_MAX_WM 0x3f
3442 #define I915_MAX_WM 0x3f
3444 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3445 #define PINEVIEW_FIFO_LINE_SIZE 64
3446 #define PINEVIEW_MAX_WM 0x1ff
3447 #define PINEVIEW_DFT_WM 0x3f
3448 #define PINEVIEW_DFT_HPLLOFF_WM 0
3449 #define PINEVIEW_GUARD_WM 10
3450 #define PINEVIEW_CURSOR_FIFO 64
3451 #define PINEVIEW_CURSOR_MAX_WM 0x3f
3452 #define PINEVIEW_CURSOR_DFT_WM 0
3453 #define PINEVIEW_CURSOR_GUARD_WM 5
3455 #define VALLEYVIEW_CURSOR_MAX_WM 64
3456 #define I965_CURSOR_FIFO 64
3457 #define I965_CURSOR_MAX_WM 32
3458 #define I965_CURSOR_DFT_WM 8
3460 /* define the Watermark register on Ironlake */
3461 #define WM0_PIPEA_ILK 0x45100
3462 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
3463 #define WM0_PIPE_PLANE_SHIFT 16
3464 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
3465 #define WM0_PIPE_SPRITE_SHIFT 8
3466 #define WM0_PIPE_CURSOR_MASK (0xff)
3468 #define WM0_PIPEB_ILK 0x45104
3469 #define WM0_PIPEC_IVB 0x45200
3470 #define WM1_LP_ILK 0x45108
3471 #define WM1_LP_SR_EN (1<<31)
3472 #define WM1_LP_LATENCY_SHIFT 24
3473 #define WM1_LP_LATENCY_MASK (0x7f<<24)
3474 #define WM1_LP_FBC_MASK (0xf<<20)
3475 #define WM1_LP_FBC_SHIFT 20
3476 #define WM1_LP_FBC_SHIFT_BDW 19
3477 #define WM1_LP_SR_MASK (0x7ff<<8)
3478 #define WM1_LP_SR_SHIFT 8
3479 #define WM1_LP_CURSOR_MASK (0xff)
3480 #define WM2_LP_ILK 0x4510c
3481 #define WM2_LP_EN (1<<31)
3482 #define WM3_LP_ILK 0x45110
3483 #define WM3_LP_EN (1<<31)
3484 #define WM1S_LP_ILK 0x45120
3485 #define WM2S_LP_IVB 0x45124
3486 #define WM3S_LP_IVB 0x45128
3487 #define WM1S_LP_EN (1<<31)
3489 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3490 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3491 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3493 /* Memory latency timer register */
3494 #define MLTR_ILK 0x11222
3495 #define MLTR_WM1_SHIFT 0
3496 #define MLTR_WM2_SHIFT 8
3497 /* the unit of memory self-refresh latency time is 0.5us */
3498 #define ILK_SRLT_MASK 0x3f
3501 /* the address where we get all kinds of latency value */
3502 #define SSKPD 0x5d10
3503 #define SSKPD_WM_MASK 0x3f
3504 #define SSKPD_WM0_SHIFT 0
3505 #define SSKPD_WM1_SHIFT 8
3506 #define SSKPD_WM2_SHIFT 16
3507 #define SSKPD_WM3_SHIFT 24
3510 * The two pipe frame counter registers are not synchronized, so
3511 * reading a stable value is somewhat tricky. The following code
3515 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3516 * PIPE_FRAME_HIGH_SHIFT;
3517 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3518 * PIPE_FRAME_LOW_SHIFT);
3519 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3520 * PIPE_FRAME_HIGH_SHIFT);
3521 * } while (high1 != high2);
3522 * frame = (high1 << 8) | low1;
3524 #define _PIPEAFRAMEHIGH 0x70040
3525 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
3526 #define PIPE_FRAME_HIGH_SHIFT 0
3527 #define _PIPEAFRAMEPIXEL 0x70044
3528 #define PIPE_FRAME_LOW_MASK 0xff000000
3529 #define PIPE_FRAME_LOW_SHIFT 24
3530 #define PIPE_PIXEL_MASK 0x00ffffff
3531 #define PIPE_PIXEL_SHIFT 0
3532 /* GM45+ just has to be different */
3533 #define _PIPEA_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70040)
3534 #define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70044)
3535 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3537 /* Cursor A & B regs */
3538 #define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080)
3539 /* Old style CUR*CNTR flags (desktop 8xx) */
3540 #define CURSOR_ENABLE 0x80000000
3541 #define CURSOR_GAMMA_ENABLE 0x40000000
3542 #define CURSOR_STRIDE_MASK 0x30000000
3543 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
3544 #define CURSOR_FORMAT_SHIFT 24
3545 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
3546 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
3547 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
3548 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
3549 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
3550 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
3551 /* New style CUR*CNTR flags */
3552 #define CURSOR_MODE 0x27
3553 #define CURSOR_MODE_DISABLE 0x00
3554 #define CURSOR_MODE_64_32B_AX 0x07
3555 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3556 #define MCURSOR_PIPE_SELECT (1 << 28)
3557 #define MCURSOR_PIPE_A 0x00
3558 #define MCURSOR_PIPE_B (1 << 28)
3559 #define MCURSOR_GAMMA_ENABLE (1 << 26)
3560 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
3561 #define _CURABASE (dev_priv->info.display_mmio_offset + 0x70084)
3562 #define _CURAPOS (dev_priv->info.display_mmio_offset + 0x70088)
3563 #define CURSOR_POS_MASK 0x007FF
3564 #define CURSOR_POS_SIGN 0x8000
3565 #define CURSOR_X_SHIFT 0
3566 #define CURSOR_Y_SHIFT 16
3567 #define CURSIZE 0x700a0
3568 #define _CURBCNTR (dev_priv->info.display_mmio_offset + 0x700c0)
3569 #define _CURBBASE (dev_priv->info.display_mmio_offset + 0x700c4)
3570 #define _CURBPOS (dev_priv->info.display_mmio_offset + 0x700c8)
3572 #define _CURBCNTR_IVB 0x71080
3573 #define _CURBBASE_IVB 0x71084
3574 #define _CURBPOS_IVB 0x71088
3576 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3577 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3578 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3580 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3581 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3582 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3584 /* Display A control */
3585 #define _DSPACNTR 0x70180
3586 #define DISPLAY_PLANE_ENABLE (1<<31)
3587 #define DISPLAY_PLANE_DISABLE 0
3588 #define DISPPLANE_GAMMA_ENABLE (1<<30)
3589 #define DISPPLANE_GAMMA_DISABLE 0
3590 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3591 #define DISPPLANE_YUV422 (0x0<<26)
3592 #define DISPPLANE_8BPP (0x2<<26)
3593 #define DISPPLANE_BGRA555 (0x3<<26)
3594 #define DISPPLANE_BGRX555 (0x4<<26)
3595 #define DISPPLANE_BGRX565 (0x5<<26)
3596 #define DISPPLANE_BGRX888 (0x6<<26)
3597 #define DISPPLANE_BGRA888 (0x7<<26)
3598 #define DISPPLANE_RGBX101010 (0x8<<26)
3599 #define DISPPLANE_RGBA101010 (0x9<<26)
3600 #define DISPPLANE_BGRX101010 (0xa<<26)
3601 #define DISPPLANE_RGBX161616 (0xc<<26)
3602 #define DISPPLANE_RGBX888 (0xe<<26)
3603 #define DISPPLANE_RGBA888 (0xf<<26)
3604 #define DISPPLANE_STEREO_ENABLE (1<<25)
3605 #define DISPPLANE_STEREO_DISABLE 0
3606 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
3607 #define DISPPLANE_SEL_PIPE_SHIFT 24
3608 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3609 #define DISPPLANE_SEL_PIPE_A 0
3610 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3611 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3612 #define DISPPLANE_SRC_KEY_DISABLE 0
3613 #define DISPPLANE_LINE_DOUBLE (1<<20)
3614 #define DISPPLANE_NO_LINE_DOUBLE 0
3615 #define DISPPLANE_STEREO_POLARITY_FIRST 0
3616 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3617 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3618 #define DISPPLANE_TILED (1<<10)
3619 #define _DSPAADDR 0x70184
3620 #define _DSPASTRIDE 0x70188
3621 #define _DSPAPOS 0x7018C /* reserved */
3622 #define _DSPASIZE 0x70190
3623 #define _DSPASURF 0x7019C /* 965+ only */
3624 #define _DSPATILEOFF 0x701A4 /* 965+ only */
3625 #define _DSPAOFFSET 0x701A4 /* HSW */
3626 #define _DSPASURFLIVE 0x701AC
3628 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
3629 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
3630 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
3631 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
3632 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
3633 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
3634 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
3635 #define DSPLINOFF(plane) DSPADDR(plane)
3636 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
3637 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
3639 /* Display/Sprite base address macros */
3640 #define DISP_BASEADDR_MASK (0xfffff000)
3641 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3642 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3645 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
3646 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
3647 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
3648 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
3649 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
3650 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
3651 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
3652 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
3653 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
3654 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
3655 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
3656 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
3657 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
3660 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
3661 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
3662 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
3663 #define _PIPEBFRAMEHIGH 0x71040
3664 #define _PIPEBFRAMEPIXEL 0x71044
3665 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
3666 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
3669 /* Display B control */
3670 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
3671 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3672 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
3673 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3674 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3675 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
3676 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
3677 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
3678 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
3679 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
3680 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
3681 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
3682 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
3684 /* Sprite A control */
3685 #define _DVSACNTR 0x72180
3686 #define DVS_ENABLE (1<<31)
3687 #define DVS_GAMMA_ENABLE (1<<30)
3688 #define DVS_PIXFORMAT_MASK (3<<25)
3689 #define DVS_FORMAT_YUV422 (0<<25)
3690 #define DVS_FORMAT_RGBX101010 (1<<25)
3691 #define DVS_FORMAT_RGBX888 (2<<25)
3692 #define DVS_FORMAT_RGBX161616 (3<<25)
3693 #define DVS_PIPE_CSC_ENABLE (1<<24)
3694 #define DVS_SOURCE_KEY (1<<22)
3695 #define DVS_RGB_ORDER_XBGR (1<<20)
3696 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3697 #define DVS_YUV_ORDER_YUYV (0<<16)
3698 #define DVS_YUV_ORDER_UYVY (1<<16)
3699 #define DVS_YUV_ORDER_YVYU (2<<16)
3700 #define DVS_YUV_ORDER_VYUY (3<<16)
3701 #define DVS_DEST_KEY (1<<2)
3702 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
3703 #define DVS_TILED (1<<10)
3704 #define _DVSALINOFF 0x72184
3705 #define _DVSASTRIDE 0x72188
3706 #define _DVSAPOS 0x7218c
3707 #define _DVSASIZE 0x72190
3708 #define _DVSAKEYVAL 0x72194
3709 #define _DVSAKEYMSK 0x72198
3710 #define _DVSASURF 0x7219c
3711 #define _DVSAKEYMAXVAL 0x721a0
3712 #define _DVSATILEOFF 0x721a4
3713 #define _DVSASURFLIVE 0x721ac
3714 #define _DVSASCALE 0x72204
3715 #define DVS_SCALE_ENABLE (1<<31)
3716 #define DVS_FILTER_MASK (3<<29)
3717 #define DVS_FILTER_MEDIUM (0<<29)
3718 #define DVS_FILTER_ENHANCING (1<<29)
3719 #define DVS_FILTER_SOFTENING (2<<29)
3720 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3721 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3722 #define _DVSAGAMC 0x72300
3724 #define _DVSBCNTR 0x73180
3725 #define _DVSBLINOFF 0x73184
3726 #define _DVSBSTRIDE 0x73188
3727 #define _DVSBPOS 0x7318c
3728 #define _DVSBSIZE 0x73190
3729 #define _DVSBKEYVAL 0x73194
3730 #define _DVSBKEYMSK 0x73198
3731 #define _DVSBSURF 0x7319c
3732 #define _DVSBKEYMAXVAL 0x731a0
3733 #define _DVSBTILEOFF 0x731a4
3734 #define _DVSBSURFLIVE 0x731ac
3735 #define _DVSBSCALE 0x73204
3736 #define _DVSBGAMC 0x73300
3738 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3739 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3740 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3741 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3742 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3743 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3744 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3745 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3746 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3747 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3748 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3749 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3751 #define _SPRA_CTL 0x70280
3752 #define SPRITE_ENABLE (1<<31)
3753 #define SPRITE_GAMMA_ENABLE (1<<30)
3754 #define SPRITE_PIXFORMAT_MASK (7<<25)
3755 #define SPRITE_FORMAT_YUV422 (0<<25)
3756 #define SPRITE_FORMAT_RGBX101010 (1<<25)
3757 #define SPRITE_FORMAT_RGBX888 (2<<25)
3758 #define SPRITE_FORMAT_RGBX161616 (3<<25)
3759 #define SPRITE_FORMAT_YUV444 (4<<25)
3760 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
3761 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
3762 #define SPRITE_SOURCE_KEY (1<<22)
3763 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3764 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3765 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3766 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3767 #define SPRITE_YUV_ORDER_YUYV (0<<16)
3768 #define SPRITE_YUV_ORDER_UYVY (1<<16)
3769 #define SPRITE_YUV_ORDER_YVYU (2<<16)
3770 #define SPRITE_YUV_ORDER_VYUY (3<<16)
3771 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3772 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
3773 #define SPRITE_TILED (1<<10)
3774 #define SPRITE_DEST_KEY (1<<2)
3775 #define _SPRA_LINOFF 0x70284
3776 #define _SPRA_STRIDE 0x70288
3777 #define _SPRA_POS 0x7028c
3778 #define _SPRA_SIZE 0x70290
3779 #define _SPRA_KEYVAL 0x70294
3780 #define _SPRA_KEYMSK 0x70298
3781 #define _SPRA_SURF 0x7029c
3782 #define _SPRA_KEYMAX 0x702a0
3783 #define _SPRA_TILEOFF 0x702a4
3784 #define _SPRA_OFFSET 0x702a4
3785 #define _SPRA_SURFLIVE 0x702ac
3786 #define _SPRA_SCALE 0x70304
3787 #define SPRITE_SCALE_ENABLE (1<<31)
3788 #define SPRITE_FILTER_MASK (3<<29)
3789 #define SPRITE_FILTER_MEDIUM (0<<29)
3790 #define SPRITE_FILTER_ENHANCING (1<<29)
3791 #define SPRITE_FILTER_SOFTENING (2<<29)
3792 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3793 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3794 #define _SPRA_GAMC 0x70400
3796 #define _SPRB_CTL 0x71280
3797 #define _SPRB_LINOFF 0x71284
3798 #define _SPRB_STRIDE 0x71288
3799 #define _SPRB_POS 0x7128c
3800 #define _SPRB_SIZE 0x71290
3801 #define _SPRB_KEYVAL 0x71294
3802 #define _SPRB_KEYMSK 0x71298
3803 #define _SPRB_SURF 0x7129c
3804 #define _SPRB_KEYMAX 0x712a0
3805 #define _SPRB_TILEOFF 0x712a4
3806 #define _SPRB_OFFSET 0x712a4
3807 #define _SPRB_SURFLIVE 0x712ac
3808 #define _SPRB_SCALE 0x71304
3809 #define _SPRB_GAMC 0x71400
3811 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3812 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3813 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3814 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3815 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3816 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3817 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3818 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3819 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3820 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3821 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3822 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3823 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3824 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3826 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3827 #define SP_ENABLE (1<<31)
3828 #define SP_GAMMA_ENABLE (1<<30)
3829 #define SP_PIXFORMAT_MASK (0xf<<26)
3830 #define SP_FORMAT_YUV422 (0<<26)
3831 #define SP_FORMAT_BGR565 (5<<26)
3832 #define SP_FORMAT_BGRX8888 (6<<26)
3833 #define SP_FORMAT_BGRA8888 (7<<26)
3834 #define SP_FORMAT_RGBX1010102 (8<<26)
3835 #define SP_FORMAT_RGBA1010102 (9<<26)
3836 #define SP_FORMAT_RGBX8888 (0xe<<26)
3837 #define SP_FORMAT_RGBA8888 (0xf<<26)
3838 #define SP_SOURCE_KEY (1<<22)
3839 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
3840 #define SP_YUV_ORDER_YUYV (0<<16)
3841 #define SP_YUV_ORDER_UYVY (1<<16)
3842 #define SP_YUV_ORDER_YVYU (2<<16)
3843 #define SP_YUV_ORDER_VYUY (3<<16)
3844 #define SP_TILED (1<<10)
3845 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3846 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3847 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3848 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3849 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3850 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3851 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3852 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3853 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3854 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3855 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
3857 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3858 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3859 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3860 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3861 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3862 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3863 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3864 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3865 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3866 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3867 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3868 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
3870 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3871 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3872 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3873 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3874 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3875 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3876 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3877 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3878 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3879 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3880 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3881 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3884 #define VGACNTRL 0x71400
3885 # define VGA_DISP_DISABLE (1 << 31)
3886 # define VGA_2X_MODE (1 << 30)
3887 # define VGA_PIPE_B_SELECT (1 << 29)
3889 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3893 #define CPU_VGACNTRL 0x41000
3895 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3896 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3897 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3898 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3899 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3900 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3901 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
3902 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3903 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3905 /* refresh rate hardware control */
3906 #define RR_HW_CTL 0x45300
3907 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3908 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3910 #define FDI_PLL_BIOS_0 0x46000
3911 #define FDI_PLL_FB_CLOCK_MASK 0xff
3912 #define FDI_PLL_BIOS_1 0x46004
3913 #define FDI_PLL_BIOS_2 0x46008
3914 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3915 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
3916 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
3918 #define PCH_3DCGDIS0 0x46020
3919 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3920 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3922 #define PCH_3DCGDIS1 0x46024
3923 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3925 #define FDI_PLL_FREQ_CTL 0x46030
3926 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3927 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3928 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3931 #define _PIPEA_DATA_M1 0x60030
3932 #define PIPE_DATA_M1_OFFSET 0
3933 #define _PIPEA_DATA_N1 0x60034
3934 #define PIPE_DATA_N1_OFFSET 0
3936 #define _PIPEA_DATA_M2 0x60038
3937 #define PIPE_DATA_M2_OFFSET 0
3938 #define _PIPEA_DATA_N2 0x6003c
3939 #define PIPE_DATA_N2_OFFSET 0
3941 #define _PIPEA_LINK_M1 0x60040
3942 #define PIPE_LINK_M1_OFFSET 0
3943 #define _PIPEA_LINK_N1 0x60044
3944 #define PIPE_LINK_N1_OFFSET 0
3946 #define _PIPEA_LINK_M2 0x60048
3947 #define PIPE_LINK_M2_OFFSET 0
3948 #define _PIPEA_LINK_N2 0x6004c
3949 #define PIPE_LINK_N2_OFFSET 0
3951 /* PIPEB timing regs are same start from 0x61000 */
3953 #define _PIPEB_DATA_M1 0x61030
3954 #define _PIPEB_DATA_N1 0x61034
3955 #define _PIPEB_DATA_M2 0x61038
3956 #define _PIPEB_DATA_N2 0x6103c
3957 #define _PIPEB_LINK_M1 0x61040
3958 #define _PIPEB_LINK_N1 0x61044
3959 #define _PIPEB_LINK_M2 0x61048
3960 #define _PIPEB_LINK_N2 0x6104c
3962 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
3963 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
3964 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
3965 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
3966 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
3967 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
3968 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
3969 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
3971 /* CPU panel fitter */
3972 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3973 #define _PFA_CTL_1 0x68080
3974 #define _PFB_CTL_1 0x68880
3975 #define PF_ENABLE (1<<31)
3976 #define PF_PIPE_SEL_MASK_IVB (3<<29)
3977 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
3978 #define PF_FILTER_MASK (3<<23)
3979 #define PF_FILTER_PROGRAMMED (0<<23)
3980 #define PF_FILTER_MED_3x3 (1<<23)
3981 #define PF_FILTER_EDGE_ENHANCE (2<<23)
3982 #define PF_FILTER_EDGE_SOFTEN (3<<23)
3983 #define _PFA_WIN_SZ 0x68074
3984 #define _PFB_WIN_SZ 0x68874
3985 #define _PFA_WIN_POS 0x68070
3986 #define _PFB_WIN_POS 0x68870
3987 #define _PFA_VSCALE 0x68084
3988 #define _PFB_VSCALE 0x68884
3989 #define _PFA_HSCALE 0x68090
3990 #define _PFB_HSCALE 0x68890
3992 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3993 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3994 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3995 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3996 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3998 /* legacy palette */
3999 #define _LGC_PALETTE_A 0x4a000
4000 #define _LGC_PALETTE_B 0x4a800
4001 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
4003 #define _GAMMA_MODE_A 0x4a480
4004 #define _GAMMA_MODE_B 0x4ac80
4005 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4006 #define GAMMA_MODE_MODE_MASK (3 << 0)
4007 #define GAMMA_MODE_MODE_8BIT (0 << 0)
4008 #define GAMMA_MODE_MODE_10BIT (1 << 0)
4009 #define GAMMA_MODE_MODE_12BIT (2 << 0)
4010 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
4013 #define DE_MASTER_IRQ_CONTROL (1 << 31)
4014 #define DE_SPRITEB_FLIP_DONE (1 << 29)
4015 #define DE_SPRITEA_FLIP_DONE (1 << 28)
4016 #define DE_PLANEB_FLIP_DONE (1 << 27)
4017 #define DE_PLANEA_FLIP_DONE (1 << 26)
4018 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
4019 #define DE_PCU_EVENT (1 << 25)
4020 #define DE_GTT_FAULT (1 << 24)
4021 #define DE_POISON (1 << 23)
4022 #define DE_PERFORM_COUNTER (1 << 22)
4023 #define DE_PCH_EVENT (1 << 21)
4024 #define DE_AUX_CHANNEL_A (1 << 20)
4025 #define DE_DP_A_HOTPLUG (1 << 19)
4026 #define DE_GSE (1 << 18)
4027 #define DE_PIPEB_VBLANK (1 << 15)
4028 #define DE_PIPEB_EVEN_FIELD (1 << 14)
4029 #define DE_PIPEB_ODD_FIELD (1 << 13)
4030 #define DE_PIPEB_LINE_COMPARE (1 << 12)
4031 #define DE_PIPEB_VSYNC (1 << 11)
4032 #define DE_PIPEB_CRC_DONE (1 << 10)
4033 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4034 #define DE_PIPEA_VBLANK (1 << 7)
4035 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
4036 #define DE_PIPEA_EVEN_FIELD (1 << 6)
4037 #define DE_PIPEA_ODD_FIELD (1 << 5)
4038 #define DE_PIPEA_LINE_COMPARE (1 << 4)
4039 #define DE_PIPEA_VSYNC (1 << 3)
4040 #define DE_PIPEA_CRC_DONE (1 << 2)
4041 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
4042 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
4043 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
4045 /* More Ivybridge lolz */
4046 #define DE_ERR_INT_IVB (1<<30)
4047 #define DE_GSE_IVB (1<<29)
4048 #define DE_PCH_EVENT_IVB (1<<28)
4049 #define DE_DP_A_HOTPLUG_IVB (1<<27)
4050 #define DE_AUX_CHANNEL_A_IVB (1<<26)
4051 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
4052 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
4053 #define DE_PIPEC_VBLANK_IVB (1<<10)
4054 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
4055 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
4056 #define DE_PIPEB_VBLANK_IVB (1<<5)
4057 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
4058 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
4059 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
4060 #define DE_PIPEA_VBLANK_IVB (1<<0)
4061 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4063 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
4064 #define MASTER_INTERRUPT_ENABLE (1<<31)
4066 #define DEISR 0x44000
4067 #define DEIMR 0x44004
4068 #define DEIIR 0x44008
4069 #define DEIER 0x4400c
4071 #define GTISR 0x44010
4072 #define GTIMR 0x44014
4073 #define GTIIR 0x44018
4074 #define GTIER 0x4401c
4076 #define GEN8_MASTER_IRQ 0x44200
4077 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
4078 #define GEN8_PCU_IRQ (1<<30)
4079 #define GEN8_DE_PCH_IRQ (1<<23)
4080 #define GEN8_DE_MISC_IRQ (1<<22)
4081 #define GEN8_DE_PORT_IRQ (1<<20)
4082 #define GEN8_DE_PIPE_C_IRQ (1<<18)
4083 #define GEN8_DE_PIPE_B_IRQ (1<<17)
4084 #define GEN8_DE_PIPE_A_IRQ (1<<16)
4085 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
4086 #define GEN8_GT_VECS_IRQ (1<<6)
4087 #define GEN8_GT_VCS2_IRQ (1<<3)
4088 #define GEN8_GT_VCS1_IRQ (1<<2)
4089 #define GEN8_GT_BCS_IRQ (1<<1)
4090 #define GEN8_GT_RCS_IRQ (1<<0)
4092 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
4093 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
4094 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
4095 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
4097 #define GEN8_BCS_IRQ_SHIFT 16
4098 #define GEN8_RCS_IRQ_SHIFT 0
4099 #define GEN8_VCS2_IRQ_SHIFT 16
4100 #define GEN8_VCS1_IRQ_SHIFT 0
4101 #define GEN8_VECS_IRQ_SHIFT 0
4103 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4104 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4105 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4106 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
4107 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
4108 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4109 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4110 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4111 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4112 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4113 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
4114 #define GEN8_PIPE_FLIP_DONE (1 << 4)
4115 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4116 #define GEN8_PIPE_VSYNC (1 << 1)
4117 #define GEN8_PIPE_VBLANK (1 << 0)
4118 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4119 (GEN8_PIPE_CURSOR_FAULT | \
4120 GEN8_PIPE_SPRITE_FAULT | \
4121 GEN8_PIPE_PRIMARY_FAULT)
4123 #define GEN8_DE_PORT_ISR 0x44440
4124 #define GEN8_DE_PORT_IMR 0x44444
4125 #define GEN8_DE_PORT_IIR 0x44448
4126 #define GEN8_DE_PORT_IER 0x4444c
4127 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4128 #define GEN8_AUX_CHANNEL_A (1 << 0)
4130 #define GEN8_DE_MISC_ISR 0x44460
4131 #define GEN8_DE_MISC_IMR 0x44464
4132 #define GEN8_DE_MISC_IIR 0x44468
4133 #define GEN8_DE_MISC_IER 0x4446c
4134 #define GEN8_DE_MISC_GSE (1 << 27)
4136 #define GEN8_PCU_ISR 0x444e0
4137 #define GEN8_PCU_IMR 0x444e4
4138 #define GEN8_PCU_IIR 0x444e8
4139 #define GEN8_PCU_IER 0x444ec
4141 #define ILK_DISPLAY_CHICKEN2 0x42004
4142 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
4143 #define ILK_ELPIN_409_SELECT (1 << 25)
4144 #define ILK_DPARB_GATE (1<<22)
4145 #define ILK_VSDPFD_FULL (1<<21)
4146 #define FUSE_STRAP 0x42014
4147 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
4148 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
4149 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
4150 #define ILK_HDCP_DISABLE (1 << 25)
4151 #define ILK_eDP_A_DISABLE (1 << 24)
4152 #define HSW_CDCLK_LIMIT (1 << 24)
4153 #define ILK_DESKTOP (1 << 23)
4155 #define ILK_DSPCLK_GATE_D 0x42020
4156 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4157 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4158 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4159 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4160 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
4162 #define IVB_CHICKEN3 0x4200c
4163 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4164 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4166 #define CHICKEN_PAR1_1 0x42080
4167 #define DPA_MASK_VBLANK_SRD (1 << 15)
4168 #define FORCE_ARB_IDLE_PLANES (1 << 14)
4170 #define _CHICKEN_PIPESL_1_A 0x420b0
4171 #define _CHICKEN_PIPESL_1_B 0x420b4
4172 #define HSW_FBCQ_DIS (1 << 22)
4173 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
4174 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4176 #define DISP_ARB_CTL 0x45000
4177 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
4178 #define DISP_FBC_WM_DIS (1<<15)
4179 #define DISP_ARB_CTL2 0x45004
4180 #define DISP_DATA_PARTITION_5_6 (1<<6)
4181 #define GEN7_MSG_CTL 0x45010
4182 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
4183 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
4184 #define HSW_NDE_RSTWRN_OPT 0x46408
4185 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
4188 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4189 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
4190 #define COMMON_SLICE_CHICKEN2 0x7014
4191 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
4193 #define GEN7_L3SQCREG1 0xB010
4194 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
4196 #define GEN7_L3CNTLREG1 0xB01C
4197 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
4198 #define GEN7_L3AGDIS (1<<19)
4200 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4201 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4203 #define GEN7_L3SQCREG4 0xb034
4204 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4207 #define HDC_CHICKEN0 0x7300
4208 #define HDC_FORCE_NON_COHERENT (1<<4)
4210 /* WaCatErrorRejectionIssue */
4211 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4212 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4214 #define HSW_SCRATCH1 0xb038
4215 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4219 /* south display engine interrupt: IBX */
4220 #define SDE_AUDIO_POWER_D (1 << 27)
4221 #define SDE_AUDIO_POWER_C (1 << 26)
4222 #define SDE_AUDIO_POWER_B (1 << 25)
4223 #define SDE_AUDIO_POWER_SHIFT (25)
4224 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4225 #define SDE_GMBUS (1 << 24)
4226 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4227 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4228 #define SDE_AUDIO_HDCP_MASK (3 << 22)
4229 #define SDE_AUDIO_TRANSB (1 << 21)
4230 #define SDE_AUDIO_TRANSA (1 << 20)
4231 #define SDE_AUDIO_TRANS_MASK (3 << 20)
4232 #define SDE_POISON (1 << 19)
4234 #define SDE_FDI_RXB (1 << 17)
4235 #define SDE_FDI_RXA (1 << 16)
4236 #define SDE_FDI_MASK (3 << 16)
4237 #define SDE_AUXD (1 << 15)
4238 #define SDE_AUXC (1 << 14)
4239 #define SDE_AUXB (1 << 13)
4240 #define SDE_AUX_MASK (7 << 13)
4242 #define SDE_CRT_HOTPLUG (1 << 11)
4243 #define SDE_PORTD_HOTPLUG (1 << 10)
4244 #define SDE_PORTC_HOTPLUG (1 << 9)
4245 #define SDE_PORTB_HOTPLUG (1 << 8)
4246 #define SDE_SDVOB_HOTPLUG (1 << 6)
4247 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4248 SDE_SDVOB_HOTPLUG | \
4249 SDE_PORTB_HOTPLUG | \
4250 SDE_PORTC_HOTPLUG | \
4252 #define SDE_TRANSB_CRC_DONE (1 << 5)
4253 #define SDE_TRANSB_CRC_ERR (1 << 4)
4254 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
4255 #define SDE_TRANSA_CRC_DONE (1 << 2)
4256 #define SDE_TRANSA_CRC_ERR (1 << 1)
4257 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
4258 #define SDE_TRANS_MASK (0x3f)
4260 /* south display engine interrupt: CPT/PPT */
4261 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
4262 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
4263 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
4264 #define SDE_AUDIO_POWER_SHIFT_CPT 29
4265 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4266 #define SDE_AUXD_CPT (1 << 27)
4267 #define SDE_AUXC_CPT (1 << 26)
4268 #define SDE_AUXB_CPT (1 << 25)
4269 #define SDE_AUX_MASK_CPT (7 << 25)
4270 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4271 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4272 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
4273 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
4274 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
4275 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
4276 SDE_SDVOB_HOTPLUG_CPT | \
4277 SDE_PORTD_HOTPLUG_CPT | \
4278 SDE_PORTC_HOTPLUG_CPT | \
4279 SDE_PORTB_HOTPLUG_CPT)
4280 #define SDE_GMBUS_CPT (1 << 17)
4281 #define SDE_ERROR_CPT (1 << 16)
4282 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4283 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4284 #define SDE_FDI_RXC_CPT (1 << 8)
4285 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4286 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4287 #define SDE_FDI_RXB_CPT (1 << 4)
4288 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4289 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4290 #define SDE_FDI_RXA_CPT (1 << 0)
4291 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4292 SDE_AUDIO_CP_REQ_B_CPT | \
4293 SDE_AUDIO_CP_REQ_A_CPT)
4294 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4295 SDE_AUDIO_CP_CHG_B_CPT | \
4296 SDE_AUDIO_CP_CHG_A_CPT)
4297 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4301 #define SDEISR 0xc4000
4302 #define SDEIMR 0xc4004
4303 #define SDEIIR 0xc4008
4304 #define SDEIER 0xc400c
4306 #define SERR_INT 0xc4040
4307 #define SERR_INT_POISON (1<<31)
4308 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4309 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4310 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
4311 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
4313 /* digital port hotplug */
4314 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
4315 #define PORTD_HOTPLUG_ENABLE (1 << 20)
4316 #define PORTD_PULSE_DURATION_2ms (0)
4317 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4318 #define PORTD_PULSE_DURATION_6ms (2 << 18)
4319 #define PORTD_PULSE_DURATION_100ms (3 << 18)
4320 #define PORTD_PULSE_DURATION_MASK (3 << 18)
4321 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4322 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4323 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4324 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
4325 #define PORTC_HOTPLUG_ENABLE (1 << 12)
4326 #define PORTC_PULSE_DURATION_2ms (0)
4327 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4328 #define PORTC_PULSE_DURATION_6ms (2 << 10)
4329 #define PORTC_PULSE_DURATION_100ms (3 << 10)
4330 #define PORTC_PULSE_DURATION_MASK (3 << 10)
4331 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4332 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4333 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4334 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
4335 #define PORTB_HOTPLUG_ENABLE (1 << 4)
4336 #define PORTB_PULSE_DURATION_2ms (0)
4337 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4338 #define PORTB_PULSE_DURATION_6ms (2 << 2)
4339 #define PORTB_PULSE_DURATION_100ms (3 << 2)
4340 #define PORTB_PULSE_DURATION_MASK (3 << 2)
4341 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4342 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4343 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4344 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
4346 #define PCH_GPIOA 0xc5010
4347 #define PCH_GPIOB 0xc5014
4348 #define PCH_GPIOC 0xc5018
4349 #define PCH_GPIOD 0xc501c
4350 #define PCH_GPIOE 0xc5020
4351 #define PCH_GPIOF 0xc5024
4353 #define PCH_GMBUS0 0xc5100
4354 #define PCH_GMBUS1 0xc5104
4355 #define PCH_GMBUS2 0xc5108
4356 #define PCH_GMBUS3 0xc510c
4357 #define PCH_GMBUS4 0xc5110
4358 #define PCH_GMBUS5 0xc5120
4360 #define _PCH_DPLL_A 0xc6014
4361 #define _PCH_DPLL_B 0xc6018
4362 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4364 #define _PCH_FPA0 0xc6040
4365 #define FP_CB_TUNE (0x3<<22)
4366 #define _PCH_FPA1 0xc6044
4367 #define _PCH_FPB0 0xc6048
4368 #define _PCH_FPB1 0xc604c
4369 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4370 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
4372 #define PCH_DPLL_TEST 0xc606c
4374 #define PCH_DREF_CONTROL 0xC6200
4375 #define DREF_CONTROL_MASK 0x7fc3
4376 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4377 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4378 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4379 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4380 #define DREF_SSC_SOURCE_DISABLE (0<<11)
4381 #define DREF_SSC_SOURCE_ENABLE (2<<11)
4382 #define DREF_SSC_SOURCE_MASK (3<<11)
4383 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4384 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4385 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
4386 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
4387 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4388 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
4389 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
4390 #define DREF_SSC4_DOWNSPREAD (0<<6)
4391 #define DREF_SSC4_CENTERSPREAD (1<<6)
4392 #define DREF_SSC1_DISABLE (0<<1)
4393 #define DREF_SSC1_ENABLE (1<<1)
4394 #define DREF_SSC4_DISABLE (0)
4395 #define DREF_SSC4_ENABLE (1)
4397 #define PCH_RAWCLK_FREQ 0xc6204
4398 #define FDL_TP1_TIMER_SHIFT 12
4399 #define FDL_TP1_TIMER_MASK (3<<12)
4400 #define FDL_TP2_TIMER_SHIFT 10
4401 #define FDL_TP2_TIMER_MASK (3<<10)
4402 #define RAWCLK_FREQ_MASK 0x3ff
4404 #define PCH_DPLL_TMR_CFG 0xc6208
4406 #define PCH_SSC4_PARMS 0xc6210
4407 #define PCH_SSC4_AUX_PARMS 0xc6214
4409 #define PCH_DPLL_SEL 0xc7000
4410 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4411 #define TRANS_DPLLA_SEL(pipe) 0
4412 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
4416 #define _PCH_TRANS_HTOTAL_A 0xe0000
4417 #define TRANS_HTOTAL_SHIFT 16
4418 #define TRANS_HACTIVE_SHIFT 0
4419 #define _PCH_TRANS_HBLANK_A 0xe0004
4420 #define TRANS_HBLANK_END_SHIFT 16
4421 #define TRANS_HBLANK_START_SHIFT 0
4422 #define _PCH_TRANS_HSYNC_A 0xe0008
4423 #define TRANS_HSYNC_END_SHIFT 16
4424 #define TRANS_HSYNC_START_SHIFT 0
4425 #define _PCH_TRANS_VTOTAL_A 0xe000c
4426 #define TRANS_VTOTAL_SHIFT 16
4427 #define TRANS_VACTIVE_SHIFT 0
4428 #define _PCH_TRANS_VBLANK_A 0xe0010
4429 #define TRANS_VBLANK_END_SHIFT 16
4430 #define TRANS_VBLANK_START_SHIFT 0
4431 #define _PCH_TRANS_VSYNC_A 0xe0014
4432 #define TRANS_VSYNC_END_SHIFT 16
4433 #define TRANS_VSYNC_START_SHIFT 0
4434 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
4436 #define _PCH_TRANSA_DATA_M1 0xe0030
4437 #define _PCH_TRANSA_DATA_N1 0xe0034
4438 #define _PCH_TRANSA_DATA_M2 0xe0038
4439 #define _PCH_TRANSA_DATA_N2 0xe003c
4440 #define _PCH_TRANSA_LINK_M1 0xe0040
4441 #define _PCH_TRANSA_LINK_N1 0xe0044
4442 #define _PCH_TRANSA_LINK_M2 0xe0048
4443 #define _PCH_TRANSA_LINK_N2 0xe004c
4445 /* Per-transcoder DIP controls */
4447 #define _VIDEO_DIP_CTL_A 0xe0200
4448 #define _VIDEO_DIP_DATA_A 0xe0208
4449 #define _VIDEO_DIP_GCP_A 0xe0210
4451 #define _VIDEO_DIP_CTL_B 0xe1200
4452 #define _VIDEO_DIP_DATA_B 0xe1208
4453 #define _VIDEO_DIP_GCP_B 0xe1210
4455 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4456 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4457 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4459 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4460 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4461 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
4463 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4464 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4465 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
4467 #define VLV_TVIDEO_DIP_CTL(pipe) \
4468 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4469 #define VLV_TVIDEO_DIP_DATA(pipe) \
4470 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4471 #define VLV_TVIDEO_DIP_GCP(pipe) \
4472 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4474 /* Haswell DIP controls */
4475 #define HSW_VIDEO_DIP_CTL_A 0x60200
4476 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4477 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4478 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4479 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4480 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4481 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4482 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4483 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4484 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4485 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4486 #define HSW_VIDEO_DIP_GCP_A 0x60210
4488 #define HSW_VIDEO_DIP_CTL_B 0x61200
4489 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4490 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4491 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4492 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4493 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4494 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4495 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4496 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4497 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4498 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4499 #define HSW_VIDEO_DIP_GCP_B 0x61210
4501 #define HSW_TVIDEO_DIP_CTL(trans) \
4502 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
4503 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4504 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
4505 #define HSW_TVIDEO_DIP_VS_DATA(trans) \
4506 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
4507 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4508 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
4509 #define HSW_TVIDEO_DIP_GCP(trans) \
4510 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
4511 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4512 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
4514 #define HSW_STEREO_3D_CTL_A 0x70020
4515 #define S3D_ENABLE (1<<31)
4516 #define HSW_STEREO_3D_CTL_B 0x71020
4518 #define HSW_STEREO_3D_CTL(trans) \
4519 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
4521 #define _PCH_TRANS_HTOTAL_B 0xe1000
4522 #define _PCH_TRANS_HBLANK_B 0xe1004
4523 #define _PCH_TRANS_HSYNC_B 0xe1008
4524 #define _PCH_TRANS_VTOTAL_B 0xe100c
4525 #define _PCH_TRANS_VBLANK_B 0xe1010
4526 #define _PCH_TRANS_VSYNC_B 0xe1014
4527 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
4529 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4530 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4531 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4532 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4533 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4534 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4535 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4536 _PCH_TRANS_VSYNCSHIFT_B)
4538 #define _PCH_TRANSB_DATA_M1 0xe1030
4539 #define _PCH_TRANSB_DATA_N1 0xe1034
4540 #define _PCH_TRANSB_DATA_M2 0xe1038
4541 #define _PCH_TRANSB_DATA_N2 0xe103c
4542 #define _PCH_TRANSB_LINK_M1 0xe1040
4543 #define _PCH_TRANSB_LINK_N1 0xe1044
4544 #define _PCH_TRANSB_LINK_M2 0xe1048
4545 #define _PCH_TRANSB_LINK_N2 0xe104c
4547 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4548 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4549 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4550 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4551 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4552 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4553 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4554 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4556 #define _PCH_TRANSACONF 0xf0008
4557 #define _PCH_TRANSBCONF 0xf1008
4558 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4559 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
4560 #define TRANS_DISABLE (0<<31)
4561 #define TRANS_ENABLE (1<<31)
4562 #define TRANS_STATE_MASK (1<<30)
4563 #define TRANS_STATE_DISABLE (0<<30)
4564 #define TRANS_STATE_ENABLE (1<<30)
4565 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
4566 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
4567 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
4568 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
4569 #define TRANS_INTERLACE_MASK (7<<21)
4570 #define TRANS_PROGRESSIVE (0<<21)
4571 #define TRANS_INTERLACED (3<<21)
4572 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
4573 #define TRANS_8BPC (0<<5)
4574 #define TRANS_10BPC (1<<5)
4575 #define TRANS_6BPC (2<<5)
4576 #define TRANS_12BPC (3<<5)
4578 #define _TRANSA_CHICKEN1 0xf0060
4579 #define _TRANSB_CHICKEN1 0xf1060
4580 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4581 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
4582 #define _TRANSA_CHICKEN2 0xf0064
4583 #define _TRANSB_CHICKEN2 0xf1064
4584 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
4585 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
4586 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
4587 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
4588 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
4589 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
4591 #define SOUTH_CHICKEN1 0xc2000
4592 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
4593 #define FDIA_PHASE_SYNC_SHIFT_EN 18
4594 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4595 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4596 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
4597 #define SOUTH_CHICKEN2 0xc2004
4598 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
4599 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
4600 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
4602 #define _FDI_RXA_CHICKEN 0xc200c
4603 #define _FDI_RXB_CHICKEN 0xc2010
4604 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
4605 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
4606 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4608 #define SOUTH_DSPCLK_GATE_D 0xc2020
4609 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
4610 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4611 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
4612 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
4615 #define _FDI_TXA_CTL 0x60100
4616 #define _FDI_TXB_CTL 0x61100
4617 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
4618 #define FDI_TX_DISABLE (0<<31)
4619 #define FDI_TX_ENABLE (1<<31)
4620 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
4621 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
4622 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
4623 #define FDI_LINK_TRAIN_NONE (3<<28)
4624 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
4625 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
4626 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
4627 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
4628 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4629 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4630 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
4631 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
4632 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4633 SNB has different settings. */
4634 /* SNB A-stepping */
4635 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4636 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4637 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4638 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4639 /* SNB B-stepping */
4640 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
4641 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
4642 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
4643 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
4644 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
4645 #define FDI_DP_PORT_WIDTH_SHIFT 19
4646 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
4647 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
4648 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
4649 /* Ironlake: hardwired to 1 */
4650 #define FDI_TX_PLL_ENABLE (1<<14)
4652 /* Ivybridge has different bits for lolz */
4653 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
4654 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
4655 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
4656 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
4658 /* both Tx and Rx */
4659 #define FDI_COMPOSITE_SYNC (1<<11)
4660 #define FDI_LINK_TRAIN_AUTO (1<<10)
4661 #define FDI_SCRAMBLING_ENABLE (0<<7)
4662 #define FDI_SCRAMBLING_DISABLE (1<<7)
4664 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
4665 #define _FDI_RXA_CTL 0xf000c
4666 #define _FDI_RXB_CTL 0xf100c
4667 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4668 #define FDI_RX_ENABLE (1<<31)
4669 /* train, dp width same as FDI_TX */
4670 #define FDI_FS_ERRC_ENABLE (1<<27)
4671 #define FDI_FE_ERRC_ENABLE (1<<26)
4672 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
4673 #define FDI_8BPC (0<<16)
4674 #define FDI_10BPC (1<<16)
4675 #define FDI_6BPC (2<<16)
4676 #define FDI_12BPC (3<<16)
4677 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
4678 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
4679 #define FDI_RX_PLL_ENABLE (1<<13)
4680 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
4681 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
4682 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
4683 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
4684 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
4685 #define FDI_PCDCLK (1<<4)
4687 #define FDI_AUTO_TRAINING (1<<10)
4688 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
4689 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
4690 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
4691 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
4692 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
4694 #define _FDI_RXA_MISC 0xf0010
4695 #define _FDI_RXB_MISC 0xf1010
4696 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
4697 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
4698 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
4699 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
4700 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
4701 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
4702 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
4703 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4705 #define _FDI_RXA_TUSIZE1 0xf0030
4706 #define _FDI_RXA_TUSIZE2 0xf0038
4707 #define _FDI_RXB_TUSIZE1 0xf1030
4708 #define _FDI_RXB_TUSIZE2 0xf1038
4709 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4710 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4712 /* FDI_RX interrupt register format */
4713 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
4714 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
4715 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
4716 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
4717 #define FDI_RX_FS_CODE_ERR (1<<6)
4718 #define FDI_RX_FE_CODE_ERR (1<<5)
4719 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
4720 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
4721 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
4722 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
4723 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
4725 #define _FDI_RXA_IIR 0xf0014
4726 #define _FDI_RXA_IMR 0xf0018
4727 #define _FDI_RXB_IIR 0xf1014
4728 #define _FDI_RXB_IMR 0xf1018
4729 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4730 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4732 #define FDI_PLL_CTL_1 0xfe000
4733 #define FDI_PLL_CTL_2 0xfe004
4735 #define PCH_LVDS 0xe1180
4736 #define LVDS_DETECTED (1 << 1)
4738 /* vlv has 2 sets of panel control regs. */
4739 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4740 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4741 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
4742 #define PANEL_PORT_SELECT_DPB_VLV (1 << 30)
4743 #define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
4744 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4745 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4747 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4748 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4749 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4750 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4751 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
4753 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4754 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4755 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
4756 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4757 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4758 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4759 #define VLV_PIPE_PP_DIVISOR(pipe) \
4760 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4762 #define PCH_PP_STATUS 0xc7200
4763 #define PCH_PP_CONTROL 0xc7204
4764 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4765 #define PANEL_UNLOCK_MASK (0xffff << 16)
4766 #define EDP_FORCE_VDD (1 << 3)
4767 #define EDP_BLC_ENABLE (1 << 2)
4768 #define PANEL_POWER_RESET (1 << 1)
4769 #define PANEL_POWER_OFF (0 << 0)
4770 #define PANEL_POWER_ON (1 << 0)
4771 #define PCH_PP_ON_DELAYS 0xc7208
4772 #define PANEL_PORT_SELECT_MASK (3 << 30)
4773 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4774 #define PANEL_PORT_SELECT_DPA (1 << 30)
4775 #define PANEL_PORT_SELECT_DPC (2 << 30)
4776 #define PANEL_PORT_SELECT_DPD (3 << 30)
4777 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4778 #define PANEL_POWER_UP_DELAY_SHIFT 16
4779 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4780 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4782 #define PCH_PP_OFF_DELAYS 0xc720c
4783 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4784 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4785 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4786 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4788 #define PCH_PP_DIVISOR 0xc7210
4789 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4790 #define PP_REFERENCE_DIVIDER_SHIFT 8
4791 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4792 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4794 #define PCH_DP_B 0xe4100
4795 #define PCH_DPB_AUX_CH_CTL 0xe4110
4796 #define PCH_DPB_AUX_CH_DATA1 0xe4114
4797 #define PCH_DPB_AUX_CH_DATA2 0xe4118
4798 #define PCH_DPB_AUX_CH_DATA3 0xe411c
4799 #define PCH_DPB_AUX_CH_DATA4 0xe4120
4800 #define PCH_DPB_AUX_CH_DATA5 0xe4124
4802 #define PCH_DP_C 0xe4200
4803 #define PCH_DPC_AUX_CH_CTL 0xe4210
4804 #define PCH_DPC_AUX_CH_DATA1 0xe4214
4805 #define PCH_DPC_AUX_CH_DATA2 0xe4218
4806 #define PCH_DPC_AUX_CH_DATA3 0xe421c
4807 #define PCH_DPC_AUX_CH_DATA4 0xe4220
4808 #define PCH_DPC_AUX_CH_DATA5 0xe4224
4810 #define PCH_DP_D 0xe4300
4811 #define PCH_DPD_AUX_CH_CTL 0xe4310
4812 #define PCH_DPD_AUX_CH_DATA1 0xe4314
4813 #define PCH_DPD_AUX_CH_DATA2 0xe4318
4814 #define PCH_DPD_AUX_CH_DATA3 0xe431c
4815 #define PCH_DPD_AUX_CH_DATA4 0xe4320
4816 #define PCH_DPD_AUX_CH_DATA5 0xe4324
4819 #define PORT_TRANS_A_SEL_CPT 0
4820 #define PORT_TRANS_B_SEL_CPT (1<<29)
4821 #define PORT_TRANS_C_SEL_CPT (2<<29)
4822 #define PORT_TRANS_SEL_MASK (3<<29)
4823 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4824 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4825 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4827 #define TRANS_DP_CTL_A 0xe0300
4828 #define TRANS_DP_CTL_B 0xe1300
4829 #define TRANS_DP_CTL_C 0xe2300
4830 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4831 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
4832 #define TRANS_DP_PORT_SEL_B (0<<29)
4833 #define TRANS_DP_PORT_SEL_C (1<<29)
4834 #define TRANS_DP_PORT_SEL_D (2<<29)
4835 #define TRANS_DP_PORT_SEL_NONE (3<<29)
4836 #define TRANS_DP_PORT_SEL_MASK (3<<29)
4837 #define TRANS_DP_AUDIO_ONLY (1<<26)
4838 #define TRANS_DP_ENH_FRAMING (1<<18)
4839 #define TRANS_DP_8BPC (0<<9)
4840 #define TRANS_DP_10BPC (1<<9)
4841 #define TRANS_DP_6BPC (2<<9)
4842 #define TRANS_DP_12BPC (3<<9)
4843 #define TRANS_DP_BPC_MASK (3<<9)
4844 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4845 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
4846 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4847 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
4848 #define TRANS_DP_SYNC_MASK (3<<3)
4850 /* SNB eDP training params */
4851 /* SNB A-stepping */
4852 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4853 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4854 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4855 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4856 /* SNB B-stepping */
4857 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4858 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4859 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4860 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4861 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4862 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4865 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4866 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4867 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4868 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4869 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4870 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4871 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
4874 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4875 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4876 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4877 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4878 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4880 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4882 #define FORCEWAKE 0xA18C
4883 #define FORCEWAKE_VLV 0x1300b0
4884 #define FORCEWAKE_ACK_VLV 0x1300b4
4885 #define FORCEWAKE_MEDIA_VLV 0x1300b8
4886 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
4887 #define FORCEWAKE_ACK_HSW 0x130044
4888 #define FORCEWAKE_ACK 0x130090
4889 #define VLV_GTLC_WAKE_CTRL 0x130090
4890 #define VLV_GTLC_PW_STATUS 0x130094
4891 #define VLV_GTLC_PW_RENDER_STATUS_MASK 0x80
4892 #define VLV_GTLC_PW_MEDIA_STATUS_MASK 0x20
4893 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
4894 #define FORCEWAKE_KERNEL 0x1
4895 #define FORCEWAKE_USER 0x2
4896 #define FORCEWAKE_MT_ACK 0x130040
4897 #define ECOBUS 0xa180
4898 #define FORCEWAKE_MT_ENABLE (1<<5)
4900 #define GTFIFODBG 0x120000
4901 #define GT_FIFO_SBDROPERR (1<<6)
4902 #define GT_FIFO_BLOBDROPERR (1<<5)
4903 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
4904 #define GT_FIFO_DROPERR (1<<3)
4905 #define GT_FIFO_OVFERR (1<<2)
4906 #define GT_FIFO_IAWRERR (1<<1)
4907 #define GT_FIFO_IARDERR (1<<0)
4909 #define GTFIFOCTL 0x120008
4910 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
4911 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
4913 #define HSW_IDICR 0x9008
4914 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
4915 #define HSW_EDRAM_PRESENT 0x120010
4917 #define GEN6_UCGCTL1 0x9400
4918 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4919 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4921 #define GEN6_UCGCTL2 0x9404
4922 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4923 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4924 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4925 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4926 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4928 #define GEN7_UCGCTL4 0x940c
4929 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4931 #define GEN8_UCGCTL6 0x9430
4932 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
4934 #define GEN6_RPNSWREQ 0xA008
4935 #define GEN6_TURBO_DISABLE (1<<31)
4936 #define GEN6_FREQUENCY(x) ((x)<<25)
4937 #define HSW_FREQUENCY(x) ((x)<<24)
4938 #define GEN6_OFFSET(x) ((x)<<19)
4939 #define GEN6_AGGRESSIVE_TURBO (0<<15)
4940 #define GEN6_RC_VIDEO_FREQ 0xA00C
4941 #define GEN6_RC_CONTROL 0xA090
4942 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4943 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4944 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4945 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4946 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4947 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
4948 #define GEN7_RC_CTL_TO_MODE (1<<28)
4949 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4950 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
4951 #define GEN6_RP_DOWN_TIMEOUT 0xA010
4952 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
4953 #define GEN6_RPSTAT1 0xA01C
4954 #define GEN6_CAGF_SHIFT 8
4955 #define HSW_CAGF_SHIFT 7
4956 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4957 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
4958 #define GEN6_RP_CONTROL 0xA024
4959 #define GEN6_RP_MEDIA_TURBO (1<<11)
4960 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4961 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4962 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4963 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
4964 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
4965 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
4966 #define GEN6_RP_ENABLE (1<<7)
4967 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4968 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4969 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4970 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
4971 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4972 #define GEN6_RP_UP_THRESHOLD 0xA02C
4973 #define GEN6_RP_DOWN_THRESHOLD 0xA030
4974 #define GEN6_RP_CUR_UP_EI 0xA050
4975 #define GEN6_CURICONT_MASK 0xffffff
4976 #define GEN6_RP_CUR_UP 0xA054
4977 #define GEN6_CURBSYTAVG_MASK 0xffffff
4978 #define GEN6_RP_PREV_UP 0xA058
4979 #define GEN6_RP_CUR_DOWN_EI 0xA05C
4980 #define GEN6_CURIAVG_MASK 0xffffff
4981 #define GEN6_RP_CUR_DOWN 0xA060
4982 #define GEN6_RP_PREV_DOWN 0xA064
4983 #define GEN6_RP_UP_EI 0xA068
4984 #define GEN6_RP_DOWN_EI 0xA06C
4985 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
4986 #define GEN6_RC_STATE 0xA094
4987 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4988 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4989 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4990 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4991 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4992 #define GEN6_RC_SLEEP 0xA0B0
4993 #define GEN6_RC1e_THRESHOLD 0xA0B4
4994 #define GEN6_RC6_THRESHOLD 0xA0B8
4995 #define GEN6_RC6p_THRESHOLD 0xA0BC
4996 #define GEN6_RC6pp_THRESHOLD 0xA0C0
4997 #define GEN6_PMINTRMSK 0xA168
4999 #define GEN6_PMISR 0x44020
5000 #define GEN6_PMIMR 0x44024 /* rps_lock */
5001 #define GEN6_PMIIR 0x44028
5002 #define GEN6_PMIER 0x4402C
5003 #define GEN6_PM_MBOX_EVENT (1<<25)
5004 #define GEN6_PM_THERMAL_EVENT (1<<24)
5005 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
5006 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
5007 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
5008 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
5009 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
5010 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
5011 GEN6_PM_RP_DOWN_THRESHOLD | \
5012 GEN6_PM_RP_DOWN_TIMEOUT)
5014 #define VLV_GTLC_SURVIVABILITY_REG 0x130098
5015 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
5016 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
5018 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
5019 #define VLV_COUNTER_CONTROL 0x138104
5020 #define VLV_COUNT_RANGE_HIGH (1<<15)
5021 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
5022 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
5023 #define GEN6_GT_GFX_RC6 0x138108
5024 #define GEN6_GT_GFX_RC6p 0x13810C
5025 #define GEN6_GT_GFX_RC6pp 0x138110
5027 #define GEN6_PCODE_MAILBOX 0x138124
5028 #define GEN6_PCODE_READY (1<<31)
5029 #define GEN6_READ_OC_PARAMS 0xc
5030 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
5031 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
5032 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
5033 #define GEN6_PCODE_READ_RC6VIDS 0x5
5034 #define GEN6_PCODE_READ_D_COMP 0x10
5035 #define GEN6_PCODE_WRITE_D_COMP 0x11
5036 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5037 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
5038 #define DISPLAY_IPS_CONTROL 0x19
5039 #define GEN6_PCODE_DATA 0x138128
5040 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
5041 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
5043 #define GEN6_GT_CORE_STATUS 0x138060
5044 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
5045 #define GEN6_RCn_MASK 7
5051 #define GEN7_MISCCPCTL (0x9424)
5052 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
5055 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
5056 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
5057 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
5058 #define GEN7_PARITY_ERROR_VALID (1<<13)
5059 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
5060 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
5061 #define GEN7_PARITY_ERROR_ROW(reg) \
5062 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5063 #define GEN7_PARITY_ERROR_BANK(reg) \
5064 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5065 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
5066 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5067 #define GEN7_L3CDERRST1_ENABLE (1<<7)
5069 #define GEN7_L3LOG_BASE 0xB070
5070 #define HSW_L3LOG_BASE_SLICE1 0xB270
5071 #define GEN7_L3LOG_SIZE 0x80
5073 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
5074 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
5075 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
5076 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
5077 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
5079 #define GEN8_ROW_CHICKEN 0xe4f0
5080 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
5081 #define STALL_DOP_GATING_DISABLE (1<<5)
5083 #define GEN7_ROW_CHICKEN2 0xe4f4
5084 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
5085 #define DOP_CLOCK_GATING_DISABLE (1<<0)
5087 #define HSW_ROW_CHICKEN3 0xe49c
5088 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
5090 #define HALF_SLICE_CHICKEN3 0xe184
5091 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
5092 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
5094 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
5095 #define INTEL_AUDIO_DEVCL 0x808629FB
5096 #define INTEL_AUDIO_DEVBLC 0x80862801
5097 #define INTEL_AUDIO_DEVCTG 0x80862802
5099 #define G4X_AUD_CNTL_ST 0x620B4
5100 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
5101 #define G4X_ELDV_DEVCTG (1 << 14)
5102 #define G4X_ELD_ADDR (0xf << 5)
5103 #define G4X_ELD_ACK (1 << 4)
5104 #define G4X_HDMIW_HDMIEDID 0x6210C
5106 #define IBX_HDMIW_HDMIEDID_A 0xE2050
5107 #define IBX_HDMIW_HDMIEDID_B 0xE2150
5108 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5109 IBX_HDMIW_HDMIEDID_A, \
5110 IBX_HDMIW_HDMIEDID_B)
5111 #define IBX_AUD_CNTL_ST_A 0xE20B4
5112 #define IBX_AUD_CNTL_ST_B 0xE21B4
5113 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5114 IBX_AUD_CNTL_ST_A, \
5116 #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
5117 #define IBX_ELD_ADDRESS (0x1f << 5)
5118 #define IBX_ELD_ACK (1 << 4)
5119 #define IBX_AUD_CNTL_ST2 0xE20C0
5120 #define IBX_ELD_VALIDB (1 << 0)
5121 #define IBX_CP_READYB (1 << 1)
5123 #define CPT_HDMIW_HDMIEDID_A 0xE5050
5124 #define CPT_HDMIW_HDMIEDID_B 0xE5150
5125 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5126 CPT_HDMIW_HDMIEDID_A, \
5127 CPT_HDMIW_HDMIEDID_B)
5128 #define CPT_AUD_CNTL_ST_A 0xE50B4
5129 #define CPT_AUD_CNTL_ST_B 0xE51B4
5130 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5131 CPT_AUD_CNTL_ST_A, \
5133 #define CPT_AUD_CNTRL_ST2 0xE50C0
5135 #define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
5136 #define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
5137 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5138 VLV_HDMIW_HDMIEDID_A, \
5139 VLV_HDMIW_HDMIEDID_B)
5140 #define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
5141 #define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
5142 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5143 VLV_AUD_CNTL_ST_A, \
5145 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
5147 /* These are the 4 32-bit write offset registers for each stream
5148 * output buffer. It determines the offset from the
5149 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5151 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
5153 #define IBX_AUD_CONFIG_A 0xe2000
5154 #define IBX_AUD_CONFIG_B 0xe2100
5155 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5158 #define CPT_AUD_CONFIG_A 0xe5000
5159 #define CPT_AUD_CONFIG_B 0xe5100
5160 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5163 #define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
5164 #define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
5165 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5169 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
5170 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
5171 #define AUD_CONFIG_UPPER_N_SHIFT 20
5172 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
5173 #define AUD_CONFIG_LOWER_N_SHIFT 4
5174 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
5175 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
5176 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
5177 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
5178 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
5179 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
5180 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
5181 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
5182 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
5183 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
5184 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
5185 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
5186 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
5187 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
5190 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
5191 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
5192 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5196 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
5197 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
5198 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5199 HSW_AUD_MISC_CTRL_A, \
5200 HSW_AUD_MISC_CTRL_B)
5202 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
5203 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
5204 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5205 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5206 HSW_AUD_DIP_ELD_CTRL_ST_B)
5208 /* Audio Digital Converter */
5209 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
5210 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
5211 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5212 HSW_AUD_DIG_CNVT_1, \
5214 #define DIP_PORT_SEL_MASK 0x3
5216 #define HSW_AUD_EDID_DATA_A 0x65050
5217 #define HSW_AUD_EDID_DATA_B 0x65150
5218 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5219 HSW_AUD_EDID_DATA_A, \
5220 HSW_AUD_EDID_DATA_B)
5222 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5223 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
5224 #define AUDIO_INACTIVE_C (1<<11)
5225 #define AUDIO_INACTIVE_B (1<<7)
5226 #define AUDIO_INACTIVE_A (1<<3)
5227 #define AUDIO_OUTPUT_ENABLE_A (1<<2)
5228 #define AUDIO_OUTPUT_ENABLE_B (1<<6)
5229 #define AUDIO_OUTPUT_ENABLE_C (1<<10)
5230 #define AUDIO_ELD_VALID_A (1<<0)
5231 #define AUDIO_ELD_VALID_B (1<<4)
5232 #define AUDIO_ELD_VALID_C (1<<8)
5233 #define AUDIO_CP_READY_A (1<<1)
5234 #define AUDIO_CP_READY_B (1<<5)
5235 #define AUDIO_CP_READY_C (1<<9)
5237 /* HSW Power Wells */
5238 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
5239 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
5240 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
5241 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
5242 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5243 #define HSW_PWR_WELL_STATE_ENABLED (1<<30)
5244 #define HSW_PWR_WELL_CTL5 0x45410
5245 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5246 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
5247 #define HSW_PWR_WELL_FORCE_ON (1<<19)
5248 #define HSW_PWR_WELL_CTL6 0x45414
5250 /* Per-pipe DDI Function Control */
5251 #define TRANS_DDI_FUNC_CTL_A 0x60400
5252 #define TRANS_DDI_FUNC_CTL_B 0x61400
5253 #define TRANS_DDI_FUNC_CTL_C 0x62400
5254 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
5255 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
5257 #define TRANS_DDI_FUNC_ENABLE (1<<31)
5258 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
5259 #define TRANS_DDI_PORT_MASK (7<<28)
5260 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5261 #define TRANS_DDI_PORT_NONE (0<<28)
5262 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5263 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5264 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5265 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5266 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5267 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5268 #define TRANS_DDI_BPC_MASK (7<<20)
5269 #define TRANS_DDI_BPC_8 (0<<20)
5270 #define TRANS_DDI_BPC_10 (1<<20)
5271 #define TRANS_DDI_BPC_6 (2<<20)
5272 #define TRANS_DDI_BPC_12 (3<<20)
5273 #define TRANS_DDI_PVSYNC (1<<17)
5274 #define TRANS_DDI_PHSYNC (1<<16)
5275 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5276 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5277 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5278 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5279 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5280 #define TRANS_DDI_BFI_ENABLE (1<<4)
5282 /* DisplayPort Transport Control */
5283 #define DP_TP_CTL_A 0x64040
5284 #define DP_TP_CTL_B 0x64140
5285 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5286 #define DP_TP_CTL_ENABLE (1<<31)
5287 #define DP_TP_CTL_MODE_SST (0<<27)
5288 #define DP_TP_CTL_MODE_MST (1<<27)
5289 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
5290 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
5291 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5292 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5293 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
5294 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5295 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
5296 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
5297 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
5299 /* DisplayPort Transport Status */
5300 #define DP_TP_STATUS_A 0x64044
5301 #define DP_TP_STATUS_B 0x64144
5302 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
5303 #define DP_TP_STATUS_IDLE_DONE (1<<25)
5304 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5306 /* DDI Buffer Control */
5307 #define DDI_BUF_CTL_A 0x64000
5308 #define DDI_BUF_CTL_B 0x64100
5309 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5310 #define DDI_BUF_CTL_ENABLE (1<<31)
5312 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
5313 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
5314 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
5315 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
5316 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
5317 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
5318 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
5319 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
5320 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
5322 #define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */
5323 #define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */
5324 #define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */
5325 #define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */
5326 #define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */
5327 #define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */
5328 #define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */
5329 #define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */
5330 #define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */
5331 #define DDI_BUF_EMP_MASK (0xf<<24)
5332 #define DDI_BUF_PORT_REVERSAL (1<<16)
5333 #define DDI_BUF_IS_IDLE (1<<7)
5334 #define DDI_A_4_LANES (1<<4)
5335 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
5336 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
5338 /* DDI Buffer Translations */
5339 #define DDI_BUF_TRANS_A 0x64E00
5340 #define DDI_BUF_TRANS_B 0x64E60
5341 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
5343 /* Sideband Interface (SBI) is programmed indirectly, via
5344 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5345 * which contains the payload */
5346 #define SBI_ADDR 0xC6000
5347 #define SBI_DATA 0xC6004
5348 #define SBI_CTL_STAT 0xC6008
5349 #define SBI_CTL_DEST_ICLK (0x0<<16)
5350 #define SBI_CTL_DEST_MPHY (0x1<<16)
5351 #define SBI_CTL_OP_IORD (0x2<<8)
5352 #define SBI_CTL_OP_IOWR (0x3<<8)
5353 #define SBI_CTL_OP_CRRD (0x6<<8)
5354 #define SBI_CTL_OP_CRWR (0x7<<8)
5355 #define SBI_RESPONSE_FAIL (0x1<<1)
5356 #define SBI_RESPONSE_SUCCESS (0x0<<1)
5357 #define SBI_BUSY (0x1<<0)
5358 #define SBI_READY (0x0<<0)
5361 #define SBI_SSCDIVINTPHASE6 0x0600
5362 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
5363 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
5364 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
5365 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
5366 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
5367 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
5368 #define SBI_SSCCTL 0x020c
5369 #define SBI_SSCCTL6 0x060C
5370 #define SBI_SSCCTL_PATHALT (1<<3)
5371 #define SBI_SSCCTL_DISABLE (1<<0)
5372 #define SBI_SSCAUXDIV6 0x0610
5373 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
5374 #define SBI_DBUFF0 0x2a00
5375 #define SBI_GEN0 0x1f00
5376 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
5378 /* LPT PIXCLK_GATE */
5379 #define PIXCLK_GATE 0xC6020
5380 #define PIXCLK_GATE_UNGATE (1<<0)
5381 #define PIXCLK_GATE_GATE (0<<0)
5384 #define SPLL_CTL 0x46020
5385 #define SPLL_PLL_ENABLE (1<<31)
5386 #define SPLL_PLL_SSC (1<<28)
5387 #define SPLL_PLL_NON_SSC (2<<28)
5388 #define SPLL_PLL_LCPLL (3<<28)
5389 #define SPLL_PLL_REF_MASK (3<<28)
5390 #define SPLL_PLL_FREQ_810MHz (0<<26)
5391 #define SPLL_PLL_FREQ_1350MHz (1<<26)
5392 #define SPLL_PLL_FREQ_2700MHz (2<<26)
5393 #define SPLL_PLL_FREQ_MASK (3<<26)
5396 #define WRPLL_CTL1 0x46040
5397 #define WRPLL_CTL2 0x46060
5398 #define WRPLL_PLL_ENABLE (1<<31)
5399 #define WRPLL_PLL_SELECT_SSC (0x01<<28)
5400 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
5401 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
5402 /* WRPLL divider programming */
5403 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
5404 #define WRPLL_DIVIDER_REF_MASK (0xff)
5405 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
5406 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
5407 #define WRPLL_DIVIDER_POST_SHIFT 8
5408 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
5409 #define WRPLL_DIVIDER_FB_SHIFT 16
5410 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
5412 /* Port clock selection */
5413 #define PORT_CLK_SEL_A 0x46100
5414 #define PORT_CLK_SEL_B 0x46104
5415 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
5416 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
5417 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
5418 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
5419 #define PORT_CLK_SEL_SPLL (3<<29)
5420 #define PORT_CLK_SEL_WRPLL1 (4<<29)
5421 #define PORT_CLK_SEL_WRPLL2 (5<<29)
5422 #define PORT_CLK_SEL_NONE (7<<29)
5423 #define PORT_CLK_SEL_MASK (7<<29)
5425 /* Transcoder clock selection */
5426 #define TRANS_CLK_SEL_A 0x46140
5427 #define TRANS_CLK_SEL_B 0x46144
5428 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5429 /* For each transcoder, we need to select the corresponding port clock */
5430 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
5431 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
5433 #define TRANSA_MSA_MISC 0x60410
5434 #define TRANSB_MSA_MISC 0x61410
5435 #define TRANSC_MSA_MISC 0x62410
5436 #define TRANS_EDP_MSA_MISC 0x6f410
5437 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
5439 #define TRANS_MSA_SYNC_CLK (1<<0)
5440 #define TRANS_MSA_6_BPC (0<<5)
5441 #define TRANS_MSA_8_BPC (1<<5)
5442 #define TRANS_MSA_10_BPC (2<<5)
5443 #define TRANS_MSA_12_BPC (3<<5)
5444 #define TRANS_MSA_16_BPC (4<<5)
5447 #define LCPLL_CTL 0x130040
5448 #define LCPLL_PLL_DISABLE (1<<31)
5449 #define LCPLL_PLL_LOCK (1<<30)
5450 #define LCPLL_CLK_FREQ_MASK (3<<26)
5451 #define LCPLL_CLK_FREQ_450 (0<<26)
5452 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
5453 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
5454 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
5455 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
5456 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
5457 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
5458 #define LCPLL_CD_SOURCE_FCLK (1<<21)
5459 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5461 #define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5462 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5463 #define D_COMP_COMP_FORCE (1<<8)
5464 #define D_COMP_COMP_DISABLE (1<<0)
5466 /* Pipe WM_LINETIME - watermark line time */
5467 #define PIPE_WM_LINETIME_A 0x45270
5468 #define PIPE_WM_LINETIME_B 0x45274
5469 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5471 #define PIPE_WM_LINETIME_MASK (0x1ff)
5472 #define PIPE_WM_LINETIME_TIME(x) ((x))
5473 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
5474 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
5477 #define SFUSE_STRAP 0xc2014
5478 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
5479 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
5480 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5481 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5482 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
5484 #define WM_MISC 0x45260
5485 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5487 #define WM_DBG 0x45280
5488 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5489 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5490 #define WM_DBG_DISALLOW_SPRITE (1<<2)
5493 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5494 #define _PIPE_A_CSC_COEFF_BY 0x49014
5495 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5496 #define _PIPE_A_CSC_COEFF_BU 0x4901c
5497 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5498 #define _PIPE_A_CSC_COEFF_BV 0x49024
5499 #define _PIPE_A_CSC_MODE 0x49028
5500 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
5501 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
5502 #define CSC_MODE_YUV_TO_RGB (1 << 0)
5503 #define _PIPE_A_CSC_PREOFF_HI 0x49030
5504 #define _PIPE_A_CSC_PREOFF_ME 0x49034
5505 #define _PIPE_A_CSC_PREOFF_LO 0x49038
5506 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
5507 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
5508 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
5510 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
5511 #define _PIPE_B_CSC_COEFF_BY 0x49114
5512 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
5513 #define _PIPE_B_CSC_COEFF_BU 0x4911c
5514 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
5515 #define _PIPE_B_CSC_COEFF_BV 0x49124
5516 #define _PIPE_B_CSC_MODE 0x49128
5517 #define _PIPE_B_CSC_PREOFF_HI 0x49130
5518 #define _PIPE_B_CSC_PREOFF_ME 0x49134
5519 #define _PIPE_B_CSC_PREOFF_LO 0x49138
5520 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
5521 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
5522 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
5524 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5525 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5526 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5527 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5528 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5529 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5530 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5531 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5532 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5533 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5534 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5535 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5536 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5538 /* VLV MIPI registers */
5540 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
5541 #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
5542 #define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
5543 #define DPI_ENABLE (1 << 31) /* A + B */
5544 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
5545 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
5546 #define DUAL_LINK_MODE_MASK (1 << 26)
5547 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
5548 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
5549 #define DITHERING_ENABLE (1 << 25) /* A + B */
5550 #define FLOPPED_HSTX (1 << 23)
5551 #define DE_INVERT (1 << 19) /* XXX */
5552 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
5553 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
5554 #define AFE_LATCHOUT (1 << 17)
5555 #define LP_OUTPUT_HOLD (1 << 16)
5556 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
5557 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
5558 #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
5559 #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
5561 #define CSB_MASK (3 << 9)
5562 #define CSB_20MHZ (0 << 9)
5563 #define CSB_10MHZ (1 << 9)
5564 #define CSB_40MHZ (2 << 9)
5565 #define BANDGAP_MASK (1 << 8)
5566 #define BANDGAP_PNW_CIRCUIT (0 << 8)
5567 #define BANDGAP_LNC_CIRCUIT (1 << 8)
5568 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
5569 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
5570 #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
5571 #define TEARING_EFFECT_SHIFT 2 /* A + B */
5572 #define TEARING_EFFECT_MASK (3 << 2)
5573 #define TEARING_EFFECT_OFF (0 << 2)
5574 #define TEARING_EFFECT_DSI (1 << 2)
5575 #define TEARING_EFFECT_GPIO (2 << 2)
5576 #define LANE_CONFIGURATION_SHIFT 0
5577 #define LANE_CONFIGURATION_MASK (3 << 0)
5578 #define LANE_CONFIGURATION_4LANE (0 << 0)
5579 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
5580 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
5582 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
5583 #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
5584 #define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
5585 #define TEARING_EFFECT_DELAY_SHIFT 0
5586 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
5588 /* XXX: all bits reserved */
5589 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
5591 /* MIPI DSI Controller and D-PHY registers */
5593 #define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
5594 #define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
5595 #define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
5596 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
5597 #define ULPS_STATE_MASK (3 << 1)
5598 #define ULPS_STATE_ENTER (2 << 1)
5599 #define ULPS_STATE_EXIT (1 << 1)
5600 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
5601 #define DEVICE_READY (1 << 0)
5603 #define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
5604 #define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
5605 #define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
5606 #define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
5607 #define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
5608 #define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
5609 #define TEARING_EFFECT (1 << 31)
5610 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
5611 #define GEN_READ_DATA_AVAIL (1 << 29)
5612 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
5613 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
5614 #define RX_PROT_VIOLATION (1 << 26)
5615 #define RX_INVALID_TX_LENGTH (1 << 25)
5616 #define ACK_WITH_NO_ERROR (1 << 24)
5617 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
5618 #define LP_RX_TIMEOUT (1 << 22)
5619 #define HS_TX_TIMEOUT (1 << 21)
5620 #define DPI_FIFO_UNDERRUN (1 << 20)
5621 #define LOW_CONTENTION (1 << 19)
5622 #define HIGH_CONTENTION (1 << 18)
5623 #define TXDSI_VC_ID_INVALID (1 << 17)
5624 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
5625 #define TXCHECKSUM_ERROR (1 << 15)
5626 #define TXECC_MULTIBIT_ERROR (1 << 14)
5627 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
5628 #define TXFALSE_CONTROL_ERROR (1 << 12)
5629 #define RXDSI_VC_ID_INVALID (1 << 11)
5630 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
5631 #define RXCHECKSUM_ERROR (1 << 9)
5632 #define RXECC_MULTIBIT_ERROR (1 << 8)
5633 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
5634 #define RXFALSE_CONTROL_ERROR (1 << 6)
5635 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
5636 #define RX_LP_TX_SYNC_ERROR (1 << 4)
5637 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
5638 #define RXEOT_SYNC_ERROR (1 << 2)
5639 #define RXSOT_SYNC_ERROR (1 << 1)
5640 #define RXSOT_ERROR (1 << 0)
5642 #define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
5643 #define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
5644 #define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
5645 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
5646 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
5647 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
5648 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
5649 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
5650 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
5651 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
5652 #define VID_MODE_FORMAT_MASK (0xf << 7)
5653 #define VID_MODE_NOT_SUPPORTED (0 << 7)
5654 #define VID_MODE_FORMAT_RGB565 (1 << 7)
5655 #define VID_MODE_FORMAT_RGB666 (2 << 7)
5656 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
5657 #define VID_MODE_FORMAT_RGB888 (4 << 7)
5658 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
5659 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
5660 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
5661 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
5662 #define DATA_LANES_PRG_REG_SHIFT 0
5663 #define DATA_LANES_PRG_REG_MASK (7 << 0)
5665 #define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
5666 #define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
5667 #define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
5668 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
5670 #define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
5671 #define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
5672 #define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
5673 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
5675 #define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
5676 #define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
5677 #define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
5678 #define TURN_AROUND_TIMEOUT_MASK 0x3f
5680 #define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
5681 #define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
5682 #define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
5683 #define DEVICE_RESET_TIMER_MASK 0xffff
5685 #define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
5686 #define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
5687 #define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
5688 #define VERTICAL_ADDRESS_SHIFT 16
5689 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
5690 #define HORIZONTAL_ADDRESS_SHIFT 0
5691 #define HORIZONTAL_ADDRESS_MASK 0xffff
5693 #define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
5694 #define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
5695 #define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
5696 #define DBI_FIFO_EMPTY_HALF (0 << 0)
5697 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
5698 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
5700 /* regs below are bits 15:0 */
5701 #define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
5702 #define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
5703 #define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
5705 #define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
5706 #define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
5707 #define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
5709 #define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
5710 #define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
5711 #define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
5713 #define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
5714 #define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
5715 #define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
5717 #define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
5718 #define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
5719 #define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
5721 #define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
5722 #define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
5723 #define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
5725 #define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
5726 #define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
5727 #define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
5729 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
5730 #define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
5731 #define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
5732 /* regs above are bits 15:0 */
5734 #define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
5735 #define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
5736 #define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
5737 #define DPI_LP_MODE (1 << 6)
5738 #define BACKLIGHT_OFF (1 << 5)
5739 #define BACKLIGHT_ON (1 << 4)
5740 #define COLOR_MODE_OFF (1 << 3)
5741 #define COLOR_MODE_ON (1 << 2)
5742 #define TURN_ON (1 << 1)
5743 #define SHUTDOWN (1 << 0)
5745 #define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
5746 #define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
5747 #define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
5748 #define COMMAND_BYTE_SHIFT 0
5749 #define COMMAND_BYTE_MASK (0x3f << 0)
5751 #define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
5752 #define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
5753 #define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
5754 #define MASTER_INIT_TIMER_SHIFT 0
5755 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
5757 #define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
5758 #define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
5759 #define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
5760 #define MAX_RETURN_PKT_SIZE_SHIFT 0
5761 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
5763 #define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
5764 #define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
5765 #define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
5766 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
5767 #define DISABLE_VIDEO_BTA (1 << 3)
5768 #define IP_TG_CONFIG (1 << 2)
5769 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
5770 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
5771 #define VIDEO_MODE_BURST (3 << 0)
5773 #define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
5774 #define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
5775 #define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
5776 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
5777 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
5778 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
5779 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
5780 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
5781 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
5782 #define CLOCKSTOP (1 << 1)
5783 #define EOT_DISABLE (1 << 0)
5785 #define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
5786 #define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
5787 #define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
5788 #define LP_BYTECLK_SHIFT 0
5789 #define LP_BYTECLK_MASK (0xffff << 0)
5792 #define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
5793 #define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
5794 #define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
5797 #define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
5798 #define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
5799 #define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
5801 #define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
5802 #define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
5803 #define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
5804 #define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
5805 #define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
5806 #define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
5807 #define LONG_PACKET_WORD_COUNT_SHIFT 8
5808 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
5809 #define SHORT_PACKET_PARAM_SHIFT 8
5810 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
5811 #define VIRTUAL_CHANNEL_SHIFT 6
5812 #define VIRTUAL_CHANNEL_MASK (3 << 6)
5813 #define DATA_TYPE_SHIFT 0
5814 #define DATA_TYPE_MASK (3f << 0)
5815 /* data type values, see include/video/mipi_display.h */
5817 #define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
5818 #define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
5819 #define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
5820 #define DPI_FIFO_EMPTY (1 << 28)
5821 #define DBI_FIFO_EMPTY (1 << 27)
5822 #define LP_CTRL_FIFO_EMPTY (1 << 26)
5823 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
5824 #define LP_CTRL_FIFO_FULL (1 << 24)
5825 #define HS_CTRL_FIFO_EMPTY (1 << 18)
5826 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
5827 #define HS_CTRL_FIFO_FULL (1 << 16)
5828 #define LP_DATA_FIFO_EMPTY (1 << 10)
5829 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
5830 #define LP_DATA_FIFO_FULL (1 << 8)
5831 #define HS_DATA_FIFO_EMPTY (1 << 2)
5832 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
5833 #define HS_DATA_FIFO_FULL (1 << 0)
5835 #define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
5836 #define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
5837 #define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
5838 #define DBI_HS_LP_MODE_MASK (1 << 0)
5839 #define DBI_LP_MODE (1 << 0)
5840 #define DBI_HS_MODE (0 << 0)
5842 #define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
5843 #define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
5844 #define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
5845 #define EXIT_ZERO_COUNT_SHIFT 24
5846 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
5847 #define TRAIL_COUNT_SHIFT 16
5848 #define TRAIL_COUNT_MASK (0x1f << 16)
5849 #define CLK_ZERO_COUNT_SHIFT 8
5850 #define CLK_ZERO_COUNT_MASK (0xff << 8)
5851 #define PREPARE_COUNT_SHIFT 0
5852 #define PREPARE_COUNT_MASK (0x3f << 0)
5855 #define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
5856 #define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
5857 #define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
5859 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
5860 #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
5861 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
5862 #define LP_HS_SSW_CNT_SHIFT 16
5863 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
5864 #define HS_LP_PWR_SW_CNT_SHIFT 0
5865 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
5867 #define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
5868 #define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
5869 #define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
5870 #define STOP_STATE_STALL_COUNTER_SHIFT 0
5871 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
5873 #define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
5874 #define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
5875 #define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
5876 #define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
5877 #define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
5878 #define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
5879 #define RX_CONTENTION_DETECTED (1 << 0)
5881 /* XXX: only pipe A ?!? */
5882 #define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
5883 #define DBI_TYPEC_ENABLE (1 << 31)
5884 #define DBI_TYPEC_WIP (1 << 30)
5885 #define DBI_TYPEC_OPTION_SHIFT 28
5886 #define DBI_TYPEC_OPTION_MASK (3 << 28)
5887 #define DBI_TYPEC_FREQ_SHIFT 24
5888 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
5889 #define DBI_TYPEC_OVERRIDE (1 << 8)
5890 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
5891 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
5894 /* MIPI adapter registers */
5896 #define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
5897 #define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
5898 #define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
5899 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
5900 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
5901 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
5902 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
5903 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
5904 #define READ_REQUEST_PRIORITY_SHIFT 3
5905 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
5906 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
5907 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
5908 #define RGB_FLIP_TO_BGR (1 << 2)
5910 #define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
5911 #define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
5912 #define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
5913 #define DATA_MEM_ADDRESS_SHIFT 5
5914 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
5915 #define DATA_VALID (1 << 0)
5917 #define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
5918 #define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
5919 #define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
5920 #define DATA_LENGTH_SHIFT 0
5921 #define DATA_LENGTH_MASK (0xfffff << 0)
5923 #define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
5924 #define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
5925 #define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
5926 #define COMMAND_MEM_ADDRESS_SHIFT 5
5927 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
5928 #define AUTO_PWG_ENABLE (1 << 2)
5929 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
5930 #define COMMAND_VALID (1 << 0)
5932 #define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
5933 #define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
5934 #define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
5935 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
5936 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
5938 #define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
5939 #define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
5940 #define MIPI_READ_DATA_RETURN(pipe, n) \
5941 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
5943 #define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
5944 #define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
5945 #define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
5946 #define READ_DATA_VALID(n) (1 << (n))
5948 /* For UMS only (deprecated): */
5949 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
5950 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
5951 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
5952 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
5953 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
5954 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
5956 #endif /* _I915_REG_H_ */
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