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drm/i915: move modeset checks out of save/restore_modeset_reg
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_suspend.c
1 /*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "intel_drv.h"
30 #include "i915_reg.h"
31
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33 {
34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg;
36
37 /* On IVB, 3rd pipe shares PLL with another one */
38 if (pipe > 1)
39 return false;
40
41 if (HAS_PCH_SPLIT(dev))
42 dpll_reg = _PCH_DPLL(pipe);
43 else
44 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
45
46 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
47 }
48
49 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
50 {
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
53 u32 *array;
54 int i;
55
56 if (!i915_pipe_enabled(dev, pipe))
57 return;
58
59 if (HAS_PCH_SPLIT(dev))
60 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
61
62 if (pipe == PIPE_A)
63 array = dev_priv->regfile.save_palette_a;
64 else
65 array = dev_priv->regfile.save_palette_b;
66
67 for (i = 0; i < 256; i++)
68 array[i] = I915_READ(reg + (i << 2));
69 }
70
71 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
72 {
73 struct drm_i915_private *dev_priv = dev->dev_private;
74 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
75 u32 *array;
76 int i;
77
78 if (!i915_pipe_enabled(dev, pipe))
79 return;
80
81 if (HAS_PCH_SPLIT(dev))
82 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
83
84 if (pipe == PIPE_A)
85 array = dev_priv->regfile.save_palette_a;
86 else
87 array = dev_priv->regfile.save_palette_b;
88
89 for (i = 0; i < 256; i++)
90 I915_WRITE(reg + (i << 2), array[i]);
91 }
92
93 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
94 {
95 struct drm_i915_private *dev_priv = dev->dev_private;
96
97 I915_WRITE8(index_port, reg);
98 return I915_READ8(data_port);
99 }
100
101 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
102 {
103 struct drm_i915_private *dev_priv = dev->dev_private;
104
105 I915_READ8(st01);
106 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
107 return I915_READ8(VGA_AR_DATA_READ);
108 }
109
110 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
111 {
112 struct drm_i915_private *dev_priv = dev->dev_private;
113
114 I915_READ8(st01);
115 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
116 I915_WRITE8(VGA_AR_DATA_WRITE, val);
117 }
118
119 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
120 {
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 I915_WRITE8(index_port, reg);
124 I915_WRITE8(data_port, val);
125 }
126
127 static void i915_save_vga(struct drm_device *dev)
128 {
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 int i;
131 u16 cr_index, cr_data, st01;
132
133 /* VGA color palette registers */
134 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
135
136 /* MSR bits */
137 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
138 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
139 cr_index = VGA_CR_INDEX_CGA;
140 cr_data = VGA_CR_DATA_CGA;
141 st01 = VGA_ST01_CGA;
142 } else {
143 cr_index = VGA_CR_INDEX_MDA;
144 cr_data = VGA_CR_DATA_MDA;
145 st01 = VGA_ST01_MDA;
146 }
147
148 /* CRT controller regs */
149 i915_write_indexed(dev, cr_index, cr_data, 0x11,
150 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
151 (~0x80));
152 for (i = 0; i <= 0x24; i++)
153 dev_priv->regfile.saveCR[i] =
154 i915_read_indexed(dev, cr_index, cr_data, i);
155 /* Make sure we don't turn off CR group 0 writes */
156 dev_priv->regfile.saveCR[0x11] &= ~0x80;
157
158 /* Attribute controller registers */
159 I915_READ8(st01);
160 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
161 for (i = 0; i <= 0x14; i++)
162 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
163 I915_READ8(st01);
164 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
165 I915_READ8(st01);
166
167 /* Graphics controller registers */
168 for (i = 0; i < 9; i++)
169 dev_priv->regfile.saveGR[i] =
170 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
171
172 dev_priv->regfile.saveGR[0x10] =
173 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
174 dev_priv->regfile.saveGR[0x11] =
175 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
176 dev_priv->regfile.saveGR[0x18] =
177 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
178
179 /* Sequencer registers */
180 for (i = 0; i < 8; i++)
181 dev_priv->regfile.saveSR[i] =
182 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
183 }
184
185 static void i915_restore_vga(struct drm_device *dev)
186 {
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 int i;
189 u16 cr_index, cr_data, st01;
190
191 /* MSR bits */
192 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
193 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
194 cr_index = VGA_CR_INDEX_CGA;
195 cr_data = VGA_CR_DATA_CGA;
196 st01 = VGA_ST01_CGA;
197 } else {
198 cr_index = VGA_CR_INDEX_MDA;
199 cr_data = VGA_CR_DATA_MDA;
200 st01 = VGA_ST01_MDA;
201 }
202
203 /* Sequencer registers, don't write SR07 */
204 for (i = 0; i < 7; i++)
205 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
206 dev_priv->regfile.saveSR[i]);
207
208 /* CRT controller regs */
209 /* Enable CR group 0 writes */
210 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
211 for (i = 0; i <= 0x24; i++)
212 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
213
214 /* Graphics controller regs */
215 for (i = 0; i < 9; i++)
216 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
217 dev_priv->regfile.saveGR[i]);
218
219 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
220 dev_priv->regfile.saveGR[0x10]);
221 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
222 dev_priv->regfile.saveGR[0x11]);
223 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
224 dev_priv->regfile.saveGR[0x18]);
225
226 /* Attribute controller registers */
227 I915_READ8(st01); /* switch back to index mode */
228 for (i = 0; i <= 0x14; i++)
229 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
230 I915_READ8(st01); /* switch back to index mode */
231 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
232 I915_READ8(st01);
233
234 /* VGA color palette registers */
235 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
236 }
237
238 static void i915_save_modeset_reg(struct drm_device *dev)
239 {
240 struct drm_i915_private *dev_priv = dev->dev_private;
241 int i;
242
243 /* Cursor state */
244 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
245 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
246 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
247 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
248 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
249 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
250 if (IS_GEN2(dev))
251 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
252
253 if (HAS_PCH_SPLIT(dev)) {
254 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
255 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
256 }
257
258 /* Pipe & plane A info */
259 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
260 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
261 if (HAS_PCH_SPLIT(dev)) {
262 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
263 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
264 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
265 } else {
266 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
267 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
268 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
269 }
270 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
271 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
272 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
273 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
274 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
275 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
276 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
277 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
278 if (!HAS_PCH_SPLIT(dev))
279 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
280
281 if (HAS_PCH_SPLIT(dev)) {
282 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
283 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
284 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
285 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
286
287 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
288 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
289
290 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
291 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
292 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
293
294 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
295 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
296 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
297 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
298 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
299 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
300 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
301 }
302
303 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
304 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
305 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
306 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
307 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
308 if (INTEL_INFO(dev)->gen >= 4) {
309 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
310 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
311 }
312 i915_save_palette(dev, PIPE_A);
313 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
314
315 /* Pipe & plane B info */
316 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
317 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
318 if (HAS_PCH_SPLIT(dev)) {
319 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
320 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
321 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
322 } else {
323 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
324 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
325 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
326 }
327 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
328 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
329 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
330 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
331 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
332 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
333 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
334 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
335 if (!HAS_PCH_SPLIT(dev))
336 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
337
338 if (HAS_PCH_SPLIT(dev)) {
339 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
340 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
341 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
342 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
343
344 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
345 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
346
347 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
348 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
349 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
350
351 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
352 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
353 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
354 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
355 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
356 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
357 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
358 }
359
360 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
361 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
362 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
363 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
364 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
365 if (INTEL_INFO(dev)->gen >= 4) {
366 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
367 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
368 }
369 i915_save_palette(dev, PIPE_B);
370 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
371
372 /* Fences */
373 switch (INTEL_INFO(dev)->gen) {
374 case 7:
375 case 6:
376 for (i = 0; i < 16; i++)
377 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
378 break;
379 case 5:
380 case 4:
381 for (i = 0; i < 16; i++)
382 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
383 break;
384 case 3:
385 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
386 for (i = 0; i < 8; i++)
387 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
388 case 2:
389 for (i = 0; i < 8; i++)
390 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
391 break;
392 }
393
394 /* CRT state */
395 if (HAS_PCH_SPLIT(dev))
396 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
397 else
398 dev_priv->regfile.saveADPA = I915_READ(ADPA);
399
400 return;
401 }
402
403 static void i915_restore_modeset_reg(struct drm_device *dev)
404 {
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 int dpll_a_reg, fpa0_reg, fpa1_reg;
407 int dpll_b_reg, fpb0_reg, fpb1_reg;
408 int i;
409
410 /* Display port ratios (must be done before clock is set) */
411 if (SUPPORTS_INTEGRATED_DP(dev)) {
412 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
413 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
414 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
415 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
416 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
417 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
418 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
419 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
420 }
421
422 /* Fences */
423 switch (INTEL_INFO(dev)->gen) {
424 case 7:
425 case 6:
426 for (i = 0; i < 16; i++)
427 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
428 break;
429 case 5:
430 case 4:
431 for (i = 0; i < 16; i++)
432 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
433 break;
434 case 3:
435 case 2:
436 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
437 for (i = 0; i < 8; i++)
438 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
439 for (i = 0; i < 8; i++)
440 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
441 break;
442 }
443
444
445 if (HAS_PCH_SPLIT(dev)) {
446 dpll_a_reg = _PCH_DPLL_A;
447 dpll_b_reg = _PCH_DPLL_B;
448 fpa0_reg = _PCH_FPA0;
449 fpb0_reg = _PCH_FPB0;
450 fpa1_reg = _PCH_FPA1;
451 fpb1_reg = _PCH_FPB1;
452 } else {
453 dpll_a_reg = _DPLL_A;
454 dpll_b_reg = _DPLL_B;
455 fpa0_reg = _FPA0;
456 fpb0_reg = _FPB0;
457 fpa1_reg = _FPA1;
458 fpb1_reg = _FPB1;
459 }
460
461 if (HAS_PCH_SPLIT(dev)) {
462 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
463 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
464 }
465
466 /* Pipe & plane A info */
467 /* Prime the clock */
468 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
469 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
470 ~DPLL_VCO_ENABLE);
471 POSTING_READ(dpll_a_reg);
472 udelay(150);
473 }
474 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
475 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
476 /* Actually enable it */
477 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
478 POSTING_READ(dpll_a_reg);
479 udelay(150);
480 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
481 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
482 POSTING_READ(_DPLL_A_MD);
483 }
484 udelay(150);
485
486 /* Restore mode */
487 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
488 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
489 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
490 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
491 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
492 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
493 if (!HAS_PCH_SPLIT(dev))
494 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
495
496 if (HAS_PCH_SPLIT(dev)) {
497 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
498 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
499 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
500 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
501
502 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
503 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
504
505 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
506 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
507 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
508
509 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
510 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
511 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
512 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
513 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
514 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
515 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
516 }
517
518 /* Restore plane info */
519 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
520 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
521 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
522 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
523 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
524 if (INTEL_INFO(dev)->gen >= 4) {
525 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
526 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
527 }
528
529 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
530
531 i915_restore_palette(dev, PIPE_A);
532 /* Enable the plane */
533 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
534 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
535
536 /* Pipe & plane B info */
537 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
538 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
539 ~DPLL_VCO_ENABLE);
540 POSTING_READ(dpll_b_reg);
541 udelay(150);
542 }
543 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
544 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
545 /* Actually enable it */
546 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
547 POSTING_READ(dpll_b_reg);
548 udelay(150);
549 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
550 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
551 POSTING_READ(_DPLL_B_MD);
552 }
553 udelay(150);
554
555 /* Restore mode */
556 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
557 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
558 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
559 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
560 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
561 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
562 if (!HAS_PCH_SPLIT(dev))
563 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
564
565 if (HAS_PCH_SPLIT(dev)) {
566 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
567 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
568 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
569 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
570
571 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
572 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
573
574 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
575 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
576 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
577
578 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
579 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
580 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
581 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
582 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
583 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
584 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
585 }
586
587 /* Restore plane info */
588 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
589 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
590 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
591 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
592 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
593 if (INTEL_INFO(dev)->gen >= 4) {
594 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
595 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
596 }
597
598 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
599
600 i915_restore_palette(dev, PIPE_B);
601 /* Enable the plane */
602 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
603 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
604
605 /* Cursor state */
606 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
607 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
608 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
609 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
610 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
611 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
612 if (IS_GEN2(dev))
613 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
614
615 /* CRT state */
616 if (HAS_PCH_SPLIT(dev))
617 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
618 else
619 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
620
621 return;
622 }
623
624 static void i915_save_display(struct drm_device *dev)
625 {
626 struct drm_i915_private *dev_priv = dev->dev_private;
627
628 /* Display arbitration control */
629 if (INTEL_INFO(dev)->gen <= 4)
630 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
631
632 /* This is only meaningful in non-KMS mode */
633 /* Don't regfile.save them in KMS mode */
634 if (!drm_core_check_feature(dev, DRIVER_MODESET))
635 i915_save_modeset_reg(dev);
636
637 /* LVDS state */
638 if (HAS_PCH_SPLIT(dev)) {
639 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
640 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
641 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
642 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
643 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
644 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
645 } else {
646 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
647 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
648 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
649 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
650 if (INTEL_INFO(dev)->gen >= 4)
651 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
652 if (IS_MOBILE(dev) && !IS_I830(dev))
653 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
654 }
655
656 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
657 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
658
659 if (HAS_PCH_SPLIT(dev)) {
660 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
661 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
662 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
663 } else {
664 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
665 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
666 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
667 }
668
669 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
670 /* Display Port state */
671 if (SUPPORTS_INTEGRATED_DP(dev)) {
672 dev_priv->regfile.saveDP_B = I915_READ(DP_B);
673 dev_priv->regfile.saveDP_C = I915_READ(DP_C);
674 dev_priv->regfile.saveDP_D = I915_READ(DP_D);
675 dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
676 dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
677 dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
678 dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
679 dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
680 dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
681 dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
682 dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
683 }
684 /* FIXME: regfile.save TV & SDVO state */
685 }
686
687 /* Only regfile.save FBC state on the platform that supports FBC */
688 if (I915_HAS_FBC(dev)) {
689 if (HAS_PCH_SPLIT(dev)) {
690 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
691 } else if (IS_GM45(dev)) {
692 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
693 } else {
694 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
695 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
696 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
697 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
698 }
699 }
700
701 /* VGA state */
702 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
703 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
704 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
705 if (HAS_PCH_SPLIT(dev))
706 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
707 else
708 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
709
710 i915_save_vga(dev);
711 }
712
713 static void i915_restore_display(struct drm_device *dev)
714 {
715 struct drm_i915_private *dev_priv = dev->dev_private;
716
717 /* Display arbitration */
718 if (INTEL_INFO(dev)->gen <= 4)
719 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
720
721 if (!drm_core_check_feature(dev, DRIVER_MODESET))
722 i915_restore_modeset_reg(dev);
723
724 /* LVDS state */
725 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
726 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
727
728 if (HAS_PCH_SPLIT(dev)) {
729 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
730 } else if (IS_MOBILE(dev) && !IS_I830(dev))
731 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
732
733 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
734 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
735
736 if (HAS_PCH_SPLIT(dev)) {
737 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
738 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
739 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
740 * otherwise we get blank eDP screen after S3 on some machines
741 */
742 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
743 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
744 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
745 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
746 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
747 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
748 I915_WRITE(RSTDBYCTL,
749 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
750 } else {
751 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
752 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
753 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
754 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
755 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
756 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
757 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
758 }
759
760 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
761 /* Display Port state */
762 if (SUPPORTS_INTEGRATED_DP(dev)) {
763 I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
764 I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
765 I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
766 }
767 /* FIXME: restore TV & SDVO state */
768 }
769
770 /* only restore FBC info on the platform that supports FBC*/
771 intel_disable_fbc(dev);
772 if (I915_HAS_FBC(dev)) {
773 if (HAS_PCH_SPLIT(dev)) {
774 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
775 } else if (IS_GM45(dev)) {
776 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
777 } else {
778 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
779 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
780 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
781 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
782 }
783 }
784 /* VGA state */
785 if (HAS_PCH_SPLIT(dev))
786 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
787 else
788 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
789
790 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
791 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
792 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
793 POSTING_READ(VGA_PD);
794 udelay(150);
795
796 i915_restore_vga(dev);
797 }
798
799 int i915_save_state(struct drm_device *dev)
800 {
801 struct drm_i915_private *dev_priv = dev->dev_private;
802 int i;
803
804 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
805
806 mutex_lock(&dev->struct_mutex);
807
808 i915_save_display(dev);
809
810 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
811 /* Interrupt state */
812 if (HAS_PCH_SPLIT(dev)) {
813 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
814 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
815 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
816 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
817 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
818 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
819 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
820 I915_READ(RSTDBYCTL);
821 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
822 } else {
823 dev_priv->regfile.saveIER = I915_READ(IER);
824 dev_priv->regfile.saveIMR = I915_READ(IMR);
825 }
826 }
827
828 intel_disable_gt_powersave(dev);
829
830 /* Cache mode state */
831 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
832
833 /* Memory Arbitration state */
834 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
835
836 /* Scratch space */
837 for (i = 0; i < 16; i++) {
838 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
839 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
840 }
841 for (i = 0; i < 3; i++)
842 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
843
844 mutex_unlock(&dev->struct_mutex);
845
846 return 0;
847 }
848
849 int i915_restore_state(struct drm_device *dev)
850 {
851 struct drm_i915_private *dev_priv = dev->dev_private;
852 int i;
853
854 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
855
856 mutex_lock(&dev->struct_mutex);
857
858 i915_restore_display(dev);
859
860 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
861 /* Interrupt state */
862 if (HAS_PCH_SPLIT(dev)) {
863 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
864 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
865 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
866 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
867 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
868 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
869 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
870 } else {
871 I915_WRITE(IER, dev_priv->regfile.saveIER);
872 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
873 }
874 }
875
876 /* Cache mode state */
877 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
878
879 /* Memory arbitration state */
880 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
881
882 for (i = 0; i < 16; i++) {
883 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
884 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
885 }
886 for (i = 0; i < 3; i++)
887 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
888
889 mutex_unlock(&dev->struct_mutex);
890
891 intel_i2c_reset(dev);
892
893 return 0;
894 }
Linux kernel - Deliverables
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