2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
35 #define dev_to_drm_minor(d) dev_get_drvdata((d))
38 static u32
calc_residency(struct drm_device
*dev
, const u32 reg
)
40 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
41 u64 raw_time
; /* 32b value may overflow during fixed point math */
42 u64 units
= 128ULL, div
= 100000ULL, bias
= 100ULL;
45 if (!intel_enable_rc6(dev
))
48 intel_runtime_pm_get(dev_priv
);
50 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
51 if (IS_VALLEYVIEW(dev
)) {
52 u32 reg
, czcount_30ns
;
54 if (IS_CHERRYVIEW(dev
))
59 czcount_30ns
= I915_READ(reg
) >> CLK_CTL2_CZCOUNT_30NS_SHIFT
;
62 WARN(!czcount_30ns
, "bogus CZ count value");
70 if (IS_CHERRYVIEW(dev
)) {
71 /* Special case for 320Mhz */
72 if (czcount_30ns
== 1) {
76 /* chv counts are one less */
82 units
= DIV_ROUND_UP_ULL(30ULL * bias
,
85 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
91 raw_time
= I915_READ(reg
) * units
;
92 ret
= DIV_ROUND_UP_ULL(raw_time
, div
);
95 intel_runtime_pm_put(dev_priv
);
100 show_rc6_mask(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
102 struct drm_minor
*dminor
= dev_to_drm_minor(kdev
);
103 return snprintf(buf
, PAGE_SIZE
, "%x\n", intel_enable_rc6(dminor
->dev
));
107 show_rc6_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
109 struct drm_minor
*dminor
= dev_get_drvdata(kdev
);
110 u32 rc6_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6
);
111 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6_residency
);
115 show_rc6p_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
117 struct drm_minor
*dminor
= dev_to_drm_minor(kdev
);
118 u32 rc6p_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6p
);
119 if (IS_VALLEYVIEW(dminor
->dev
))
121 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6p_residency
);
125 show_rc6pp_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
127 struct drm_minor
*dminor
= dev_to_drm_minor(kdev
);
128 u32 rc6pp_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6pp
);
129 if (IS_VALLEYVIEW(dminor
->dev
))
131 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6pp_residency
);
134 static DEVICE_ATTR(rc6_enable
, S_IRUGO
, show_rc6_mask
, NULL
);
135 static DEVICE_ATTR(rc6_residency_ms
, S_IRUGO
, show_rc6_ms
, NULL
);
136 static DEVICE_ATTR(rc6p_residency_ms
, S_IRUGO
, show_rc6p_ms
, NULL
);
137 static DEVICE_ATTR(rc6pp_residency_ms
, S_IRUGO
, show_rc6pp_ms
, NULL
);
139 static struct attribute
*rc6_attrs
[] = {
140 &dev_attr_rc6_enable
.attr
,
141 &dev_attr_rc6_residency_ms
.attr
,
145 static struct attribute_group rc6_attr_group
= {
146 .name
= power_group_name
,
150 static struct attribute
*rc6p_attrs
[] = {
151 &dev_attr_rc6p_residency_ms
.attr
,
152 &dev_attr_rc6pp_residency_ms
.attr
,
156 static struct attribute_group rc6p_attr_group
= {
157 .name
= power_group_name
,
162 static int l3_access_valid(struct drm_device
*dev
, loff_t offset
)
164 if (!HAS_L3_DPF(dev
))
170 if (offset
>= GEN7_L3LOG_SIZE
)
177 i915_l3_read(struct file
*filp
, struct kobject
*kobj
,
178 struct bin_attribute
*attr
, char *buf
,
179 loff_t offset
, size_t count
)
181 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
182 struct drm_minor
*dminor
= dev_to_drm_minor(dev
);
183 struct drm_device
*drm_dev
= dminor
->dev
;
184 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
185 int slice
= (int)(uintptr_t)attr
->private;
188 count
= round_down(count
, 4);
190 ret
= l3_access_valid(drm_dev
, offset
);
194 count
= min_t(size_t, GEN7_L3LOG_SIZE
- offset
, count
);
196 ret
= i915_mutex_lock_interruptible(drm_dev
);
200 if (dev_priv
->l3_parity
.remap_info
[slice
])
202 dev_priv
->l3_parity
.remap_info
[slice
] + (offset
/4),
205 memset(buf
, 0, count
);
207 mutex_unlock(&drm_dev
->struct_mutex
);
213 i915_l3_write(struct file
*filp
, struct kobject
*kobj
,
214 struct bin_attribute
*attr
, char *buf
,
215 loff_t offset
, size_t count
)
217 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
218 struct drm_minor
*dminor
= dev_to_drm_minor(dev
);
219 struct drm_device
*drm_dev
= dminor
->dev
;
220 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
221 struct intel_context
*ctx
;
222 u32
*temp
= NULL
; /* Just here to make handling failures easy */
223 int slice
= (int)(uintptr_t)attr
->private;
226 if (!HAS_HW_CONTEXTS(drm_dev
))
229 ret
= l3_access_valid(drm_dev
, offset
);
233 ret
= i915_mutex_lock_interruptible(drm_dev
);
237 if (!dev_priv
->l3_parity
.remap_info
[slice
]) {
238 temp
= kzalloc(GEN7_L3LOG_SIZE
, GFP_KERNEL
);
240 mutex_unlock(&drm_dev
->struct_mutex
);
245 ret
= i915_gpu_idle(drm_dev
);
248 mutex_unlock(&drm_dev
->struct_mutex
);
252 /* TODO: Ideally we really want a GPU reset here to make sure errors
253 * aren't propagated. Since I cannot find a stable way to reset the GPU
254 * at this point it is left as a TODO.
257 dev_priv
->l3_parity
.remap_info
[slice
] = temp
;
259 memcpy(dev_priv
->l3_parity
.remap_info
[slice
] + (offset
/4), buf
, count
);
261 /* NB: We defer the remapping until we switch to the context */
262 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
263 ctx
->remap_slice
|= (1<<slice
);
265 mutex_unlock(&drm_dev
->struct_mutex
);
270 static struct bin_attribute dpf_attrs
= {
271 .attr
= {.name
= "l3_parity", .mode
= (S_IRUSR
| S_IWUSR
)},
272 .size
= GEN7_L3LOG_SIZE
,
273 .read
= i915_l3_read
,
274 .write
= i915_l3_write
,
279 static struct bin_attribute dpf_attrs_1
= {
280 .attr
= {.name
= "l3_parity_slice_1", .mode
= (S_IRUSR
| S_IWUSR
)},
281 .size
= GEN7_L3LOG_SIZE
,
282 .read
= i915_l3_read
,
283 .write
= i915_l3_write
,
288 static ssize_t
gt_cur_freq_mhz_show(struct device
*kdev
,
289 struct device_attribute
*attr
, char *buf
)
291 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
292 struct drm_device
*dev
= minor
->dev
;
293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
296 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
298 intel_runtime_pm_get(dev_priv
);
300 mutex_lock(&dev_priv
->rps
.hw_lock
);
301 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
303 freq
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
304 ret
= vlv_gpu_freq(dev_priv
, (freq
>> 8) & 0xff);
306 ret
= dev_priv
->rps
.cur_freq
* GT_FREQUENCY_MULTIPLIER
;
308 mutex_unlock(&dev_priv
->rps
.hw_lock
);
310 intel_runtime_pm_put(dev_priv
);
312 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
315 static ssize_t
vlv_rpe_freq_mhz_show(struct device
*kdev
,
316 struct device_attribute
*attr
, char *buf
)
318 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
319 struct drm_device
*dev
= minor
->dev
;
320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
322 return snprintf(buf
, PAGE_SIZE
, "%d\n",
323 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
326 static ssize_t
gt_max_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
328 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
329 struct drm_device
*dev
= minor
->dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
335 mutex_lock(&dev_priv
->rps
.hw_lock
);
336 if (IS_VALLEYVIEW(dev_priv
->dev
))
337 ret
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
339 ret
= dev_priv
->rps
.max_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
340 mutex_unlock(&dev_priv
->rps
.hw_lock
);
342 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
345 static ssize_t
gt_max_freq_mhz_store(struct device
*kdev
,
346 struct device_attribute
*attr
,
347 const char *buf
, size_t count
)
349 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
350 struct drm_device
*dev
= minor
->dev
;
351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
355 ret
= kstrtou32(buf
, 0, &val
);
359 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
361 mutex_lock(&dev_priv
->rps
.hw_lock
);
363 if (IS_VALLEYVIEW(dev_priv
->dev
))
364 val
= vlv_freq_opcode(dev_priv
, val
);
366 val
/= GT_FREQUENCY_MULTIPLIER
;
368 if (val
< dev_priv
->rps
.min_freq
||
369 val
> dev_priv
->rps
.max_freq
||
370 val
< dev_priv
->rps
.min_freq_softlimit
) {
371 mutex_unlock(&dev_priv
->rps
.hw_lock
);
375 if (val
> dev_priv
->rps
.rp0_freq
)
376 DRM_DEBUG("User requested overclocking to %d\n",
377 val
* GT_FREQUENCY_MULTIPLIER
);
379 dev_priv
->rps
.max_freq_softlimit
= val
;
381 if (dev_priv
->rps
.cur_freq
> val
) {
382 if (IS_VALLEYVIEW(dev
))
383 valleyview_set_rps(dev
, val
);
385 gen6_set_rps(dev
, val
);
386 } else if (!IS_VALLEYVIEW(dev
)) {
387 /* We still need gen6_set_rps to process the new max_delay and
388 * update the interrupt limits even though frequency request is
390 gen6_set_rps(dev
, dev_priv
->rps
.cur_freq
);
393 mutex_unlock(&dev_priv
->rps
.hw_lock
);
398 static ssize_t
gt_min_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
400 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
401 struct drm_device
*dev
= minor
->dev
;
402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
405 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
407 mutex_lock(&dev_priv
->rps
.hw_lock
);
408 if (IS_VALLEYVIEW(dev_priv
->dev
))
409 ret
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
411 ret
= dev_priv
->rps
.min_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
412 mutex_unlock(&dev_priv
->rps
.hw_lock
);
414 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
417 static ssize_t
gt_min_freq_mhz_store(struct device
*kdev
,
418 struct device_attribute
*attr
,
419 const char *buf
, size_t count
)
421 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
422 struct drm_device
*dev
= minor
->dev
;
423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
427 ret
= kstrtou32(buf
, 0, &val
);
431 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
433 mutex_lock(&dev_priv
->rps
.hw_lock
);
435 if (IS_VALLEYVIEW(dev
))
436 val
= vlv_freq_opcode(dev_priv
, val
);
438 val
/= GT_FREQUENCY_MULTIPLIER
;
440 if (val
< dev_priv
->rps
.min_freq
||
441 val
> dev_priv
->rps
.max_freq
||
442 val
> dev_priv
->rps
.max_freq_softlimit
) {
443 mutex_unlock(&dev_priv
->rps
.hw_lock
);
447 dev_priv
->rps
.min_freq_softlimit
= val
;
449 if (dev_priv
->rps
.cur_freq
< val
) {
450 if (IS_VALLEYVIEW(dev
))
451 valleyview_set_rps(dev
, val
);
453 gen6_set_rps(dev
, val
);
454 } else if (!IS_VALLEYVIEW(dev
)) {
455 /* We still need gen6_set_rps to process the new min_delay and
456 * update the interrupt limits even though frequency request is
458 gen6_set_rps(dev
, dev_priv
->rps
.cur_freq
);
461 mutex_unlock(&dev_priv
->rps
.hw_lock
);
467 static DEVICE_ATTR(gt_cur_freq_mhz
, S_IRUGO
, gt_cur_freq_mhz_show
, NULL
);
468 static DEVICE_ATTR(gt_max_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_max_freq_mhz_show
, gt_max_freq_mhz_store
);
469 static DEVICE_ATTR(gt_min_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_min_freq_mhz_show
, gt_min_freq_mhz_store
);
471 static DEVICE_ATTR(vlv_rpe_freq_mhz
, S_IRUGO
, vlv_rpe_freq_mhz_show
, NULL
);
473 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
);
474 static DEVICE_ATTR(gt_RP0_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
475 static DEVICE_ATTR(gt_RP1_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
476 static DEVICE_ATTR(gt_RPn_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
478 /* For now we have a static number of RP states */
479 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
481 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
482 struct drm_device
*dev
= minor
->dev
;
483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 u32 val
, rp_state_cap
;
487 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
490 intel_runtime_pm_get(dev_priv
);
491 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
492 intel_runtime_pm_put(dev_priv
);
493 mutex_unlock(&dev
->struct_mutex
);
495 if (attr
== &dev_attr_gt_RP0_freq_mhz
) {
496 if (IS_VALLEYVIEW(dev
))
497 val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp0_freq
);
499 val
= ((rp_state_cap
& 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER
;
500 } else if (attr
== &dev_attr_gt_RP1_freq_mhz
) {
501 if (IS_VALLEYVIEW(dev
))
502 val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
);
504 val
= ((rp_state_cap
& 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER
;
505 } else if (attr
== &dev_attr_gt_RPn_freq_mhz
) {
506 if (IS_VALLEYVIEW(dev
))
507 val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
);
509 val
= ((rp_state_cap
& 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER
;
513 return snprintf(buf
, PAGE_SIZE
, "%d\n", val
);
516 static const struct attribute
*gen6_attrs
[] = {
517 &dev_attr_gt_cur_freq_mhz
.attr
,
518 &dev_attr_gt_max_freq_mhz
.attr
,
519 &dev_attr_gt_min_freq_mhz
.attr
,
520 &dev_attr_gt_RP0_freq_mhz
.attr
,
521 &dev_attr_gt_RP1_freq_mhz
.attr
,
522 &dev_attr_gt_RPn_freq_mhz
.attr
,
526 static const struct attribute
*vlv_attrs
[] = {
527 &dev_attr_gt_cur_freq_mhz
.attr
,
528 &dev_attr_gt_max_freq_mhz
.attr
,
529 &dev_attr_gt_min_freq_mhz
.attr
,
530 &dev_attr_gt_RP0_freq_mhz
.attr
,
531 &dev_attr_gt_RP1_freq_mhz
.attr
,
532 &dev_attr_gt_RPn_freq_mhz
.attr
,
533 &dev_attr_vlv_rpe_freq_mhz
.attr
,
537 static ssize_t
error_state_read(struct file
*filp
, struct kobject
*kobj
,
538 struct bin_attribute
*attr
, char *buf
,
539 loff_t off
, size_t count
)
542 struct device
*kdev
= container_of(kobj
, struct device
, kobj
);
543 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
544 struct drm_device
*dev
= minor
->dev
;
545 struct i915_error_state_file_priv error_priv
;
546 struct drm_i915_error_state_buf error_str
;
547 ssize_t ret_count
= 0;
550 memset(&error_priv
, 0, sizeof(error_priv
));
552 ret
= i915_error_state_buf_init(&error_str
, to_i915(dev
), count
, off
);
556 error_priv
.dev
= dev
;
557 i915_error_state_get(dev
, &error_priv
);
559 ret
= i915_error_state_to_str(&error_str
, &error_priv
);
563 ret_count
= count
< error_str
.bytes
? count
: error_str
.bytes
;
565 memcpy(buf
, error_str
.buf
, ret_count
);
567 i915_error_state_put(&error_priv
);
568 i915_error_state_buf_release(&error_str
);
570 return ret
?: ret_count
;
573 static ssize_t
error_state_write(struct file
*file
, struct kobject
*kobj
,
574 struct bin_attribute
*attr
, char *buf
,
575 loff_t off
, size_t count
)
577 struct device
*kdev
= container_of(kobj
, struct device
, kobj
);
578 struct drm_minor
*minor
= dev_to_drm_minor(kdev
);
579 struct drm_device
*dev
= minor
->dev
;
582 DRM_DEBUG_DRIVER("Resetting error state\n");
584 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
588 i915_destroy_error_state(dev
);
589 mutex_unlock(&dev
->struct_mutex
);
594 static struct bin_attribute error_state_attr
= {
595 .attr
.name
= "error",
596 .attr
.mode
= S_IRUSR
| S_IWUSR
,
598 .read
= error_state_read
,
599 .write
= error_state_write
,
602 void i915_setup_sysfs(struct drm_device
*dev
)
608 ret
= sysfs_merge_group(&dev
->primary
->kdev
->kobj
,
611 DRM_ERROR("RC6 residency sysfs setup failed\n");
614 ret
= sysfs_merge_group(&dev
->primary
->kdev
->kobj
,
617 DRM_ERROR("RC6p residency sysfs setup failed\n");
620 if (HAS_L3_DPF(dev
)) {
621 ret
= device_create_bin_file(dev
->primary
->kdev
, &dpf_attrs
);
623 DRM_ERROR("l3 parity sysfs setup failed\n");
625 if (NUM_L3_SLICES(dev
) > 1) {
626 ret
= device_create_bin_file(dev
->primary
->kdev
,
629 DRM_ERROR("l3 parity slice 1 setup failed\n");
634 if (IS_VALLEYVIEW(dev
))
635 ret
= sysfs_create_files(&dev
->primary
->kdev
->kobj
, vlv_attrs
);
636 else if (INTEL_INFO(dev
)->gen
>= 6)
637 ret
= sysfs_create_files(&dev
->primary
->kdev
->kobj
, gen6_attrs
);
639 DRM_ERROR("RPS sysfs setup failed\n");
641 ret
= sysfs_create_bin_file(&dev
->primary
->kdev
->kobj
,
644 DRM_ERROR("error_state sysfs setup failed\n");
647 void i915_teardown_sysfs(struct drm_device
*dev
)
649 sysfs_remove_bin_file(&dev
->primary
->kdev
->kobj
, &error_state_attr
);
650 if (IS_VALLEYVIEW(dev
))
651 sysfs_remove_files(&dev
->primary
->kdev
->kobj
, vlv_attrs
);
653 sysfs_remove_files(&dev
->primary
->kdev
->kobj
, gen6_attrs
);
654 device_remove_bin_file(dev
->primary
->kdev
, &dpf_attrs_1
);
655 device_remove_bin_file(dev
->primary
->kdev
, &dpf_attrs
);
657 sysfs_unmerge_group(&dev
->primary
->kdev
->kobj
, &rc6_attr_group
);
658 sysfs_unmerge_group(&dev
->primary
->kdev
->kobj
, &rc6p_attr_group
);