2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
36 static u32
calc_residency(struct drm_device
*dev
, const u32 reg
)
38 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
39 u64 raw_time
; /* 32b value may overflow during fixed point math */
41 if (!intel_enable_rc6(dev
))
44 raw_time
= I915_READ(reg
) * 128ULL;
45 return DIV_ROUND_UP_ULL(raw_time
, 100000);
49 show_rc6_mask(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
51 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
52 return snprintf(buf
, PAGE_SIZE
, "%x", intel_enable_rc6(dminor
->dev
));
56 show_rc6_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
58 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
59 u32 rc6_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6
);
60 return snprintf(buf
, PAGE_SIZE
, "%u", rc6_residency
);
64 show_rc6p_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
66 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
67 u32 rc6p_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6p
);
68 return snprintf(buf
, PAGE_SIZE
, "%u", rc6p_residency
);
72 show_rc6pp_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
74 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
75 u32 rc6pp_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6pp
);
76 return snprintf(buf
, PAGE_SIZE
, "%u", rc6pp_residency
);
79 static DEVICE_ATTR(rc6_enable
, S_IRUGO
, show_rc6_mask
, NULL
);
80 static DEVICE_ATTR(rc6_residency_ms
, S_IRUGO
, show_rc6_ms
, NULL
);
81 static DEVICE_ATTR(rc6p_residency_ms
, S_IRUGO
, show_rc6p_ms
, NULL
);
82 static DEVICE_ATTR(rc6pp_residency_ms
, S_IRUGO
, show_rc6pp_ms
, NULL
);
84 static struct attribute
*rc6_attrs
[] = {
85 &dev_attr_rc6_enable
.attr
,
86 &dev_attr_rc6_residency_ms
.attr
,
87 &dev_attr_rc6p_residency_ms
.attr
,
88 &dev_attr_rc6pp_residency_ms
.attr
,
92 static struct attribute_group rc6_attr_group
= {
93 .name
= power_group_name
,
98 static int l3_access_valid(struct drm_device
*dev
, loff_t offset
)
100 if (!HAS_L3_GPU_CACHE(dev
))
106 if (offset
>= GEN7_L3LOG_SIZE
)
113 i915_l3_read(struct file
*filp
, struct kobject
*kobj
,
114 struct bin_attribute
*attr
, char *buf
,
115 loff_t offset
, size_t count
)
117 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
118 struct drm_minor
*dminor
= container_of(dev
, struct drm_minor
, kdev
);
119 struct drm_device
*drm_dev
= dminor
->dev
;
120 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
124 ret
= l3_access_valid(drm_dev
, offset
);
128 ret
= i915_mutex_lock_interruptible(drm_dev
);
132 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
133 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
135 for (i
= offset
; count
>= 4 && i
< GEN7_L3LOG_SIZE
; i
+= 4, count
-= 4)
136 *((uint32_t *)(&buf
[i
])) = I915_READ(GEN7_L3LOG_BASE
+ i
);
138 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
140 mutex_unlock(&drm_dev
->struct_mutex
);
146 i915_l3_write(struct file
*filp
, struct kobject
*kobj
,
147 struct bin_attribute
*attr
, char *buf
,
148 loff_t offset
, size_t count
)
150 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
151 struct drm_minor
*dminor
= container_of(dev
, struct drm_minor
, kdev
);
152 struct drm_device
*drm_dev
= dminor
->dev
;
153 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
154 u32
*temp
= NULL
; /* Just here to make handling failures easy */
157 ret
= l3_access_valid(drm_dev
, offset
);
161 ret
= i915_mutex_lock_interruptible(drm_dev
);
165 if (!dev_priv
->l3_parity
.remap_info
) {
166 temp
= kzalloc(GEN7_L3LOG_SIZE
, GFP_KERNEL
);
168 mutex_unlock(&drm_dev
->struct_mutex
);
173 ret
= i915_gpu_idle(drm_dev
);
176 mutex_unlock(&drm_dev
->struct_mutex
);
180 /* TODO: Ideally we really want a GPU reset here to make sure errors
181 * aren't propagated. Since I cannot find a stable way to reset the GPU
182 * at this point it is left as a TODO.
185 dev_priv
->l3_parity
.remap_info
= temp
;
187 memcpy(dev_priv
->l3_parity
.remap_info
+ (offset
/4),
191 i915_gem_l3_remap(drm_dev
);
193 mutex_unlock(&drm_dev
->struct_mutex
);
198 static struct bin_attribute dpf_attrs
= {
199 .attr
= {.name
= "l3_parity", .mode
= (S_IRUSR
| S_IWUSR
)},
200 .size
= GEN7_L3LOG_SIZE
,
201 .read
= i915_l3_read
,
202 .write
= i915_l3_write
,
206 static ssize_t
gt_cur_freq_mhz_show(struct device
*kdev
,
207 struct device_attribute
*attr
, char *buf
)
209 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
210 struct drm_device
*dev
= minor
->dev
;
211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
214 mutex_lock(&dev_priv
->rps
.hw_lock
);
215 ret
= dev_priv
->rps
.cur_delay
* GT_FREQUENCY_MULTIPLIER
;
216 mutex_unlock(&dev_priv
->rps
.hw_lock
);
218 return snprintf(buf
, PAGE_SIZE
, "%d", ret
);
221 static ssize_t
gt_max_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
223 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
224 struct drm_device
*dev
= minor
->dev
;
225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
228 mutex_lock(&dev_priv
->rps
.hw_lock
);
229 ret
= dev_priv
->rps
.max_delay
* GT_FREQUENCY_MULTIPLIER
;
230 mutex_unlock(&dev_priv
->rps
.hw_lock
);
232 return snprintf(buf
, PAGE_SIZE
, "%d", ret
);
235 static ssize_t
gt_max_freq_mhz_store(struct device
*kdev
,
236 struct device_attribute
*attr
,
237 const char *buf
, size_t count
)
239 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
240 struct drm_device
*dev
= minor
->dev
;
241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
242 u32 val
, rp_state_cap
, hw_max
, hw_min
;
245 ret
= kstrtou32(buf
, 0, &val
);
249 val
/= GT_FREQUENCY_MULTIPLIER
;
251 mutex_lock(&dev_priv
->rps
.hw_lock
);
253 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
254 hw_max
= (rp_state_cap
& 0xff);
255 hw_min
= ((rp_state_cap
& 0xff0000) >> 16);
257 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_delay
) {
258 mutex_unlock(&dev_priv
->rps
.hw_lock
);
262 if (dev_priv
->rps
.cur_delay
> val
)
263 gen6_set_rps(dev_priv
->dev
, val
);
265 dev_priv
->rps
.max_delay
= val
;
267 mutex_unlock(&dev_priv
->rps
.hw_lock
);
272 static ssize_t
gt_min_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
274 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
275 struct drm_device
*dev
= minor
->dev
;
276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
279 mutex_lock(&dev_priv
->rps
.hw_lock
);
280 ret
= dev_priv
->rps
.min_delay
* GT_FREQUENCY_MULTIPLIER
;
281 mutex_unlock(&dev_priv
->rps
.hw_lock
);
283 return snprintf(buf
, PAGE_SIZE
, "%d", ret
);
286 static ssize_t
gt_min_freq_mhz_store(struct device
*kdev
,
287 struct device_attribute
*attr
,
288 const char *buf
, size_t count
)
290 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
291 struct drm_device
*dev
= minor
->dev
;
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
293 u32 val
, rp_state_cap
, hw_max
, hw_min
;
296 ret
= kstrtou32(buf
, 0, &val
);
300 val
/= GT_FREQUENCY_MULTIPLIER
;
302 mutex_lock(&dev_priv
->rps
.hw_lock
);
304 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
305 hw_max
= (rp_state_cap
& 0xff);
306 hw_min
= ((rp_state_cap
& 0xff0000) >> 16);
308 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_delay
) {
309 mutex_unlock(&dev_priv
->rps
.hw_lock
);
313 if (dev_priv
->rps
.cur_delay
< val
)
314 gen6_set_rps(dev_priv
->dev
, val
);
316 dev_priv
->rps
.min_delay
= val
;
318 mutex_unlock(&dev_priv
->rps
.hw_lock
);
324 static DEVICE_ATTR(gt_cur_freq_mhz
, S_IRUGO
, gt_cur_freq_mhz_show
, NULL
);
325 static DEVICE_ATTR(gt_max_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_max_freq_mhz_show
, gt_max_freq_mhz_store
);
326 static DEVICE_ATTR(gt_min_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_min_freq_mhz_show
, gt_min_freq_mhz_store
);
329 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
);
330 static DEVICE_ATTR(gt_RP0_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
331 static DEVICE_ATTR(gt_RP1_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
332 static DEVICE_ATTR(gt_RPn_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
334 /* For now we have a static number of RP states */
335 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
337 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
338 struct drm_device
*dev
= minor
->dev
;
339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 u32 val
, rp_state_cap
;
343 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
346 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
347 mutex_unlock(&dev
->struct_mutex
);
349 if (attr
== &dev_attr_gt_RP0_freq_mhz
) {
350 val
= ((rp_state_cap
& 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER
;
351 } else if (attr
== &dev_attr_gt_RP1_freq_mhz
) {
352 val
= ((rp_state_cap
& 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER
;
353 } else if (attr
== &dev_attr_gt_RPn_freq_mhz
) {
354 val
= ((rp_state_cap
& 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER
;
358 return snprintf(buf
, PAGE_SIZE
, "%d", val
);
361 static const struct attribute
*gen6_attrs
[] = {
362 &dev_attr_gt_cur_freq_mhz
.attr
,
363 &dev_attr_gt_max_freq_mhz
.attr
,
364 &dev_attr_gt_min_freq_mhz
.attr
,
365 &dev_attr_gt_RP0_freq_mhz
.attr
,
366 &dev_attr_gt_RP1_freq_mhz
.attr
,
367 &dev_attr_gt_RPn_freq_mhz
.attr
,
371 void i915_setup_sysfs(struct drm_device
*dev
)
376 if (INTEL_INFO(dev
)->gen
>= 6) {
377 ret
= sysfs_merge_group(&dev
->primary
->kdev
.kobj
,
380 DRM_ERROR("RC6 residency sysfs setup failed\n");
383 if (HAS_L3_GPU_CACHE(dev
)) {
384 ret
= device_create_bin_file(&dev
->primary
->kdev
, &dpf_attrs
);
386 DRM_ERROR("l3 parity sysfs setup failed\n");
389 if (INTEL_INFO(dev
)->gen
>= 6) {
390 ret
= sysfs_create_files(&dev
->primary
->kdev
.kobj
, gen6_attrs
);
392 DRM_ERROR("gen6 sysfs setup failed\n");
396 void i915_teardown_sysfs(struct drm_device
*dev
)
398 sysfs_remove_files(&dev
->primary
->kdev
.kobj
, gen6_attrs
);
399 device_remove_bin_file(&dev
->primary
->kdev
, &dpf_attrs
);
401 sysfs_unmerge_group(&dev
->primary
->kdev
.kobj
, &rc6_attr_group
);