drivers/gpu/drm/i915/i915_sysfs.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *
  26  */
  27
  28 #include <linux/device.h>
  29 #include <linux/module.h>
  30 #include <linux/stat.h>
  31 #include <linux/sysfs.h>
  32 #include "intel_drv.h"
  33 #include "i915_drv.h"
  34
  35 #ifdef CONFIG_PM
  36 static u32 calc_residency(struct drm_device *dev, const u32 reg)
  37 {
  38         struct drm_i915_private *dev_priv = dev->dev_private;
  39         u64 raw_time; /* 32b value may overflow during fixed point math */
  40
  41         if (!intel_enable_rc6(dev))
  42                 return 0;
  43
  44         raw_time = I915_READ(reg) * 128ULL;
  45         return DIV_ROUND_UP_ULL(raw_time, 100000);
  46 }
  47
  48 static ssize_t
  49 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
  50 {
  51         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  52         return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
  53 }
  54
  55 static ssize_t
  56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  57 {
  58         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  59         u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
  60         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  61 }
  62
  63 static ssize_t
  64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  65 {
  66         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  67         u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
  68         return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
  69 }
  70
  71 static ssize_t
  72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  73 {
  74         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  75         u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
  76         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
  77 }
  78
  79 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
  80 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
  81 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
  82 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
  83
  84 static struct attribute *rc6_attrs[] = {
  85         &dev_attr_rc6_enable.attr,
  86         &dev_attr_rc6_residency_ms.attr,
  87         &dev_attr_rc6p_residency_ms.attr,
  88         &dev_attr_rc6pp_residency_ms.attr,
  89         NULL
  90 };
  91
  92 static struct attribute_group rc6_attr_group = {
  93         .name = power_group_name,
  94         .attrs =  rc6_attrs
  95 };
  96 #endif
  97
  98 static int l3_access_valid(struct drm_device *dev, loff_t offset)
  99 {
 100         if (!HAS_L3_GPU_CACHE(dev))
 101                 return -EPERM;
 102
 103         if (offset % 4 != 0)
 104                 return -EINVAL;
 105
 106         if (offset >= GEN7_L3LOG_SIZE)
 107                 return -ENXIO;
 108
 109         return 0;
 110 }
 111
 112 static ssize_t
 113 i915_l3_read(struct file *filp, struct kobject *kobj,
 114              struct bin_attribute *attr, char *buf,
 115              loff_t offset, size_t count)
 116 {
 117         struct device *dev = container_of(kobj, struct device, kobj);
 118         struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
 119         struct drm_device *drm_dev = dminor->dev;
 120         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 121         uint32_t misccpctl;
 122         int i, ret;
 123
 124         count = round_down(count, 4);
 125
 126         ret = l3_access_valid(drm_dev, offset);
 127         if (ret)
 128                 return ret;
 129
 130         count = min_t(int, GEN7_L3LOG_SIZE-offset, count);
 131
 132         ret = i915_mutex_lock_interruptible(drm_dev);
 133         if (ret)
 134                 return ret;
 135
 136         if (IS_HASWELL(drm_dev)) {
 137                 if (dev_priv->l3_parity.remap_info)
 138                         memcpy(buf,
 139                                dev_priv->l3_parity.remap_info + (offset/4),
 140                                count);
 141                 else
 142                         memset(buf, 0, count);
 143
 144                 goto out;
 145         }
 146
 147         misccpctl = I915_READ(GEN7_MISCCPCTL);
 148         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 149
 150         for (i = 0; i < count; i += 4)
 151                 *((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + offset + i);
 152
 153         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 154
 155 out:
 156         mutex_unlock(&drm_dev->struct_mutex);
 157
 158         return count;
 159 }
 160
 161 static ssize_t
 162 i915_l3_write(struct file *filp, struct kobject *kobj,
 163               struct bin_attribute *attr, char *buf,
 164               loff_t offset, size_t count)
 165 {
 166         struct device *dev = container_of(kobj, struct device, kobj);
 167         struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
 168         struct drm_device *drm_dev = dminor->dev;
 169         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 170         u32 *temp = NULL; /* Just here to make handling failures easy */
 171         int ret;
 172
 173         ret = l3_access_valid(drm_dev, offset);
 174         if (ret)
 175                 return ret;
 176
 177         ret = i915_mutex_lock_interruptible(drm_dev);
 178         if (ret)
 179                 return ret;
 180
 181         if (!dev_priv->l3_parity.remap_info) {
 182                 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
 183                 if (!temp) {
 184                         mutex_unlock(&drm_dev->struct_mutex);
 185                         return -ENOMEM;
 186                 }
 187         }
 188
 189         ret = i915_gpu_idle(drm_dev);
 190         if (ret) {
 191                 kfree(temp);
 192                 mutex_unlock(&drm_dev->struct_mutex);
 193                 return ret;
 194         }
 195
 196         /* TODO: Ideally we really want a GPU reset here to make sure errors
 197          * aren't propagated. Since I cannot find a stable way to reset the GPU
 198          * at this point it is left as a TODO.
 199         */
 200         if (temp)
 201                 dev_priv->l3_parity.remap_info = temp;
 202
 203         memcpy(dev_priv->l3_parity.remap_info + (offset/4), buf, count);
 204
 205         i915_gem_l3_remap(drm_dev);
 206
 207         mutex_unlock(&drm_dev->struct_mutex);
 208
 209         return count;
 210 }
 211
 212 static struct bin_attribute dpf_attrs = {
 213         .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
 214         .size = GEN7_L3LOG_SIZE,
 215         .read = i915_l3_read,
 216         .write = i915_l3_write,
 217         .mmap = NULL
 218 };
 219
 220 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 221                                     struct device_attribute *attr, char *buf)
 222 {
 223         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 224         struct drm_device *dev = minor->dev;
 225         struct drm_i915_private *dev_priv = dev->dev_private;
 226         int ret;
 227
 228         mutex_lock(&dev_priv->rps.hw_lock);
 229         if (IS_VALLEYVIEW(dev_priv->dev)) {
 230                 u32 freq;
 231                 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 232                 ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
 233         } else {
 234                 ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
 235         }
 236         mutex_unlock(&dev_priv->rps.hw_lock);
 237
 238         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 239 }
 240
 241 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 242                                      struct device_attribute *attr, char *buf)
 243 {
 244         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 245         struct drm_device *dev = minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247
 248         return snprintf(buf, PAGE_SIZE, "%d\n",
 249                         vlv_gpu_freq(dev_priv->mem_freq,
 250                                      dev_priv->rps.rpe_delay));
 251 }
 252
 253 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 254 {
 255         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 256         struct drm_device *dev = minor->dev;
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         int ret;
 259
 260         mutex_lock(&dev_priv->rps.hw_lock);
 261         if (IS_VALLEYVIEW(dev_priv->dev))
 262                 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
 263         else
 264                 ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
 265         mutex_unlock(&dev_priv->rps.hw_lock);
 266
 267         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 268 }
 269
 270 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 271                                      struct device_attribute *attr,
 272                                      const char *buf, size_t count)
 273 {
 274         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 275         struct drm_device *dev = minor->dev;
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
 278         ssize_t ret;
 279
 280         ret = kstrtou32(buf, 0, &val);
 281         if (ret)
 282                 return ret;
 283
 284         mutex_lock(&dev_priv->rps.hw_lock);
 285
 286         if (IS_VALLEYVIEW(dev_priv->dev)) {
 287                 val = vlv_freq_opcode(dev_priv->mem_freq, val);
 288
 289                 hw_max = valleyview_rps_max_freq(dev_priv);
 290                 hw_min = valleyview_rps_min_freq(dev_priv);
 291                 non_oc_max = hw_max;
 292         } else {
 293                 val /= GT_FREQUENCY_MULTIPLIER;
 294
 295                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 296                 hw_max = dev_priv->rps.hw_max;
 297                 non_oc_max = (rp_state_cap & 0xff);
 298                 hw_min = ((rp_state_cap & 0xff0000) >> 16);
 299         }
 300
 301         if (val < hw_min || val > hw_max ||
 302             val < dev_priv->rps.min_delay) {
 303                 mutex_unlock(&dev_priv->rps.hw_lock);
 304                 return -EINVAL;
 305         }
 306
 307         if (val > non_oc_max)
 308                 DRM_DEBUG("User requested overclocking to %d\n",
 309                           val * GT_FREQUENCY_MULTIPLIER);
 310
 311         if (dev_priv->rps.cur_delay > val) {
 312                 if (IS_VALLEYVIEW(dev_priv->dev))
 313                         valleyview_set_rps(dev_priv->dev, val);
 314                 else
 315                         gen6_set_rps(dev_priv->dev, val);
 316         }
 317
 318         dev_priv->rps.max_delay = val;
 319
 320         mutex_unlock(&dev_priv->rps.hw_lock);
 321
 322         return count;
 323 }
 324
 325 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 326 {
 327         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 328         struct drm_device *dev = minor->dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         int ret;
 331
 332         mutex_lock(&dev_priv->rps.hw_lock);
 333         if (IS_VALLEYVIEW(dev_priv->dev))
 334                 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
 335         else
 336                 ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
 337         mutex_unlock(&dev_priv->rps.hw_lock);
 338
 339         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 340 }
 341
 342 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 343                                      struct device_attribute *attr,
 344                                      const char *buf, size_t count)
 345 {
 346         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 347         struct drm_device *dev = minor->dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         u32 val, rp_state_cap, hw_max, hw_min;
 350         ssize_t ret;
 351
 352         ret = kstrtou32(buf, 0, &val);
 353         if (ret)
 354                 return ret;
 355
 356         mutex_lock(&dev_priv->rps.hw_lock);
 357
 358         if (IS_VALLEYVIEW(dev)) {
 359                 val = vlv_freq_opcode(dev_priv->mem_freq, val);
 360
 361                 hw_max = valleyview_rps_max_freq(dev_priv);
 362                 hw_min = valleyview_rps_min_freq(dev_priv);
 363         } else {
 364                 val /= GT_FREQUENCY_MULTIPLIER;
 365
 366                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 367                 hw_max = dev_priv->rps.hw_max;
 368                 hw_min = ((rp_state_cap & 0xff0000) >> 16);
 369         }
 370
 371         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
 372                 mutex_unlock(&dev_priv->rps.hw_lock);
 373                 return -EINVAL;
 374         }
 375
 376         if (dev_priv->rps.cur_delay < val) {
 377                 if (IS_VALLEYVIEW(dev))
 378                         valleyview_set_rps(dev, val);
 379                 else
 380                         gen6_set_rps(dev_priv->dev, val);
 381         }
 382
 383         dev_priv->rps.min_delay = val;
 384
 385         mutex_unlock(&dev_priv->rps.hw_lock);
 386
 387         return count;
 388
 389 }
 390
 391 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
 392 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 393 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
 394
 395 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
 396
 397 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
 398 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 399 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 400 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 401
 402 /* For now we have a static number of RP states */
 403 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 404 {
 405         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 406         struct drm_device *dev = minor->dev;
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408         u32 val, rp_state_cap;
 409         ssize_t ret;
 410
 411         ret = mutex_lock_interruptible(&dev->struct_mutex);
 412         if (ret)
 413                 return ret;
 414         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 415         mutex_unlock(&dev->struct_mutex);
 416
 417         if (attr == &dev_attr_gt_RP0_freq_mhz) {
 418                 val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
 419         } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
 420                 val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
 421         } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
 422                 val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
 423         } else {
 424                 BUG();
 425         }
 426         return snprintf(buf, PAGE_SIZE, "%d\n", val);
 427 }
 428
 429 static const struct attribute *gen6_attrs[] = {
 430         &dev_attr_gt_cur_freq_mhz.attr,
 431         &dev_attr_gt_max_freq_mhz.attr,
 432         &dev_attr_gt_min_freq_mhz.attr,
 433         &dev_attr_gt_RP0_freq_mhz.attr,
 434         &dev_attr_gt_RP1_freq_mhz.attr,
 435         &dev_attr_gt_RPn_freq_mhz.attr,
 436         NULL,
 437 };
 438
 439 static const struct attribute *vlv_attrs[] = {
 440         &dev_attr_gt_cur_freq_mhz.attr,
 441         &dev_attr_gt_max_freq_mhz.attr,
 442         &dev_attr_gt_min_freq_mhz.attr,
 443         &dev_attr_vlv_rpe_freq_mhz.attr,
 444         NULL,
 445 };
 446
 447 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 448                                 struct bin_attribute *attr, char *buf,
 449                                 loff_t off, size_t count)
 450 {
 451
 452         struct device *kdev = container_of(kobj, struct device, kobj);
 453         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 454         struct drm_device *dev = minor->dev;
 455         struct i915_error_state_file_priv error_priv;
 456         struct drm_i915_error_state_buf error_str;
 457         ssize_t ret_count = 0;
 458         int ret;
 459
 460         memset(&error_priv, 0, sizeof(error_priv));
 461
 462         ret = i915_error_state_buf_init(&error_str, count, off);
 463         if (ret)
 464                 return ret;
 465
 466         error_priv.dev = dev;
 467         i915_error_state_get(dev, &error_priv);
 468
 469         ret = i915_error_state_to_str(&error_str, &error_priv);
 470         if (ret)
 471                 goto out;
 472
 473         ret_count = count < error_str.bytes ? count : error_str.bytes;
 474
 475         memcpy(buf, error_str.buf, ret_count);
 476 out:
 477         i915_error_state_put(&error_priv);
 478         i915_error_state_buf_release(&error_str);
 479
 480         return ret ?: ret_count;
 481 }
 482
 483 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
 484                                  struct bin_attribute *attr, char *buf,
 485                                  loff_t off, size_t count)
 486 {
 487         struct device *kdev = container_of(kobj, struct device, kobj);
 488         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 489         struct drm_device *dev = minor->dev;
 490         int ret;
 491
 492         DRM_DEBUG_DRIVER("Resetting error state\n");
 493
 494         ret = mutex_lock_interruptible(&dev->struct_mutex);
 495         if (ret)
 496                 return ret;
 497
 498         i915_destroy_error_state(dev);
 499         mutex_unlock(&dev->struct_mutex);
 500
 501         return count;
 502 }
 503
 504 static struct bin_attribute error_state_attr = {
 505         .attr.name = "error",
 506         .attr.mode = S_IRUSR | S_IWUSR,
 507         .size = 0,
 508         .read = error_state_read,
 509         .write = error_state_write,
 510 };
 511
 512 void i915_setup_sysfs(struct drm_device *dev)
 513 {
 514         int ret;
 515
 516 #ifdef CONFIG_PM
 517         if (INTEL_INFO(dev)->gen >= 6) {
 518                 ret = sysfs_merge_group(&dev->primary->kdev.kobj,
 519                                         &rc6_attr_group);
 520                 if (ret)
 521                         DRM_ERROR("RC6 residency sysfs setup failed\n");
 522         }
 523 #endif
 524         if (HAS_L3_GPU_CACHE(dev)) {
 525                 ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
 526                 if (ret)
 527                         DRM_ERROR("l3 parity sysfs setup failed\n");
 528         }
 529
 530         ret = 0;
 531         if (IS_VALLEYVIEW(dev))
 532                 ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
 533         else if (INTEL_INFO(dev)->gen >= 6)
 534                 ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
 535         if (ret)
 536                 DRM_ERROR("RPS sysfs setup failed\n");
 537
 538         ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
 539                                     &error_state_attr);
 540         if (ret)
 541                 DRM_ERROR("error_state sysfs setup failed\n");
 542 }
 543
 544 void i915_teardown_sysfs(struct drm_device *dev)
 545 {
 546         sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
 547         if (IS_VALLEYVIEW(dev))
 548                 sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
 549         else
 550                 sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
 551         device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
 552 #ifdef CONFIG_PM
 553         sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
 554 #endif
 555 }