2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
36 static u32
calc_residency(struct drm_device
*dev
, const u32 reg
)
38 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
39 u64 raw_time
; /* 32b value may overflow during fixed point math */
41 if (!intel_enable_rc6(dev
))
44 raw_time
= I915_READ(reg
) * 128ULL;
45 return DIV_ROUND_UP_ULL(raw_time
, 100000);
49 show_rc6_mask(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
51 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
52 return snprintf(buf
, PAGE_SIZE
, "%x\n", intel_enable_rc6(dminor
->dev
));
56 show_rc6_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
58 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
59 u32 rc6_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6
);
60 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6_residency
);
64 show_rc6p_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
66 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
67 u32 rc6p_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6p
);
68 if (IS_VALLEYVIEW(dminor
->dev
))
70 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6p_residency
);
74 show_rc6pp_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
76 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
77 u32 rc6pp_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6pp
);
78 if (IS_VALLEYVIEW(dminor
->dev
))
80 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6pp_residency
);
83 static DEVICE_ATTR(rc6_enable
, S_IRUGO
, show_rc6_mask
, NULL
);
84 static DEVICE_ATTR(rc6_residency_ms
, S_IRUGO
, show_rc6_ms
, NULL
);
85 static DEVICE_ATTR(rc6p_residency_ms
, S_IRUGO
, show_rc6p_ms
, NULL
);
86 static DEVICE_ATTR(rc6pp_residency_ms
, S_IRUGO
, show_rc6pp_ms
, NULL
);
88 static struct attribute
*rc6_attrs
[] = {
89 &dev_attr_rc6_enable
.attr
,
90 &dev_attr_rc6_residency_ms
.attr
,
91 &dev_attr_rc6p_residency_ms
.attr
,
92 &dev_attr_rc6pp_residency_ms
.attr
,
96 static struct attribute_group rc6_attr_group
= {
97 .name
= power_group_name
,
102 static int l3_access_valid(struct drm_device
*dev
, loff_t offset
)
104 if (!HAS_L3_DPF(dev
))
110 if (offset
>= GEN7_L3LOG_SIZE
)
117 i915_l3_read(struct file
*filp
, struct kobject
*kobj
,
118 struct bin_attribute
*attr
, char *buf
,
119 loff_t offset
, size_t count
)
121 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
122 struct drm_minor
*dminor
= container_of(dev
, struct drm_minor
, kdev
);
123 struct drm_device
*drm_dev
= dminor
->dev
;
124 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
125 int slice
= (int)(uintptr_t)attr
->private;
128 count
= round_down(count
, 4);
130 ret
= l3_access_valid(drm_dev
, offset
);
134 count
= min_t(size_t, GEN7_L3LOG_SIZE
- offset
, count
);
136 ret
= i915_mutex_lock_interruptible(drm_dev
);
140 if (dev_priv
->l3_parity
.remap_info
[slice
])
142 dev_priv
->l3_parity
.remap_info
[slice
] + (offset
/4),
145 memset(buf
, 0, count
);
147 mutex_unlock(&drm_dev
->struct_mutex
);
153 i915_l3_write(struct file
*filp
, struct kobject
*kobj
,
154 struct bin_attribute
*attr
, char *buf
,
155 loff_t offset
, size_t count
)
157 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
158 struct drm_minor
*dminor
= container_of(dev
, struct drm_minor
, kdev
);
159 struct drm_device
*drm_dev
= dminor
->dev
;
160 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
161 struct i915_hw_context
*ctx
;
162 u32
*temp
= NULL
; /* Just here to make handling failures easy */
163 int slice
= (int)(uintptr_t)attr
->private;
166 ret
= l3_access_valid(drm_dev
, offset
);
170 if (dev_priv
->hw_contexts_disabled
)
173 ret
= i915_mutex_lock_interruptible(drm_dev
);
177 if (!dev_priv
->l3_parity
.remap_info
[slice
]) {
178 temp
= kzalloc(GEN7_L3LOG_SIZE
, GFP_KERNEL
);
180 mutex_unlock(&drm_dev
->struct_mutex
);
185 ret
= i915_gpu_idle(drm_dev
);
188 mutex_unlock(&drm_dev
->struct_mutex
);
192 /* TODO: Ideally we really want a GPU reset here to make sure errors
193 * aren't propagated. Since I cannot find a stable way to reset the GPU
194 * at this point it is left as a TODO.
197 dev_priv
->l3_parity
.remap_info
[slice
] = temp
;
199 memcpy(dev_priv
->l3_parity
.remap_info
[slice
] + (offset
/4), buf
, count
);
201 /* NB: We defer the remapping until we switch to the context */
202 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
203 ctx
->remap_slice
|= (1<<slice
);
205 mutex_unlock(&drm_dev
->struct_mutex
);
210 static struct bin_attribute dpf_attrs
= {
211 .attr
= {.name
= "l3_parity", .mode
= (S_IRUSR
| S_IWUSR
)},
212 .size
= GEN7_L3LOG_SIZE
,
213 .read
= i915_l3_read
,
214 .write
= i915_l3_write
,
219 static struct bin_attribute dpf_attrs_1
= {
220 .attr
= {.name
= "l3_parity_slice_1", .mode
= (S_IRUSR
| S_IWUSR
)},
221 .size
= GEN7_L3LOG_SIZE
,
222 .read
= i915_l3_read
,
223 .write
= i915_l3_write
,
228 static ssize_t
gt_cur_freq_mhz_show(struct device
*kdev
,
229 struct device_attribute
*attr
, char *buf
)
231 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
232 struct drm_device
*dev
= minor
->dev
;
233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
236 mutex_lock(&dev_priv
->rps
.hw_lock
);
237 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
239 freq
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
240 ret
= vlv_gpu_freq(dev_priv
->mem_freq
, (freq
>> 8) & 0xff);
242 ret
= dev_priv
->rps
.cur_delay
* GT_FREQUENCY_MULTIPLIER
;
244 mutex_unlock(&dev_priv
->rps
.hw_lock
);
246 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
249 static ssize_t
vlv_rpe_freq_mhz_show(struct device
*kdev
,
250 struct device_attribute
*attr
, char *buf
)
252 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
253 struct drm_device
*dev
= minor
->dev
;
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
256 return snprintf(buf
, PAGE_SIZE
, "%d\n",
257 vlv_gpu_freq(dev_priv
->mem_freq
,
258 dev_priv
->rps
.rpe_delay
));
261 static ssize_t
gt_max_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
263 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
264 struct drm_device
*dev
= minor
->dev
;
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 mutex_lock(&dev_priv
->rps
.hw_lock
);
269 if (IS_VALLEYVIEW(dev_priv
->dev
))
270 ret
= vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.max_delay
);
272 ret
= dev_priv
->rps
.max_delay
* GT_FREQUENCY_MULTIPLIER
;
273 mutex_unlock(&dev_priv
->rps
.hw_lock
);
275 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
278 static ssize_t
gt_max_freq_mhz_store(struct device
*kdev
,
279 struct device_attribute
*attr
,
280 const char *buf
, size_t count
)
282 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
283 struct drm_device
*dev
= minor
->dev
;
284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
285 u32 val
, rp_state_cap
, hw_max
, hw_min
, non_oc_max
;
288 ret
= kstrtou32(buf
, 0, &val
);
292 mutex_lock(&dev_priv
->rps
.hw_lock
);
294 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
295 val
= vlv_freq_opcode(dev_priv
->mem_freq
, val
);
297 hw_max
= valleyview_rps_max_freq(dev_priv
);
298 hw_min
= valleyview_rps_min_freq(dev_priv
);
301 val
/= GT_FREQUENCY_MULTIPLIER
;
303 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
304 hw_max
= dev_priv
->rps
.hw_max
;
305 non_oc_max
= (rp_state_cap
& 0xff);
306 hw_min
= ((rp_state_cap
& 0xff0000) >> 16);
309 if (val
< hw_min
|| val
> hw_max
||
310 val
< dev_priv
->rps
.min_delay
) {
311 mutex_unlock(&dev_priv
->rps
.hw_lock
);
315 if (val
> non_oc_max
)
316 DRM_DEBUG("User requested overclocking to %d\n",
317 val
* GT_FREQUENCY_MULTIPLIER
);
319 if (dev_priv
->rps
.cur_delay
> val
) {
320 if (IS_VALLEYVIEW(dev_priv
->dev
))
321 valleyview_set_rps(dev_priv
->dev
, val
);
323 gen6_set_rps(dev_priv
->dev
, val
);
326 dev_priv
->rps
.max_delay
= val
;
328 mutex_unlock(&dev_priv
->rps
.hw_lock
);
333 static ssize_t
gt_min_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
335 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
336 struct drm_device
*dev
= minor
->dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 mutex_lock(&dev_priv
->rps
.hw_lock
);
341 if (IS_VALLEYVIEW(dev_priv
->dev
))
342 ret
= vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.min_delay
);
344 ret
= dev_priv
->rps
.min_delay
* GT_FREQUENCY_MULTIPLIER
;
345 mutex_unlock(&dev_priv
->rps
.hw_lock
);
347 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
350 static ssize_t
gt_min_freq_mhz_store(struct device
*kdev
,
351 struct device_attribute
*attr
,
352 const char *buf
, size_t count
)
354 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
355 struct drm_device
*dev
= minor
->dev
;
356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
357 u32 val
, rp_state_cap
, hw_max
, hw_min
;
360 ret
= kstrtou32(buf
, 0, &val
);
364 mutex_lock(&dev_priv
->rps
.hw_lock
);
366 if (IS_VALLEYVIEW(dev
)) {
367 val
= vlv_freq_opcode(dev_priv
->mem_freq
, val
);
369 hw_max
= valleyview_rps_max_freq(dev_priv
);
370 hw_min
= valleyview_rps_min_freq(dev_priv
);
372 val
/= GT_FREQUENCY_MULTIPLIER
;
374 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
375 hw_max
= dev_priv
->rps
.hw_max
;
376 hw_min
= ((rp_state_cap
& 0xff0000) >> 16);
379 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_delay
) {
380 mutex_unlock(&dev_priv
->rps
.hw_lock
);
384 if (dev_priv
->rps
.cur_delay
< val
) {
385 if (IS_VALLEYVIEW(dev
))
386 valleyview_set_rps(dev
, val
);
388 gen6_set_rps(dev_priv
->dev
, val
);
391 dev_priv
->rps
.min_delay
= val
;
393 mutex_unlock(&dev_priv
->rps
.hw_lock
);
399 static DEVICE_ATTR(gt_cur_freq_mhz
, S_IRUGO
, gt_cur_freq_mhz_show
, NULL
);
400 static DEVICE_ATTR(gt_max_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_max_freq_mhz_show
, gt_max_freq_mhz_store
);
401 static DEVICE_ATTR(gt_min_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_min_freq_mhz_show
, gt_min_freq_mhz_store
);
403 static DEVICE_ATTR(vlv_rpe_freq_mhz
, S_IRUGO
, vlv_rpe_freq_mhz_show
, NULL
);
405 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
);
406 static DEVICE_ATTR(gt_RP0_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
407 static DEVICE_ATTR(gt_RP1_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
408 static DEVICE_ATTR(gt_RPn_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
410 /* For now we have a static number of RP states */
411 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
413 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
414 struct drm_device
*dev
= minor
->dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 u32 val
, rp_state_cap
;
419 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
422 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
423 mutex_unlock(&dev
->struct_mutex
);
425 if (attr
== &dev_attr_gt_RP0_freq_mhz
) {
426 val
= ((rp_state_cap
& 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER
;
427 } else if (attr
== &dev_attr_gt_RP1_freq_mhz
) {
428 val
= ((rp_state_cap
& 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER
;
429 } else if (attr
== &dev_attr_gt_RPn_freq_mhz
) {
430 val
= ((rp_state_cap
& 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER
;
434 return snprintf(buf
, PAGE_SIZE
, "%d\n", val
);
437 static const struct attribute
*gen6_attrs
[] = {
438 &dev_attr_gt_cur_freq_mhz
.attr
,
439 &dev_attr_gt_max_freq_mhz
.attr
,
440 &dev_attr_gt_min_freq_mhz
.attr
,
441 &dev_attr_gt_RP0_freq_mhz
.attr
,
442 &dev_attr_gt_RP1_freq_mhz
.attr
,
443 &dev_attr_gt_RPn_freq_mhz
.attr
,
447 static const struct attribute
*vlv_attrs
[] = {
448 &dev_attr_gt_cur_freq_mhz
.attr
,
449 &dev_attr_gt_max_freq_mhz
.attr
,
450 &dev_attr_gt_min_freq_mhz
.attr
,
451 &dev_attr_vlv_rpe_freq_mhz
.attr
,
455 static ssize_t
error_state_read(struct file
*filp
, struct kobject
*kobj
,
456 struct bin_attribute
*attr
, char *buf
,
457 loff_t off
, size_t count
)
460 struct device
*kdev
= container_of(kobj
, struct device
, kobj
);
461 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
462 struct drm_device
*dev
= minor
->dev
;
463 struct i915_error_state_file_priv error_priv
;
464 struct drm_i915_error_state_buf error_str
;
465 ssize_t ret_count
= 0;
468 memset(&error_priv
, 0, sizeof(error_priv
));
470 ret
= i915_error_state_buf_init(&error_str
, count
, off
);
474 error_priv
.dev
= dev
;
475 i915_error_state_get(dev
, &error_priv
);
477 ret
= i915_error_state_to_str(&error_str
, &error_priv
);
481 ret_count
= count
< error_str
.bytes
? count
: error_str
.bytes
;
483 memcpy(buf
, error_str
.buf
, ret_count
);
485 i915_error_state_put(&error_priv
);
486 i915_error_state_buf_release(&error_str
);
488 return ret
?: ret_count
;
491 static ssize_t
error_state_write(struct file
*file
, struct kobject
*kobj
,
492 struct bin_attribute
*attr
, char *buf
,
493 loff_t off
, size_t count
)
495 struct device
*kdev
= container_of(kobj
, struct device
, kobj
);
496 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
497 struct drm_device
*dev
= minor
->dev
;
500 DRM_DEBUG_DRIVER("Resetting error state\n");
502 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
506 i915_destroy_error_state(dev
);
507 mutex_unlock(&dev
->struct_mutex
);
512 static struct bin_attribute error_state_attr
= {
513 .attr
.name
= "error",
514 .attr
.mode
= S_IRUSR
| S_IWUSR
,
516 .read
= error_state_read
,
517 .write
= error_state_write
,
520 void i915_setup_sysfs(struct drm_device
*dev
)
525 if (INTEL_INFO(dev
)->gen
>= 6) {
526 ret
= sysfs_merge_group(&dev
->primary
->kdev
.kobj
,
529 DRM_ERROR("RC6 residency sysfs setup failed\n");
532 if (HAS_L3_DPF(dev
)) {
533 ret
= device_create_bin_file(&dev
->primary
->kdev
, &dpf_attrs
);
535 DRM_ERROR("l3 parity sysfs setup failed\n");
537 if (NUM_L3_SLICES(dev
) > 1) {
538 ret
= device_create_bin_file(&dev
->primary
->kdev
,
541 DRM_ERROR("l3 parity slice 1 setup failed\n");
546 if (IS_VALLEYVIEW(dev
))
547 ret
= sysfs_create_files(&dev
->primary
->kdev
.kobj
, vlv_attrs
);
548 else if (INTEL_INFO(dev
)->gen
>= 6)
549 ret
= sysfs_create_files(&dev
->primary
->kdev
.kobj
, gen6_attrs
);
551 DRM_ERROR("RPS sysfs setup failed\n");
553 ret
= sysfs_create_bin_file(&dev
->primary
->kdev
.kobj
,
556 DRM_ERROR("error_state sysfs setup failed\n");
559 void i915_teardown_sysfs(struct drm_device
*dev
)
561 sysfs_remove_bin_file(&dev
->primary
->kdev
.kobj
, &error_state_attr
);
562 if (IS_VALLEYVIEW(dev
))
563 sysfs_remove_files(&dev
->primary
->kdev
.kobj
, vlv_attrs
);
565 sysfs_remove_files(&dev
->primary
->kdev
.kobj
, gen6_attrs
);
566 device_remove_bin_file(&dev
->primary
->kdev
, &dpf_attrs_1
);
567 device_remove_bin_file(&dev
->primary
->kdev
, &dpf_attrs
);
569 sysfs_unmerge_group(&dev
->primary
->kdev
.kobj
, &rc6_attr_group
);