2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
36 static u32
calc_residency(struct drm_device
*dev
, const u32 reg
)
38 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
39 u64 raw_time
; /* 32b value may overflow during fixed point math */
41 if (!intel_enable_rc6(dev
))
44 raw_time
= I915_READ(reg
) * 128ULL;
45 return DIV_ROUND_UP_ULL(raw_time
, 100000);
49 show_rc6_mask(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
51 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
52 return snprintf(buf
, PAGE_SIZE
, "%x\n", intel_enable_rc6(dminor
->dev
));
56 show_rc6_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
58 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
59 u32 rc6_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6
);
60 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6_residency
);
64 show_rc6p_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
66 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
67 u32 rc6p_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6p
);
68 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6p_residency
);
72 show_rc6pp_ms(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
74 struct drm_minor
*dminor
= container_of(kdev
, struct drm_minor
, kdev
);
75 u32 rc6pp_residency
= calc_residency(dminor
->dev
, GEN6_GT_GFX_RC6pp
);
76 return snprintf(buf
, PAGE_SIZE
, "%u\n", rc6pp_residency
);
79 static DEVICE_ATTR(rc6_enable
, S_IRUGO
, show_rc6_mask
, NULL
);
80 static DEVICE_ATTR(rc6_residency_ms
, S_IRUGO
, show_rc6_ms
, NULL
);
81 static DEVICE_ATTR(rc6p_residency_ms
, S_IRUGO
, show_rc6p_ms
, NULL
);
82 static DEVICE_ATTR(rc6pp_residency_ms
, S_IRUGO
, show_rc6pp_ms
, NULL
);
84 static struct attribute
*rc6_attrs
[] = {
85 &dev_attr_rc6_enable
.attr
,
86 &dev_attr_rc6_residency_ms
.attr
,
87 &dev_attr_rc6p_residency_ms
.attr
,
88 &dev_attr_rc6pp_residency_ms
.attr
,
92 static struct attribute_group rc6_attr_group
= {
93 .name
= power_group_name
,
98 static int l3_access_valid(struct drm_device
*dev
, loff_t offset
)
100 if (!HAS_L3_GPU_CACHE(dev
))
106 if (offset
>= GEN7_L3LOG_SIZE
)
113 i915_l3_read(struct file
*filp
, struct kobject
*kobj
,
114 struct bin_attribute
*attr
, char *buf
,
115 loff_t offset
, size_t count
)
117 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
118 struct drm_minor
*dminor
= container_of(dev
, struct drm_minor
, kdev
);
119 struct drm_device
*drm_dev
= dminor
->dev
;
120 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
124 ret
= l3_access_valid(drm_dev
, offset
);
128 ret
= i915_mutex_lock_interruptible(drm_dev
);
132 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
133 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
135 for (i
= offset
; count
>= 4 && i
< GEN7_L3LOG_SIZE
; i
+= 4, count
-= 4)
136 *((uint32_t *)(&buf
[i
])) = I915_READ(GEN7_L3LOG_BASE
+ i
);
138 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
140 mutex_unlock(&drm_dev
->struct_mutex
);
146 i915_l3_write(struct file
*filp
, struct kobject
*kobj
,
147 struct bin_attribute
*attr
, char *buf
,
148 loff_t offset
, size_t count
)
150 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
151 struct drm_minor
*dminor
= container_of(dev
, struct drm_minor
, kdev
);
152 struct drm_device
*drm_dev
= dminor
->dev
;
153 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
154 u32
*temp
= NULL
; /* Just here to make handling failures easy */
157 ret
= l3_access_valid(drm_dev
, offset
);
161 ret
= i915_mutex_lock_interruptible(drm_dev
);
165 if (!dev_priv
->l3_parity
.remap_info
) {
166 temp
= kzalloc(GEN7_L3LOG_SIZE
, GFP_KERNEL
);
168 mutex_unlock(&drm_dev
->struct_mutex
);
173 ret
= i915_gpu_idle(drm_dev
);
176 mutex_unlock(&drm_dev
->struct_mutex
);
180 /* TODO: Ideally we really want a GPU reset here to make sure errors
181 * aren't propagated. Since I cannot find a stable way to reset the GPU
182 * at this point it is left as a TODO.
185 dev_priv
->l3_parity
.remap_info
= temp
;
187 memcpy(dev_priv
->l3_parity
.remap_info
+ (offset
/4),
191 i915_gem_l3_remap(drm_dev
);
193 mutex_unlock(&drm_dev
->struct_mutex
);
198 static struct bin_attribute dpf_attrs
= {
199 .attr
= {.name
= "l3_parity", .mode
= (S_IRUSR
| S_IWUSR
)},
200 .size
= GEN7_L3LOG_SIZE
,
201 .read
= i915_l3_read
,
202 .write
= i915_l3_write
,
206 static ssize_t
gt_cur_freq_mhz_show(struct device
*kdev
,
207 struct device_attribute
*attr
, char *buf
)
209 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
210 struct drm_device
*dev
= minor
->dev
;
211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
214 mutex_lock(&dev_priv
->rps
.hw_lock
);
215 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
217 freq
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
218 ret
= vlv_gpu_freq(dev_priv
->mem_freq
, (freq
>> 8) & 0xff);
220 ret
= dev_priv
->rps
.cur_delay
* GT_FREQUENCY_MULTIPLIER
;
222 mutex_unlock(&dev_priv
->rps
.hw_lock
);
224 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
227 static ssize_t
gt_max_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
229 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
230 struct drm_device
*dev
= minor
->dev
;
231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
234 mutex_lock(&dev_priv
->rps
.hw_lock
);
235 if (IS_VALLEYVIEW(dev_priv
->dev
))
236 ret
= vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.max_delay
);
238 ret
= dev_priv
->rps
.max_delay
* GT_FREQUENCY_MULTIPLIER
;
239 mutex_unlock(&dev_priv
->rps
.hw_lock
);
241 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
244 static ssize_t
gt_max_freq_mhz_store(struct device
*kdev
,
245 struct device_attribute
*attr
,
246 const char *buf
, size_t count
)
248 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
249 struct drm_device
*dev
= minor
->dev
;
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
251 u32 val
, rp_state_cap
, hw_max
, hw_min
, non_oc_max
;
254 ret
= kstrtou32(buf
, 0, &val
);
258 mutex_lock(&dev_priv
->rps
.hw_lock
);
260 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
261 val
= vlv_freq_opcode(dev_priv
->mem_freq
, val
);
263 hw_max
= valleyview_rps_max_freq(dev_priv
);
264 hw_min
= valleyview_rps_min_freq(dev_priv
);
267 val
/= GT_FREQUENCY_MULTIPLIER
;
269 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
270 hw_max
= dev_priv
->rps
.hw_max
;
271 non_oc_max
= (rp_state_cap
& 0xff);
272 hw_min
= ((rp_state_cap
& 0xff0000) >> 16);
275 if (val
< hw_min
|| val
> hw_max
||
276 val
< dev_priv
->rps
.min_delay
) {
277 mutex_unlock(&dev_priv
->rps
.hw_lock
);
281 if (val
> non_oc_max
)
282 DRM_DEBUG("User requested overclocking to %d\n",
283 val
* GT_FREQUENCY_MULTIPLIER
);
285 if (dev_priv
->rps
.cur_delay
> val
) {
286 if (IS_VALLEYVIEW(dev_priv
->dev
))
287 valleyview_set_rps(dev_priv
->dev
, val
);
289 gen6_set_rps(dev_priv
->dev
, val
);
292 dev_priv
->rps
.max_delay
= val
;
294 mutex_unlock(&dev_priv
->rps
.hw_lock
);
299 static ssize_t
gt_min_freq_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
301 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
302 struct drm_device
*dev
= minor
->dev
;
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 mutex_lock(&dev_priv
->rps
.hw_lock
);
307 if (IS_VALLEYVIEW(dev_priv
->dev
))
308 ret
= vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.min_delay
);
310 ret
= dev_priv
->rps
.min_delay
* GT_FREQUENCY_MULTIPLIER
;
311 mutex_unlock(&dev_priv
->rps
.hw_lock
);
313 return snprintf(buf
, PAGE_SIZE
, "%d\n", ret
);
316 static ssize_t
gt_min_freq_mhz_store(struct device
*kdev
,
317 struct device_attribute
*attr
,
318 const char *buf
, size_t count
)
320 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
321 struct drm_device
*dev
= minor
->dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
323 u32 val
, rp_state_cap
, hw_max
, hw_min
;
326 ret
= kstrtou32(buf
, 0, &val
);
330 mutex_lock(&dev_priv
->rps
.hw_lock
);
332 if (IS_VALLEYVIEW(dev
)) {
333 val
= vlv_freq_opcode(dev_priv
->mem_freq
, val
);
335 hw_max
= valleyview_rps_max_freq(dev_priv
);
336 hw_min
= valleyview_rps_min_freq(dev_priv
);
338 val
/= GT_FREQUENCY_MULTIPLIER
;
340 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
341 hw_max
= dev_priv
->rps
.hw_max
;
342 hw_min
= ((rp_state_cap
& 0xff0000) >> 16);
345 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_delay
) {
346 mutex_unlock(&dev_priv
->rps
.hw_lock
);
350 if (dev_priv
->rps
.cur_delay
< val
) {
351 if (IS_VALLEYVIEW(dev
))
352 valleyview_set_rps(dev
, val
);
354 gen6_set_rps(dev_priv
->dev
, val
);
357 dev_priv
->rps
.min_delay
= val
;
359 mutex_unlock(&dev_priv
->rps
.hw_lock
);
365 static DEVICE_ATTR(gt_cur_freq_mhz
, S_IRUGO
, gt_cur_freq_mhz_show
, NULL
);
366 static DEVICE_ATTR(gt_max_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_max_freq_mhz_show
, gt_max_freq_mhz_store
);
367 static DEVICE_ATTR(gt_min_freq_mhz
, S_IRUGO
| S_IWUSR
, gt_min_freq_mhz_show
, gt_min_freq_mhz_store
);
370 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
);
371 static DEVICE_ATTR(gt_RP0_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
372 static DEVICE_ATTR(gt_RP1_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
373 static DEVICE_ATTR(gt_RPn_freq_mhz
, S_IRUGO
, gt_rp_mhz_show
, NULL
);
375 /* For now we have a static number of RP states */
376 static ssize_t
gt_rp_mhz_show(struct device
*kdev
, struct device_attribute
*attr
, char *buf
)
378 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
379 struct drm_device
*dev
= minor
->dev
;
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 u32 val
, rp_state_cap
;
384 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
387 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
388 mutex_unlock(&dev
->struct_mutex
);
390 if (attr
== &dev_attr_gt_RP0_freq_mhz
) {
391 val
= ((rp_state_cap
& 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER
;
392 } else if (attr
== &dev_attr_gt_RP1_freq_mhz
) {
393 val
= ((rp_state_cap
& 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER
;
394 } else if (attr
== &dev_attr_gt_RPn_freq_mhz
) {
395 val
= ((rp_state_cap
& 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER
;
399 return snprintf(buf
, PAGE_SIZE
, "%d\n", val
);
402 static const struct attribute
*gen6_attrs
[] = {
403 &dev_attr_gt_cur_freq_mhz
.attr
,
404 &dev_attr_gt_max_freq_mhz
.attr
,
405 &dev_attr_gt_min_freq_mhz
.attr
,
406 &dev_attr_gt_RP0_freq_mhz
.attr
,
407 &dev_attr_gt_RP1_freq_mhz
.attr
,
408 &dev_attr_gt_RPn_freq_mhz
.attr
,
412 static ssize_t
error_state_read(struct file
*filp
, struct kobject
*kobj
,
413 struct bin_attribute
*attr
, char *buf
,
414 loff_t off
, size_t count
)
417 struct device
*kdev
= container_of(kobj
, struct device
, kobj
);
418 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
419 struct drm_device
*dev
= minor
->dev
;
420 struct i915_error_state_file_priv error_priv
;
421 struct drm_i915_error_state_buf error_str
;
422 ssize_t ret_count
= 0;
425 memset(&error_priv
, 0, sizeof(error_priv
));
427 ret
= i915_error_state_buf_init(&error_str
, count
, off
);
431 error_priv
.dev
= dev
;
432 i915_error_state_get(dev
, &error_priv
);
434 ret
= i915_error_state_to_str(&error_str
, &error_priv
);
438 ret_count
= count
< error_str
.bytes
? count
: error_str
.bytes
;
440 memcpy(buf
, error_str
.buf
, ret_count
);
442 i915_error_state_put(&error_priv
);
443 i915_error_state_buf_release(&error_str
);
445 return ret
?: ret_count
;
448 static ssize_t
error_state_write(struct file
*file
, struct kobject
*kobj
,
449 struct bin_attribute
*attr
, char *buf
,
450 loff_t off
, size_t count
)
452 struct device
*kdev
= container_of(kobj
, struct device
, kobj
);
453 struct drm_minor
*minor
= container_of(kdev
, struct drm_minor
, kdev
);
454 struct drm_device
*dev
= minor
->dev
;
457 DRM_DEBUG_DRIVER("Resetting error state\n");
459 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
463 i915_destroy_error_state(dev
);
464 mutex_unlock(&dev
->struct_mutex
);
469 static struct bin_attribute error_state_attr
= {
470 .attr
.name
= "error",
471 .attr
.mode
= S_IRUSR
| S_IWUSR
,
473 .read
= error_state_read
,
474 .write
= error_state_write
,
477 void i915_setup_sysfs(struct drm_device
*dev
)
482 if (INTEL_INFO(dev
)->gen
>= 6) {
483 ret
= sysfs_merge_group(&dev
->primary
->kdev
.kobj
,
486 DRM_ERROR("RC6 residency sysfs setup failed\n");
489 if (HAS_L3_GPU_CACHE(dev
)) {
490 ret
= device_create_bin_file(&dev
->primary
->kdev
, &dpf_attrs
);
492 DRM_ERROR("l3 parity sysfs setup failed\n");
495 if (INTEL_INFO(dev
)->gen
>= 6) {
496 ret
= sysfs_create_files(&dev
->primary
->kdev
.kobj
, gen6_attrs
);
498 DRM_ERROR("gen6 sysfs setup failed\n");
501 ret
= sysfs_create_bin_file(&dev
->primary
->kdev
.kobj
,
504 DRM_ERROR("error_state sysfs setup failed\n");
507 void i915_teardown_sysfs(struct drm_device
*dev
)
509 sysfs_remove_bin_file(&dev
->primary
->kdev
.kobj
, &error_state_attr
);
510 sysfs_remove_files(&dev
->primary
->kdev
.kobj
, gen6_attrs
);
511 device_remove_bin_file(&dev
->primary
->kdev
, &dpf_attrs
);
513 sysfs_unmerge_group(&dev
->primary
->kdev
.kobj
, &rc6_attr_group
);