drivers/gpu/drm/i915/intel_atomic.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic modeset support
  26  *
  27  * The functions here implement the state management and hardware programming
  28  * dispatch required by the atomic modeset infrastructure.
  29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
  30  */
  31
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include "intel_drv.h"
  37
  38
  39 /**
  40  * intel_atomic_check - validate state object
  41  * @dev: drm device
  42  * @state: state to validate
  43  */
  44 int intel_atomic_check(struct drm_device *dev,
  45                        struct drm_atomic_state *state)
  46 {
  47         int nplanes = dev->mode_config.num_total_plane;
  48         int ncrtcs = dev->mode_config.num_crtc;
  49         int nconnectors = dev->mode_config.num_connector;
  50         enum pipe nuclear_pipe = INVALID_PIPE;
  51         struct intel_crtc *nuclear_crtc = NULL;
  52         struct intel_crtc_state *crtc_state = NULL;
  53         int ret;
  54         int i;
  55         bool not_nuclear = false;
  56
  57         /*
  58          * FIXME:  At the moment, we only support "nuclear pageflip" on a
  59          * single CRTC.  Cross-crtc updates will be added later.
  60          */
  61         for (i = 0; i < nplanes; i++) {
  62                 struct intel_plane *plane = to_intel_plane(state->planes[i]);
  63                 if (!plane)
  64                         continue;
  65
  66                 if (nuclear_pipe == INVALID_PIPE) {
  67                         nuclear_pipe = plane->pipe;
  68                 } else if (nuclear_pipe != plane->pipe) {
  69                         DRM_DEBUG_KMS("i915 only support atomic plane operations on a single CRTC at the moment\n");
  70                         return -EINVAL;
  71                 }
  72         }
  73
  74         /*
  75          * FIXME:  We only handle planes for now; make sure there are no CRTC's
  76          * or connectors involved.
  77          */
  78         state->allow_modeset = false;
  79         for (i = 0; i < ncrtcs; i++) {
  80                 struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);
  81                 if (crtc)
  82                         memset(&crtc->atomic, 0, sizeof(crtc->atomic));
  83                 if (crtc && crtc->pipe != nuclear_pipe)
  84                         not_nuclear = true;
  85                 if (crtc && crtc->pipe == nuclear_pipe) {
  86                         nuclear_crtc = crtc;
  87                         crtc_state = to_intel_crtc_state(state->crtc_states[i]);
  88                 }
  89         }
  90         for (i = 0; i < nconnectors; i++)
  91                 if (state->connectors[i] != NULL)
  92                         not_nuclear = true;
  93
  94         if (not_nuclear) {
  95                 DRM_DEBUG_KMS("i915 only supports atomic plane operations at the moment\n");
  96                 return -EINVAL;
  97         }
  98
  99         ret = drm_atomic_helper_check_planes(dev, state);
 100         if (ret)
 101                 return ret;
 102
 103         /* FIXME: move to crtc atomic check function once it is ready */
 104         ret = intel_atomic_setup_scalers(dev, nuclear_crtc, crtc_state);
 105         if (ret)
 106                 return ret;
 107
 108         return ret;
 109 }
 110
 111
 112 /**
 113  * intel_atomic_commit - commit validated state object
 114  * @dev: DRM device
 115  * @state: the top-level driver state object
 116  * @async: asynchronous commit
 117  *
 118  * This function commits a top-level state object that has been validated
 119  * with drm_atomic_helper_check().
 120  *
 121  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
 122  * we can only handle plane-related operations and do not yet support
 123  * asynchronous commit.
 124  *
 125  * RETURNS
 126  * Zero for success or -errno.
 127  */
 128 int intel_atomic_commit(struct drm_device *dev,
 129                         struct drm_atomic_state *state,
 130                         bool async)
 131 {
 132         int ret;
 133         int i;
 134
 135         if (async) {
 136                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
 137                 return -EINVAL;
 138         }
 139
 140         ret = drm_atomic_helper_prepare_planes(dev, state);
 141         if (ret)
 142                 return ret;
 143
 144         /* Point of no return */
 145
 146         /*
 147          * FIXME:  The proper sequence here will eventually be:
 148          *
 149          * drm_atomic_helper_swap_state(dev, state)
 150          * drm_atomic_helper_commit_modeset_disables(dev, state);
 151          * drm_atomic_helper_commit_planes(dev, state);
 152          * drm_atomic_helper_commit_modeset_enables(dev, state);
 153          * drm_atomic_helper_wait_for_vblanks(dev, state);
 154          * drm_atomic_helper_cleanup_planes(dev, state);
 155          * drm_atomic_state_free(state);
 156          *
 157          * once we have full atomic modeset.  For now, just manually update
 158          * plane states to avoid clobbering good states with dummy states
 159          * while nuclear pageflipping.
 160          */
 161         for (i = 0; i < dev->mode_config.num_total_plane; i++) {
 162                 struct drm_plane *plane = state->planes[i];
 163
 164                 if (!plane)
 165                         continue;
 166
 167                 plane->state->state = state;
 168                 swap(state->plane_states[i], plane->state);
 169                 plane->state->state = NULL;
 170         }
 171
 172         /* swap crtc_scaler_state */
 173         for (i = 0; i < dev->mode_config.num_crtc; i++) {
 174                 struct drm_crtc *crtc = state->crtcs[i];
 175                 if (!crtc) {
 176                         continue;
 177                 }
 178
 179                 to_intel_crtc(crtc)->config->scaler_state =
 180                         to_intel_crtc_state(state->crtc_states[i])->scaler_state;
 181
 182                 if (INTEL_INFO(dev)->gen >= 9)
 183                         skl_detach_scalers(to_intel_crtc(crtc));
 184         }
 185
 186         drm_atomic_helper_commit_planes(dev, state);
 187         drm_atomic_helper_wait_for_vblanks(dev, state);
 188         drm_atomic_helper_cleanup_planes(dev, state);
 189         drm_atomic_state_free(state);
 190
 191         return 0;
 192 }
 193
 194 /**
 195  * intel_connector_atomic_get_property - fetch connector property value
 196  * @connector: connector to fetch property for
 197  * @state: state containing the property value
 198  * @property: property to look up
 199  * @val: pointer to write property value into
 200  *
 201  * The DRM core does not store shadow copies of properties for
 202  * atomic-capable drivers.  This entrypoint is used to fetch
 203  * the current value of a driver-specific connector property.
 204  */
 205 int
 206 intel_connector_atomic_get_property(struct drm_connector *connector,
 207                                     const struct drm_connector_state *state,
 208                                     struct drm_property *property,
 209                                     uint64_t *val)
 210 {
 211         int i;
 212
 213         /*
 214          * TODO: We only have atomic modeset for planes at the moment, so the
 215          * crtc/connector code isn't quite ready yet.  Until it's ready,
 216          * continue to look up all property values in the DRM's shadow copy
 217          * in obj->properties->values[].
 218          *
 219          * When the crtc/connector state work matures, this function should
 220          * be updated to read the values out of the state structure instead.
 221          */
 222         for (i = 0; i < connector->base.properties->count; i++) {
 223                 if (connector->base.properties->properties[i] == property) {
 224                         *val = connector->base.properties->values[i];
 225                         return 0;
 226                 }
 227         }
 228
 229         return -EINVAL;
 230 }
 231
 232 /*
 233  * intel_crtc_duplicate_state - duplicate crtc state
 234  * @crtc: drm crtc
 235  *
 236  * Allocates and returns a copy of the crtc state (both common and
 237  * Intel-specific) for the specified crtc.
 238  *
 239  * Returns: The newly allocated crtc state, or NULL on failure.
 240  */
 241 struct drm_crtc_state *
 242 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 243 {
 244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 245         struct intel_crtc_state *crtc_state;
 246
 247         if (WARN_ON(!intel_crtc->config))
 248                 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
 249         else
 250                 crtc_state = kmemdup(intel_crtc->config,
 251                                      sizeof(*intel_crtc->config), GFP_KERNEL);
 252
 253         if (!crtc_state)
 254                 return NULL;
 255
 256         __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
 257
 258         crtc_state->base.crtc = crtc;
 259
 260         return &crtc_state->base;
 261 }
 262
 263 /**
 264  * intel_crtc_destroy_state - destroy crtc state
 265  * @crtc: drm crtc
 266  *
 267  * Destroys the crtc state (both common and Intel-specific) for the
 268  * specified crtc.
 269  */
 270 void
 271 intel_crtc_destroy_state(struct drm_crtc *crtc,
 272                           struct drm_crtc_state *state)
 273 {
 274         drm_atomic_helper_crtc_destroy_state(crtc, state);
 275 }
 276
 277 /**
 278  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
 279  * @dev: DRM device
 280  * @crtc: intel crtc
 281  * @crtc_state: incoming crtc_state to validate and setup scalers
 282  *
 283  * This function sets up scalers based on staged scaling requests for
 284  * a @crtc and its planes. It is called from crtc level check path. If request
 285  * is a supportable request, it attaches scalers to requested planes and crtc.
 286  *
 287  * This function takes into account the current scaler(s) in use by any planes
 288  * not being part of this atomic state
 289  *
 290  *  Returns:
 291  *         0 - scalers were setup succesfully
 292  *         error code - otherwise
 293  */
 294 int intel_atomic_setup_scalers(struct drm_device *dev,
 295         struct intel_crtc *intel_crtc,
 296         struct intel_crtc_state *crtc_state)
 297 {
 298         struct drm_plane *plane = NULL;
 299         struct intel_plane *intel_plane;
 300         struct intel_plane_state *plane_state = NULL;
 301         struct intel_crtc_scaler_state *scaler_state;
 302         struct drm_atomic_state *drm_state;
 303         int num_scalers_need;
 304         int i, j;
 305
 306         if (INTEL_INFO(dev)->gen < 9 || !intel_crtc || !crtc_state)
 307                 return 0;
 308
 309         scaler_state = &crtc_state->scaler_state;
 310         drm_state = crtc_state->base.state;
 311
 312         num_scalers_need = hweight32(scaler_state->scaler_users);
 313         DRM_DEBUG_KMS("crtc_state = %p need = %d avail = %d scaler_users = 0x%x\n",
 314                 crtc_state, num_scalers_need, intel_crtc->num_scalers,
 315                 scaler_state->scaler_users);
 316
 317         /*
 318          * High level flow:
 319          * - staged scaler requests are already in scaler_state->scaler_users
 320          * - check whether staged scaling requests can be supported
 321          * - add planes using scalers that aren't in current transaction
 322          * - assign scalers to requested users
 323          * - as part of plane commit, scalers will be committed
 324          *   (i.e., either attached or detached) to respective planes in hw
 325          * - as part of crtc_commit, scaler will be either attached or detached
 326          *   to crtc in hw
 327          */
 328
 329         /* fail if required scalers > available scalers */
 330         if (num_scalers_need > intel_crtc->num_scalers){
 331                 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
 332                         num_scalers_need, intel_crtc->num_scalers);
 333                 return -EINVAL;
 334         }
 335
 336         /* walkthrough scaler_users bits and start assigning scalers */
 337         for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 338                 int *scaler_id;
 339
 340                 /* skip if scaler not required */
 341                 if (!(scaler_state->scaler_users & (1 << i)))
 342                         continue;
 343
 344                 if (i == SKL_CRTC_INDEX) {
 345                         /* panel fitter case: assign as a crtc scaler */
 346                         scaler_id = &scaler_state->scaler_id;
 347                 } else {
 348                         if (!drm_state)
 349                                 continue;
 350
 351                         /* plane scaler case: assign as a plane scaler */
 352                         /* find the plane that set the bit as scaler_user */
 353                         plane = drm_state->planes[i];
 354
 355                         /*
 356                          * to enable/disable hq mode, add planes that are using scaler
 357                          * into this transaction
 358                          */
 359                         if (!plane) {
 360                                 struct drm_plane_state *state;
 361                                 plane = drm_plane_from_index(dev, i);
 362                                 state = drm_atomic_get_plane_state(drm_state, plane);
 363                                 if (IS_ERR(state)) {
 364                                         DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
 365                                                 plane->base.id);
 366                                         return PTR_ERR(state);
 367                                 }
 368                         }
 369
 370                         intel_plane = to_intel_plane(plane);
 371
 372                         /* plane on different crtc cannot be a scaler user of this crtc */
 373                         if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) {
 374                                 continue;
 375                         }
 376
 377                         plane_state = to_intel_plane_state(drm_state->plane_states[i]);
 378                         scaler_id = &plane_state->scaler_id;
 379                 }
 380
 381                 if (*scaler_id < 0) {
 382                         /* find a free scaler */
 383                         for (j = 0; j < intel_crtc->num_scalers; j++) {
 384                                 if (!scaler_state->scalers[j].in_use) {
 385                                         scaler_state->scalers[j].in_use = 1;
 386                                         *scaler_id = scaler_state->scalers[j].id;
 387                                         DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
 388                                                 intel_crtc->pipe,
 389                                                 i == SKL_CRTC_INDEX ? scaler_state->scaler_id :
 390                                                         plane_state->scaler_id,
 391                                                 i == SKL_CRTC_INDEX ? "CRTC" : "PLANE",
 392                                                 i == SKL_CRTC_INDEX ?  intel_crtc->base.base.id :
 393                                                 plane->base.id);
 394                                         break;
 395                                 }
 396                         }
 397                 }
 398
 399                 if (WARN_ON(*scaler_id < 0)) {
 400                         DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n",
 401                                 i == SKL_CRTC_INDEX ? "CRTC" : "PLANE",
 402                                 i == SKL_CRTC_INDEX ? intel_crtc->base.base.id:plane->base.id);
 403                         continue;
 404                 }
 405
 406                 /* set scaler mode */
 407                 if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
 408                         /*
 409                          * when only 1 scaler is in use on either pipe A or B,
 410                          * scaler 0 operates in high quality (HQ) mode.
 411                          * In this case use scaler 0 to take advantage of HQ mode
 412                          */
 413                         *scaler_id = 0;
 414                         scaler_state->scalers[0].in_use = 1;
 415                         scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ;
 416                         scaler_state->scalers[1].in_use = 0;
 417                 } else {
 418                         scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN;
 419                 }
 420         }
 421
 422         return 0;
 423 }
 424
 425 static void
 426 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
 427                                   struct intel_shared_dpll_config *shared_dpll)
 428 {
 429         enum intel_dpll_id i;
 430
 431         /* Copy shared dpll state */
 432         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 433                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 434
 435                 shared_dpll[i] = pll->config;
 436         }
 437 }
 438
 439 struct intel_shared_dpll_config *
 440 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
 441 {
 442         struct intel_atomic_state *state = to_intel_atomic_state(s);
 443
 444         WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
 445
 446         if (!state->dpll_set) {
 447                 state->dpll_set = true;
 448
 449                 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
 450                                                   state->shared_dpll);
 451         }
 452
 453         return state->shared_dpll;
 454 }
 455
 456 struct drm_atomic_state *
 457 intel_atomic_state_alloc(struct drm_device *dev)
 458 {
 459         struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 460
 461         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 462                 kfree(state);
 463                 return NULL;
 464         }
 465
 466         return &state->base;
 467 }
 468
 469 void intel_atomic_state_clear(struct drm_atomic_state *s)
 470 {
 471         struct intel_atomic_state *state = to_intel_atomic_state(s);
 472         drm_atomic_state_default_clear(&state->base);
 473         state->dpll_set = false;
 474 }