2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
54 * The struct i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct i915_audio_component_ops *ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
63 } hdmi_audio_clock
[] = {
64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
76 /* HDMI N/CTS table */
77 #define TMDS_297M 297000
78 #define TMDS_296M 296703
85 { 44100, TMDS_296M
, 4459, 234375 },
86 { 44100, TMDS_297M
, 4704, 247500 },
87 { 48000, TMDS_296M
, 5824, 281250 },
88 { 48000, TMDS_297M
, 5120, 247500 },
89 { 32000, TMDS_296M
, 5824, 421875 },
90 { 32000, TMDS_297M
, 3072, 222750 },
91 { 88200, TMDS_296M
, 8918, 234375 },
92 { 88200, TMDS_297M
, 9408, 247500 },
93 { 96000, TMDS_296M
, 11648, 281250 },
94 { 96000, TMDS_297M
, 10240, 247500 },
95 { 176400, TMDS_296M
, 17836, 234375 },
96 { 176400, TMDS_297M
, 18816, 247500 },
97 { 192000, TMDS_296M
, 23296, 281250 },
98 { 192000, TMDS_297M
, 20480, 247500 },
101 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
102 static u32
audio_config_hdmi_pixel_clock(const struct drm_display_mode
*adjusted_mode
)
106 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
107 if (adjusted_mode
->crtc_clock
== hdmi_audio_clock
[i
].clock
)
111 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
112 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
113 adjusted_mode
->crtc_clock
);
117 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
118 hdmi_audio_clock
[i
].clock
,
119 hdmi_audio_clock
[i
].config
);
121 return hdmi_audio_clock
[i
].config
;
124 static int audio_config_get_n(const struct drm_display_mode
*mode
, int rate
)
128 for (i
= 0; i
< ARRAY_SIZE(aud_ncts
); i
++) {
129 if ((rate
== aud_ncts
[i
].sample_rate
) &&
130 (mode
->clock
== aud_ncts
[i
].clock
)) {
131 return aud_ncts
[i
].n
;
137 static uint32_t audio_config_setup_n_reg(int n
, uint32_t val
)
143 n_up
= (n
>> 12) & 0xff;
144 tmp
&= ~(AUD_CONFIG_UPPER_N_MASK
| AUD_CONFIG_LOWER_N_MASK
);
145 tmp
|= ((n_up
<< AUD_CONFIG_UPPER_N_SHIFT
) |
146 (n_low
<< AUD_CONFIG_LOWER_N_SHIFT
) |
147 AUD_CONFIG_N_PROG_ENABLE
);
151 /* check whether N/CTS/M need be set manually */
152 static bool audio_rate_need_prog(struct intel_crtc
*crtc
,
153 const struct drm_display_mode
*mode
)
155 if (((mode
->clock
== TMDS_297M
) ||
156 (mode
->clock
== TMDS_296M
)) &&
157 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
163 static bool intel_eld_uptodate(struct drm_connector
*connector
,
164 i915_reg_t reg_eldv
, uint32_t bits_eldv
,
165 i915_reg_t reg_elda
, uint32_t bits_elda
,
168 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
169 uint8_t *eld
= connector
->eld
;
173 tmp
= I915_READ(reg_eldv
);
179 tmp
= I915_READ(reg_elda
);
181 I915_WRITE(reg_elda
, tmp
);
183 for (i
= 0; i
< drm_eld_size(eld
) / 4; i
++)
184 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
190 static void g4x_audio_codec_disable(struct intel_encoder
*encoder
)
192 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
195 DRM_DEBUG_KMS("Disable audio codec\n");
197 tmp
= I915_READ(G4X_AUD_VID_DID
);
198 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
199 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
201 eldv
= G4X_ELDV_DEVCTG
;
204 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
206 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
209 static void g4x_audio_codec_enable(struct drm_connector
*connector
,
210 struct intel_encoder
*encoder
,
211 const struct drm_display_mode
*adjusted_mode
)
213 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
214 uint8_t *eld
= connector
->eld
;
219 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld
[2]);
221 tmp
= I915_READ(G4X_AUD_VID_DID
);
222 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
223 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
225 eldv
= G4X_ELDV_DEVCTG
;
227 if (intel_eld_uptodate(connector
,
228 G4X_AUD_CNTL_ST
, eldv
,
229 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR_MASK
,
233 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
234 tmp
&= ~(eldv
| G4X_ELD_ADDR_MASK
);
235 len
= (tmp
>> 9) & 0x1f; /* ELD buffer size */
236 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
238 len
= min(drm_eld_size(eld
) / 4, len
);
239 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
240 for (i
= 0; i
< len
; i
++)
241 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
243 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
245 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
248 static void hsw_audio_codec_disable(struct intel_encoder
*encoder
)
250 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
251 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
252 enum pipe pipe
= intel_crtc
->pipe
;
255 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe
));
257 mutex_lock(&dev_priv
->av_mutex
);
259 /* Disable timestamps */
260 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
261 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
262 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
263 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
264 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
265 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
266 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DP_MST
))
267 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
268 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
271 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
272 tmp
&= ~AUDIO_ELD_VALID(pipe
);
273 tmp
&= ~AUDIO_OUTPUT_ENABLE(pipe
);
274 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
276 mutex_unlock(&dev_priv
->av_mutex
);
279 static void hsw_audio_codec_enable(struct drm_connector
*connector
,
280 struct intel_encoder
*encoder
,
281 const struct drm_display_mode
*adjusted_mode
)
283 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
284 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
285 enum pipe pipe
= intel_crtc
->pipe
;
286 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
287 const uint8_t *eld
= connector
->eld
;
288 struct intel_digital_port
*intel_dig_port
=
289 enc_to_dig_port(&encoder
->base
);
290 enum port port
= intel_dig_port
->port
;
295 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
296 pipe_name(pipe
), drm_eld_size(eld
));
298 mutex_lock(&dev_priv
->av_mutex
);
300 /* Enable audio presence detect, invalidate ELD */
301 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
302 tmp
|= AUDIO_OUTPUT_ENABLE(pipe
);
303 tmp
&= ~AUDIO_ELD_VALID(pipe
);
304 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
307 * FIXME: We're supposed to wait for vblank here, but we have vblanks
308 * disabled during the mode set. The proper fix would be to push the
309 * rest of the setup into a vblank work item, queued here, but the
310 * infrastructure is not there yet.
313 /* Reset ELD write address */
314 tmp
= I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe
));
315 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
316 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe
), tmp
);
318 /* Up to 84 bytes of hw ELD buffer */
319 len
= min(drm_eld_size(eld
), 84);
320 for (i
= 0; i
< len
/ 4; i
++)
321 I915_WRITE(HSW_AUD_EDID_DATA(pipe
), *((uint32_t *)eld
+ i
));
324 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
325 tmp
|= AUDIO_ELD_VALID(pipe
);
326 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
328 /* Enable timestamps */
329 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
330 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
331 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
332 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
333 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
335 tmp
|= audio_config_hdmi_pixel_clock(adjusted_mode
);
337 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
338 if (audio_rate_need_prog(intel_crtc
, adjusted_mode
)) {
341 else if (port
>= PORT_A
&& port
<= PORT_E
)
342 rate
= acomp
->aud_sample_rate
[port
];
344 DRM_ERROR("invalid port: %d\n", port
);
347 n
= audio_config_get_n(adjusted_mode
, rate
);
349 tmp
= audio_config_setup_n_reg(n
, tmp
);
351 DRM_DEBUG_KMS("no suitable N value is found\n");
354 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
356 mutex_unlock(&dev_priv
->av_mutex
);
359 static void ilk_audio_codec_disable(struct intel_encoder
*encoder
)
361 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
362 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
363 struct intel_digital_port
*intel_dig_port
=
364 enc_to_dig_port(&encoder
->base
);
365 enum port port
= intel_dig_port
->port
;
366 enum pipe pipe
= intel_crtc
->pipe
;
368 i915_reg_t aud_config
, aud_cntrl_st2
;
370 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
371 port_name(port
), pipe_name(pipe
));
373 if (WARN_ON(port
== PORT_A
))
376 if (HAS_PCH_IBX(dev_priv
)) {
377 aud_config
= IBX_AUD_CFG(pipe
);
378 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
379 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
380 aud_config
= VLV_AUD_CFG(pipe
);
381 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
383 aud_config
= CPT_AUD_CFG(pipe
);
384 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
387 /* Disable timestamps */
388 tmp
= I915_READ(aud_config
);
389 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
390 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
391 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
392 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
393 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
394 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
395 I915_WRITE(aud_config
, tmp
);
397 eldv
= IBX_ELD_VALID(port
);
400 tmp
= I915_READ(aud_cntrl_st2
);
402 I915_WRITE(aud_cntrl_st2
, tmp
);
405 static void ilk_audio_codec_enable(struct drm_connector
*connector
,
406 struct intel_encoder
*encoder
,
407 const struct drm_display_mode
*adjusted_mode
)
409 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
411 struct intel_digital_port
*intel_dig_port
=
412 enc_to_dig_port(&encoder
->base
);
413 enum port port
= intel_dig_port
->port
;
414 enum pipe pipe
= intel_crtc
->pipe
;
415 uint8_t *eld
= connector
->eld
;
419 i915_reg_t hdmiw_hdmiedid
, aud_config
, aud_cntl_st
, aud_cntrl_st2
;
421 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
422 port_name(port
), pipe_name(pipe
), drm_eld_size(eld
));
424 if (WARN_ON(port
== PORT_A
))
428 * FIXME: We're supposed to wait for vblank here, but we have vblanks
429 * disabled during the mode set. The proper fix would be to push the
430 * rest of the setup into a vblank work item, queued here, but the
431 * infrastructure is not there yet.
434 if (HAS_PCH_IBX(connector
->dev
)) {
435 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
436 aud_config
= IBX_AUD_CFG(pipe
);
437 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
438 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
439 } else if (IS_VALLEYVIEW(connector
->dev
) ||
440 IS_CHERRYVIEW(connector
->dev
)) {
441 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
442 aud_config
= VLV_AUD_CFG(pipe
);
443 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
444 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
446 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
447 aud_config
= CPT_AUD_CFG(pipe
);
448 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
449 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
452 eldv
= IBX_ELD_VALID(port
);
455 tmp
= I915_READ(aud_cntrl_st2
);
457 I915_WRITE(aud_cntrl_st2
, tmp
);
459 /* Reset ELD write address */
460 tmp
= I915_READ(aud_cntl_st
);
461 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
462 I915_WRITE(aud_cntl_st
, tmp
);
464 /* Up to 84 bytes of hw ELD buffer */
465 len
= min(drm_eld_size(eld
), 84);
466 for (i
= 0; i
< len
/ 4; i
++)
467 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
470 tmp
= I915_READ(aud_cntrl_st2
);
472 I915_WRITE(aud_cntrl_st2
, tmp
);
474 /* Enable timestamps */
475 tmp
= I915_READ(aud_config
);
476 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
477 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
478 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
479 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
480 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DP_MST
))
481 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
483 tmp
|= audio_config_hdmi_pixel_clock(adjusted_mode
);
484 I915_WRITE(aud_config
, tmp
);
488 * intel_audio_codec_enable - Enable the audio codec for HD audio
489 * @intel_encoder: encoder on which to enable audio
491 * The enable sequences may only be performed after enabling the transcoder and
492 * port, and after completed link training.
494 void intel_audio_codec_enable(struct intel_encoder
*intel_encoder
)
496 struct drm_encoder
*encoder
= &intel_encoder
->base
;
497 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
498 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
499 struct drm_connector
*connector
;
500 struct drm_device
*dev
= encoder
->dev
;
501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
502 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
503 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
504 enum port port
= intel_dig_port
->port
;
506 connector
= drm_select_eld(encoder
);
510 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
513 connector
->encoder
->base
.id
,
514 connector
->encoder
->name
);
517 connector
->eld
[5] &= ~(3 << 2);
518 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
519 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DP_MST
))
520 connector
->eld
[5] |= (1 << 2);
522 connector
->eld
[6] = drm_av_sync_delay(connector
, adjusted_mode
) / 2;
524 if (dev_priv
->display
.audio_codec_enable
)
525 dev_priv
->display
.audio_codec_enable(connector
, intel_encoder
,
528 mutex_lock(&dev_priv
->av_mutex
);
529 intel_dig_port
->audio_connector
= connector
;
530 /* referred in audio callbacks */
531 dev_priv
->dig_port_map
[port
] = intel_encoder
;
532 mutex_unlock(&dev_priv
->av_mutex
);
534 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
)
535 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
, (int) port
);
539 * intel_audio_codec_disable - Disable the audio codec for HD audio
540 * @intel_encoder: encoder on which to disable audio
542 * The disable sequences must be performed before disabling the transcoder or
545 void intel_audio_codec_disable(struct intel_encoder
*intel_encoder
)
547 struct drm_encoder
*encoder
= &intel_encoder
->base
;
548 struct drm_device
*dev
= encoder
->dev
;
549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
550 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
551 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
552 enum port port
= intel_dig_port
->port
;
554 if (dev_priv
->display
.audio_codec_disable
)
555 dev_priv
->display
.audio_codec_disable(intel_encoder
);
557 mutex_lock(&dev_priv
->av_mutex
);
558 intel_dig_port
->audio_connector
= NULL
;
559 dev_priv
->dig_port_map
[port
] = NULL
;
560 mutex_unlock(&dev_priv
->av_mutex
);
562 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
)
563 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
, (int) port
);
567 * intel_init_audio_hooks - Set up chip specific audio hooks
568 * @dev_priv: device private
570 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
)
572 if (IS_G4X(dev_priv
)) {
573 dev_priv
->display
.audio_codec_enable
= g4x_audio_codec_enable
;
574 dev_priv
->display
.audio_codec_disable
= g4x_audio_codec_disable
;
575 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
576 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
577 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
578 } else if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8) {
579 dev_priv
->display
.audio_codec_enable
= hsw_audio_codec_enable
;
580 dev_priv
->display
.audio_codec_disable
= hsw_audio_codec_disable
;
581 } else if (HAS_PCH_SPLIT(dev_priv
)) {
582 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
583 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
587 static void i915_audio_component_get_power(struct device
*dev
)
589 intel_display_power_get(dev_to_i915(dev
), POWER_DOMAIN_AUDIO
);
592 static void i915_audio_component_put_power(struct device
*dev
)
594 intel_display_power_put(dev_to_i915(dev
), POWER_DOMAIN_AUDIO
);
597 static void i915_audio_component_codec_wake_override(struct device
*dev
,
600 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
603 if (!IS_SKYLAKE(dev_priv
) && !IS_KABYLAKE(dev_priv
))
607 * Enable/disable generating the codec wake signal, overriding the
608 * internal logic to generate the codec wake to controller.
610 tmp
= I915_READ(HSW_AUD_CHICKENBIT
);
611 tmp
&= ~SKL_AUD_CODEC_WAKE_SIGNAL
;
612 I915_WRITE(HSW_AUD_CHICKENBIT
, tmp
);
613 usleep_range(1000, 1500);
616 tmp
= I915_READ(HSW_AUD_CHICKENBIT
);
617 tmp
|= SKL_AUD_CODEC_WAKE_SIGNAL
;
618 I915_WRITE(HSW_AUD_CHICKENBIT
, tmp
);
619 usleep_range(1000, 1500);
623 /* Get CDCLK in kHz */
624 static int i915_audio_component_get_cdclk_freq(struct device
*dev
)
626 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
629 if (WARN_ON_ONCE(!HAS_DDI(dev_priv
)))
632 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
633 ret
= dev_priv
->display
.get_display_clock_speed(dev_priv
->dev
);
635 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
640 static int i915_audio_component_sync_audio_rate(struct device
*dev
,
643 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
644 struct intel_encoder
*intel_encoder
;
645 struct intel_crtc
*crtc
;
646 struct drm_display_mode
*mode
;
647 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
648 enum pipe pipe
= INVALID_PIPE
;
653 /* HSW, BDW, SKL, KBL need this fix */
654 if (!IS_SKYLAKE(dev_priv
) &&
655 !IS_KABYLAKE(dev_priv
) &&
656 !IS_BROADWELL(dev_priv
) &&
657 !IS_HASWELL(dev_priv
))
660 mutex_lock(&dev_priv
->av_mutex
);
661 /* 1. get the pipe */
662 intel_encoder
= dev_priv
->dig_port_map
[port
];
663 /* intel_encoder might be NULL for DP MST */
664 if (!intel_encoder
|| !intel_encoder
->base
.crtc
||
665 intel_encoder
->type
!= INTEL_OUTPUT_HDMI
) {
666 DRM_DEBUG_KMS("no valid port %c\n", port_name(port
));
670 crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
672 if (pipe
== INVALID_PIPE
) {
673 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port
));
678 DRM_DEBUG_KMS("pipe %c connects port %c\n",
679 pipe_name(pipe
), port_name(port
));
680 mode
= &crtc
->config
->base
.adjusted_mode
;
682 /* port must be valid now, otherwise the pipe will be invalid */
683 acomp
->aud_sample_rate
[port
] = rate
;
685 /* 2. check whether to set the N/CTS/M manually or not */
686 if (!audio_rate_need_prog(crtc
, mode
)) {
687 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
688 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
689 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
693 n
= audio_config_get_n(mode
, rate
);
695 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
697 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
698 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
699 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
703 /* 3. set the N/CTS/M */
704 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
705 tmp
= audio_config_setup_n_reg(n
, tmp
);
706 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
709 mutex_unlock(&dev_priv
->av_mutex
);
713 static int i915_audio_component_get_eld(struct device
*dev
, int port
,
715 unsigned char *buf
, int max_bytes
)
717 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
718 struct intel_encoder
*intel_encoder
;
719 struct intel_digital_port
*intel_dig_port
;
723 mutex_lock(&dev_priv
->av_mutex
);
724 intel_encoder
= dev_priv
->dig_port_map
[port
];
725 /* intel_encoder might be NULL for DP MST */
728 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
729 *enabled
= intel_dig_port
->audio_connector
!= NULL
;
731 eld
= intel_dig_port
->audio_connector
->eld
;
732 ret
= drm_eld_size(eld
);
733 memcpy(buf
, eld
, min(max_bytes
, ret
));
737 mutex_unlock(&dev_priv
->av_mutex
);
741 static const struct i915_audio_component_ops i915_audio_component_ops
= {
742 .owner
= THIS_MODULE
,
743 .get_power
= i915_audio_component_get_power
,
744 .put_power
= i915_audio_component_put_power
,
745 .codec_wake_override
= i915_audio_component_codec_wake_override
,
746 .get_cdclk_freq
= i915_audio_component_get_cdclk_freq
,
747 .sync_audio_rate
= i915_audio_component_sync_audio_rate
,
748 .get_eld
= i915_audio_component_get_eld
,
751 static int i915_audio_component_bind(struct device
*i915_dev
,
752 struct device
*hda_dev
, void *data
)
754 struct i915_audio_component
*acomp
= data
;
755 struct drm_i915_private
*dev_priv
= dev_to_i915(i915_dev
);
758 if (WARN_ON(acomp
->ops
|| acomp
->dev
))
761 drm_modeset_lock_all(dev_priv
->dev
);
762 acomp
->ops
= &i915_audio_component_ops
;
763 acomp
->dev
= i915_dev
;
764 BUILD_BUG_ON(MAX_PORTS
!= I915_MAX_PORTS
);
765 for (i
= 0; i
< ARRAY_SIZE(acomp
->aud_sample_rate
); i
++)
766 acomp
->aud_sample_rate
[i
] = 0;
767 dev_priv
->audio_component
= acomp
;
768 drm_modeset_unlock_all(dev_priv
->dev
);
773 static void i915_audio_component_unbind(struct device
*i915_dev
,
774 struct device
*hda_dev
, void *data
)
776 struct i915_audio_component
*acomp
= data
;
777 struct drm_i915_private
*dev_priv
= dev_to_i915(i915_dev
);
779 drm_modeset_lock_all(dev_priv
->dev
);
782 dev_priv
->audio_component
= NULL
;
783 drm_modeset_unlock_all(dev_priv
->dev
);
786 static const struct component_ops i915_audio_component_bind_ops
= {
787 .bind
= i915_audio_component_bind
,
788 .unbind
= i915_audio_component_unbind
,
792 * i915_audio_component_init - initialize and register the audio component
793 * @dev_priv: i915 device instance
795 * This will register with the component framework a child component which
796 * will bind dynamically to the snd_hda_intel driver's corresponding master
797 * component when the latter is registered. During binding the child
798 * initializes an instance of struct i915_audio_component which it receives
799 * from the master. The master can then start to use the interface defined by
800 * this struct. Each side can break the binding at any point by deregistering
801 * its own component after which each side's component unbind callback is
804 * We ignore any error during registration and continue with reduced
805 * functionality (i.e. without HDMI audio).
807 void i915_audio_component_init(struct drm_i915_private
*dev_priv
)
811 ret
= component_add(dev_priv
->dev
->dev
, &i915_audio_component_bind_ops
);
813 DRM_ERROR("failed to add audio component (%d)\n", ret
);
814 /* continue with reduced functionality */
818 dev_priv
->audio_component_registered
= true;
822 * i915_audio_component_cleanup - deregister the audio component
823 * @dev_priv: i915 device instance
825 * Deregisters the audio component, breaking any existing binding to the
826 * corresponding snd_hda_intel driver's master component.
828 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
)
830 if (!dev_priv
->audio_component_registered
)
833 component_del(dev_priv
->dev
->dev
, &i915_audio_component_bind_ops
);
834 dev_priv
->audio_component_registered
= false;