2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
27 #include <drm/drm_edid.h>
28 #include "intel_drv.h"
34 } hdmi_audio_clock
[] = {
35 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
36 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
37 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
38 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
39 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
40 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
41 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
42 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
43 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
44 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
47 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
48 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
52 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
53 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
57 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
58 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
62 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
63 hdmi_audio_clock
[i
].clock
,
64 hdmi_audio_clock
[i
].config
);
66 return hdmi_audio_clock
[i
].config
;
69 static bool intel_eld_uptodate(struct drm_connector
*connector
,
70 int reg_eldv
, uint32_t bits_eldv
,
71 int reg_elda
, uint32_t bits_elda
,
74 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
75 uint8_t *eld
= connector
->eld
;
79 tmp
= I915_READ(reg_eldv
);
85 tmp
= I915_READ(reg_elda
);
87 I915_WRITE(reg_elda
, tmp
);
89 for (i
= 0; i
< eld
[2]; i
++)
90 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
96 static void g4x_audio_codec_disable(struct intel_encoder
*encoder
)
98 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
101 DRM_DEBUG_KMS("Disable audio codec\n");
103 tmp
= I915_READ(G4X_AUD_VID_DID
);
104 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
105 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
107 eldv
= G4X_ELDV_DEVCTG
;
110 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
112 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
115 static void g4x_audio_codec_enable(struct drm_connector
*connector
,
116 struct intel_encoder
*encoder
,
117 struct drm_display_mode
*mode
)
119 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
120 uint8_t *eld
= connector
->eld
;
125 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld
[2]);
127 tmp
= I915_READ(G4X_AUD_VID_DID
);
128 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
129 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
131 eldv
= G4X_ELDV_DEVCTG
;
133 if (intel_eld_uptodate(connector
,
134 G4X_AUD_CNTL_ST
, eldv
,
135 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR_MASK
,
139 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
140 tmp
&= ~(eldv
| G4X_ELD_ADDR_MASK
);
141 len
= (tmp
>> 9) & 0x1f; /* ELD buffer size */
142 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
144 len
= min_t(int, eld
[2], len
);
145 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
146 for (i
= 0; i
< len
; i
++)
147 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
149 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
151 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
154 static void hsw_audio_codec_disable(struct intel_encoder
*encoder
)
156 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
157 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
158 enum pipe pipe
= intel_crtc
->pipe
;
161 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe
));
163 /* Disable timestamps */
164 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
165 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
166 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
167 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
168 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
169 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
170 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
171 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
174 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
175 tmp
&= ~AUDIO_ELD_VALID(pipe
);
176 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
179 static void hsw_audio_codec_enable(struct drm_connector
*connector
,
180 struct intel_encoder
*encoder
,
181 struct drm_display_mode
*mode
)
183 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
184 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
185 enum pipe pipe
= intel_crtc
->pipe
;
186 const uint8_t *eld
= connector
->eld
;
190 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
191 pipe_name(pipe
), eld
[2]);
193 /* Enable audio presence detect, invalidate ELD */
194 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
195 tmp
|= AUDIO_OUTPUT_ENABLE(pipe
);
196 tmp
&= ~AUDIO_ELD_VALID(pipe
);
197 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
200 * FIXME: We're supposed to wait for vblank here, but we have vblanks
201 * disabled during the mode set. The proper fix would be to push the
202 * rest of the setup into a vblank work item, queued here, but the
203 * infrastructure is not there yet.
206 /* Reset ELD write address */
207 tmp
= I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe
));
208 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
209 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe
), tmp
);
211 /* Up to 84 bytes of hw ELD buffer */
212 len
= min_t(int, eld
[2], 21);
213 for (i
= 0; i
< len
; i
++)
214 I915_WRITE(HSW_AUD_EDID_DATA(pipe
), *((uint32_t *)eld
+ i
));
217 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
218 tmp
|= AUDIO_ELD_VALID(pipe
);
219 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
221 /* Enable timestamps */
222 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
223 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
224 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
225 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
226 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
227 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
229 tmp
|= audio_config_hdmi_pixel_clock(mode
);
230 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
233 static void ilk_audio_codec_disable(struct intel_encoder
*encoder
)
235 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
236 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
237 struct intel_digital_port
*intel_dig_port
=
238 enc_to_dig_port(&encoder
->base
);
239 enum port port
= intel_dig_port
->port
;
240 enum pipe pipe
= intel_crtc
->pipe
;
245 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
246 port_name(port
), pipe_name(pipe
));
248 if (HAS_PCH_IBX(dev_priv
->dev
)) {
249 aud_config
= IBX_AUD_CFG(pipe
);
250 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
251 } else if (IS_VALLEYVIEW(dev_priv
)) {
252 aud_config
= VLV_AUD_CFG(pipe
);
253 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
255 aud_config
= CPT_AUD_CFG(pipe
);
256 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
259 /* Disable timestamps */
260 tmp
= I915_READ(aud_config
);
261 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
262 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
263 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
264 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
265 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
266 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
267 I915_WRITE(aud_config
, tmp
);
269 if (WARN_ON(!port
)) {
270 eldv
= IBX_ELD_VALID(PORT_B
) | IBX_ELD_VALID(PORT_C
) |
271 IBX_ELD_VALID(PORT_D
);
273 eldv
= IBX_ELD_VALID(port
);
277 tmp
= I915_READ(aud_cntrl_st2
);
279 I915_WRITE(aud_cntrl_st2
, tmp
);
282 static void ilk_audio_codec_enable(struct drm_connector
*connector
,
283 struct intel_encoder
*encoder
,
284 struct drm_display_mode
*mode
)
286 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
287 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
288 struct intel_digital_port
*intel_dig_port
=
289 enc_to_dig_port(&encoder
->base
);
290 enum port port
= intel_dig_port
->port
;
291 enum pipe pipe
= intel_crtc
->pipe
;
292 uint8_t *eld
= connector
->eld
;
301 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
302 port_name(port
), pipe_name(pipe
), eld
[2]);
305 * FIXME: We're supposed to wait for vblank here, but we have vblanks
306 * disabled during the mode set. The proper fix would be to push the
307 * rest of the setup into a vblank work item, queued here, but the
308 * infrastructure is not there yet.
311 if (HAS_PCH_IBX(connector
->dev
)) {
312 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
313 aud_config
= IBX_AUD_CFG(pipe
);
314 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
315 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
316 } else if (IS_VALLEYVIEW(connector
->dev
)) {
317 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
318 aud_config
= VLV_AUD_CFG(pipe
);
319 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
320 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
322 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
323 aud_config
= CPT_AUD_CFG(pipe
);
324 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
325 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
328 if (WARN_ON(!port
)) {
329 eldv
= IBX_ELD_VALID(PORT_B
) | IBX_ELD_VALID(PORT_C
) |
330 IBX_ELD_VALID(PORT_D
);
332 eldv
= IBX_ELD_VALID(port
);
336 tmp
= I915_READ(aud_cntrl_st2
);
338 I915_WRITE(aud_cntrl_st2
, tmp
);
340 /* Reset ELD write address */
341 tmp
= I915_READ(aud_cntl_st
);
342 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
343 I915_WRITE(aud_cntl_st
, tmp
);
345 /* Up to 84 bytes of hw ELD buffer */
346 len
= min_t(int, eld
[2], 21);
347 for (i
= 0; i
< len
; i
++)
348 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
351 tmp
= I915_READ(aud_cntrl_st2
);
353 I915_WRITE(aud_cntrl_st2
, tmp
);
355 /* Enable timestamps */
356 tmp
= I915_READ(aud_config
);
357 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
358 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
359 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
360 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
361 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
363 tmp
|= audio_config_hdmi_pixel_clock(mode
);
364 I915_WRITE(aud_config
, tmp
);
368 * intel_audio_codec_enable - Enable the audio codec for HD audio
369 * @intel_encoder: encoder on which to enable audio
371 * The enable sequences may only be performed after enabling the transcoder and
372 * port, and after completed link training.
374 void intel_audio_codec_enable(struct intel_encoder
*intel_encoder
)
376 struct drm_encoder
*encoder
= &intel_encoder
->base
;
377 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
378 struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
379 struct drm_connector
*connector
;
380 struct drm_device
*dev
= encoder
->dev
;
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 connector
= drm_select_eld(encoder
, mode
);
387 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
390 connector
->encoder
->base
.id
,
391 connector
->encoder
->name
);
394 connector
->eld
[5] &= ~(3 << 2);
395 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
396 connector
->eld
[5] |= (1 << 2);
398 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
400 if (dev_priv
->display
.audio_codec_enable
)
401 dev_priv
->display
.audio_codec_enable(connector
, intel_encoder
, mode
);
405 * intel_audio_codec_disable - Disable the audio codec for HD audio
406 * @encoder: encoder on which to disable audio
408 * The disable sequences must be performed before disabling the transcoder or
411 void intel_audio_codec_disable(struct intel_encoder
*encoder
)
413 struct drm_device
*dev
= encoder
->base
.dev
;
414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 if (dev_priv
->display
.audio_codec_disable
)
417 dev_priv
->display
.audio_codec_disable(encoder
);
421 * intel_init_audio - Set up chip specific audio functions
424 void intel_init_audio(struct drm_device
*dev
)
426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
429 dev_priv
->display
.audio_codec_enable
= g4x_audio_codec_enable
;
430 dev_priv
->display
.audio_codec_disable
= g4x_audio_codec_disable
;
431 } else if (IS_VALLEYVIEW(dev
)) {
432 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
433 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
434 } else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) {
435 dev_priv
->display
.audio_codec_enable
= hsw_audio_codec_enable
;
436 dev_priv
->display
.audio_codec_disable
= hsw_audio_codec_disable
;
437 } else if (HAS_PCH_SPLIT(dev
)) {
438 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
439 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;