2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
54 * The struct i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct i915_audio_component_ops *ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
63 } hdmi_audio_clock
[] = {
64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
76 /* HDMI N/CTS table */
77 #define TMDS_297M 297000
78 #define TMDS_296M 296703
85 { 44100, TMDS_296M
, 4459, 234375 },
86 { 44100, TMDS_297M
, 4704, 247500 },
87 { 48000, TMDS_296M
, 5824, 281250 },
88 { 48000, TMDS_297M
, 5120, 247500 },
89 { 32000, TMDS_296M
, 5824, 421875 },
90 { 32000, TMDS_297M
, 3072, 222750 },
91 { 88200, TMDS_296M
, 8918, 234375 },
92 { 88200, TMDS_297M
, 9408, 247500 },
93 { 96000, TMDS_296M
, 11648, 281250 },
94 { 96000, TMDS_297M
, 10240, 247500 },
95 { 176400, TMDS_296M
, 17836, 234375 },
96 { 176400, TMDS_297M
, 18816, 247500 },
97 { 192000, TMDS_296M
, 23296, 281250 },
98 { 192000, TMDS_297M
, 20480, 247500 },
101 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
102 static u32
audio_config_hdmi_pixel_clock(const struct drm_display_mode
*adjusted_mode
)
106 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
107 if (adjusted_mode
->crtc_clock
== hdmi_audio_clock
[i
].clock
)
111 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
112 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
113 adjusted_mode
->crtc_clock
);
117 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
118 hdmi_audio_clock
[i
].clock
,
119 hdmi_audio_clock
[i
].config
);
121 return hdmi_audio_clock
[i
].config
;
124 static int audio_config_get_n(const struct drm_display_mode
*mode
, int rate
)
128 for (i
= 0; i
< ARRAY_SIZE(aud_ncts
); i
++) {
129 if ((rate
== aud_ncts
[i
].sample_rate
) &&
130 (mode
->clock
== aud_ncts
[i
].clock
)) {
131 return aud_ncts
[i
].n
;
137 static uint32_t audio_config_setup_n_reg(int n
, uint32_t val
)
143 n_up
= (n
>> 12) & 0xff;
144 tmp
&= ~(AUD_CONFIG_UPPER_N_MASK
| AUD_CONFIG_LOWER_N_MASK
);
145 tmp
|= ((n_up
<< AUD_CONFIG_UPPER_N_SHIFT
) |
146 (n_low
<< AUD_CONFIG_LOWER_N_SHIFT
) |
147 AUD_CONFIG_N_PROG_ENABLE
);
151 /* check whether N/CTS/M need be set manually */
152 static bool audio_rate_need_prog(struct intel_crtc
*crtc
,
153 const struct drm_display_mode
*mode
)
155 if (((mode
->clock
== TMDS_297M
) ||
156 (mode
->clock
== TMDS_296M
)) &&
157 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
163 static bool intel_eld_uptodate(struct drm_connector
*connector
,
164 i915_reg_t reg_eldv
, uint32_t bits_eldv
,
165 i915_reg_t reg_elda
, uint32_t bits_elda
,
168 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
169 uint8_t *eld
= connector
->eld
;
173 tmp
= I915_READ(reg_eldv
);
179 tmp
= I915_READ(reg_elda
);
181 I915_WRITE(reg_elda
, tmp
);
183 for (i
= 0; i
< drm_eld_size(eld
) / 4; i
++)
184 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
190 static void g4x_audio_codec_disable(struct intel_encoder
*encoder
)
192 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
195 DRM_DEBUG_KMS("Disable audio codec\n");
197 tmp
= I915_READ(G4X_AUD_VID_DID
);
198 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
199 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
201 eldv
= G4X_ELDV_DEVCTG
;
204 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
206 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
209 static void g4x_audio_codec_enable(struct drm_connector
*connector
,
210 struct intel_encoder
*encoder
,
211 const struct drm_display_mode
*adjusted_mode
)
213 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
214 uint8_t *eld
= connector
->eld
;
219 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld
[2]);
221 tmp
= I915_READ(G4X_AUD_VID_DID
);
222 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
223 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
225 eldv
= G4X_ELDV_DEVCTG
;
227 if (intel_eld_uptodate(connector
,
228 G4X_AUD_CNTL_ST
, eldv
,
229 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR_MASK
,
233 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
234 tmp
&= ~(eldv
| G4X_ELD_ADDR_MASK
);
235 len
= (tmp
>> 9) & 0x1f; /* ELD buffer size */
236 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
238 len
= min(drm_eld_size(eld
) / 4, len
);
239 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
240 for (i
= 0; i
< len
; i
++)
241 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
243 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
245 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
248 static void hsw_audio_codec_disable(struct intel_encoder
*encoder
)
250 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
251 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
252 enum pipe pipe
= intel_crtc
->pipe
;
255 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe
));
257 mutex_lock(&dev_priv
->av_mutex
);
259 /* Disable timestamps */
260 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
261 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
262 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
263 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
264 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
265 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
266 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
267 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
270 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
271 tmp
&= ~AUDIO_ELD_VALID(pipe
);
272 tmp
&= ~AUDIO_OUTPUT_ENABLE(pipe
);
273 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
275 mutex_unlock(&dev_priv
->av_mutex
);
278 static void hsw_audio_codec_enable(struct drm_connector
*connector
,
279 struct intel_encoder
*encoder
,
280 const struct drm_display_mode
*adjusted_mode
)
282 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
283 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
284 enum pipe pipe
= intel_crtc
->pipe
;
285 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
286 const uint8_t *eld
= connector
->eld
;
287 struct intel_digital_port
*intel_dig_port
=
288 enc_to_dig_port(&encoder
->base
);
289 enum port port
= intel_dig_port
->port
;
294 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
295 pipe_name(pipe
), drm_eld_size(eld
));
297 mutex_lock(&dev_priv
->av_mutex
);
299 /* Enable audio presence detect, invalidate ELD */
300 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
301 tmp
|= AUDIO_OUTPUT_ENABLE(pipe
);
302 tmp
&= ~AUDIO_ELD_VALID(pipe
);
303 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
306 * FIXME: We're supposed to wait for vblank here, but we have vblanks
307 * disabled during the mode set. The proper fix would be to push the
308 * rest of the setup into a vblank work item, queued here, but the
309 * infrastructure is not there yet.
312 /* Reset ELD write address */
313 tmp
= I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe
));
314 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
315 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe
), tmp
);
317 /* Up to 84 bytes of hw ELD buffer */
318 len
= min(drm_eld_size(eld
), 84);
319 for (i
= 0; i
< len
/ 4; i
++)
320 I915_WRITE(HSW_AUD_EDID_DATA(pipe
), *((uint32_t *)eld
+ i
));
323 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
324 tmp
|= AUDIO_ELD_VALID(pipe
);
325 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
327 /* Enable timestamps */
328 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
329 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
330 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
331 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
332 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
334 tmp
|= audio_config_hdmi_pixel_clock(adjusted_mode
);
336 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
337 if (audio_rate_need_prog(intel_crtc
, adjusted_mode
)) {
340 else if (port
>= PORT_A
&& port
<= PORT_E
)
341 rate
= acomp
->aud_sample_rate
[port
];
343 DRM_ERROR("invalid port: %d\n", port
);
346 n
= audio_config_get_n(adjusted_mode
, rate
);
348 tmp
= audio_config_setup_n_reg(n
, tmp
);
350 DRM_DEBUG_KMS("no suitable N value is found\n");
353 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
355 mutex_unlock(&dev_priv
->av_mutex
);
358 static void ilk_audio_codec_disable(struct intel_encoder
*encoder
)
360 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
361 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
362 struct intel_digital_port
*intel_dig_port
=
363 enc_to_dig_port(&encoder
->base
);
364 enum port port
= intel_dig_port
->port
;
365 enum pipe pipe
= intel_crtc
->pipe
;
367 i915_reg_t aud_config
, aud_cntrl_st2
;
369 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
370 port_name(port
), pipe_name(pipe
));
372 if (WARN_ON(port
== PORT_A
))
375 if (HAS_PCH_IBX(dev_priv
->dev
)) {
376 aud_config
= IBX_AUD_CFG(pipe
);
377 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
378 } else if (IS_VALLEYVIEW(dev_priv
)) {
379 aud_config
= VLV_AUD_CFG(pipe
);
380 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
382 aud_config
= CPT_AUD_CFG(pipe
);
383 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
386 /* Disable timestamps */
387 tmp
= I915_READ(aud_config
);
388 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
389 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
390 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
391 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
392 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
393 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
394 I915_WRITE(aud_config
, tmp
);
396 eldv
= IBX_ELD_VALID(port
);
399 tmp
= I915_READ(aud_cntrl_st2
);
401 I915_WRITE(aud_cntrl_st2
, tmp
);
404 static void ilk_audio_codec_enable(struct drm_connector
*connector
,
405 struct intel_encoder
*encoder
,
406 const struct drm_display_mode
*adjusted_mode
)
408 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
409 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
410 struct intel_digital_port
*intel_dig_port
=
411 enc_to_dig_port(&encoder
->base
);
412 enum port port
= intel_dig_port
->port
;
413 enum pipe pipe
= intel_crtc
->pipe
;
414 uint8_t *eld
= connector
->eld
;
418 i915_reg_t hdmiw_hdmiedid
, aud_config
, aud_cntl_st
, aud_cntrl_st2
;
420 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
421 port_name(port
), pipe_name(pipe
), drm_eld_size(eld
));
423 if (WARN_ON(port
== PORT_A
))
427 * FIXME: We're supposed to wait for vblank here, but we have vblanks
428 * disabled during the mode set. The proper fix would be to push the
429 * rest of the setup into a vblank work item, queued here, but the
430 * infrastructure is not there yet.
433 if (HAS_PCH_IBX(connector
->dev
)) {
434 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
435 aud_config
= IBX_AUD_CFG(pipe
);
436 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
437 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
438 } else if (IS_VALLEYVIEW(connector
->dev
)) {
439 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
440 aud_config
= VLV_AUD_CFG(pipe
);
441 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
442 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
444 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
445 aud_config
= CPT_AUD_CFG(pipe
);
446 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
447 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
450 eldv
= IBX_ELD_VALID(port
);
453 tmp
= I915_READ(aud_cntrl_st2
);
455 I915_WRITE(aud_cntrl_st2
, tmp
);
457 /* Reset ELD write address */
458 tmp
= I915_READ(aud_cntl_st
);
459 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
460 I915_WRITE(aud_cntl_st
, tmp
);
462 /* Up to 84 bytes of hw ELD buffer */
463 len
= min(drm_eld_size(eld
), 84);
464 for (i
= 0; i
< len
/ 4; i
++)
465 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
468 tmp
= I915_READ(aud_cntrl_st2
);
470 I915_WRITE(aud_cntrl_st2
, tmp
);
472 /* Enable timestamps */
473 tmp
= I915_READ(aud_config
);
474 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
475 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
476 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
477 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
478 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
480 tmp
|= audio_config_hdmi_pixel_clock(adjusted_mode
);
481 I915_WRITE(aud_config
, tmp
);
485 * intel_audio_codec_enable - Enable the audio codec for HD audio
486 * @intel_encoder: encoder on which to enable audio
488 * The enable sequences may only be performed after enabling the transcoder and
489 * port, and after completed link training.
491 void intel_audio_codec_enable(struct intel_encoder
*intel_encoder
)
493 struct drm_encoder
*encoder
= &intel_encoder
->base
;
494 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
495 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
496 struct drm_connector
*connector
;
497 struct drm_device
*dev
= encoder
->dev
;
498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
499 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
500 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
501 enum port port
= intel_dig_port
->port
;
503 connector
= drm_select_eld(encoder
);
507 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
510 connector
->encoder
->base
.id
,
511 connector
->encoder
->name
);
514 connector
->eld
[5] &= ~(3 << 2);
515 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
516 connector
->eld
[5] |= (1 << 2);
518 connector
->eld
[6] = drm_av_sync_delay(connector
, adjusted_mode
) / 2;
520 if (dev_priv
->display
.audio_codec_enable
)
521 dev_priv
->display
.audio_codec_enable(connector
, intel_encoder
,
524 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
)
525 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
, (int) port
);
529 * intel_audio_codec_disable - Disable the audio codec for HD audio
530 * @intel_encoder: encoder on which to disable audio
532 * The disable sequences must be performed before disabling the transcoder or
535 void intel_audio_codec_disable(struct intel_encoder
*intel_encoder
)
537 struct drm_encoder
*encoder
= &intel_encoder
->base
;
538 struct drm_device
*dev
= encoder
->dev
;
539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
540 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
541 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
542 enum port port
= intel_dig_port
->port
;
544 if (dev_priv
->display
.audio_codec_disable
)
545 dev_priv
->display
.audio_codec_disable(intel_encoder
);
547 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
)
548 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
, (int) port
);
552 * intel_init_audio - Set up chip specific audio functions
555 void intel_init_audio(struct drm_device
*dev
)
557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
560 dev_priv
->display
.audio_codec_enable
= g4x_audio_codec_enable
;
561 dev_priv
->display
.audio_codec_disable
= g4x_audio_codec_disable
;
562 } else if (IS_VALLEYVIEW(dev
)) {
563 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
564 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
565 } else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) {
566 dev_priv
->display
.audio_codec_enable
= hsw_audio_codec_enable
;
567 dev_priv
->display
.audio_codec_disable
= hsw_audio_codec_disable
;
568 } else if (HAS_PCH_SPLIT(dev
)) {
569 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
570 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
574 static void i915_audio_component_get_power(struct device
*dev
)
576 intel_display_power_get(dev_to_i915(dev
), POWER_DOMAIN_AUDIO
);
579 static void i915_audio_component_put_power(struct device
*dev
)
581 intel_display_power_put(dev_to_i915(dev
), POWER_DOMAIN_AUDIO
);
584 static void i915_audio_component_codec_wake_override(struct device
*dev
,
587 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
590 if (!IS_SKYLAKE(dev_priv
) && !IS_KABYLAKE(dev_priv
))
594 * Enable/disable generating the codec wake signal, overriding the
595 * internal logic to generate the codec wake to controller.
597 tmp
= I915_READ(HSW_AUD_CHICKENBIT
);
598 tmp
&= ~SKL_AUD_CODEC_WAKE_SIGNAL
;
599 I915_WRITE(HSW_AUD_CHICKENBIT
, tmp
);
600 usleep_range(1000, 1500);
603 tmp
= I915_READ(HSW_AUD_CHICKENBIT
);
604 tmp
|= SKL_AUD_CODEC_WAKE_SIGNAL
;
605 I915_WRITE(HSW_AUD_CHICKENBIT
, tmp
);
606 usleep_range(1000, 1500);
610 /* Get CDCLK in kHz */
611 static int i915_audio_component_get_cdclk_freq(struct device
*dev
)
613 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
616 if (WARN_ON_ONCE(!HAS_DDI(dev_priv
)))
619 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
620 ret
= dev_priv
->display
.get_display_clock_speed(dev_priv
->dev
);
622 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
627 static int i915_audio_component_sync_audio_rate(struct device
*dev
,
630 struct drm_i915_private
*dev_priv
= dev_to_i915(dev
);
631 struct drm_device
*drm_dev
= dev_priv
->dev
;
632 struct intel_encoder
*intel_encoder
;
633 struct intel_digital_port
*intel_dig_port
;
634 struct intel_crtc
*crtc
;
635 struct drm_display_mode
*mode
;
636 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
641 /* HSW, BDW, SKL, KBL need this fix */
642 if (!IS_SKYLAKE(dev_priv
) &&
643 !IS_KABYLAKE(dev_priv
) &&
644 !IS_BROADWELL(dev_priv
) &&
645 !IS_HASWELL(dev_priv
))
648 mutex_lock(&dev_priv
->av_mutex
);
649 /* 1. get the pipe */
650 for_each_intel_encoder(drm_dev
, intel_encoder
) {
651 if (intel_encoder
->type
!= INTEL_OUTPUT_HDMI
)
653 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
654 if (port
== intel_dig_port
->port
) {
655 crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
657 DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__
);
665 if (pipe
== INVALID_PIPE
) {
666 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port
));
667 mutex_unlock(&dev_priv
->av_mutex
);
670 DRM_DEBUG_KMS("pipe %c connects port %c\n",
671 pipe_name(pipe
), port_name(port
));
672 mode
= &crtc
->config
->base
.adjusted_mode
;
674 /* port must be valid now, otherwise the pipe will be invalid */
675 acomp
->aud_sample_rate
[port
] = rate
;
677 /* 2. check whether to set the N/CTS/M manually or not */
678 if (!audio_rate_need_prog(crtc
, mode
)) {
679 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
680 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
681 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
682 mutex_unlock(&dev_priv
->av_mutex
);
686 n
= audio_config_get_n(mode
, rate
);
688 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
690 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
691 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
692 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
693 mutex_unlock(&dev_priv
->av_mutex
);
697 /* 3. set the N/CTS/M */
698 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
699 tmp
= audio_config_setup_n_reg(n
, tmp
);
700 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
702 mutex_unlock(&dev_priv
->av_mutex
);
706 static const struct i915_audio_component_ops i915_audio_component_ops
= {
707 .owner
= THIS_MODULE
,
708 .get_power
= i915_audio_component_get_power
,
709 .put_power
= i915_audio_component_put_power
,
710 .codec_wake_override
= i915_audio_component_codec_wake_override
,
711 .get_cdclk_freq
= i915_audio_component_get_cdclk_freq
,
712 .sync_audio_rate
= i915_audio_component_sync_audio_rate
,
715 static int i915_audio_component_bind(struct device
*i915_dev
,
716 struct device
*hda_dev
, void *data
)
718 struct i915_audio_component
*acomp
= data
;
719 struct drm_i915_private
*dev_priv
= dev_to_i915(i915_dev
);
722 if (WARN_ON(acomp
->ops
|| acomp
->dev
))
725 drm_modeset_lock_all(dev_priv
->dev
);
726 acomp
->ops
= &i915_audio_component_ops
;
727 acomp
->dev
= i915_dev
;
728 BUILD_BUG_ON(MAX_PORTS
!= I915_MAX_PORTS
);
729 for (i
= 0; i
< ARRAY_SIZE(acomp
->aud_sample_rate
); i
++)
730 acomp
->aud_sample_rate
[i
] = 0;
731 dev_priv
->audio_component
= acomp
;
732 drm_modeset_unlock_all(dev_priv
->dev
);
737 static void i915_audio_component_unbind(struct device
*i915_dev
,
738 struct device
*hda_dev
, void *data
)
740 struct i915_audio_component
*acomp
= data
;
741 struct drm_i915_private
*dev_priv
= dev_to_i915(i915_dev
);
743 drm_modeset_lock_all(dev_priv
->dev
);
746 dev_priv
->audio_component
= NULL
;
747 drm_modeset_unlock_all(dev_priv
->dev
);
750 static const struct component_ops i915_audio_component_bind_ops
= {
751 .bind
= i915_audio_component_bind
,
752 .unbind
= i915_audio_component_unbind
,
756 * i915_audio_component_init - initialize and register the audio component
757 * @dev_priv: i915 device instance
759 * This will register with the component framework a child component which
760 * will bind dynamically to the snd_hda_intel driver's corresponding master
761 * component when the latter is registered. During binding the child
762 * initializes an instance of struct i915_audio_component which it receives
763 * from the master. The master can then start to use the interface defined by
764 * this struct. Each side can break the binding at any point by deregistering
765 * its own component after which each side's component unbind callback is
768 * We ignore any error during registration and continue with reduced
769 * functionality (i.e. without HDMI audio).
771 void i915_audio_component_init(struct drm_i915_private
*dev_priv
)
775 ret
= component_add(dev_priv
->dev
->dev
, &i915_audio_component_bind_ops
);
777 DRM_ERROR("failed to add audio component (%d)\n", ret
);
778 /* continue with reduced functionality */
782 dev_priv
->audio_component_registered
= true;
786 * i915_audio_component_cleanup - deregister the audio component
787 * @dev_priv: i915 device instance
789 * Deregisters the audio component, breaking any existing binding to the
790 * corresponding snd_hda_intel driver's master component.
792 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
)
794 if (!dev_priv
->audio_component_registered
)
797 component_del(dev_priv
->dev
->dev
, &i915_audio_component_bind_ops
);
798 dev_priv
->audio_component_registered
= false;