drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/component.h>
  26 #include <drm/i915_component.h>
  27 #include "intel_drv.h"
  28
  29 #include <drm/drmP.h>
  30 #include <drm/drm_edid.h>
  31 #include "i915_drv.h"
  32
  33 /**
  34  * DOC: High Definition Audio over HDMI and Display Port
  35  *
  36  * The graphics and audio drivers together support High Definition Audio over
  37  * HDMI and Display Port. The audio programming sequences are divided into audio
  38  * codec and controller enable and disable sequences. The graphics driver
  39  * handles the audio codec sequences, while the audio driver handles the audio
  40  * controller sequences.
  41  *
  42  * The disable sequences must be performed before disabling the transcoder or
  43  * port. The enable sequences may only be performed after enabling the
  44  * transcoder and port, and after completed link training. Therefore the audio
  45  * enable/disable sequences are part of the modeset sequence.
  46  *
  47  * The codec and controller sequences could be done either parallel or serial,
  48  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  49  * driver that the controller sequence should start. Indeed, most of the
  50  * co-operation between the graphics and audio drivers is handled via audio
  51  * related registers. (The notable exception is the power management, not
  52  * covered here.)
  53  */
  54
  55 static const struct {
  56         int clock;
  57         u32 config;
  58 } hdmi_audio_clock[] = {
  59         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  60         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  61         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  62         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  63         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  64         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  65         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  66         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  67         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  68         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  69 };
  70
  71 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
  72 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
  73 {
  74         int i;
  75
  76         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
  77                 if (mode->clock == hdmi_audio_clock[i].clock)
  78                         break;
  79         }
  80
  81         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
  82                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
  83                 i = 1;
  84         }
  85
  86         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
  87                       hdmi_audio_clock[i].clock,
  88                       hdmi_audio_clock[i].config);
  89
  90         return hdmi_audio_clock[i].config;
  91 }
  92
  93 static bool intel_eld_uptodate(struct drm_connector *connector,
  94                                int reg_eldv, uint32_t bits_eldv,
  95                                int reg_elda, uint32_t bits_elda,
  96                                int reg_edid)
  97 {
  98         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  99         uint8_t *eld = connector->eld;
 100         uint32_t tmp;
 101         int i;
 102
 103         tmp = I915_READ(reg_eldv);
 104         tmp &= bits_eldv;
 105
 106         if (!tmp)
 107                 return false;
 108
 109         tmp = I915_READ(reg_elda);
 110         tmp &= ~bits_elda;
 111         I915_WRITE(reg_elda, tmp);
 112
 113         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 114                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
 115                         return false;
 116
 117         return true;
 118 }
 119
 120 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
 121 {
 122         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 123         uint32_t eldv, tmp;
 124
 125         DRM_DEBUG_KMS("Disable audio codec\n");
 126
 127         tmp = I915_READ(G4X_AUD_VID_DID);
 128         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 129                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 130         else
 131                 eldv = G4X_ELDV_DEVCTG;
 132
 133         /* Invalidate ELD */
 134         tmp = I915_READ(G4X_AUD_CNTL_ST);
 135         tmp &= ~eldv;
 136         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 137 }
 138
 139 static void g4x_audio_codec_enable(struct drm_connector *connector,
 140                                    struct intel_encoder *encoder,
 141                                    struct drm_display_mode *mode)
 142 {
 143         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 144         uint8_t *eld = connector->eld;
 145         uint32_t eldv;
 146         uint32_t tmp;
 147         int len, i;
 148
 149         DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
 150
 151         tmp = I915_READ(G4X_AUD_VID_DID);
 152         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 153                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 154         else
 155                 eldv = G4X_ELDV_DEVCTG;
 156
 157         if (intel_eld_uptodate(connector,
 158                                G4X_AUD_CNTL_ST, eldv,
 159                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 160                                G4X_HDMIW_HDMIEDID))
 161                 return;
 162
 163         tmp = I915_READ(G4X_AUD_CNTL_ST);
 164         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 165         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 166         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 167
 168         len = min(drm_eld_size(eld) / 4, len);
 169         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 170         for (i = 0; i < len; i++)
 171                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 172
 173         tmp = I915_READ(G4X_AUD_CNTL_ST);
 174         tmp |= eldv;
 175         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 176 }
 177
 178 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
 179 {
 180         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 181         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 182         enum pipe pipe = intel_crtc->pipe;
 183         uint32_t tmp;
 184
 185         DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
 186
 187         /* Disable timestamps */
 188         tmp = I915_READ(HSW_AUD_CFG(pipe));
 189         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 190         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 191         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 192         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 193         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 194                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 195         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 196
 197         /* Invalidate ELD */
 198         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 199         tmp &= ~AUDIO_ELD_VALID(pipe);
 200         tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
 201         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 202 }
 203
 204 static void hsw_audio_codec_enable(struct drm_connector *connector,
 205                                    struct intel_encoder *encoder,
 206                                    struct drm_display_mode *mode)
 207 {
 208         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 209         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 210         enum pipe pipe = intel_crtc->pipe;
 211         const uint8_t *eld = connector->eld;
 212         uint32_t tmp;
 213         int len, i;
 214
 215         DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
 216                       pipe_name(pipe), drm_eld_size(eld));
 217
 218         /* Enable audio presence detect, invalidate ELD */
 219         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 220         tmp |= AUDIO_OUTPUT_ENABLE(pipe);
 221         tmp &= ~AUDIO_ELD_VALID(pipe);
 222         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 223
 224         /*
 225          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 226          * disabled during the mode set. The proper fix would be to push the
 227          * rest of the setup into a vblank work item, queued here, but the
 228          * infrastructure is not there yet.
 229          */
 230
 231         /* Reset ELD write address */
 232         tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
 233         tmp &= ~IBX_ELD_ADDRESS_MASK;
 234         I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
 235
 236         /* Up to 84 bytes of hw ELD buffer */
 237         len = min(drm_eld_size(eld), 84);
 238         for (i = 0; i < len / 4; i++)
 239                 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
 240
 241         /* ELD valid */
 242         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 243         tmp |= AUDIO_ELD_VALID(pipe);
 244         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 245
 246         /* Enable timestamps */
 247         tmp = I915_READ(HSW_AUD_CFG(pipe));
 248         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 249         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 250         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 251         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 252                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 253         else
 254                 tmp |= audio_config_hdmi_pixel_clock(mode);
 255         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 256 }
 257
 258 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 259 {
 260         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 261         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 262         struct intel_digital_port *intel_dig_port =
 263                 enc_to_dig_port(&encoder->base);
 264         enum port port = intel_dig_port->port;
 265         enum pipe pipe = intel_crtc->pipe;
 266         uint32_t tmp, eldv;
 267         int aud_config;
 268         int aud_cntrl_st2;
 269
 270         DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
 271                       port_name(port), pipe_name(pipe));
 272
 273         if (WARN_ON(port == PORT_A))
 274                 return;
 275
 276         if (HAS_PCH_IBX(dev_priv->dev)) {
 277                 aud_config = IBX_AUD_CFG(pipe);
 278                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 279         } else if (IS_VALLEYVIEW(dev_priv)) {
 280                 aud_config = VLV_AUD_CFG(pipe);
 281                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 282         } else {
 283                 aud_config = CPT_AUD_CFG(pipe);
 284                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 285         }
 286
 287         /* Disable timestamps */
 288         tmp = I915_READ(aud_config);
 289         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 290         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 291         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 292         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 293         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 294                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 295         I915_WRITE(aud_config, tmp);
 296
 297         eldv = IBX_ELD_VALID(port);
 298
 299         /* Invalidate ELD */
 300         tmp = I915_READ(aud_cntrl_st2);
 301         tmp &= ~eldv;
 302         I915_WRITE(aud_cntrl_st2, tmp);
 303 }
 304
 305 static void ilk_audio_codec_enable(struct drm_connector *connector,
 306                                    struct intel_encoder *encoder,
 307                                    struct drm_display_mode *mode)
 308 {
 309         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 310         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 311         struct intel_digital_port *intel_dig_port =
 312                 enc_to_dig_port(&encoder->base);
 313         enum port port = intel_dig_port->port;
 314         enum pipe pipe = intel_crtc->pipe;
 315         uint8_t *eld = connector->eld;
 316         uint32_t eldv;
 317         uint32_t tmp;
 318         int len, i;
 319         int hdmiw_hdmiedid;
 320         int aud_config;
 321         int aud_cntl_st;
 322         int aud_cntrl_st2;
 323
 324         DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
 325                       port_name(port), pipe_name(pipe), drm_eld_size(eld));
 326
 327         if (WARN_ON(port == PORT_A))
 328                 return;
 329
 330         /*
 331          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 332          * disabled during the mode set. The proper fix would be to push the
 333          * rest of the setup into a vblank work item, queued here, but the
 334          * infrastructure is not there yet.
 335          */
 336
 337         if (HAS_PCH_IBX(connector->dev)) {
 338                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 339                 aud_config = IBX_AUD_CFG(pipe);
 340                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 341                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 342         } else if (IS_VALLEYVIEW(connector->dev)) {
 343                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 344                 aud_config = VLV_AUD_CFG(pipe);
 345                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 346                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 347         } else {
 348                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 349                 aud_config = CPT_AUD_CFG(pipe);
 350                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 351                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 352         }
 353
 354         eldv = IBX_ELD_VALID(port);
 355
 356         /* Invalidate ELD */
 357         tmp = I915_READ(aud_cntrl_st2);
 358         tmp &= ~eldv;
 359         I915_WRITE(aud_cntrl_st2, tmp);
 360
 361         /* Reset ELD write address */
 362         tmp = I915_READ(aud_cntl_st);
 363         tmp &= ~IBX_ELD_ADDRESS_MASK;
 364         I915_WRITE(aud_cntl_st, tmp);
 365
 366         /* Up to 84 bytes of hw ELD buffer */
 367         len = min(drm_eld_size(eld), 84);
 368         for (i = 0; i < len / 4; i++)
 369                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 370
 371         /* ELD valid */
 372         tmp = I915_READ(aud_cntrl_st2);
 373         tmp |= eldv;
 374         I915_WRITE(aud_cntrl_st2, tmp);
 375
 376         /* Enable timestamps */
 377         tmp = I915_READ(aud_config);
 378         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 379         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 380         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 381         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 382                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 383         else
 384                 tmp |= audio_config_hdmi_pixel_clock(mode);
 385         I915_WRITE(aud_config, tmp);
 386 }
 387
 388 /**
 389  * intel_audio_codec_enable - Enable the audio codec for HD audio
 390  * @intel_encoder: encoder on which to enable audio
 391  *
 392  * The enable sequences may only be performed after enabling the transcoder and
 393  * port, and after completed link training.
 394  */
 395 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 396 {
 397         struct drm_encoder *encoder = &intel_encoder->base;
 398         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 399         struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
 400         struct drm_connector *connector;
 401         struct drm_device *dev = encoder->dev;
 402         struct drm_i915_private *dev_priv = dev->dev_private;
 403         struct i915_audio_component *acomp = dev_priv->audio_component;
 404         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 405         enum port port = intel_dig_port->port;
 406
 407         connector = drm_select_eld(encoder, mode);
 408         if (!connector)
 409                 return;
 410
 411         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 412                          connector->base.id,
 413                          connector->name,
 414                          connector->encoder->base.id,
 415                          connector->encoder->name);
 416
 417         /* ELD Conn_Type */
 418         connector->eld[5] &= ~(3 << 2);
 419         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 420                 connector->eld[5] |= (1 << 2);
 421
 422         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
 423
 424         if (dev_priv->display.audio_codec_enable)
 425                 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
 426
 427         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 428                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
 429 }
 430
 431 /**
 432  * intel_audio_codec_disable - Disable the audio codec for HD audio
 433  * @encoder: encoder on which to disable audio
 434  *
 435  * The disable sequences must be performed before disabling the transcoder or
 436  * port.
 437  */
 438 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 439 {
 440         struct drm_encoder *encoder = &intel_encoder->base;
 441         struct drm_device *dev = encoder->dev;
 442         struct drm_i915_private *dev_priv = dev->dev_private;
 443         struct i915_audio_component *acomp = dev_priv->audio_component;
 444         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 445         enum port port = intel_dig_port->port;
 446
 447         if (dev_priv->display.audio_codec_disable)
 448                 dev_priv->display.audio_codec_disable(intel_encoder);
 449
 450         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 451                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
 452 }
 453
 454 /**
 455  * intel_init_audio - Set up chip specific audio functions
 456  * @dev: drm device
 457  */
 458 void intel_init_audio(struct drm_device *dev)
 459 {
 460         struct drm_i915_private *dev_priv = dev->dev_private;
 461
 462         if (IS_G4X(dev)) {
 463                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 464                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 465         } else if (IS_VALLEYVIEW(dev)) {
 466                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 467                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 468         } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
 469                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 470                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 471         } else if (HAS_PCH_SPLIT(dev)) {
 472                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 473                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 474         }
 475 }
 476
 477 static void i915_audio_component_get_power(struct device *dev)
 478 {
 479         intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 480 }
 481
 482 static void i915_audio_component_put_power(struct device *dev)
 483 {
 484         intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 485 }
 486
 487 static void i915_audio_component_codec_wake_override(struct device *dev,
 488                                                      bool enable)
 489 {
 490         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 491         u32 tmp;
 492
 493         if (!IS_SKYLAKE(dev_priv))
 494                 return;
 495
 496         /*
 497          * Enable/disable generating the codec wake signal, overriding the
 498          * internal logic to generate the codec wake to controller.
 499          */
 500         tmp = I915_READ(HSW_AUD_CHICKENBIT);
 501         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
 502         I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 503         usleep_range(1000, 1500);
 504
 505         if (enable) {
 506                 tmp = I915_READ(HSW_AUD_CHICKENBIT);
 507                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
 508                 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 509                 usleep_range(1000, 1500);
 510         }
 511 }
 512
 513 /* Get CDCLK in kHz  */
 514 static int i915_audio_component_get_cdclk_freq(struct device *dev)
 515 {
 516         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 517         int ret;
 518
 519         if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
 520                 return -ENODEV;
 521
 522         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
 523         ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
 524
 525         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
 526
 527         return ret;
 528 }
 529
 530 static const struct i915_audio_component_ops i915_audio_component_ops = {
 531         .owner          = THIS_MODULE,
 532         .get_power      = i915_audio_component_get_power,
 533         .put_power      = i915_audio_component_put_power,
 534         .codec_wake_override = i915_audio_component_codec_wake_override,
 535         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
 536 };
 537
 538 static int i915_audio_component_bind(struct device *i915_dev,
 539                                      struct device *hda_dev, void *data)
 540 {
 541         struct i915_audio_component *acomp = data;
 542         struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
 543
 544         if (WARN_ON(acomp->ops || acomp->dev))
 545                 return -EEXIST;
 546
 547         drm_modeset_lock_all(dev_priv->dev);
 548         acomp->ops = &i915_audio_component_ops;
 549         acomp->dev = i915_dev;
 550         dev_priv->audio_component = acomp;
 551         drm_modeset_unlock_all(dev_priv->dev);
 552
 553         return 0;
 554 }
 555
 556 static void i915_audio_component_unbind(struct device *i915_dev,
 557                                         struct device *hda_dev, void *data)
 558 {
 559         struct i915_audio_component *acomp = data;
 560         struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
 561
 562         drm_modeset_lock_all(dev_priv->dev);
 563         acomp->ops = NULL;
 564         acomp->dev = NULL;
 565         dev_priv->audio_component = NULL;
 566         drm_modeset_unlock_all(dev_priv->dev);
 567 }
 568
 569 static const struct component_ops i915_audio_component_bind_ops = {
 570         .bind   = i915_audio_component_bind,
 571         .unbind = i915_audio_component_unbind,
 572 };
 573
 574 /**
 575  * i915_audio_component_init - initialize and register the audio component
 576  * @dev_priv: i915 device instance
 577  *
 578  * This will register with the component framework a child component which
 579  * will bind dynamically to the snd_hda_intel driver's corresponding master
 580  * component when the latter is registered. During binding the child
 581  * initializes an instance of struct i915_audio_component which it receives
 582  * from the master. The master can then start to use the interface defined by
 583  * this struct. Each side can break the binding at any point by deregistering
 584  * its own component after which each side's component unbind callback is
 585  * called.
 586  *
 587  * We ignore any error during registration and continue with reduced
 588  * functionality (i.e. without HDMI audio).
 589  */
 590 void i915_audio_component_init(struct drm_i915_private *dev_priv)
 591 {
 592         int ret;
 593
 594         ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
 595         if (ret < 0) {
 596                 DRM_ERROR("failed to add audio component (%d)\n", ret);
 597                 /* continue with reduced functionality */
 598                 return;
 599         }
 600
 601         dev_priv->audio_component_registered = true;
 602 }
 603
 604 /**
 605  * i915_audio_component_cleanup - deregister the audio component
 606  * @dev_priv: i915 device instance
 607  *
 608  * Deregisters the audio component, breaking any existing binding to the
 609  * corresponding snd_hda_intel driver's master component.
 610  */
 611 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
 612 {
 613         if (!dev_priv->audio_component_registered)
 614                 return;
 615
 616         component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
 617         dev_priv->audio_component_registered = false;
 618 }