drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include "intel_drv.h"
  29 #include "i915_drv.h"
  30
  31 static const struct {
  32         int clock;
  33         u32 config;
  34 } hdmi_audio_clock[] = {
  35         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  36         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  37         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  38         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  39         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  40         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  41         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  42         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  43         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  44         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  45 };
  46
  47 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
  48 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
  49 {
  50         int i;
  51
  52         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
  53                 if (mode->clock == hdmi_audio_clock[i].clock)
  54                         break;
  55         }
  56
  57         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
  58                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
  59                 i = 1;
  60         }
  61
  62         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
  63                       hdmi_audio_clock[i].clock,
  64                       hdmi_audio_clock[i].config);
  65
  66         return hdmi_audio_clock[i].config;
  67 }
  68
  69 static bool intel_eld_uptodate(struct drm_connector *connector,
  70                                int reg_eldv, uint32_t bits_eldv,
  71                                int reg_elda, uint32_t bits_elda,
  72                                int reg_edid)
  73 {
  74         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  75         uint8_t *eld = connector->eld;
  76         uint32_t tmp;
  77         int i;
  78
  79         tmp = I915_READ(reg_eldv);
  80         tmp &= bits_eldv;
  81
  82         if (!tmp)
  83                 return false;
  84
  85         tmp = I915_READ(reg_elda);
  86         tmp &= ~bits_elda;
  87         I915_WRITE(reg_elda, tmp);
  88
  89         for (i = 0; i < eld[2]; i++)
  90                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  91                         return false;
  92
  93         return true;
  94 }
  95
  96 static void g4x_audio_codec_enable(struct drm_connector *connector,
  97                                    struct intel_encoder *encoder,
  98                                    struct drm_display_mode *mode)
  99 {
 100         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 101         uint8_t *eld = connector->eld;
 102         uint32_t eldv;
 103         uint32_t tmp;
 104         int len, i;
 105
 106         tmp = I915_READ(G4X_AUD_VID_DID);
 107         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 108                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 109         else
 110                 eldv = G4X_ELDV_DEVCTG;
 111
 112         if (intel_eld_uptodate(connector,
 113                                G4X_AUD_CNTL_ST, eldv,
 114                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 115                                G4X_HDMIW_HDMIEDID))
 116                 return;
 117
 118         tmp = I915_READ(G4X_AUD_CNTL_ST);
 119         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 120         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 121         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 122
 123         len = min_t(int, eld[2], len);
 124         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 125         for (i = 0; i < len; i++)
 126                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 127
 128         tmp = I915_READ(G4X_AUD_CNTL_ST);
 129         tmp |= eldv;
 130         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 131 }
 132
 133 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
 134 {
 135         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 136         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 137         enum pipe pipe = intel_crtc->pipe;
 138         uint32_t tmp;
 139
 140         DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
 141
 142         /* Disable timestamps */
 143         tmp = I915_READ(HSW_AUD_CFG(pipe));
 144         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 145         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 146         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 147         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 148         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 149                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 150         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 151
 152         /* Invalidate ELD */
 153         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 154         tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
 155         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 156 }
 157
 158 static void hsw_audio_codec_enable(struct drm_connector *connector,
 159                                    struct intel_encoder *encoder,
 160                                    struct drm_display_mode *mode)
 161 {
 162         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 163         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 164         enum pipe pipe = intel_crtc->pipe;
 165         const uint8_t *eld = connector->eld;
 166         uint32_t tmp;
 167         int len, i;
 168
 169         DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
 170                       pipe_name(pipe), eld[2]);
 171
 172         /* Enable audio presence detect, invalidate ELD */
 173         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 174         tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
 175         tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
 176         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 177
 178         /*
 179          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 180          * disabled during the mode set. The proper fix would be to push the
 181          * rest of the setup into a vblank work item, queued here, but the
 182          * infrastructure is not there yet.
 183          */
 184
 185         /* Reset ELD write address */
 186         tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
 187         tmp &= ~IBX_ELD_ADDRESS_MASK;
 188         I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
 189
 190         /* Up to 84 bytes of hw ELD buffer */
 191         len = min_t(int, eld[2], 21);
 192         for (i = 0; i < len; i++)
 193                 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
 194
 195         /* ELD valid */
 196         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 197         tmp |= AUDIO_ELD_VALID_A << (pipe * 4);
 198         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 199
 200         /* Enable timestamps */
 201         tmp = I915_READ(HSW_AUD_CFG(pipe));
 202         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 203         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 204         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 205         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 206                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 207         else
 208                 tmp |= audio_config_hdmi_pixel_clock(mode);
 209         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 210 }
 211
 212 static void ilk_audio_codec_enable(struct drm_connector *connector,
 213                                    struct intel_encoder *encoder,
 214                                    struct drm_display_mode *mode)
 215 {
 216         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 217         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 218         uint8_t *eld = connector->eld;
 219         uint32_t eldv;
 220         uint32_t tmp;
 221         int len, i;
 222         int hdmiw_hdmiedid;
 223         int aud_config;
 224         int aud_cntl_st;
 225         int aud_cntrl_st2;
 226         enum pipe pipe = intel_crtc->pipe;
 227         enum port port;
 228
 229         if (HAS_PCH_IBX(connector->dev)) {
 230                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 231                 aud_config = IBX_AUD_CFG(pipe);
 232                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 233                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 234         } else if (IS_VALLEYVIEW(connector->dev)) {
 235                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 236                 aud_config = VLV_AUD_CFG(pipe);
 237                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 238                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 239         } else {
 240                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 241                 aud_config = CPT_AUD_CFG(pipe);
 242                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 243                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 244         }
 245
 246         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 247
 248         if (IS_VALLEYVIEW(connector->dev))  {
 249                 struct intel_digital_port *intel_dig_port;
 250
 251                 intel_dig_port = enc_to_dig_port(&encoder->base);
 252                 port = intel_dig_port->port;
 253         } else {
 254                 tmp = I915_READ(aud_cntl_st);
 255                 port = (tmp >> 29) & DIP_PORT_SEL_MASK;
 256                 /* DIP_Port_Select, 0x1 = PortB */
 257         }
 258
 259         if (!port) {
 260                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 261                 /* operate blindly on all ports */
 262                 eldv = IBX_ELD_VALIDB;
 263                 eldv |= IBX_ELD_VALIDB << 4;
 264                 eldv |= IBX_ELD_VALIDB << 8;
 265         } else {
 266                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(port));
 267                 eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
 268         }
 269
 270         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 271                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 272         else
 273                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 274
 275         if (intel_eld_uptodate(connector,
 276                                aud_cntrl_st2, eldv,
 277                                aud_cntl_st, IBX_ELD_ADDRESS_MASK,
 278                                hdmiw_hdmiedid))
 279                 return;
 280
 281         tmp = I915_READ(aud_cntrl_st2);
 282         tmp &= ~eldv;
 283         I915_WRITE(aud_cntrl_st2, tmp);
 284
 285         tmp = I915_READ(aud_cntl_st);
 286         tmp &= ~IBX_ELD_ADDRESS_MASK;
 287         I915_WRITE(aud_cntl_st, tmp);
 288
 289         len = min_t(int, eld[2], 21);   /* 84 bytes of hw ELD buffer */
 290         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 291         for (i = 0; i < len; i++)
 292                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 293
 294         tmp = I915_READ(aud_cntrl_st2);
 295         tmp |= eldv;
 296         I915_WRITE(aud_cntrl_st2, tmp);
 297 }
 298
 299 /**
 300  * intel_audio_codec_enable - Enable the audio codec for HD audio
 301  * @intel_encoder: encoder on which to enable audio
 302  *
 303  * The enable sequences may only be performed after enabling the transcoder and
 304  * port, and after completed link training.
 305  */
 306 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 307 {
 308         struct drm_encoder *encoder = &intel_encoder->base;
 309         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 310         struct drm_display_mode *mode = &crtc->config.adjusted_mode;
 311         struct drm_connector *connector;
 312         struct drm_device *dev = encoder->dev;
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         connector = drm_select_eld(encoder, mode);
 316         if (!connector)
 317                 return;
 318
 319         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 320                          connector->base.id,
 321                          connector->name,
 322                          connector->encoder->base.id,
 323                          connector->encoder->name);
 324
 325         /* ELD Conn_Type */
 326         connector->eld[5] &= ~(3 << 2);
 327         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 328                 connector->eld[5] |= (1 << 2);
 329
 330         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
 331
 332         if (dev_priv->display.audio_codec_enable)
 333                 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
 334 }
 335
 336 /**
 337  * intel_audio_codec_disable - Disable the audio codec for HD audio
 338  * @encoder: encoder on which to disable audio
 339  *
 340  * The disable sequences must be performed before disabling the transcoder or
 341  * port.
 342  */
 343 void intel_audio_codec_disable(struct intel_encoder *encoder)
 344 {
 345         struct drm_device *dev = encoder->base.dev;
 346         struct drm_i915_private *dev_priv = dev->dev_private;
 347
 348         if (dev_priv->display.audio_codec_disable)
 349                 dev_priv->display.audio_codec_disable(encoder);
 350 }
 351
 352 /**
 353  * intel_init_audio - Set up chip specific audio functions
 354  * @dev: drm device
 355  */
 356 void intel_init_audio(struct drm_device *dev)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359
 360         if (IS_G4X(dev)) {
 361                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 362         } else if (IS_VALLEYVIEW(dev)) {
 363                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 364         } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
 365                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 366                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 367         } else if (HAS_PCH_SPLIT(dev)) {
 368                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 369         }
 370 }