2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
27 #include <drm/drm_edid.h>
28 #include "intel_drv.h"
34 } hdmi_audio_clock
[] = {
35 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
36 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
37 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
38 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
39 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
40 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
41 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
42 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
43 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
44 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
47 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
48 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
52 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
53 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
57 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
58 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
62 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
63 hdmi_audio_clock
[i
].clock
,
64 hdmi_audio_clock
[i
].config
);
66 return hdmi_audio_clock
[i
].config
;
69 static bool intel_eld_uptodate(struct drm_connector
*connector
,
70 int reg_eldv
, uint32_t bits_eldv
,
71 int reg_elda
, uint32_t bits_elda
,
74 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
75 uint8_t *eld
= connector
->eld
;
79 tmp
= I915_READ(reg_eldv
);
88 tmp
= I915_READ(reg_elda
);
90 I915_WRITE(reg_elda
, tmp
);
92 for (i
= 0; i
< eld
[2]; i
++)
93 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
99 static void g4x_audio_codec_enable(struct drm_connector
*connector
,
100 struct intel_encoder
*encoder
,
101 struct drm_display_mode
*mode
)
103 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
104 uint8_t *eld
= connector
->eld
;
109 tmp
= I915_READ(G4X_AUD_VID_DID
);
110 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
111 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
113 eldv
= G4X_ELDV_DEVCTG
;
115 if (intel_eld_uptodate(connector
,
116 G4X_AUD_CNTL_ST
, eldv
,
117 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
121 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
122 tmp
&= ~(eldv
| G4X_ELD_ADDR
);
123 len
= (tmp
>> 9) & 0x1f; /* ELD buffer size */
124 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
129 len
= min_t(int, eld
[2], len
);
130 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
131 for (i
= 0; i
< len
; i
++)
132 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
134 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
136 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
139 static void hsw_audio_codec_disable(struct intel_encoder
*encoder
)
141 struct drm_device
*dev
= encoder
->base
.dev
;
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
144 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
147 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
148 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
149 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
152 static void hsw_audio_codec_enable(struct drm_connector
*connector
,
153 struct intel_encoder
*encoder
,
154 struct drm_display_mode
*mode
)
156 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
157 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
158 uint8_t *eld
= connector
->eld
;
162 enum pipe pipe
= intel_crtc
->pipe
;
164 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
165 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
166 int aud_config
= HSW_AUD_CFG(pipe
);
167 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
169 /* Audio output enable */
170 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
171 tmp
= I915_READ(aud_cntrl_st2
);
172 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
173 I915_WRITE(aud_cntrl_st2
, tmp
);
174 POSTING_READ(aud_cntrl_st2
);
176 /* Set ELD valid state */
177 tmp
= I915_READ(aud_cntrl_st2
);
178 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
179 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
180 I915_WRITE(aud_cntrl_st2
, tmp
);
181 tmp
= I915_READ(aud_cntrl_st2
);
182 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
184 /* Enable HDMI mode */
185 tmp
= I915_READ(aud_config
);
186 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
187 /* clear N_programing_enable and N_value_index */
188 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
189 I915_WRITE(aud_config
, tmp
);
191 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
193 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
195 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
196 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
198 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
200 if (intel_eld_uptodate(connector
,
202 aud_cntl_st
, IBX_ELD_ADDRESS
,
206 tmp
= I915_READ(aud_cntrl_st2
);
208 I915_WRITE(aud_cntrl_st2
, tmp
);
213 tmp
= I915_READ(aud_cntl_st
);
214 tmp
&= ~IBX_ELD_ADDRESS
;
215 I915_WRITE(aud_cntl_st
, tmp
);
216 port
= (tmp
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
217 DRM_DEBUG_DRIVER("port num:%d\n", port
);
219 len
= min_t(int, eld
[2], 21); /* 84 bytes of hw ELD buffer */
220 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
221 for (i
= 0; i
< len
; i
++)
222 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
224 tmp
= I915_READ(aud_cntrl_st2
);
226 I915_WRITE(aud_cntrl_st2
, tmp
);
228 /* XXX: Transitional */
229 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
230 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
231 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
234 static void ilk_audio_codec_enable(struct drm_connector
*connector
,
235 struct intel_encoder
*encoder
,
236 struct drm_display_mode
*mode
)
238 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
239 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
240 uint8_t *eld
= connector
->eld
;
248 enum pipe pipe
= intel_crtc
->pipe
;
251 if (HAS_PCH_IBX(connector
->dev
)) {
252 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
253 aud_config
= IBX_AUD_CFG(pipe
);
254 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
255 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
256 } else if (IS_VALLEYVIEW(connector
->dev
)) {
257 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
258 aud_config
= VLV_AUD_CFG(pipe
);
259 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
260 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
262 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
263 aud_config
= CPT_AUD_CFG(pipe
);
264 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
265 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
268 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
270 if (IS_VALLEYVIEW(connector
->dev
)) {
271 struct intel_digital_port
*intel_dig_port
;
273 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
274 port
= intel_dig_port
->port
;
276 tmp
= I915_READ(aud_cntl_st
);
277 port
= (tmp
>> 29) & DIP_PORT_SEL_MASK
;
278 /* DIP_Port_Select, 0x1 = PortB */
282 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
283 /* operate blindly on all ports */
284 eldv
= IBX_ELD_VALIDB
;
285 eldv
|= IBX_ELD_VALIDB
<< 4;
286 eldv
|= IBX_ELD_VALIDB
<< 8;
288 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(port
));
289 eldv
= IBX_ELD_VALIDB
<< ((port
- 1) * 4);
292 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DISPLAYPORT
))
293 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
295 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
297 if (intel_eld_uptodate(connector
,
299 aud_cntl_st
, IBX_ELD_ADDRESS
,
303 tmp
= I915_READ(aud_cntrl_st2
);
305 I915_WRITE(aud_cntrl_st2
, tmp
);
310 tmp
= I915_READ(aud_cntl_st
);
311 tmp
&= ~IBX_ELD_ADDRESS
;
312 I915_WRITE(aud_cntl_st
, tmp
);
314 len
= min_t(int, eld
[2], 21); /* 84 bytes of hw ELD buffer */
315 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
316 for (i
= 0; i
< len
; i
++)
317 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
319 tmp
= I915_READ(aud_cntrl_st2
);
321 I915_WRITE(aud_cntrl_st2
, tmp
);
325 * intel_audio_codec_enable - Enable the audio codec for HD audio
326 * @intel_encoder: encoder on which to enable audio
328 * The enable sequences may only be performed after enabling the transcoder and
329 * port, and after completed link training.
331 void intel_audio_codec_enable(struct intel_encoder
*intel_encoder
)
333 struct drm_encoder
*encoder
= &intel_encoder
->base
;
334 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
335 struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
336 struct drm_connector
*connector
;
337 struct drm_device
*dev
= encoder
->dev
;
338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 connector
= drm_select_eld(encoder
, mode
);
344 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
347 connector
->encoder
->base
.id
,
348 connector
->encoder
->name
);
351 connector
->eld
[5] &= ~(3 << 2);
352 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
353 connector
->eld
[5] |= (1 << 2);
355 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
357 if (dev_priv
->display
.audio_codec_enable
)
358 dev_priv
->display
.audio_codec_enable(connector
, intel_encoder
, mode
);
362 * intel_audio_codec_disable - Disable the audio codec for HD audio
363 * @encoder: encoder on which to disable audio
365 * The disable sequences must be performed before disabling the transcoder or
368 void intel_audio_codec_disable(struct intel_encoder
*encoder
)
370 struct drm_device
*dev
= encoder
->base
.dev
;
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
373 if (dev_priv
->display
.audio_codec_disable
)
374 dev_priv
->display
.audio_codec_disable(encoder
);
378 * intel_init_audio - Set up chip specific audio functions
381 void intel_init_audio(struct drm_device
*dev
)
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
386 dev_priv
->display
.audio_codec_enable
= g4x_audio_codec_enable
;
387 } else if (IS_VALLEYVIEW(dev
)) {
388 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
389 } else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) {
390 dev_priv
->display
.audio_codec_enable
= hsw_audio_codec_enable
;
391 dev_priv
->display
.audio_codec_disable
= hsw_audio_codec_disable
;
392 } else if (HAS_PCH_SPLIT(dev
)) {
393 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;