2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 /* Here's the desired hotplug mode */
40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
45 ADPA_CRT_HOTPLUG_ENABLE)
48 struct intel_encoder base
;
49 /* DPMS state is stored in the connector, which we need in the
50 * encoder's enable/disable callbacks */
51 struct intel_connector
*connector
;
52 bool force_hotplug_required
;
56 static struct intel_crt
*intel_encoder_to_crt(struct intel_encoder
*encoder
)
58 return container_of(encoder
, struct intel_crt
, base
);
61 static struct intel_crt
*intel_attached_crt(struct drm_connector
*connector
)
63 return intel_encoder_to_crt(intel_attached_encoder(connector
));
66 static bool intel_crt_get_hw_state(struct intel_encoder
*encoder
,
69 struct drm_device
*dev
= encoder
->base
.dev
;
70 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
71 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
72 enum intel_display_power_domain power_domain
;
75 power_domain
= intel_display_port_power_domain(encoder
);
76 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
79 tmp
= I915_READ(crt
->adpa_reg
);
81 if (!(tmp
& ADPA_DAC_ENABLE
))
85 *pipe
= PORT_TO_PIPE_CPT(tmp
);
87 *pipe
= PORT_TO_PIPE(tmp
);
92 static unsigned int intel_crt_get_flags(struct intel_encoder
*encoder
)
94 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
95 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
98 tmp
= I915_READ(crt
->adpa_reg
);
100 if (tmp
& ADPA_HSYNC_ACTIVE_HIGH
)
101 flags
|= DRM_MODE_FLAG_PHSYNC
;
103 flags
|= DRM_MODE_FLAG_NHSYNC
;
105 if (tmp
& ADPA_VSYNC_ACTIVE_HIGH
)
106 flags
|= DRM_MODE_FLAG_PVSYNC
;
108 flags
|= DRM_MODE_FLAG_NVSYNC
;
113 static void intel_crt_get_config(struct intel_encoder
*encoder
,
114 struct intel_crtc_state
*pipe_config
)
116 struct drm_device
*dev
= encoder
->base
.dev
;
119 pipe_config
->base
.adjusted_mode
.flags
|= intel_crt_get_flags(encoder
);
121 dotclock
= pipe_config
->port_clock
;
123 if (HAS_PCH_SPLIT(dev
))
124 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
126 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
129 static void hsw_crt_get_config(struct intel_encoder
*encoder
,
130 struct intel_crtc_state
*pipe_config
)
132 intel_ddi_get_config(encoder
, pipe_config
);
134 pipe_config
->base
.adjusted_mode
.flags
&= ~(DRM_MODE_FLAG_PHSYNC
|
135 DRM_MODE_FLAG_NHSYNC
|
136 DRM_MODE_FLAG_PVSYNC
|
137 DRM_MODE_FLAG_NVSYNC
);
138 pipe_config
->base
.adjusted_mode
.flags
|= intel_crt_get_flags(encoder
);
141 static void hsw_crt_pre_enable(struct intel_encoder
*encoder
)
143 struct drm_device
*dev
= encoder
->base
.dev
;
144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL already enabled\n");
148 SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
);
149 POSTING_READ(SPLL_CTL
);
153 /* Note: The caller is required to filter out dpms modes not supported by the
155 static void intel_crt_set_dpms(struct intel_encoder
*encoder
, int mode
)
157 struct drm_device
*dev
= encoder
->base
.dev
;
158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
159 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
160 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
161 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
164 if (INTEL_INFO(dev
)->gen
>= 5)
165 adpa
= ADPA_HOTPLUG_BITS
;
169 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
170 adpa
|= ADPA_HSYNC_ACTIVE_HIGH
;
171 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
172 adpa
|= ADPA_VSYNC_ACTIVE_HIGH
;
174 /* For CPT allow 3 pipe config, for others just use A or B */
175 if (HAS_PCH_LPT(dev
))
176 ; /* Those bits don't exist here */
177 else if (HAS_PCH_CPT(dev
))
178 adpa
|= PORT_TRANS_SEL_CPT(crtc
->pipe
);
179 else if (crtc
->pipe
== 0)
180 adpa
|= ADPA_PIPE_A_SELECT
;
182 adpa
|= ADPA_PIPE_B_SELECT
;
184 if (!HAS_PCH_SPLIT(dev
))
185 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
188 case DRM_MODE_DPMS_ON
:
189 adpa
|= ADPA_DAC_ENABLE
;
191 case DRM_MODE_DPMS_STANDBY
:
192 adpa
|= ADPA_DAC_ENABLE
| ADPA_HSYNC_CNTL_DISABLE
;
194 case DRM_MODE_DPMS_SUSPEND
:
195 adpa
|= ADPA_DAC_ENABLE
| ADPA_VSYNC_CNTL_DISABLE
;
197 case DRM_MODE_DPMS_OFF
:
198 adpa
|= ADPA_HSYNC_CNTL_DISABLE
| ADPA_VSYNC_CNTL_DISABLE
;
202 I915_WRITE(crt
->adpa_reg
, adpa
);
205 static void intel_disable_crt(struct intel_encoder
*encoder
)
207 intel_crt_set_dpms(encoder
, DRM_MODE_DPMS_OFF
);
210 static void pch_disable_crt(struct intel_encoder
*encoder
)
214 static void pch_post_disable_crt(struct intel_encoder
*encoder
)
216 intel_disable_crt(encoder
);
219 static void hsw_crt_post_disable(struct intel_encoder
*encoder
)
221 struct drm_device
*dev
= encoder
->base
.dev
;
222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
225 DRM_DEBUG_KMS("Disabling SPLL\n");
226 val
= I915_READ(SPLL_CTL
);
227 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
228 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
229 POSTING_READ(SPLL_CTL
);
232 static void intel_enable_crt(struct intel_encoder
*encoder
)
234 struct intel_crt
*crt
= intel_encoder_to_crt(encoder
);
236 intel_crt_set_dpms(encoder
, crt
->connector
->base
.dpms
);
239 static enum drm_mode_status
240 intel_crt_mode_valid(struct drm_connector
*connector
,
241 struct drm_display_mode
*mode
)
243 struct drm_device
*dev
= connector
->dev
;
246 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
247 return MODE_NO_DBLESCAN
;
249 if (mode
->clock
< 25000)
250 return MODE_CLOCK_LOW
;
256 if (mode
->clock
> max_clock
)
257 return MODE_CLOCK_HIGH
;
259 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
260 if (HAS_PCH_LPT(dev
) &&
261 (ironlake_get_lanes_required(mode
->clock
, 270000, 24) > 2))
262 return MODE_CLOCK_HIGH
;
267 static bool intel_crt_compute_config(struct intel_encoder
*encoder
,
268 struct intel_crtc_state
*pipe_config
)
270 struct drm_device
*dev
= encoder
->base
.dev
;
272 if (HAS_PCH_SPLIT(dev
))
273 pipe_config
->has_pch_encoder
= true;
275 /* LPT FDI RX only supports 8bpc. */
276 if (HAS_PCH_LPT(dev
))
277 pipe_config
->pipe_bpp
= 24;
279 /* FDI must always be 2.7 GHz */
281 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
282 pipe_config
->port_clock
= 135000 * 2;
288 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector
*connector
)
290 struct drm_device
*dev
= connector
->dev
;
291 struct intel_crt
*crt
= intel_attached_crt(connector
);
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
296 /* The first time through, trigger an explicit detection cycle */
297 if (crt
->force_hotplug_required
) {
298 bool turn_off_dac
= HAS_PCH_SPLIT(dev
);
301 crt
->force_hotplug_required
= 0;
303 save_adpa
= adpa
= I915_READ(crt
->adpa_reg
);
304 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa
);
306 adpa
|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER
;
308 adpa
&= ~ADPA_DAC_ENABLE
;
310 I915_WRITE(crt
->adpa_reg
, adpa
);
312 if (wait_for((I915_READ(crt
->adpa_reg
) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER
) == 0,
314 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
317 I915_WRITE(crt
->adpa_reg
, save_adpa
);
318 POSTING_READ(crt
->adpa_reg
);
322 /* Check the status to see if both blue and green are on now */
323 adpa
= I915_READ(crt
->adpa_reg
);
324 if ((adpa
& ADPA_CRT_HOTPLUG_MONITOR_MASK
) != 0)
328 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa
, ret
);
333 static bool valleyview_crt_detect_hotplug(struct drm_connector
*connector
)
335 struct drm_device
*dev
= connector
->dev
;
336 struct intel_crt
*crt
= intel_attached_crt(connector
);
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 save_adpa
= adpa
= I915_READ(crt
->adpa_reg
);
343 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa
);
345 adpa
|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER
;
347 I915_WRITE(crt
->adpa_reg
, adpa
);
349 if (wait_for((I915_READ(crt
->adpa_reg
) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER
) == 0,
351 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
352 I915_WRITE(crt
->adpa_reg
, save_adpa
);
355 /* Check the status to see if both blue and green are on now */
356 adpa
= I915_READ(crt
->adpa_reg
);
357 if ((adpa
& ADPA_CRT_HOTPLUG_MONITOR_MASK
) != 0)
362 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa
, ret
);
368 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
370 * Not for i915G/i915GM
372 * \return true if CRT is connected.
373 * \return false if CRT is disconnected.
375 static bool intel_crt_detect_hotplug(struct drm_connector
*connector
)
377 struct drm_device
*dev
= connector
->dev
;
378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 if (HAS_PCH_SPLIT(dev
))
384 return intel_ironlake_crt_detect_hotplug(connector
);
386 if (IS_VALLEYVIEW(dev
))
387 return valleyview_crt_detect_hotplug(connector
);
390 * On 4 series desktop, CRT detect sequence need to be done twice
391 * to get a reliable result.
394 if (IS_G4X(dev
) && !IS_GM45(dev
))
399 for (i
= 0; i
< tries
; i
++) {
400 /* turn on the FORCE_DETECT */
401 i915_hotplug_interrupt_update(dev_priv
,
402 CRT_HOTPLUG_FORCE_DETECT
,
403 CRT_HOTPLUG_FORCE_DETECT
);
404 /* wait for FORCE_DETECT to go off */
405 if (wait_for((I915_READ(PORT_HOTPLUG_EN
) &
406 CRT_HOTPLUG_FORCE_DETECT
) == 0,
408 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
411 stat
= I915_READ(PORT_HOTPLUG_STAT
);
412 if ((stat
& CRT_HOTPLUG_MONITOR_MASK
) != CRT_HOTPLUG_MONITOR_NONE
)
415 /* clear the interrupt we just generated, if any */
416 I915_WRITE(PORT_HOTPLUG_STAT
, CRT_HOTPLUG_INT_STATUS
);
418 i915_hotplug_interrupt_update(dev_priv
, CRT_HOTPLUG_FORCE_DETECT
, 0);
423 static struct edid
*intel_crt_get_edid(struct drm_connector
*connector
,
424 struct i2c_adapter
*i2c
)
428 edid
= drm_get_edid(connector
, i2c
);
430 if (!edid
&& !intel_gmbus_is_forced_bit(i2c
)) {
431 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
432 intel_gmbus_force_bit(i2c
, true);
433 edid
= drm_get_edid(connector
, i2c
);
434 intel_gmbus_force_bit(i2c
, false);
440 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
441 static int intel_crt_ddc_get_modes(struct drm_connector
*connector
,
442 struct i2c_adapter
*adapter
)
447 edid
= intel_crt_get_edid(connector
, adapter
);
451 ret
= intel_connector_update_modes(connector
, edid
);
457 static bool intel_crt_detect_ddc(struct drm_connector
*connector
)
459 struct intel_crt
*crt
= intel_attached_crt(connector
);
460 struct drm_i915_private
*dev_priv
= crt
->base
.base
.dev
->dev_private
;
462 struct i2c_adapter
*i2c
;
464 BUG_ON(crt
->base
.type
!= INTEL_OUTPUT_ANALOG
);
466 i2c
= intel_gmbus_get_adapter(dev_priv
, dev_priv
->vbt
.crt_ddc_pin
);
467 edid
= intel_crt_get_edid(connector
, i2c
);
470 bool is_digital
= edid
->input
& DRM_EDID_INPUT_DIGITAL
;
473 * This may be a DVI-I connector with a shared DDC
474 * link between analog and digital outputs, so we
475 * have to check the EDID input spec of the attached device.
478 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
482 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
484 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
492 static enum drm_connector_status
493 intel_crt_load_detect(struct intel_crt
*crt
)
495 struct drm_device
*dev
= crt
->base
.base
.dev
;
496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
497 uint32_t pipe
= to_intel_crtc(crt
->base
.base
.crtc
)->pipe
;
498 uint32_t save_bclrpat
;
499 uint32_t save_vtotal
;
500 uint32_t vtotal
, vactive
;
502 uint32_t vblank
, vblank_start
, vblank_end
;
504 uint32_t bclrpat_reg
;
508 uint32_t pipeconf_reg
;
509 uint32_t pipe_dsl_reg
;
511 enum drm_connector_status status
;
513 DRM_DEBUG_KMS("starting load-detect on CRT\n");
515 bclrpat_reg
= BCLRPAT(pipe
);
516 vtotal_reg
= VTOTAL(pipe
);
517 vblank_reg
= VBLANK(pipe
);
518 vsync_reg
= VSYNC(pipe
);
519 pipeconf_reg
= PIPECONF(pipe
);
520 pipe_dsl_reg
= PIPEDSL(pipe
);
522 save_bclrpat
= I915_READ(bclrpat_reg
);
523 save_vtotal
= I915_READ(vtotal_reg
);
524 vblank
= I915_READ(vblank_reg
);
526 vtotal
= ((save_vtotal
>> 16) & 0xfff) + 1;
527 vactive
= (save_vtotal
& 0x7ff) + 1;
529 vblank_start
= (vblank
& 0xfff) + 1;
530 vblank_end
= ((vblank
>> 16) & 0xfff) + 1;
532 /* Set the border color to purple. */
533 I915_WRITE(bclrpat_reg
, 0x500050);
536 uint32_t pipeconf
= I915_READ(pipeconf_reg
);
537 I915_WRITE(pipeconf_reg
, pipeconf
| PIPECONF_FORCE_BORDER
);
538 POSTING_READ(pipeconf_reg
);
539 /* Wait for next Vblank to substitue
540 * border color for Color info */
541 intel_wait_for_vblank(dev
, pipe
);
542 st00
= I915_READ8(VGA_MSR_WRITE
);
543 status
= ((st00
& (1 << 4)) != 0) ?
544 connector_status_connected
:
545 connector_status_disconnected
;
547 I915_WRITE(pipeconf_reg
, pipeconf
);
549 bool restore_vblank
= false;
553 * If there isn't any border, add some.
554 * Yes, this will flicker
556 if (vblank_start
<= vactive
&& vblank_end
>= vtotal
) {
557 uint32_t vsync
= I915_READ(vsync_reg
);
558 uint32_t vsync_start
= (vsync
& 0xffff) + 1;
560 vblank_start
= vsync_start
;
561 I915_WRITE(vblank_reg
,
563 ((vblank_end
- 1) << 16));
564 restore_vblank
= true;
566 /* sample in the vertical border, selecting the larger one */
567 if (vblank_start
- vactive
>= vtotal
- vblank_end
)
568 vsample
= (vblank_start
+ vactive
) >> 1;
570 vsample
= (vtotal
+ vblank_end
) >> 1;
573 * Wait for the border to be displayed
575 while (I915_READ(pipe_dsl_reg
) >= vactive
)
577 while ((dsl
= I915_READ(pipe_dsl_reg
)) <= vsample
)
580 * Watch ST00 for an entire scanline
586 /* Read the ST00 VGA status register */
587 st00
= I915_READ8(VGA_MSR_WRITE
);
590 } while ((I915_READ(pipe_dsl_reg
) == dsl
));
592 /* restore vblank if necessary */
594 I915_WRITE(vblank_reg
, vblank
);
596 * If more than 3/4 of the scanline detected a monitor,
597 * then it is assumed to be present. This works even on i830,
598 * where there isn't any way to force the border color across
601 status
= detect
* 4 > count
* 3 ?
602 connector_status_connected
:
603 connector_status_disconnected
;
606 /* Restore previous settings */
607 I915_WRITE(bclrpat_reg
, save_bclrpat
);
612 static enum drm_connector_status
613 intel_crt_detect(struct drm_connector
*connector
, bool force
)
615 struct drm_device
*dev
= connector
->dev
;
616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
617 struct intel_crt
*crt
= intel_attached_crt(connector
);
618 struct intel_encoder
*intel_encoder
= &crt
->base
;
619 enum intel_display_power_domain power_domain
;
620 enum drm_connector_status status
;
621 struct intel_load_detect_pipe tmp
;
622 struct drm_modeset_acquire_ctx ctx
;
624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
625 connector
->base
.id
, connector
->name
,
628 power_domain
= intel_display_port_power_domain(intel_encoder
);
629 intel_display_power_get(dev_priv
, power_domain
);
631 if (I915_HAS_HOTPLUG(dev
)) {
632 /* We can not rely on the HPD pin always being correctly wired
633 * up, for example many KVM do not pass it through, and so
634 * only trust an assertion that the monitor is connected.
636 if (intel_crt_detect_hotplug(connector
)) {
637 DRM_DEBUG_KMS("CRT detected via hotplug\n");
638 status
= connector_status_connected
;
641 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
644 if (intel_crt_detect_ddc(connector
)) {
645 status
= connector_status_connected
;
649 /* Load detection is broken on HPD capable machines. Whoever wants a
650 * broken monitor (without edid) to work behind a broken kvm (that fails
651 * to have the right resistors for HP detection) needs to fix this up.
652 * For now just bail out. */
653 if (I915_HAS_HOTPLUG(dev
) && !i915
.load_detect_test
) {
654 status
= connector_status_disconnected
;
659 status
= connector
->status
;
663 drm_modeset_acquire_init(&ctx
, 0);
665 /* for pre-945g platforms use load detect */
666 if (intel_get_load_detect_pipe(connector
, NULL
, &tmp
, &ctx
)) {
667 if (intel_crt_detect_ddc(connector
))
668 status
= connector_status_connected
;
669 else if (INTEL_INFO(dev
)->gen
< 4)
670 status
= intel_crt_load_detect(crt
);
672 status
= connector_status_unknown
;
673 intel_release_load_detect_pipe(connector
, &tmp
, &ctx
);
675 status
= connector_status_unknown
;
677 drm_modeset_drop_locks(&ctx
);
678 drm_modeset_acquire_fini(&ctx
);
681 intel_display_power_put(dev_priv
, power_domain
);
685 static void intel_crt_destroy(struct drm_connector
*connector
)
687 drm_connector_cleanup(connector
);
691 static int intel_crt_get_modes(struct drm_connector
*connector
)
693 struct drm_device
*dev
= connector
->dev
;
694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
695 struct intel_crt
*crt
= intel_attached_crt(connector
);
696 struct intel_encoder
*intel_encoder
= &crt
->base
;
697 enum intel_display_power_domain power_domain
;
699 struct i2c_adapter
*i2c
;
701 power_domain
= intel_display_port_power_domain(intel_encoder
);
702 intel_display_power_get(dev_priv
, power_domain
);
704 i2c
= intel_gmbus_get_adapter(dev_priv
, dev_priv
->vbt
.crt_ddc_pin
);
705 ret
= intel_crt_ddc_get_modes(connector
, i2c
);
706 if (ret
|| !IS_G4X(dev
))
709 /* Try to probe digital port for output in DVI-I -> VGA mode. */
710 i2c
= intel_gmbus_get_adapter(dev_priv
, GMBUS_PIN_DPB
);
711 ret
= intel_crt_ddc_get_modes(connector
, i2c
);
714 intel_display_power_put(dev_priv
, power_domain
);
719 static int intel_crt_set_property(struct drm_connector
*connector
,
720 struct drm_property
*property
,
726 static void intel_crt_reset(struct drm_connector
*connector
)
728 struct drm_device
*dev
= connector
->dev
;
729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
730 struct intel_crt
*crt
= intel_attached_crt(connector
);
732 if (INTEL_INFO(dev
)->gen
>= 5) {
735 adpa
= I915_READ(crt
->adpa_reg
);
736 adpa
&= ~ADPA_CRT_HOTPLUG_MASK
;
737 adpa
|= ADPA_HOTPLUG_BITS
;
738 I915_WRITE(crt
->adpa_reg
, adpa
);
739 POSTING_READ(crt
->adpa_reg
);
741 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa
);
742 crt
->force_hotplug_required
= 1;
748 * Routines for controlling stuff on the analog port
751 static const struct drm_connector_funcs intel_crt_connector_funcs
= {
752 .reset
= intel_crt_reset
,
753 .dpms
= drm_atomic_helper_connector_dpms
,
754 .detect
= intel_crt_detect
,
755 .fill_modes
= drm_helper_probe_single_connector_modes
,
756 .destroy
= intel_crt_destroy
,
757 .set_property
= intel_crt_set_property
,
758 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
759 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
760 .atomic_get_property
= intel_connector_atomic_get_property
,
763 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs
= {
764 .mode_valid
= intel_crt_mode_valid
,
765 .get_modes
= intel_crt_get_modes
,
766 .best_encoder
= intel_best_encoder
,
769 static const struct drm_encoder_funcs intel_crt_enc_funcs
= {
770 .destroy
= intel_encoder_destroy
,
773 static int intel_no_crt_dmi_callback(const struct dmi_system_id
*id
)
775 DRM_INFO("Skipping CRT initialization for %s\n", id
->ident
);
779 static const struct dmi_system_id intel_no_crt
[] = {
781 .callback
= intel_no_crt_dmi_callback
,
784 DMI_MATCH(DMI_SYS_VENDOR
, "ACER"),
785 DMI_MATCH(DMI_PRODUCT_NAME
, "ZGB"),
789 .callback
= intel_no_crt_dmi_callback
,
790 .ident
= "DELL XPS 8700",
792 DMI_MATCH(DMI_SYS_VENDOR
, "Dell Inc."),
793 DMI_MATCH(DMI_PRODUCT_NAME
, "XPS 8700"),
799 void intel_crt_init(struct drm_device
*dev
)
801 struct drm_connector
*connector
;
802 struct intel_crt
*crt
;
803 struct intel_connector
*intel_connector
;
804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
806 /* Skip machines without VGA that falsely report hotplug events */
807 if (dmi_check_system(intel_no_crt
))
810 crt
= kzalloc(sizeof(struct intel_crt
), GFP_KERNEL
);
814 intel_connector
= intel_connector_alloc();
815 if (!intel_connector
) {
820 connector
= &intel_connector
->base
;
821 crt
->connector
= intel_connector
;
822 drm_connector_init(dev
, &intel_connector
->base
,
823 &intel_crt_connector_funcs
, DRM_MODE_CONNECTOR_VGA
);
825 drm_encoder_init(dev
, &crt
->base
.base
, &intel_crt_enc_funcs
,
826 DRM_MODE_ENCODER_DAC
);
828 intel_connector_attach_encoder(intel_connector
, &crt
->base
);
830 crt
->base
.type
= INTEL_OUTPUT_ANALOG
;
831 crt
->base
.cloneable
= (1 << INTEL_OUTPUT_DVO
) | (1 << INTEL_OUTPUT_HDMI
);
833 crt
->base
.crtc_mask
= (1 << 0);
835 crt
->base
.crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
838 connector
->interlace_allowed
= 0;
840 connector
->interlace_allowed
= 1;
841 connector
->doublescan_allowed
= 0;
843 if (HAS_PCH_SPLIT(dev
))
844 crt
->adpa_reg
= PCH_ADPA
;
845 else if (IS_VALLEYVIEW(dev
))
846 crt
->adpa_reg
= VLV_ADPA
;
848 crt
->adpa_reg
= ADPA
;
850 crt
->base
.compute_config
= intel_crt_compute_config
;
851 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
)) {
852 crt
->base
.disable
= pch_disable_crt
;
853 crt
->base
.post_disable
= pch_post_disable_crt
;
855 crt
->base
.disable
= intel_disable_crt
;
857 crt
->base
.enable
= intel_enable_crt
;
858 if (I915_HAS_HOTPLUG(dev
))
859 crt
->base
.hpd_pin
= HPD_CRT
;
861 crt
->base
.get_config
= hsw_crt_get_config
;
862 crt
->base
.get_hw_state
= intel_ddi_get_hw_state
;
863 crt
->base
.pre_enable
= hsw_crt_pre_enable
;
864 crt
->base
.post_disable
= hsw_crt_post_disable
;
866 crt
->base
.get_config
= intel_crt_get_config
;
867 crt
->base
.get_hw_state
= intel_crt_get_hw_state
;
869 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
870 intel_connector
->unregister
= intel_connector_unregister
;
872 drm_connector_helper_add(connector
, &intel_crt_connector_helper_funcs
);
874 drm_connector_register(connector
);
876 if (!I915_HAS_HOTPLUG(dev
))
877 intel_connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
;
880 * Configure the automatic hotplug detection stuff
882 crt
->force_hotplug_required
= 0;
885 * TODO: find a proper way to discover whether we need to set the the
886 * polarity and link reversal bits or not, instead of relying on the
889 if (HAS_PCH_LPT(dev
)) {
890 u32 fdi_config
= FDI_RX_POLARITY_REVERSED_LPT
|
891 FDI_RX_LINK_REVERSAL_OVERRIDE
;
893 dev_priv
->fdi_rx_config
= I915_READ(FDI_RX_CTL(PIPE_A
)) & fdi_config
;
896 intel_crt_reset(connector
);