drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  *
  36  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37  * FW_LOADED, FW_FAILED.
  38  *
  39  * Once the firmware is written into the registers status will be moved from
  40  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41  * be moved to FW_FAILED.
  42  */
  43
  44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  46
  47 #define FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
  48
  49 MODULE_FIRMWARE(I915_CSR_SKL);
  50 MODULE_FIRMWARE(I915_CSR_BXT);
  51
  52 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 23)
  53
  54 #define CSR_MAX_FW_SIZE                 0x2FFF
  55 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  56
  57 struct intel_css_header {
  58         /* 0x09 for DMC */
  59         uint32_t module_type;
  60
  61         /* Includes the DMC specific header in dwords */
  62         uint32_t header_len;
  63
  64         /* always value would be 0x10000 */
  65         uint32_t header_ver;
  66
  67         /* Not used */
  68         uint32_t module_id;
  69
  70         /* Not used */
  71         uint32_t module_vendor;
  72
  73         /* in YYYYMMDD format */
  74         uint32_t date;
  75
  76         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  77         uint32_t size;
  78
  79         /* Not used */
  80         uint32_t key_size;
  81
  82         /* Not used */
  83         uint32_t modulus_size;
  84
  85         /* Not used */
  86         uint32_t exponent_size;
  87
  88         /* Not used */
  89         uint32_t reserved1[12];
  90
  91         /* Major Minor */
  92         uint32_t version;
  93
  94         /* Not used */
  95         uint32_t reserved2[8];
  96
  97         /* Not used */
  98         uint32_t kernel_header_info;
  99 } __packed;
 100
 101 struct intel_fw_info {
 102         uint16_t reserved1;
 103
 104         /* Stepping (A, B, C, ..., *). * is a wildcard */
 105         char stepping;
 106
 107         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 108         char substepping;
 109
 110         uint32_t offset;
 111         uint32_t reserved2;
 112 } __packed;
 113
 114 struct intel_package_header {
 115         /* DMC container header length in dwords */
 116         unsigned char header_len;
 117
 118         /* always value would be 0x01 */
 119         unsigned char header_ver;
 120
 121         unsigned char reserved[10];
 122
 123         /* Number of valid entries in the FWInfo array below */
 124         uint32_t num_entries;
 125
 126         struct intel_fw_info fw_info[20];
 127 } __packed;
 128
 129 struct intel_dmc_header {
 130         /* always value would be 0x40403E3E */
 131         uint32_t signature;
 132
 133         /* DMC binary header length */
 134         unsigned char header_len;
 135
 136         /* 0x01 */
 137         unsigned char header_ver;
 138
 139         /* Reserved */
 140         uint16_t dmcc_ver;
 141
 142         /* Major, Minor */
 143         uint32_t        project;
 144
 145         /* Firmware program size (excluding header) in dwords */
 146         uint32_t        fw_size;
 147
 148         /* Major Minor version */
 149         uint32_t fw_version;
 150
 151         /* Number of valid MMIO cycles present. */
 152         uint32_t mmio_count;
 153
 154         /* MMIO address */
 155         uint32_t mmioaddr[8];
 156
 157         /* MMIO data */
 158         uint32_t mmiodata[8];
 159
 160         /* FW filename  */
 161         unsigned char dfile[32];
 162
 163         uint32_t reserved1[2];
 164 } __packed;
 165
 166 struct stepping_info {
 167         char stepping;
 168         char substepping;
 169 };
 170
 171 /*
 172  * Kabylake derivated from Skylake H0, so SKL H0
 173  * is the right firmware for KBL A0 (revid 0).
 174  */
 175 static const struct stepping_info kbl_stepping_info[] = {
 176         {'H', '0'}, {'I', '0'}
 177 };
 178
 179 static const struct stepping_info skl_stepping_info[] = {
 180         {'A', '0'}, {'B', '0'}, {'C', '0'},
 181         {'D', '0'}, {'E', '0'}, {'F', '0'},
 182         {'G', '0'}, {'H', '0'}, {'I', '0'},
 183         {'J', '0'}, {'K', '0'}
 184 };
 185
 186 static const struct stepping_info bxt_stepping_info[] = {
 187         {'A', '0'}, {'A', '1'}, {'A', '2'},
 188         {'B', '0'}, {'B', '1'}, {'B', '2'}
 189 };
 190
 191 static const struct stepping_info no_stepping_info = { '*', '*' };
 192
 193 static const struct stepping_info *
 194 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 195 {
 196         const struct stepping_info *si;
 197         unsigned int size;
 198
 199         if (IS_KABYLAKE(dev_priv)) {
 200                 size = ARRAY_SIZE(kbl_stepping_info);
 201                 si = kbl_stepping_info;
 202         } else if (IS_SKYLAKE(dev_priv)) {
 203                 size = ARRAY_SIZE(skl_stepping_info);
 204                 si = skl_stepping_info;
 205         } else if (IS_BROXTON(dev_priv)) {
 206                 size = ARRAY_SIZE(bxt_stepping_info);
 207                 si = bxt_stepping_info;
 208         } else {
 209                 size = 0;
 210         }
 211
 212         if (INTEL_REVID(dev_priv) < size)
 213                 return si + INTEL_REVID(dev_priv);
 214
 215         return &no_stepping_info;
 216 }
 217
 218 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 219 {
 220         uint32_t val, mask;
 221
 222         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 223
 224         if (IS_BROXTON(dev_priv))
 225                 mask |= DC_STATE_DEBUG_MASK_CORES;
 226
 227         /* The below bit doesn't need to be cleared ever afterwards */
 228         val = I915_READ(DC_STATE_DEBUG);
 229         if ((val & mask) != mask) {
 230                 val |= mask;
 231                 I915_WRITE(DC_STATE_DEBUG, val);
 232                 POSTING_READ(DC_STATE_DEBUG);
 233         }
 234 }
 235
 236 /**
 237  * intel_csr_load_program() - write the firmware from memory to register.
 238  * @dev_priv: i915 drm device.
 239  *
 240  * CSR firmware is read from a .bin file and kept in internal memory one time.
 241  * Everytime display comes back from low power state this function is called to
 242  * copy the firmware from internal memory to registers.
 243  */
 244 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 245 {
 246         u32 *payload = dev_priv->csr.dmc_payload;
 247         uint32_t i, fw_size;
 248
 249         if (!IS_GEN9(dev_priv)) {
 250                 DRM_ERROR("No CSR support available for this platform\n");
 251                 return;
 252         }
 253
 254         if (!dev_priv->csr.dmc_payload) {
 255                 DRM_ERROR("Tried to program CSR with empty payload\n");
 256                 return;
 257         }
 258
 259         fw_size = dev_priv->csr.dmc_fw_size;
 260         for (i = 0; i < fw_size; i++)
 261                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 262
 263         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 264                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 265                            dev_priv->csr.mmiodata[i]);
 266         }
 267
 268         dev_priv->csr.dc_state = 0;
 269
 270         gen9_set_dc_state_debugmask(dev_priv);
 271 }
 272
 273 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 274                               const struct firmware *fw)
 275 {
 276         struct intel_css_header *css_header;
 277         struct intel_package_header *package_header;
 278         struct intel_dmc_header *dmc_header;
 279         struct intel_csr *csr = &dev_priv->csr;
 280         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 281         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 282         uint32_t i;
 283         uint32_t *dmc_payload;
 284
 285         if (!fw)
 286                 return NULL;
 287
 288         /* Extract CSS Header information*/
 289         css_header = (struct intel_css_header *)fw->data;
 290         if (sizeof(struct intel_css_header) !=
 291             (css_header->header_len * 4)) {
 292                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 293                           (css_header->header_len * 4));
 294                 return NULL;
 295         }
 296
 297         csr->version = css_header->version;
 298
 299         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 300             csr->version < SKL_CSR_VERSION_REQUIRED) {
 301                 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
 302                          " please upgrade to v%u.%u or later"
 303                            " [" FIRMWARE_URL "].\n",
 304                          CSR_VERSION_MAJOR(csr->version),
 305                          CSR_VERSION_MINOR(csr->version),
 306                          CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
 307                          CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
 308                 return NULL;
 309         }
 310
 311         readcount += sizeof(struct intel_css_header);
 312
 313         /* Extract Package Header information*/
 314         package_header = (struct intel_package_header *)
 315                 &fw->data[readcount];
 316         if (sizeof(struct intel_package_header) !=
 317             (package_header->header_len * 4)) {
 318                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 319                           (package_header->header_len * 4));
 320                 return NULL;
 321         }
 322         readcount += sizeof(struct intel_package_header);
 323
 324         /* Search for dmc_offset to find firware binary. */
 325         for (i = 0; i < package_header->num_entries; i++) {
 326                 if (package_header->fw_info[i].substepping == '*' &&
 327                     si->stepping == package_header->fw_info[i].stepping) {
 328                         dmc_offset = package_header->fw_info[i].offset;
 329                         break;
 330                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 331                            si->substepping == package_header->fw_info[i].substepping) {
 332                         dmc_offset = package_header->fw_info[i].offset;
 333                         break;
 334                 } else if (package_header->fw_info[i].stepping == '*' &&
 335                            package_header->fw_info[i].substepping == '*')
 336                         dmc_offset = package_header->fw_info[i].offset;
 337         }
 338         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 339                 DRM_ERROR("Firmware not supported for %c stepping\n",
 340                           si->stepping);
 341                 return NULL;
 342         }
 343         readcount += dmc_offset;
 344
 345         /* Extract dmc_header information. */
 346         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 347         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 348                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 349                           (dmc_header->header_len));
 350                 return NULL;
 351         }
 352         readcount += sizeof(struct intel_dmc_header);
 353
 354         /* Cache the dmc header info. */
 355         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 356                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 357                           dmc_header->mmio_count);
 358                 return NULL;
 359         }
 360         csr->mmio_count = dmc_header->mmio_count;
 361         for (i = 0; i < dmc_header->mmio_count; i++) {
 362                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 363                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 364                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 365                                   dmc_header->mmioaddr[i]);
 366                         return NULL;
 367                 }
 368                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 369                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 370         }
 371
 372         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 373         nbytes = dmc_header->fw_size * 4;
 374         if (nbytes > CSR_MAX_FW_SIZE) {
 375                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 376                 return NULL;
 377         }
 378         csr->dmc_fw_size = dmc_header->fw_size;
 379
 380         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 381         if (!dmc_payload) {
 382                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 383                 return NULL;
 384         }
 385
 386         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 387 }
 388
 389 static void csr_load_work_fn(struct work_struct *work)
 390 {
 391         struct drm_i915_private *dev_priv;
 392         struct intel_csr *csr;
 393         const struct firmware *fw;
 394         int ret;
 395
 396         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 397         csr = &dev_priv->csr;
 398
 399         ret = request_firmware(&fw, dev_priv->csr.fw_path,
 400                                &dev_priv->dev->pdev->dev);
 401         if (fw)
 402                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 403
 404         if (dev_priv->csr.dmc_payload) {
 405                 intel_csr_load_program(dev_priv);
 406
 407                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 408
 409                 DRM_INFO("Finished loading %s (v%u.%u)\n",
 410                          dev_priv->csr.fw_path,
 411                          CSR_VERSION_MAJOR(csr->version),
 412                          CSR_VERSION_MINOR(csr->version));
 413         } else {
 414                 dev_notice(dev_priv->dev->dev,
 415                            "Failed to load DMC firmware"
 416                            " [" FIRMWARE_URL "],"
 417                            " disabling runtime power management.\n");
 418         }
 419
 420         release_firmware(fw);
 421 }
 422
 423 /**
 424  * intel_csr_ucode_init() - initialize the firmware loading.
 425  * @dev_priv: i915 drm device.
 426  *
 427  * This function is called at the time of loading the display driver to read
 428  * firmware from a .bin file and copied into a internal memory.
 429  */
 430 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 431 {
 432         struct intel_csr *csr = &dev_priv->csr;
 433
 434         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 435
 436         if (!HAS_CSR(dev_priv))
 437                 return;
 438
 439         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 440                 csr->fw_path = I915_CSR_SKL;
 441         else if (IS_BROXTON(dev_priv))
 442                 csr->fw_path = I915_CSR_BXT;
 443         else {
 444                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 445                 return;
 446         }
 447
 448         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 449
 450         /*
 451          * Obtain a runtime pm reference, until CSR is loaded,
 452          * to avoid entering runtime-suspend.
 453          */
 454         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 455
 456         schedule_work(&dev_priv->csr.work);
 457 }
 458
 459 /**
 460  * intel_csr_ucode_fini() - unload the CSR firmware.
 461  * @dev_priv: i915 drm device.
 462  *
 463  * Firmmware unloading includes freeing the internal momory and reset the
 464  * firmware loading status.
 465  */
 466 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 467 {
 468         if (!HAS_CSR(dev_priv))
 469                 return;
 470
 471         flush_work(&dev_priv->csr.work);
 472
 473         kfree(dev_priv->csr.dmc_payload);
 474 }