2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
37 * FW_LOADED, FW_FAILED.
39 * Once the firmware is written into the registers status will be moved from
40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
41 * be moved to FW_FAILED.
44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
47 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
49 MODULE_FIRMWARE(I915_CSR_SKL
);
50 MODULE_FIRMWARE(I915_CSR_BXT
);
52 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
53 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
55 #define CSR_MAX_FW_SIZE 0x2FFF
56 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
58 struct intel_css_header
{
62 /* Includes the DMC specific header in dwords */
65 /* always value would be 0x10000 */
72 uint32_t module_vendor
;
74 /* in YYYYMMDD format */
77 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
84 uint32_t modulus_size
;
87 uint32_t exponent_size
;
90 uint32_t reserved1
[12];
96 uint32_t reserved2
[8];
99 uint32_t kernel_header_info
;
102 struct intel_fw_info
{
105 /* Stepping (A, B, C, ..., *). * is a wildcard */
108 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
115 struct intel_package_header
{
116 /* DMC container header length in dwords */
117 unsigned char header_len
;
119 /* always value would be 0x01 */
120 unsigned char header_ver
;
122 unsigned char reserved
[10];
124 /* Number of valid entries in the FWInfo array below */
125 uint32_t num_entries
;
127 struct intel_fw_info fw_info
[20];
130 struct intel_dmc_header
{
131 /* always value would be 0x40403E3E */
134 /* DMC binary header length */
135 unsigned char header_len
;
138 unsigned char header_ver
;
146 /* Firmware program size (excluding header) in dwords */
149 /* Major Minor version */
152 /* Number of valid MMIO cycles present. */
156 uint32_t mmioaddr
[8];
159 uint32_t mmiodata
[8];
162 unsigned char dfile
[32];
164 uint32_t reserved1
[2];
167 struct stepping_info
{
173 * Kabylake derivated from Skylake H0, so SKL H0
174 * is the right firmware for KBL A0 (revid 0).
176 static const struct stepping_info kbl_stepping_info
[] = {
177 {'H', '0'}, {'I', '0'}
180 static const struct stepping_info skl_stepping_info
[] = {
181 {'A', '0'}, {'B', '0'}, {'C', '0'},
182 {'D', '0'}, {'E', '0'}, {'F', '0'},
183 {'G', '0'}, {'H', '0'}, {'I', '0'},
184 {'J', '0'}, {'K', '0'}
187 static const struct stepping_info bxt_stepping_info
[] = {
188 {'A', '0'}, {'A', '1'}, {'A', '2'},
189 {'B', '0'}, {'B', '1'}, {'B', '2'}
192 static const struct stepping_info no_stepping_info
= { '*', '*' };
194 static const struct stepping_info
*
195 intel_get_stepping_info(struct drm_i915_private
*dev_priv
)
197 const struct stepping_info
*si
;
200 if (IS_KABYLAKE(dev_priv
)) {
201 size
= ARRAY_SIZE(kbl_stepping_info
);
202 si
= kbl_stepping_info
;
203 } else if (IS_SKYLAKE(dev_priv
)) {
204 size
= ARRAY_SIZE(skl_stepping_info
);
205 si
= skl_stepping_info
;
206 } else if (IS_BROXTON(dev_priv
)) {
207 size
= ARRAY_SIZE(bxt_stepping_info
);
208 si
= bxt_stepping_info
;
213 if (INTEL_REVID(dev_priv
) < size
)
214 return si
+ INTEL_REVID(dev_priv
);
216 return &no_stepping_info
;
219 static void gen9_set_dc_state_debugmask(struct drm_i915_private
*dev_priv
)
223 mask
= DC_STATE_DEBUG_MASK_MEMORY_UP
;
225 if (IS_BROXTON(dev_priv
))
226 mask
|= DC_STATE_DEBUG_MASK_CORES
;
228 /* The below bit doesn't need to be cleared ever afterwards */
229 val
= I915_READ(DC_STATE_DEBUG
);
230 if ((val
& mask
) != mask
) {
232 I915_WRITE(DC_STATE_DEBUG
, val
);
233 POSTING_READ(DC_STATE_DEBUG
);
238 * intel_csr_load_program() - write the firmware from memory to register.
239 * @dev_priv: i915 drm device.
241 * CSR firmware is read from a .bin file and kept in internal memory one time.
242 * Everytime display comes back from low power state this function is called to
243 * copy the firmware from internal memory to registers.
245 void intel_csr_load_program(struct drm_i915_private
*dev_priv
)
247 u32
*payload
= dev_priv
->csr
.dmc_payload
;
250 if (!IS_GEN9(dev_priv
)) {
251 DRM_ERROR("No CSR support available for this platform\n");
255 if (!dev_priv
->csr
.dmc_payload
) {
256 DRM_ERROR("Tried to program CSR with empty payload\n");
260 fw_size
= dev_priv
->csr
.dmc_fw_size
;
261 for (i
= 0; i
< fw_size
; i
++)
262 I915_WRITE(CSR_PROGRAM(i
), payload
[i
]);
264 for (i
= 0; i
< dev_priv
->csr
.mmio_count
; i
++) {
265 I915_WRITE(dev_priv
->csr
.mmioaddr
[i
],
266 dev_priv
->csr
.mmiodata
[i
]);
269 dev_priv
->csr
.dc_state
= 0;
271 gen9_set_dc_state_debugmask(dev_priv
);
274 static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv
,
275 const struct firmware
*fw
)
277 struct intel_css_header
*css_header
;
278 struct intel_package_header
*package_header
;
279 struct intel_dmc_header
*dmc_header
;
280 struct intel_csr
*csr
= &dev_priv
->csr
;
281 const struct stepping_info
*si
= intel_get_stepping_info(dev_priv
);
282 uint32_t dmc_offset
= CSR_DEFAULT_FW_OFFSET
, readcount
= 0, nbytes
;
284 uint32_t *dmc_payload
;
285 uint32_t required_min_version
;
290 /* Extract CSS Header information*/
291 css_header
= (struct intel_css_header
*)fw
->data
;
292 if (sizeof(struct intel_css_header
) !=
293 (css_header
->header_len
* 4)) {
294 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
295 (css_header
->header_len
* 4));
299 csr
->version
= css_header
->version
;
301 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
302 required_min_version
= SKL_CSR_VERSION_REQUIRED
;
303 } else if (IS_BROXTON(dev_priv
)) {
304 required_min_version
= BXT_CSR_VERSION_REQUIRED
;
306 MISSING_CASE(INTEL_REVID(dev_priv
));
307 required_min_version
= 0;
310 if (csr
->version
< required_min_version
) {
311 DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
312 " please upgrade to v%u.%u or later"
313 " [" FIRMWARE_URL
"].\n",
314 CSR_VERSION_MAJOR(csr
->version
),
315 CSR_VERSION_MINOR(csr
->version
),
316 CSR_VERSION_MAJOR(required_min_version
),
317 CSR_VERSION_MINOR(required_min_version
));
321 readcount
+= sizeof(struct intel_css_header
);
323 /* Extract Package Header information*/
324 package_header
= (struct intel_package_header
*)
325 &fw
->data
[readcount
];
326 if (sizeof(struct intel_package_header
) !=
327 (package_header
->header_len
* 4)) {
328 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
329 (package_header
->header_len
* 4));
332 readcount
+= sizeof(struct intel_package_header
);
334 /* Search for dmc_offset to find firware binary. */
335 for (i
= 0; i
< package_header
->num_entries
; i
++) {
336 if (package_header
->fw_info
[i
].substepping
== '*' &&
337 si
->stepping
== package_header
->fw_info
[i
].stepping
) {
338 dmc_offset
= package_header
->fw_info
[i
].offset
;
340 } else if (si
->stepping
== package_header
->fw_info
[i
].stepping
&&
341 si
->substepping
== package_header
->fw_info
[i
].substepping
) {
342 dmc_offset
= package_header
->fw_info
[i
].offset
;
344 } else if (package_header
->fw_info
[i
].stepping
== '*' &&
345 package_header
->fw_info
[i
].substepping
== '*')
346 dmc_offset
= package_header
->fw_info
[i
].offset
;
348 if (dmc_offset
== CSR_DEFAULT_FW_OFFSET
) {
349 DRM_ERROR("Firmware not supported for %c stepping\n",
353 readcount
+= dmc_offset
;
355 /* Extract dmc_header information. */
356 dmc_header
= (struct intel_dmc_header
*)&fw
->data
[readcount
];
357 if (sizeof(struct intel_dmc_header
) != (dmc_header
->header_len
)) {
358 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
359 (dmc_header
->header_len
));
362 readcount
+= sizeof(struct intel_dmc_header
);
364 /* Cache the dmc header info. */
365 if (dmc_header
->mmio_count
> ARRAY_SIZE(csr
->mmioaddr
)) {
366 DRM_ERROR("Firmware has wrong mmio count %u\n",
367 dmc_header
->mmio_count
);
370 csr
->mmio_count
= dmc_header
->mmio_count
;
371 for (i
= 0; i
< dmc_header
->mmio_count
; i
++) {
372 if (dmc_header
->mmioaddr
[i
] < CSR_MMIO_START_RANGE
||
373 dmc_header
->mmioaddr
[i
] > CSR_MMIO_END_RANGE
) {
374 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
375 dmc_header
->mmioaddr
[i
]);
378 csr
->mmioaddr
[i
] = _MMIO(dmc_header
->mmioaddr
[i
]);
379 csr
->mmiodata
[i
] = dmc_header
->mmiodata
[i
];
382 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
383 nbytes
= dmc_header
->fw_size
* 4;
384 if (nbytes
> CSR_MAX_FW_SIZE
) {
385 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes
);
388 csr
->dmc_fw_size
= dmc_header
->fw_size
;
390 dmc_payload
= kmalloc(nbytes
, GFP_KERNEL
);
392 DRM_ERROR("Memory allocation failed for dmc payload\n");
396 return memcpy(dmc_payload
, &fw
->data
[readcount
], nbytes
);
399 static void csr_load_work_fn(struct work_struct
*work
)
401 struct drm_i915_private
*dev_priv
;
402 struct intel_csr
*csr
;
403 const struct firmware
*fw
;
406 dev_priv
= container_of(work
, typeof(*dev_priv
), csr
.work
);
407 csr
= &dev_priv
->csr
;
409 ret
= request_firmware(&fw
, dev_priv
->csr
.fw_path
,
410 &dev_priv
->dev
->pdev
->dev
);
412 dev_priv
->csr
.dmc_payload
= parse_csr_fw(dev_priv
, fw
);
414 if (dev_priv
->csr
.dmc_payload
) {
415 intel_csr_load_program(dev_priv
);
417 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
419 DRM_INFO("Finished loading %s (v%u.%u)\n",
420 dev_priv
->csr
.fw_path
,
421 CSR_VERSION_MAJOR(csr
->version
),
422 CSR_VERSION_MINOR(csr
->version
));
424 dev_notice(dev_priv
->dev
->dev
,
425 "Failed to load DMC firmware"
426 " [" FIRMWARE_URL
"],"
427 " disabling runtime power management.\n");
430 release_firmware(fw
);
434 * intel_csr_ucode_init() - initialize the firmware loading.
435 * @dev_priv: i915 drm device.
437 * This function is called at the time of loading the display driver to read
438 * firmware from a .bin file and copied into a internal memory.
440 void intel_csr_ucode_init(struct drm_i915_private
*dev_priv
)
442 struct intel_csr
*csr
= &dev_priv
->csr
;
444 INIT_WORK(&dev_priv
->csr
.work
, csr_load_work_fn
);
446 if (!HAS_CSR(dev_priv
))
449 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
450 csr
->fw_path
= I915_CSR_SKL
;
451 else if (IS_BROXTON(dev_priv
))
452 csr
->fw_path
= I915_CSR_BXT
;
454 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
458 DRM_DEBUG_KMS("Loading %s\n", csr
->fw_path
);
461 * Obtain a runtime pm reference, until CSR is loaded,
462 * to avoid entering runtime-suspend.
464 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
466 schedule_work(&dev_priv
->csr
.work
);
470 * intel_csr_ucode_fini() - unload the CSR firmware.
471 * @dev_priv: i915 drm device.
473 * Firmmware unloading includes freeing the internal momory and reset the
474 * firmware loading status.
476 void intel_csr_ucode_fini(struct drm_i915_private
*dev_priv
)
478 if (!HAS_CSR(dev_priv
))
481 flush_work(&dev_priv
->csr
.work
);
483 kfree(dev_priv
->csr
.dmc_payload
);