2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 const u32
*ddi_translations
= ((use_fdi_mode
) ?
94 hsw_ddi_translations_fdi
:
95 hsw_ddi_translations_dp
);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode
? "FDI" : "DP");
101 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
106 I915_WRITE(reg
, ddi_translations
[i
]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device
*dev
)
119 for (port
= PORT_A
; port
< PORT_E
; port
++)
120 intel_prepare_ddi_buffers(dev
, port
, false);
122 /* DDI E is the suggested one to work in FDI mode, so program is as such by
123 * default. It will have to be re-programmed in case a digital DP output
124 * will be detected on it
126 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
130 static const long hsw_ddi_buf_ctl_values
[] = {
131 DDI_BUF_EMP_400MV_0DB_HSW
,
132 DDI_BUF_EMP_400MV_3_5DB_HSW
,
133 DDI_BUF_EMP_400MV_6DB_HSW
,
134 DDI_BUF_EMP_400MV_9_5DB_HSW
,
135 DDI_BUF_EMP_600MV_0DB_HSW
,
136 DDI_BUF_EMP_600MV_3_5DB_HSW
,
137 DDI_BUF_EMP_600MV_6DB_HSW
,
138 DDI_BUF_EMP_800MV_0DB_HSW
,
139 DDI_BUF_EMP_800MV_3_5DB_HSW
143 /* Starting with Haswell, different DDI ports can work in FDI mode for
144 * connection to the PCH-located connectors. For this, it is necessary to train
145 * both the DDI port and PCH receiver for the desired DDI buffer settings.
147 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
148 * please note that when FDI mode is active on DDI E, it shares 2 lines with
149 * DDI A (which is used for eDP)
152 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
154 struct drm_device
*dev
= crtc
->dev
;
155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
157 u32 temp
, i
, rx_ctl_val
;
159 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
160 * mode set "sequence for CRT port" document:
161 * - TP1 to TP2 time with the default value
164 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
165 FDI_RX_PWRDN_LANE0_VAL(2) |
166 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
168 /* Enable the PCH Receiver FDI PLL */
169 rx_ctl_val
= FDI_RX_PLL_ENABLE
| FDI_RX_ENHANCE_FRAME_ENABLE
|
170 ((intel_crtc
->fdi_lanes
- 1) << 19);
171 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
172 POSTING_READ(_FDI_RXA_CTL
);
175 /* Switch from Rawclk to PCDclk */
176 rx_ctl_val
|= FDI_PCDCLK
;
177 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
179 /* Configure Port Clock Select */
180 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
182 /* Start the training iterating through available voltages and emphasis,
183 * testing each value twice. */
184 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
185 /* Configure DP_TP_CTL with auto-training */
186 I915_WRITE(DP_TP_CTL(PORT_E
),
187 DP_TP_CTL_FDI_AUTOTRAIN
|
188 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
189 DP_TP_CTL_LINK_TRAIN_PAT1
|
192 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
193 I915_WRITE(DDI_BUF_CTL(PORT_E
),
195 ((intel_crtc
->fdi_lanes
- 1) << 1) |
196 hsw_ddi_buf_ctl_values
[i
/ 2]);
197 POSTING_READ(DDI_BUF_CTL(PORT_E
));
201 /* Program PCH FDI Receiver TU */
202 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
204 /* Enable PCH FDI Receiver with auto-training */
205 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
206 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
207 POSTING_READ(_FDI_RXA_CTL
);
209 /* Wait for FDI receiver lane calibration */
212 /* Unset FDI_RX_MISC pwrdn lanes */
213 temp
= I915_READ(_FDI_RXA_MISC
);
214 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
215 I915_WRITE(_FDI_RXA_MISC
, temp
);
216 POSTING_READ(_FDI_RXA_MISC
);
218 /* Wait for FDI auto training time */
221 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
222 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
223 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
225 /* Enable normal pixel sending for FDI */
226 I915_WRITE(DP_TP_CTL(PORT_E
),
227 DP_TP_CTL_FDI_AUTOTRAIN
|
228 DP_TP_CTL_LINK_TRAIN_NORMAL
|
229 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
235 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
236 I915_WRITE(DP_TP_CTL(PORT_E
),
237 I915_READ(DP_TP_CTL(PORT_E
)) & ~DP_TP_CTL_ENABLE
);
239 rx_ctl_val
&= ~FDI_RX_ENABLE
;
240 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
242 /* Reset FDI_RX_MISC pwrdn lanes */
243 temp
= I915_READ(_FDI_RXA_MISC
);
244 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
245 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
246 I915_WRITE(_FDI_RXA_MISC
, temp
);
249 DRM_ERROR("FDI link training failed!\n");
252 /* WRPLL clock dividers */
253 struct wrpll_tmds_clock
{
255 u16 p
; /* Post divider */
256 u16 n2
; /* Feedback divider */
257 u16 r2
; /* Reference divider */
260 /* Table of matching values for WRPLL clocks programming for each frequency.
261 * The code assumes this table is sorted. */
262 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
277 {27027, 18, 100, 111},
305 {40541, 22, 147, 89},
315 {44900, 20, 108, 65},
331 {54054, 16, 173, 108},
383 {81081, 6, 100, 111},
428 {108108, 8, 173, 108},
435 {111264, 8, 150, 91},
479 {135250, 6, 167, 111},
502 {148352, 4, 100, 91},
524 {162162, 4, 131, 109},
532 {169000, 4, 104, 83},
579 {202000, 4, 112, 75},
581 {203000, 4, 146, 97},
638 static void intel_ddi_mode_set(struct drm_encoder
*encoder
,
639 struct drm_display_mode
*mode
,
640 struct drm_display_mode
*adjusted_mode
)
642 struct drm_crtc
*crtc
= encoder
->crtc
;
643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
644 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
645 int port
= intel_ddi_get_encoder_port(intel_encoder
);
646 int pipe
= intel_crtc
->pipe
;
647 int type
= intel_encoder
->type
;
649 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
650 port_name(port
), pipe_name(pipe
));
652 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
653 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
655 intel_dp
->DP
= DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
656 switch (intel_dp
->lane_count
) {
658 intel_dp
->DP
|= DDI_PORT_WIDTH_X1
;
661 intel_dp
->DP
|= DDI_PORT_WIDTH_X2
;
664 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
667 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
668 WARN(1, "Unexpected DP lane count %d\n",
669 intel_dp
->lane_count
);
673 if (intel_dp
->has_audio
) {
674 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
675 pipe_name(intel_crtc
->pipe
));
678 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
679 intel_write_eld(encoder
, adjusted_mode
);
682 intel_dp_init_link_config(intel_dp
);
684 } else if (type
== INTEL_OUTPUT_HDMI
) {
685 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
687 if (intel_hdmi
->has_audio
) {
688 /* Proper support for digital audio needs a new logic
689 * and a new set of registers, so we leave it for future
692 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
693 pipe_name(intel_crtc
->pipe
));
696 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
697 intel_write_eld(encoder
, adjusted_mode
);
700 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
704 static struct intel_encoder
*
705 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
707 struct drm_device
*dev
= crtc
->dev
;
708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
709 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
710 int num_encoders
= 0;
712 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
717 if (num_encoders
!= 1)
718 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders
,
725 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
727 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
728 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
729 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
732 switch (intel_crtc
->ddi_pll_sel
) {
733 case PORT_CLK_SEL_SPLL
:
734 plls
->spll_refcount
--;
735 if (plls
->spll_refcount
== 0) {
736 DRM_DEBUG_KMS("Disabling SPLL\n");
737 val
= I915_READ(SPLL_CTL
);
738 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
739 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
740 POSTING_READ(SPLL_CTL
);
743 case PORT_CLK_SEL_WRPLL1
:
744 plls
->wrpll1_refcount
--;
745 if (plls
->wrpll1_refcount
== 0) {
746 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
747 val
= I915_READ(WRPLL_CTL1
);
748 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
749 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
750 POSTING_READ(WRPLL_CTL1
);
753 case PORT_CLK_SEL_WRPLL2
:
754 plls
->wrpll2_refcount
--;
755 if (plls
->wrpll2_refcount
== 0) {
756 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
757 val
= I915_READ(WRPLL_CTL2
);
758 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
759 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
760 POSTING_READ(WRPLL_CTL2
);
765 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
766 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
767 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
769 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
772 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
776 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
777 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
780 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
783 *p
= wrpll_tmds_clock_table
[i
].p
;
784 *n2
= wrpll_tmds_clock_table
[i
].n2
;
785 *r2
= wrpll_tmds_clock_table
[i
].r2
;
787 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
788 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
789 wrpll_tmds_clock_table
[i
].clock
, clock
);
791 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
792 clock
, *p
, *n2
, *r2
);
795 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
798 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
799 struct drm_encoder
*encoder
= &intel_encoder
->base
;
800 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
801 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
802 int type
= intel_encoder
->type
;
803 enum pipe pipe
= intel_crtc
->pipe
;
806 /* TODO: reuse PLLs when possible (compare values) */
808 intel_ddi_put_crtc_pll(crtc
);
810 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
811 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
813 switch (intel_dp
->link_bw
) {
814 case DP_LINK_BW_1_62
:
815 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
818 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
821 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
824 DRM_ERROR("Link bandwidth %d unsupported\n",
829 /* We don't need to turn any PLL on because we'll use LCPLL. */
832 } else if (type
== INTEL_OUTPUT_HDMI
) {
835 if (plls
->wrpll1_refcount
== 0) {
836 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
838 plls
->wrpll1_refcount
++;
840 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
841 } else if (plls
->wrpll2_refcount
== 0) {
842 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
844 plls
->wrpll2_refcount
++;
846 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
848 DRM_ERROR("No WRPLLs available!\n");
852 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
853 "WRPLL already enabled\n");
855 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
857 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
858 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
859 WRPLL_DIVIDER_POST(p
);
861 } else if (type
== INTEL_OUTPUT_ANALOG
) {
862 if (plls
->spll_refcount
== 0) {
863 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
865 plls
->spll_refcount
++;
867 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
870 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
871 "SPLL already enabled\n");
873 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
876 WARN(1, "Invalid DDI encoder type %d\n", type
);
880 I915_WRITE(reg
, val
);
886 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
888 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
889 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
890 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
891 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
892 int type
= intel_encoder
->type
;
895 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
897 temp
= TRANS_MSA_SYNC_CLK
;
898 switch (intel_crtc
->bpp
) {
900 temp
|= TRANS_MSA_6_BPC
;
903 temp
|= TRANS_MSA_8_BPC
;
906 temp
|= TRANS_MSA_10_BPC
;
909 temp
|= TRANS_MSA_12_BPC
;
912 temp
|= TRANS_MSA_8_BPC
;
913 WARN(1, "%d bpp unsupported by DDI function\n",
916 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
920 void intel_ddi_enable_pipe_func(struct drm_crtc
*crtc
)
922 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
923 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
924 struct drm_encoder
*encoder
= &intel_encoder
->base
;
925 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
926 enum pipe pipe
= intel_crtc
->pipe
;
927 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
928 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
929 int type
= intel_encoder
->type
;
932 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
933 temp
= TRANS_DDI_FUNC_ENABLE
;
934 temp
|= TRANS_DDI_SELECT_PORT(port
);
936 switch (intel_crtc
->bpp
) {
938 temp
|= TRANS_DDI_BPC_6
;
941 temp
|= TRANS_DDI_BPC_8
;
944 temp
|= TRANS_DDI_BPC_10
;
947 temp
|= TRANS_DDI_BPC_12
;
950 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
954 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
955 temp
|= TRANS_DDI_PVSYNC
;
956 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
957 temp
|= TRANS_DDI_PHSYNC
;
959 if (cpu_transcoder
== TRANSCODER_EDP
) {
962 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
965 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
968 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
976 if (type
== INTEL_OUTPUT_HDMI
) {
977 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
979 if (intel_hdmi
->has_hdmi_sink
)
980 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
982 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
984 } else if (type
== INTEL_OUTPUT_ANALOG
) {
985 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
986 temp
|= (intel_crtc
->fdi_lanes
- 1) << 1;
988 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
989 type
== INTEL_OUTPUT_EDP
) {
990 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
992 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
994 switch (intel_dp
->lane_count
) {
996 temp
|= TRANS_DDI_PORT_WIDTH_X1
;
999 temp
|= TRANS_DDI_PORT_WIDTH_X2
;
1002 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1005 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1006 WARN(1, "Unsupported lane count %d\n",
1007 intel_dp
->lane_count
);
1011 WARN(1, "Invalid encoder type %d for pipe %d\n",
1012 intel_encoder
->type
, pipe
);
1015 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1018 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1019 enum transcoder cpu_transcoder
)
1021 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1022 uint32_t val
= I915_READ(reg
);
1024 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1025 val
|= TRANS_DDI_PORT_NONE
;
1026 I915_WRITE(reg
, val
);
1029 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1031 struct drm_device
*dev
= intel_connector
->base
.dev
;
1032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1033 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1034 int type
= intel_connector
->base
.connector_type
;
1035 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1037 enum transcoder cpu_transcoder
;
1040 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1044 cpu_transcoder
= TRANSCODER_EDP
;
1046 cpu_transcoder
= pipe
;
1048 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1050 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1051 case TRANS_DDI_MODE_SELECT_HDMI
:
1052 case TRANS_DDI_MODE_SELECT_DVI
:
1053 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1055 case TRANS_DDI_MODE_SELECT_DP_SST
:
1056 if (type
== DRM_MODE_CONNECTOR_eDP
)
1058 case TRANS_DDI_MODE_SELECT_DP_MST
:
1059 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1061 case TRANS_DDI_MODE_SELECT_FDI
:
1062 return (type
== DRM_MODE_CONNECTOR_VGA
);
1069 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1072 struct drm_device
*dev
= encoder
->base
.dev
;
1073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1074 enum port port
= intel_ddi_get_encoder_port(encoder
);
1078 tmp
= I915_READ(DDI_BUF_CTL(port
));
1080 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1083 if (port
== PORT_A
) {
1084 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1086 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1087 case TRANS_DDI_EDP_INPUT_A_ON
:
1088 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1091 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1094 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1101 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1102 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1104 if ((tmp
& TRANS_DDI_PORT_MASK
)
1105 == TRANS_DDI_SELECT_PORT(port
)) {
1112 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port
);
1117 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1122 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1126 if (cpu_transcoder
== TRANSCODER_EDP
) {
1129 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1130 temp
&= TRANS_DDI_PORT_MASK
;
1132 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1133 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1137 ret
= I915_READ(PORT_CLK_SEL(port
));
1139 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1140 pipe_name(pipe
), port_name(port
), ret
);
1145 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1149 struct intel_crtc
*intel_crtc
;
1151 for_each_pipe(pipe
) {
1153 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1155 if (!intel_crtc
->active
)
1158 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1161 switch (intel_crtc
->ddi_pll_sel
) {
1162 case PORT_CLK_SEL_SPLL
:
1163 dev_priv
->ddi_plls
.spll_refcount
++;
1165 case PORT_CLK_SEL_WRPLL1
:
1166 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1168 case PORT_CLK_SEL_WRPLL2
:
1169 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1175 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1177 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1178 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1179 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1180 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1181 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1183 if (cpu_transcoder
!= TRANSCODER_EDP
)
1184 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1185 TRANS_CLK_SEL_PORT(port
));
1188 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1190 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1191 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1193 if (cpu_transcoder
!= TRANSCODER_EDP
)
1194 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1195 TRANS_CLK_SEL_DISABLED
);
1198 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1200 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1201 struct drm_crtc
*crtc
= encoder
->crtc
;
1202 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1203 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1204 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1205 int type
= intel_encoder
->type
;
1207 if (type
== INTEL_OUTPUT_EDP
) {
1208 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1209 ironlake_edp_panel_vdd_on(intel_dp
);
1210 ironlake_edp_panel_on(intel_dp
);
1211 ironlake_edp_panel_vdd_off(intel_dp
, true);
1214 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1215 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1217 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1218 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1220 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1221 intel_dp_start_link_train(intel_dp
);
1222 intel_dp_complete_link_train(intel_dp
);
1226 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
1229 uint32_t reg
= DDI_BUF_CTL(port
);
1232 for (i
= 0; i
< 8; i
++) {
1234 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
1237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
1240 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1242 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1243 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1244 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1245 int type
= intel_encoder
->type
;
1249 val
= I915_READ(DDI_BUF_CTL(port
));
1250 if (val
& DDI_BUF_CTL_ENABLE
) {
1251 val
&= ~DDI_BUF_CTL_ENABLE
;
1252 I915_WRITE(DDI_BUF_CTL(port
), val
);
1256 val
= I915_READ(DP_TP_CTL(port
));
1257 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1258 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1259 I915_WRITE(DP_TP_CTL(port
), val
);
1262 intel_wait_ddi_buf_idle(dev_priv
, port
);
1264 if (type
== INTEL_OUTPUT_EDP
) {
1265 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1266 ironlake_edp_panel_vdd_on(intel_dp
);
1267 ironlake_edp_panel_off(intel_dp
);
1270 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1273 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1275 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1276 struct drm_device
*dev
= encoder
->dev
;
1277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1278 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1279 int type
= intel_encoder
->type
;
1281 if (type
== INTEL_OUTPUT_HDMI
) {
1282 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1283 * are ignored so nothing special needs to be done besides
1284 * enabling the port.
1286 I915_WRITE(DDI_BUF_CTL(port
), DDI_BUF_CTL_ENABLE
);
1287 } else if (type
== INTEL_OUTPUT_EDP
) {
1288 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1290 ironlake_edp_backlight_on(intel_dp
);
1294 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1296 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1297 int type
= intel_encoder
->type
;
1299 if (type
== INTEL_OUTPUT_EDP
) {
1300 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1302 ironlake_edp_backlight_off(intel_dp
);
1306 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1308 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1310 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1313 else if (IS_ULT(dev_priv
->dev
))
1319 void intel_ddi_pll_init(struct drm_device
*dev
)
1321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1322 uint32_t val
= I915_READ(LCPLL_CTL
);
1324 /* The LCPLL register should be turned on by the BIOS. For now let's
1325 * just check its state and print errors in case something is wrong.
1326 * Don't even try to turn it on.
1329 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1330 intel_ddi_get_cdclk_freq(dev_priv
));
1332 if (val
& LCPLL_CD_SOURCE_FCLK
)
1333 DRM_ERROR("CDCLK source is not LCPLL\n");
1335 if (val
& LCPLL_PLL_DISABLE
)
1336 DRM_ERROR("LCPLL is disabled\n");
1339 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1341 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1342 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1343 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1344 enum port port
= intel_dig_port
->port
;
1348 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1349 val
= I915_READ(DDI_BUF_CTL(port
));
1350 if (val
& DDI_BUF_CTL_ENABLE
) {
1351 val
&= ~DDI_BUF_CTL_ENABLE
;
1352 I915_WRITE(DDI_BUF_CTL(port
), val
);
1356 val
= I915_READ(DP_TP_CTL(port
));
1357 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1358 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1359 I915_WRITE(DP_TP_CTL(port
), val
);
1360 POSTING_READ(DP_TP_CTL(port
));
1363 intel_wait_ddi_buf_idle(dev_priv
, port
);
1366 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1367 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1368 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1369 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1370 I915_WRITE(DP_TP_CTL(port
), val
);
1371 POSTING_READ(DP_TP_CTL(port
));
1373 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1374 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1375 POSTING_READ(DDI_BUF_CTL(port
));
1380 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1382 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1383 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1386 intel_ddi_post_disable(intel_encoder
);
1388 val
= I915_READ(_FDI_RXA_CTL
);
1389 val
&= ~FDI_RX_ENABLE
;
1390 I915_WRITE(_FDI_RXA_CTL
, val
);
1392 val
= I915_READ(_FDI_RXA_MISC
);
1393 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1394 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1395 I915_WRITE(_FDI_RXA_MISC
, val
);
1397 val
= I915_READ(_FDI_RXA_CTL
);
1399 I915_WRITE(_FDI_RXA_CTL
, val
);
1401 val
= I915_READ(_FDI_RXA_CTL
);
1402 val
&= ~FDI_RX_PLL_ENABLE
;
1403 I915_WRITE(_FDI_RXA_CTL
, val
);
1406 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1408 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1409 int type
= intel_encoder
->type
;
1411 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1412 intel_dp_check_link_status(intel_dp
);
1415 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1417 /* HDMI has nothing special to destroy, so we can go with this. */
1418 intel_dp_encoder_destroy(encoder
);
1421 static bool intel_ddi_mode_fixup(struct drm_encoder
*encoder
,
1422 const struct drm_display_mode
*mode
,
1423 struct drm_display_mode
*adjusted_mode
)
1425 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1426 int type
= intel_encoder
->type
;
1428 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "mode_fixup() on unknown output!\n");
1430 if (type
== INTEL_OUTPUT_HDMI
)
1431 return intel_hdmi_mode_fixup(encoder
, mode
, adjusted_mode
);
1433 return intel_dp_mode_fixup(encoder
, mode
, adjusted_mode
);
1436 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1437 .destroy
= intel_ddi_destroy
,
1440 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs
= {
1441 .mode_fixup
= intel_ddi_mode_fixup
,
1442 .mode_set
= intel_ddi_mode_set
,
1443 .disable
= intel_encoder_noop
,
1446 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1448 struct intel_digital_port
*intel_dig_port
;
1449 struct intel_encoder
*intel_encoder
;
1450 struct drm_encoder
*encoder
;
1451 struct intel_connector
*hdmi_connector
= NULL
;
1452 struct intel_connector
*dp_connector
= NULL
;
1454 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1455 if (!intel_dig_port
)
1458 dp_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1459 if (!dp_connector
) {
1460 kfree(intel_dig_port
);
1464 if (port
!= PORT_A
) {
1465 hdmi_connector
= kzalloc(sizeof(struct intel_connector
),
1467 if (!hdmi_connector
) {
1468 kfree(dp_connector
);
1469 kfree(intel_dig_port
);
1474 intel_encoder
= &intel_dig_port
->base
;
1475 encoder
= &intel_encoder
->base
;
1477 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1478 DRM_MODE_ENCODER_TMDS
);
1479 drm_encoder_helper_add(encoder
, &intel_ddi_helper_funcs
);
1481 intel_encoder
->enable
= intel_enable_ddi
;
1482 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1483 intel_encoder
->disable
= intel_disable_ddi
;
1484 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1485 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1487 intel_dig_port
->port
= port
;
1489 intel_dig_port
->hdmi
.sdvox_reg
= DDI_BUF_CTL(port
);
1491 intel_dig_port
->hdmi
.sdvox_reg
= 0;
1492 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1494 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1495 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1496 intel_encoder
->cloneable
= false;
1497 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1500 intel_hdmi_init_connector(intel_dig_port
, hdmi_connector
);
1501 intel_dp_init_connector(intel_dig_port
, dp_connector
);