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Merge remote-tracking branches 'asoc/topic/ux500' and 'asoc/topic/wm8962' into asoc...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
51 };
52
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
63 };
64
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
79 };
80
81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
91 };
92
93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
103 };
104
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
115 };
116
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
129 };
130
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 },
142 };
143
144 /* Skylake U */
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x80007011, 0x000000CD, 0x1 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake Y */
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x3 },
162 { 0x80009010, 0x000000C0, 0x3 },
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 },
168 };
169
170 /*
171 * Skylake H and S
172 * eDP 1.4 low vswing translation parameters
173 */
174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185 };
186
187 /*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
202 };
203
204 /*
205 * Skylake Y
206 * eDP 1.4 low vswing translation parameters
207 */
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219 };
220
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x80006012, 0x000000CD, 0x1 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
234 };
235
236 /* Skylake Y */
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x80007011, 0x000000CB, 0x3 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x80006013, 0x000000C0, 0x3 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
249 };
250
251 struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257 };
258
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
271 };
272
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285 };
286
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302 };
303
304 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
306
307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
310 {
311 struct drm_encoder *encoder = &intel_encoder->base;
312
313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
317 break;
318 default:
319 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
320 /* fallthrough and treat as unknown */
321 case INTEL_OUTPUT_DP:
322 case INTEL_OUTPUT_EDP:
323 case INTEL_OUTPUT_HDMI:
324 case INTEL_OUTPUT_UNKNOWN:
325 *dig_port = enc_to_dig_port(encoder);
326 *port = (*dig_port)->port;
327 break;
328 case INTEL_OUTPUT_ANALOG:
329 *dig_port = NULL;
330 *port = PORT_E;
331 break;
332 }
333 }
334
335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336 {
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343 }
344
345 static const struct ddi_buf_trans *
346 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
347 {
348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
350 return skl_y_ddi_translations_dp;
351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
353 return skl_u_ddi_translations_dp;
354 } else {
355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
356 return skl_ddi_translations_dp;
357 }
358 }
359
360 static const struct ddi_buf_trans *
361 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
362 {
363 if (dev_priv->vbt.edp.low_vswing) {
364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
366 return skl_y_ddi_translations_edp;
367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
369 return skl_u_ddi_translations_edp;
370 } else {
371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
372 return skl_ddi_translations_edp;
373 }
374 }
375
376 return skl_get_buf_trans_dp(dev_priv, n_entries);
377 }
378
379 static const struct ddi_buf_trans *
380 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
381 {
382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
384 return skl_y_ddi_translations_hdmi;
385 } else {
386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
387 return skl_ddi_translations_hdmi;
388 }
389 }
390
391 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
392 {
393 int n_hdmi_entries;
394 int hdmi_level;
395 int hdmi_default_entry;
396
397 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
398
399 if (IS_BROXTON(dev_priv))
400 return hdmi_level;
401
402 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
403 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
404 hdmi_default_entry = 8;
405 } else if (IS_BROADWELL(dev_priv)) {
406 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
407 hdmi_default_entry = 7;
408 } else if (IS_HASWELL(dev_priv)) {
409 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
410 hdmi_default_entry = 6;
411 } else {
412 WARN(1, "ddi translation table missing\n");
413 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
414 hdmi_default_entry = 7;
415 }
416
417 /* Choose a good default if VBT is badly populated */
418 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
419 hdmi_level >= n_hdmi_entries)
420 hdmi_level = hdmi_default_entry;
421
422 return hdmi_level;
423 }
424
425 /*
426 * Starting with Haswell, DDI port buffers must be programmed with correct
427 * values in advance. The buffer values are different for FDI and DP modes,
428 * but the HDMI/DVI fields are shared among those. So we program the DDI
429 * in either FDI or DP modes only, as HDMI connections will work with both
430 * of those
431 */
432 void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
433 {
434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
435 u32 iboost_bit = 0;
436 int i, n_hdmi_entries, n_dp_entries, n_edp_entries,
437 size;
438 int hdmi_level;
439 enum port port;
440 const struct ddi_buf_trans *ddi_translations_fdi;
441 const struct ddi_buf_trans *ddi_translations_dp;
442 const struct ddi_buf_trans *ddi_translations_edp;
443 const struct ddi_buf_trans *ddi_translations_hdmi;
444 const struct ddi_buf_trans *ddi_translations;
445
446 port = intel_ddi_get_encoder_port(encoder);
447 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
448
449 if (IS_BROXTON(dev_priv)) {
450 if (encoder->type != INTEL_OUTPUT_HDMI)
451 return;
452
453 /* Vswing programming for HDMI */
454 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
455 INTEL_OUTPUT_HDMI);
456 return;
457 }
458
459 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
460 ddi_translations_fdi = NULL;
461 ddi_translations_dp =
462 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
463 ddi_translations_edp =
464 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
465 ddi_translations_hdmi =
466 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
467 /* If we're boosting the current, set bit 31 of trans1 */
468 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
469 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
470 iboost_bit = 1<<31;
471
472 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
473 port != PORT_A && port != PORT_E &&
474 n_edp_entries > 9))
475 n_edp_entries = 9;
476 } else if (IS_BROADWELL(dev_priv)) {
477 ddi_translations_fdi = bdw_ddi_translations_fdi;
478 ddi_translations_dp = bdw_ddi_translations_dp;
479
480 if (dev_priv->vbt.edp.low_vswing) {
481 ddi_translations_edp = bdw_ddi_translations_edp;
482 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
483 } else {
484 ddi_translations_edp = bdw_ddi_translations_dp;
485 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
486 }
487
488 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
489
490 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
491 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
492 } else if (IS_HASWELL(dev_priv)) {
493 ddi_translations_fdi = hsw_ddi_translations_fdi;
494 ddi_translations_dp = hsw_ddi_translations_dp;
495 ddi_translations_edp = hsw_ddi_translations_dp;
496 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
497 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
498 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
499 } else {
500 WARN(1, "ddi translation table missing\n");
501 ddi_translations_edp = bdw_ddi_translations_dp;
502 ddi_translations_fdi = bdw_ddi_translations_fdi;
503 ddi_translations_dp = bdw_ddi_translations_dp;
504 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
505 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
506 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
507 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
508 }
509
510 switch (encoder->type) {
511 case INTEL_OUTPUT_EDP:
512 ddi_translations = ddi_translations_edp;
513 size = n_edp_entries;
514 break;
515 case INTEL_OUTPUT_DP:
516 case INTEL_OUTPUT_HDMI:
517 ddi_translations = ddi_translations_dp;
518 size = n_dp_entries;
519 break;
520 case INTEL_OUTPUT_ANALOG:
521 ddi_translations = ddi_translations_fdi;
522 size = n_dp_entries;
523 break;
524 default:
525 BUG();
526 }
527
528 for (i = 0; i < size; i++) {
529 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
530 ddi_translations[i].trans1 | iboost_bit);
531 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
532 ddi_translations[i].trans2);
533 }
534
535 if (encoder->type != INTEL_OUTPUT_HDMI)
536 return;
537
538 /* Entry 9 is for HDMI: */
539 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
540 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
541 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
542 ddi_translations_hdmi[hdmi_level].trans2);
543 }
544
545 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
546 enum port port)
547 {
548 i915_reg_t reg = DDI_BUF_CTL(port);
549 int i;
550
551 for (i = 0; i < 16; i++) {
552 udelay(1);
553 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
554 return;
555 }
556 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
557 }
558
559 /* Starting with Haswell, different DDI ports can work in FDI mode for
560 * connection to the PCH-located connectors. For this, it is necessary to train
561 * both the DDI port and PCH receiver for the desired DDI buffer settings.
562 *
563 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
564 * please note that when FDI mode is active on DDI E, it shares 2 lines with
565 * DDI A (which is used for eDP)
566 */
567
568 void hsw_fdi_link_train(struct drm_crtc *crtc)
569 {
570 struct drm_device *dev = crtc->dev;
571 struct drm_i915_private *dev_priv = to_i915(dev);
572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
573 struct intel_encoder *encoder;
574 u32 temp, i, rx_ctl_val;
575
576 for_each_encoder_on_crtc(dev, crtc, encoder) {
577 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
578 intel_prepare_ddi_buffer(encoder);
579 }
580
581 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
582 * mode set "sequence for CRT port" document:
583 * - TP1 to TP2 time with the default value
584 * - FDI delay to 90h
585 *
586 * WaFDIAutoLinkSetTimingOverrride:hsw
587 */
588 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
589 FDI_RX_PWRDN_LANE0_VAL(2) |
590 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
591
592 /* Enable the PCH Receiver FDI PLL */
593 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
594 FDI_RX_PLL_ENABLE |
595 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
596 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
597 POSTING_READ(FDI_RX_CTL(PIPE_A));
598 udelay(220);
599
600 /* Switch from Rawclk to PCDclk */
601 rx_ctl_val |= FDI_PCDCLK;
602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603
604 /* Configure Port Clock Select */
605 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
606 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
607
608 /* Start the training iterating through available voltages and emphasis,
609 * testing each value twice. */
610 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
611 /* Configure DP_TP_CTL with auto-training */
612 I915_WRITE(DP_TP_CTL(PORT_E),
613 DP_TP_CTL_FDI_AUTOTRAIN |
614 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
615 DP_TP_CTL_LINK_TRAIN_PAT1 |
616 DP_TP_CTL_ENABLE);
617
618 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
619 * DDI E does not support port reversal, the functionality is
620 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
621 * port reversal bit */
622 I915_WRITE(DDI_BUF_CTL(PORT_E),
623 DDI_BUF_CTL_ENABLE |
624 ((intel_crtc->config->fdi_lanes - 1) << 1) |
625 DDI_BUF_TRANS_SELECT(i / 2));
626 POSTING_READ(DDI_BUF_CTL(PORT_E));
627
628 udelay(600);
629
630 /* Program PCH FDI Receiver TU */
631 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
632
633 /* Enable PCH FDI Receiver with auto-training */
634 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
635 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
636 POSTING_READ(FDI_RX_CTL(PIPE_A));
637
638 /* Wait for FDI receiver lane calibration */
639 udelay(30);
640
641 /* Unset FDI_RX_MISC pwrdn lanes */
642 temp = I915_READ(FDI_RX_MISC(PIPE_A));
643 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
644 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
645 POSTING_READ(FDI_RX_MISC(PIPE_A));
646
647 /* Wait for FDI auto training time */
648 udelay(5);
649
650 temp = I915_READ(DP_TP_STATUS(PORT_E));
651 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
652 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
653 break;
654 }
655
656 /*
657 * Leave things enabled even if we failed to train FDI.
658 * Results in less fireworks from the state checker.
659 */
660 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
661 DRM_ERROR("FDI link training failed!\n");
662 break;
663 }
664
665 rx_ctl_val &= ~FDI_RX_ENABLE;
666 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
667 POSTING_READ(FDI_RX_CTL(PIPE_A));
668
669 temp = I915_READ(DDI_BUF_CTL(PORT_E));
670 temp &= ~DDI_BUF_CTL_ENABLE;
671 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
672 POSTING_READ(DDI_BUF_CTL(PORT_E));
673
674 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
675 temp = I915_READ(DP_TP_CTL(PORT_E));
676 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
677 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
678 I915_WRITE(DP_TP_CTL(PORT_E), temp);
679 POSTING_READ(DP_TP_CTL(PORT_E));
680
681 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
682
683 /* Reset FDI_RX_MISC pwrdn lanes */
684 temp = I915_READ(FDI_RX_MISC(PIPE_A));
685 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
686 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
687 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
688 POSTING_READ(FDI_RX_MISC(PIPE_A));
689 }
690
691 /* Enable normal pixel sending for FDI */
692 I915_WRITE(DP_TP_CTL(PORT_E),
693 DP_TP_CTL_FDI_AUTOTRAIN |
694 DP_TP_CTL_LINK_TRAIN_NORMAL |
695 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
696 DP_TP_CTL_ENABLE);
697 }
698
699 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
700 {
701 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
702 struct intel_digital_port *intel_dig_port =
703 enc_to_dig_port(&encoder->base);
704
705 intel_dp->DP = intel_dig_port->saved_port_bits |
706 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
707 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
708 }
709
710 static struct intel_encoder *
711 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
712 {
713 struct drm_device *dev = crtc->dev;
714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
715 struct intel_encoder *intel_encoder, *ret = NULL;
716 int num_encoders = 0;
717
718 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
719 ret = intel_encoder;
720 num_encoders++;
721 }
722
723 if (num_encoders != 1)
724 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
725 pipe_name(intel_crtc->pipe));
726
727 BUG_ON(ret == NULL);
728 return ret;
729 }
730
731 struct intel_encoder *
732 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
733 {
734 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
735 struct intel_encoder *ret = NULL;
736 struct drm_atomic_state *state;
737 struct drm_connector *connector;
738 struct drm_connector_state *connector_state;
739 int num_encoders = 0;
740 int i;
741
742 state = crtc_state->base.state;
743
744 for_each_connector_in_state(state, connector, connector_state, i) {
745 if (connector_state->crtc != crtc_state->base.crtc)
746 continue;
747
748 ret = to_intel_encoder(connector_state->best_encoder);
749 num_encoders++;
750 }
751
752 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
753 pipe_name(crtc->pipe));
754
755 BUG_ON(ret == NULL);
756 return ret;
757 }
758
759 #define LC_FREQ 2700
760
761 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
762 i915_reg_t reg)
763 {
764 int refclk = LC_FREQ;
765 int n, p, r;
766 u32 wrpll;
767
768 wrpll = I915_READ(reg);
769 switch (wrpll & WRPLL_PLL_REF_MASK) {
770 case WRPLL_PLL_SSC:
771 case WRPLL_PLL_NON_SSC:
772 /*
773 * We could calculate spread here, but our checking
774 * code only cares about 5% accuracy, and spread is a max of
775 * 0.5% downspread.
776 */
777 refclk = 135;
778 break;
779 case WRPLL_PLL_LCPLL:
780 refclk = LC_FREQ;
781 break;
782 default:
783 WARN(1, "bad wrpll refclk\n");
784 return 0;
785 }
786
787 r = wrpll & WRPLL_DIVIDER_REF_MASK;
788 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
789 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
790
791 /* Convert to KHz, p & r have a fixed point portion */
792 return (refclk * n * 100) / (p * r);
793 }
794
795 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
796 uint32_t dpll)
797 {
798 i915_reg_t cfgcr1_reg, cfgcr2_reg;
799 uint32_t cfgcr1_val, cfgcr2_val;
800 uint32_t p0, p1, p2, dco_freq;
801
802 cfgcr1_reg = DPLL_CFGCR1(dpll);
803 cfgcr2_reg = DPLL_CFGCR2(dpll);
804
805 cfgcr1_val = I915_READ(cfgcr1_reg);
806 cfgcr2_val = I915_READ(cfgcr2_reg);
807
808 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
809 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
810
811 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
812 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
813 else
814 p1 = 1;
815
816
817 switch (p0) {
818 case DPLL_CFGCR2_PDIV_1:
819 p0 = 1;
820 break;
821 case DPLL_CFGCR2_PDIV_2:
822 p0 = 2;
823 break;
824 case DPLL_CFGCR2_PDIV_3:
825 p0 = 3;
826 break;
827 case DPLL_CFGCR2_PDIV_7:
828 p0 = 7;
829 break;
830 }
831
832 switch (p2) {
833 case DPLL_CFGCR2_KDIV_5:
834 p2 = 5;
835 break;
836 case DPLL_CFGCR2_KDIV_2:
837 p2 = 2;
838 break;
839 case DPLL_CFGCR2_KDIV_3:
840 p2 = 3;
841 break;
842 case DPLL_CFGCR2_KDIV_1:
843 p2 = 1;
844 break;
845 }
846
847 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
848
849 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
850 1000) / 0x8000;
851
852 return dco_freq / (p0 * p1 * p2 * 5);
853 }
854
855 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
856 {
857 int dotclock;
858
859 if (pipe_config->has_pch_encoder)
860 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
861 &pipe_config->fdi_m_n);
862 else if (intel_crtc_has_dp_encoder(pipe_config))
863 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
864 &pipe_config->dp_m_n);
865 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
866 dotclock = pipe_config->port_clock * 2 / 3;
867 else
868 dotclock = pipe_config->port_clock;
869
870 if (pipe_config->pixel_multiplier)
871 dotclock /= pipe_config->pixel_multiplier;
872
873 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
874 }
875
876 static void skl_ddi_clock_get(struct intel_encoder *encoder,
877 struct intel_crtc_state *pipe_config)
878 {
879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
880 int link_clock = 0;
881 uint32_t dpll_ctl1, dpll;
882
883 dpll = pipe_config->ddi_pll_sel;
884
885 dpll_ctl1 = I915_READ(DPLL_CTRL1);
886
887 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
888 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
889 } else {
890 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
891 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
892
893 switch (link_clock) {
894 case DPLL_CTRL1_LINK_RATE_810:
895 link_clock = 81000;
896 break;
897 case DPLL_CTRL1_LINK_RATE_1080:
898 link_clock = 108000;
899 break;
900 case DPLL_CTRL1_LINK_RATE_1350:
901 link_clock = 135000;
902 break;
903 case DPLL_CTRL1_LINK_RATE_1620:
904 link_clock = 162000;
905 break;
906 case DPLL_CTRL1_LINK_RATE_2160:
907 link_clock = 216000;
908 break;
909 case DPLL_CTRL1_LINK_RATE_2700:
910 link_clock = 270000;
911 break;
912 default:
913 WARN(1, "Unsupported link rate\n");
914 break;
915 }
916 link_clock *= 2;
917 }
918
919 pipe_config->port_clock = link_clock;
920
921 ddi_dotclock_get(pipe_config);
922 }
923
924 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
925 struct intel_crtc_state *pipe_config)
926 {
927 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
928 int link_clock = 0;
929 u32 val, pll;
930
931 val = pipe_config->ddi_pll_sel;
932 switch (val & PORT_CLK_SEL_MASK) {
933 case PORT_CLK_SEL_LCPLL_810:
934 link_clock = 81000;
935 break;
936 case PORT_CLK_SEL_LCPLL_1350:
937 link_clock = 135000;
938 break;
939 case PORT_CLK_SEL_LCPLL_2700:
940 link_clock = 270000;
941 break;
942 case PORT_CLK_SEL_WRPLL1:
943 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
944 break;
945 case PORT_CLK_SEL_WRPLL2:
946 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
947 break;
948 case PORT_CLK_SEL_SPLL:
949 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
950 if (pll == SPLL_PLL_FREQ_810MHz)
951 link_clock = 81000;
952 else if (pll == SPLL_PLL_FREQ_1350MHz)
953 link_clock = 135000;
954 else if (pll == SPLL_PLL_FREQ_2700MHz)
955 link_clock = 270000;
956 else {
957 WARN(1, "bad spll freq\n");
958 return;
959 }
960 break;
961 default:
962 WARN(1, "bad port clock sel\n");
963 return;
964 }
965
966 pipe_config->port_clock = link_clock * 2;
967
968 ddi_dotclock_get(pipe_config);
969 }
970
971 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
972 enum intel_dpll_id dpll)
973 {
974 struct intel_shared_dpll *pll;
975 struct intel_dpll_hw_state *state;
976 struct dpll clock;
977
978 /* For DDI ports we always use a shared PLL. */
979 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
980 return 0;
981
982 pll = &dev_priv->shared_dplls[dpll];
983 state = &pll->config.hw_state;
984
985 clock.m1 = 2;
986 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
987 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
988 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
989 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
990 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
991 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
992
993 return chv_calc_dpll_params(100000, &clock);
994 }
995
996 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
997 struct intel_crtc_state *pipe_config)
998 {
999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000 enum port port = intel_ddi_get_encoder_port(encoder);
1001 uint32_t dpll = port;
1002
1003 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1004
1005 ddi_dotclock_get(pipe_config);
1006 }
1007
1008 void intel_ddi_clock_get(struct intel_encoder *encoder,
1009 struct intel_crtc_state *pipe_config)
1010 {
1011 struct drm_device *dev = encoder->base.dev;
1012
1013 if (INTEL_INFO(dev)->gen <= 8)
1014 hsw_ddi_clock_get(encoder, pipe_config);
1015 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1016 skl_ddi_clock_get(encoder, pipe_config);
1017 else if (IS_BROXTON(dev))
1018 bxt_ddi_clock_get(encoder, pipe_config);
1019 }
1020
1021 static bool
1022 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1023 struct intel_crtc_state *crtc_state,
1024 struct intel_encoder *intel_encoder)
1025 {
1026 struct intel_shared_dpll *pll;
1027
1028 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1029 intel_encoder);
1030 if (!pll)
1031 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1032 pipe_name(intel_crtc->pipe));
1033
1034 return pll;
1035 }
1036
1037 static bool
1038 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1039 struct intel_crtc_state *crtc_state,
1040 struct intel_encoder *intel_encoder)
1041 {
1042 struct intel_shared_dpll *pll;
1043
1044 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1045 if (pll == NULL) {
1046 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1047 pipe_name(intel_crtc->pipe));
1048 return false;
1049 }
1050
1051 return true;
1052 }
1053
1054 static bool
1055 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1056 struct intel_crtc_state *crtc_state,
1057 struct intel_encoder *intel_encoder)
1058 {
1059 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1060 }
1061
1062 /*
1063 * Tries to find a *shared* PLL for the CRTC and store it in
1064 * intel_crtc->ddi_pll_sel.
1065 *
1066 * For private DPLLs, compute_config() should do the selection for us. This
1067 * function should be folded into compute_config() eventually.
1068 */
1069 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1070 struct intel_crtc_state *crtc_state)
1071 {
1072 struct drm_device *dev = intel_crtc->base.dev;
1073 struct intel_encoder *intel_encoder =
1074 intel_ddi_get_crtc_new_encoder(crtc_state);
1075
1076 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1077 return skl_ddi_pll_select(intel_crtc, crtc_state,
1078 intel_encoder);
1079 else if (IS_BROXTON(dev))
1080 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1081 intel_encoder);
1082 else
1083 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1084 intel_encoder);
1085 }
1086
1087 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1088 {
1089 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1092 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1093 int type = intel_encoder->type;
1094 uint32_t temp;
1095
1096 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1097 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1098
1099 temp = TRANS_MSA_SYNC_CLK;
1100 switch (intel_crtc->config->pipe_bpp) {
1101 case 18:
1102 temp |= TRANS_MSA_6_BPC;
1103 break;
1104 case 24:
1105 temp |= TRANS_MSA_8_BPC;
1106 break;
1107 case 30:
1108 temp |= TRANS_MSA_10_BPC;
1109 break;
1110 case 36:
1111 temp |= TRANS_MSA_12_BPC;
1112 break;
1113 default:
1114 BUG();
1115 }
1116 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1117 }
1118 }
1119
1120 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1121 {
1122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1123 struct drm_device *dev = crtc->dev;
1124 struct drm_i915_private *dev_priv = to_i915(dev);
1125 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1126 uint32_t temp;
1127 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1128 if (state == true)
1129 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1130 else
1131 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1132 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1133 }
1134
1135 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1136 {
1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1138 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1139 struct drm_encoder *encoder = &intel_encoder->base;
1140 struct drm_device *dev = crtc->dev;
1141 struct drm_i915_private *dev_priv = to_i915(dev);
1142 enum pipe pipe = intel_crtc->pipe;
1143 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1144 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1145 int type = intel_encoder->type;
1146 uint32_t temp;
1147
1148 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1149 temp = TRANS_DDI_FUNC_ENABLE;
1150 temp |= TRANS_DDI_SELECT_PORT(port);
1151
1152 switch (intel_crtc->config->pipe_bpp) {
1153 case 18:
1154 temp |= TRANS_DDI_BPC_6;
1155 break;
1156 case 24:
1157 temp |= TRANS_DDI_BPC_8;
1158 break;
1159 case 30:
1160 temp |= TRANS_DDI_BPC_10;
1161 break;
1162 case 36:
1163 temp |= TRANS_DDI_BPC_12;
1164 break;
1165 default:
1166 BUG();
1167 }
1168
1169 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1170 temp |= TRANS_DDI_PVSYNC;
1171 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1172 temp |= TRANS_DDI_PHSYNC;
1173
1174 if (cpu_transcoder == TRANSCODER_EDP) {
1175 switch (pipe) {
1176 case PIPE_A:
1177 /* On Haswell, can only use the always-on power well for
1178 * eDP when not using the panel fitter, and when not
1179 * using motion blur mitigation (which we don't
1180 * support). */
1181 if (IS_HASWELL(dev) &&
1182 (intel_crtc->config->pch_pfit.enabled ||
1183 intel_crtc->config->pch_pfit.force_thru))
1184 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1185 else
1186 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1187 break;
1188 case PIPE_B:
1189 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1190 break;
1191 case PIPE_C:
1192 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1193 break;
1194 default:
1195 BUG();
1196 break;
1197 }
1198 }
1199
1200 if (type == INTEL_OUTPUT_HDMI) {
1201 if (intel_crtc->config->has_hdmi_sink)
1202 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1203 else
1204 temp |= TRANS_DDI_MODE_SELECT_DVI;
1205
1206 } else if (type == INTEL_OUTPUT_ANALOG) {
1207 temp |= TRANS_DDI_MODE_SELECT_FDI;
1208 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1209
1210 } else if (type == INTEL_OUTPUT_DP ||
1211 type == INTEL_OUTPUT_EDP) {
1212 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1213
1214 if (intel_dp->is_mst) {
1215 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1216 } else
1217 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1218
1219 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1220 } else if (type == INTEL_OUTPUT_DP_MST) {
1221 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1222
1223 if (intel_dp->is_mst) {
1224 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1225 } else
1226 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1227
1228 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1229 } else {
1230 WARN(1, "Invalid encoder type %d for pipe %c\n",
1231 intel_encoder->type, pipe_name(pipe));
1232 }
1233
1234 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1235 }
1236
1237 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1238 enum transcoder cpu_transcoder)
1239 {
1240 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1241 uint32_t val = I915_READ(reg);
1242
1243 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1244 val |= TRANS_DDI_PORT_NONE;
1245 I915_WRITE(reg, val);
1246 }
1247
1248 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1249 {
1250 struct drm_device *dev = intel_connector->base.dev;
1251 struct drm_i915_private *dev_priv = to_i915(dev);
1252 struct intel_encoder *intel_encoder = intel_connector->encoder;
1253 int type = intel_connector->base.connector_type;
1254 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1255 enum pipe pipe = 0;
1256 enum transcoder cpu_transcoder;
1257 enum intel_display_power_domain power_domain;
1258 uint32_t tmp;
1259 bool ret;
1260
1261 power_domain = intel_display_port_power_domain(intel_encoder);
1262 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1263 return false;
1264
1265 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1266 ret = false;
1267 goto out;
1268 }
1269
1270 if (port == PORT_A)
1271 cpu_transcoder = TRANSCODER_EDP;
1272 else
1273 cpu_transcoder = (enum transcoder) pipe;
1274
1275 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1276
1277 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1278 case TRANS_DDI_MODE_SELECT_HDMI:
1279 case TRANS_DDI_MODE_SELECT_DVI:
1280 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1281 break;
1282
1283 case TRANS_DDI_MODE_SELECT_DP_SST:
1284 ret = type == DRM_MODE_CONNECTOR_eDP ||
1285 type == DRM_MODE_CONNECTOR_DisplayPort;
1286 break;
1287
1288 case TRANS_DDI_MODE_SELECT_DP_MST:
1289 /* if the transcoder is in MST state then
1290 * connector isn't connected */
1291 ret = false;
1292 break;
1293
1294 case TRANS_DDI_MODE_SELECT_FDI:
1295 ret = type == DRM_MODE_CONNECTOR_VGA;
1296 break;
1297
1298 default:
1299 ret = false;
1300 break;
1301 }
1302
1303 out:
1304 intel_display_power_put(dev_priv, power_domain);
1305
1306 return ret;
1307 }
1308
1309 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1310 enum pipe *pipe)
1311 {
1312 struct drm_device *dev = encoder->base.dev;
1313 struct drm_i915_private *dev_priv = to_i915(dev);
1314 enum port port = intel_ddi_get_encoder_port(encoder);
1315 enum intel_display_power_domain power_domain;
1316 u32 tmp;
1317 int i;
1318 bool ret;
1319
1320 power_domain = intel_display_port_power_domain(encoder);
1321 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1322 return false;
1323
1324 ret = false;
1325
1326 tmp = I915_READ(DDI_BUF_CTL(port));
1327
1328 if (!(tmp & DDI_BUF_CTL_ENABLE))
1329 goto out;
1330
1331 if (port == PORT_A) {
1332 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1333
1334 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1335 case TRANS_DDI_EDP_INPUT_A_ON:
1336 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1337 *pipe = PIPE_A;
1338 break;
1339 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1340 *pipe = PIPE_B;
1341 break;
1342 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1343 *pipe = PIPE_C;
1344 break;
1345 }
1346
1347 ret = true;
1348
1349 goto out;
1350 }
1351
1352 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1353 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1354
1355 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1356 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1357 TRANS_DDI_MODE_SELECT_DP_MST)
1358 goto out;
1359
1360 *pipe = i;
1361 ret = true;
1362
1363 goto out;
1364 }
1365 }
1366
1367 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1368
1369 out:
1370 if (ret && IS_BROXTON(dev_priv)) {
1371 tmp = I915_READ(BXT_PHY_CTL(port));
1372 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1373 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1374 DRM_ERROR("Port %c enabled but PHY powered down? "
1375 "(PHY_CTL %08x)\n", port_name(port), tmp);
1376 }
1377
1378 intel_display_power_put(dev_priv, power_domain);
1379
1380 return ret;
1381 }
1382
1383 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1384 {
1385 struct drm_crtc *crtc = &intel_crtc->base;
1386 struct drm_device *dev = crtc->dev;
1387 struct drm_i915_private *dev_priv = to_i915(dev);
1388 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1389 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1390 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1391
1392 if (cpu_transcoder != TRANSCODER_EDP)
1393 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1394 TRANS_CLK_SEL_PORT(port));
1395 }
1396
1397 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1398 {
1399 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1400 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1401
1402 if (cpu_transcoder != TRANSCODER_EDP)
1403 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1404 TRANS_CLK_SEL_DISABLED);
1405 }
1406
1407 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1408 enum port port, uint8_t iboost)
1409 {
1410 u32 tmp;
1411
1412 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1413 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1414 if (iboost)
1415 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1416 else
1417 tmp |= BALANCE_LEG_DISABLE(port);
1418 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1419 }
1420
1421 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1422 {
1423 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1424 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1425 enum port port = intel_dig_port->port;
1426 int type = encoder->type;
1427 const struct ddi_buf_trans *ddi_translations;
1428 uint8_t iboost;
1429 uint8_t dp_iboost, hdmi_iboost;
1430 int n_entries;
1431
1432 /* VBT may override standard boost values */
1433 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1434 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1435
1436 if (type == INTEL_OUTPUT_DP) {
1437 if (dp_iboost) {
1438 iboost = dp_iboost;
1439 } else {
1440 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
1441 iboost = ddi_translations[level].i_boost;
1442 }
1443 } else if (type == INTEL_OUTPUT_EDP) {
1444 if (dp_iboost) {
1445 iboost = dp_iboost;
1446 } else {
1447 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1448
1449 if (WARN_ON(port != PORT_A &&
1450 port != PORT_E && n_entries > 9))
1451 n_entries = 9;
1452
1453 iboost = ddi_translations[level].i_boost;
1454 }
1455 } else if (type == INTEL_OUTPUT_HDMI) {
1456 if (hdmi_iboost) {
1457 iboost = hdmi_iboost;
1458 } else {
1459 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1460 iboost = ddi_translations[level].i_boost;
1461 }
1462 } else {
1463 return;
1464 }
1465
1466 /* Make sure that the requested I_boost is valid */
1467 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1468 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1469 return;
1470 }
1471
1472 _skl_ddi_set_iboost(dev_priv, port, iboost);
1473
1474 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1475 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1476 }
1477
1478 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1479 u32 level, enum port port, int type)
1480 {
1481 const struct bxt_ddi_buf_trans *ddi_translations;
1482 u32 n_entries, i;
1483 uint32_t val;
1484
1485 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1486 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1487 ddi_translations = bxt_ddi_translations_edp;
1488 } else if (type == INTEL_OUTPUT_DP
1489 || type == INTEL_OUTPUT_EDP) {
1490 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1491 ddi_translations = bxt_ddi_translations_dp;
1492 } else if (type == INTEL_OUTPUT_HDMI) {
1493 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1494 ddi_translations = bxt_ddi_translations_hdmi;
1495 } else {
1496 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1497 type);
1498 return;
1499 }
1500
1501 /* Check if default value has to be used */
1502 if (level >= n_entries ||
1503 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1504 for (i = 0; i < n_entries; i++) {
1505 if (ddi_translations[i].default_index) {
1506 level = i;
1507 break;
1508 }
1509 }
1510 }
1511
1512 /*
1513 * While we write to the group register to program all lanes at once we
1514 * can read only lane registers and we pick lanes 0/1 for that.
1515 */
1516 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1517 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1518 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1519
1520 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1521 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1522 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1523 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1524 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1525
1526 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1527 val &= ~SCALE_DCOMP_METHOD;
1528 if (ddi_translations[level].enable)
1529 val |= SCALE_DCOMP_METHOD;
1530
1531 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1532 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1533
1534 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1535
1536 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1537 val &= ~DE_EMPHASIS;
1538 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1539 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1540
1541 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1542 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1543 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1544 }
1545
1546 static uint32_t translate_signal_level(int signal_levels)
1547 {
1548 uint32_t level;
1549
1550 switch (signal_levels) {
1551 default:
1552 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1553 signal_levels);
1554 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1555 level = 0;
1556 break;
1557 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1558 level = 1;
1559 break;
1560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1561 level = 2;
1562 break;
1563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1564 level = 3;
1565 break;
1566
1567 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1568 level = 4;
1569 break;
1570 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1571 level = 5;
1572 break;
1573 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1574 level = 6;
1575 break;
1576
1577 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1578 level = 7;
1579 break;
1580 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1581 level = 8;
1582 break;
1583
1584 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1585 level = 9;
1586 break;
1587 }
1588
1589 return level;
1590 }
1591
1592 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1593 {
1594 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1595 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1596 struct intel_encoder *encoder = &dport->base;
1597 uint8_t train_set = intel_dp->train_set[0];
1598 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1599 DP_TRAIN_PRE_EMPHASIS_MASK);
1600 enum port port = dport->port;
1601 uint32_t level;
1602
1603 level = translate_signal_level(signal_levels);
1604
1605 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1606 skl_ddi_set_iboost(encoder, level);
1607 else if (IS_BROXTON(dev_priv))
1608 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1609
1610 return DDI_BUF_TRANS_SELECT(level);
1611 }
1612
1613 void intel_ddi_clk_select(struct intel_encoder *encoder,
1614 const struct intel_crtc_state *pipe_config)
1615 {
1616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1617 enum port port = intel_ddi_get_encoder_port(encoder);
1618
1619 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1620 uint32_t dpll = pipe_config->ddi_pll_sel;
1621 uint32_t val;
1622
1623 /* DDI -> PLL mapping */
1624 val = I915_READ(DPLL_CTRL2);
1625
1626 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1627 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1628 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1629 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1630
1631 I915_WRITE(DPLL_CTRL2, val);
1632
1633 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1634 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1635 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
1636 }
1637 }
1638
1639 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1640 {
1641 struct drm_encoder *encoder = &intel_encoder->base;
1642 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1643 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1644 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1645 int type = intel_encoder->type;
1646
1647 if (type == INTEL_OUTPUT_HDMI) {
1648 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1649
1650 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1651 }
1652
1653 intel_prepare_ddi_buffer(intel_encoder);
1654
1655 if (type == INTEL_OUTPUT_EDP) {
1656 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1657 intel_edp_panel_on(intel_dp);
1658 }
1659
1660 intel_ddi_clk_select(intel_encoder, crtc->config);
1661
1662 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1663 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1664
1665 intel_dp_set_link_params(intel_dp, crtc->config);
1666
1667 intel_ddi_init_dp_buf_reg(intel_encoder);
1668
1669 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1670 intel_dp_start_link_train(intel_dp);
1671 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
1672 intel_dp_stop_link_train(intel_dp);
1673 } else if (type == INTEL_OUTPUT_HDMI) {
1674 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1675 int level = intel_ddi_hdmi_level(dev_priv, port);
1676
1677 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1678 skl_ddi_set_iboost(intel_encoder, level);
1679
1680 intel_hdmi->set_infoframes(encoder,
1681 crtc->config->has_hdmi_sink,
1682 &crtc->config->base.adjusted_mode);
1683 }
1684 }
1685
1686 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1687 {
1688 struct drm_encoder *encoder = &intel_encoder->base;
1689 struct drm_device *dev = encoder->dev;
1690 struct drm_i915_private *dev_priv = to_i915(dev);
1691 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1692 int type = intel_encoder->type;
1693 uint32_t val;
1694 bool wait = false;
1695
1696 val = I915_READ(DDI_BUF_CTL(port));
1697 if (val & DDI_BUF_CTL_ENABLE) {
1698 val &= ~DDI_BUF_CTL_ENABLE;
1699 I915_WRITE(DDI_BUF_CTL(port), val);
1700 wait = true;
1701 }
1702
1703 val = I915_READ(DP_TP_CTL(port));
1704 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1705 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1706 I915_WRITE(DP_TP_CTL(port), val);
1707
1708 if (wait)
1709 intel_wait_ddi_buf_idle(dev_priv, port);
1710
1711 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1712 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1713 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1714 intel_edp_panel_vdd_on(intel_dp);
1715 intel_edp_panel_off(intel_dp);
1716 }
1717
1718 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1719 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1720 DPLL_CTRL2_DDI_CLK_OFF(port)));
1721 else if (INTEL_INFO(dev)->gen < 9)
1722 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1723
1724 if (type == INTEL_OUTPUT_HDMI) {
1725 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1726
1727 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1728 }
1729 }
1730
1731 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1732 {
1733 struct drm_encoder *encoder = &intel_encoder->base;
1734 struct drm_crtc *crtc = encoder->crtc;
1735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1736 struct drm_device *dev = encoder->dev;
1737 struct drm_i915_private *dev_priv = to_i915(dev);
1738 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1739 int type = intel_encoder->type;
1740
1741 if (type == INTEL_OUTPUT_HDMI) {
1742 struct intel_digital_port *intel_dig_port =
1743 enc_to_dig_port(encoder);
1744
1745 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1746 * are ignored so nothing special needs to be done besides
1747 * enabling the port.
1748 */
1749 I915_WRITE(DDI_BUF_CTL(port),
1750 intel_dig_port->saved_port_bits |
1751 DDI_BUF_CTL_ENABLE);
1752 } else if (type == INTEL_OUTPUT_EDP) {
1753 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1754
1755 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1756 intel_dp_stop_link_train(intel_dp);
1757
1758 intel_edp_backlight_on(intel_dp);
1759 intel_psr_enable(intel_dp);
1760 intel_edp_drrs_enable(intel_dp);
1761 }
1762
1763 if (intel_crtc->config->has_audio) {
1764 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1765 intel_audio_codec_enable(intel_encoder);
1766 }
1767 }
1768
1769 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1770 {
1771 struct drm_encoder *encoder = &intel_encoder->base;
1772 struct drm_crtc *crtc = encoder->crtc;
1773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1774 int type = intel_encoder->type;
1775 struct drm_device *dev = encoder->dev;
1776 struct drm_i915_private *dev_priv = to_i915(dev);
1777
1778 if (intel_crtc->config->has_audio) {
1779 intel_audio_codec_disable(intel_encoder);
1780 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1781 }
1782
1783 if (type == INTEL_OUTPUT_EDP) {
1784 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1785
1786 intel_edp_drrs_disable(intel_dp);
1787 intel_psr_disable(intel_dp);
1788 intel_edp_backlight_off(intel_dp);
1789 }
1790 }
1791
1792 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1793 enum dpio_phy phy)
1794 {
1795 enum port port;
1796
1797 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1798 return false;
1799
1800 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1801 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1802 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1803 phy);
1804
1805 return false;
1806 }
1807
1808 if (phy == DPIO_PHY1 &&
1809 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1810 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1811
1812 return false;
1813 }
1814
1815 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1816 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1817 phy);
1818
1819 return false;
1820 }
1821
1822 for_each_port_masked(port,
1823 phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1824 BIT(PORT_A)) {
1825 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1826
1827 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1828 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1829 "for port %c powered down "
1830 "(PHY_CTL %08x)\n",
1831 phy, port_name(port), tmp);
1832
1833 return false;
1834 }
1835 }
1836
1837 return true;
1838 }
1839
1840 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1841 {
1842 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1843
1844 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1845 }
1846
1847 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1848 enum dpio_phy phy)
1849 {
1850 if (intel_wait_for_register(dev_priv,
1851 BXT_PORT_REF_DW3(phy),
1852 GRC_DONE, GRC_DONE,
1853 10))
1854 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1855 }
1856
1857 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1858 {
1859 u32 val;
1860
1861 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
1862 /* Still read out the GRC value for state verification */
1863 if (phy == DPIO_PHY0)
1864 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
1865
1866 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
1867 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1868 "won't reprogram it\n", phy);
1869
1870 return;
1871 }
1872
1873 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1874 "force reprogramming it\n", phy);
1875 }
1876
1877 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1878 val |= GT_DISPLAY_POWER_ON(phy);
1879 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1880
1881 /*
1882 * The PHY registers start out inaccessible and respond to reads with
1883 * all 1s. Eventually they become accessible as they power up, then
1884 * the reserved bit will give the default 0. Poll on the reserved bit
1885 * becoming 0 to find when the PHY is accessible.
1886 * HW team confirmed that the time to reach phypowergood status is
1887 * anywhere between 50 us and 100us.
1888 */
1889 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1890 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
1891 DRM_ERROR("timeout during PHY%d power on\n", phy);
1892 }
1893
1894 /* Program PLL Rcomp code offset */
1895 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1896 val &= ~IREF0RC_OFFSET_MASK;
1897 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1898 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1899
1900 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1901 val &= ~IREF1RC_OFFSET_MASK;
1902 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1903 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1904
1905 /* Program power gating */
1906 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1907 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1908 SUS_CLK_CONFIG;
1909 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1910
1911 if (phy == DPIO_PHY0) {
1912 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1913 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1914 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1915 }
1916
1917 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1918 val &= ~OCL2_LDOFUSE_PWR_DIS;
1919 /*
1920 * On PHY1 disable power on the second channel, since no port is
1921 * connected there. On PHY0 both channels have a port, so leave it
1922 * enabled.
1923 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1924 * power down the second channel on PHY0 as well.
1925 *
1926 * FIXME: Clarify programming of the following, the register is
1927 * read-only with bit 6 fixed at 0 at least in stepping A.
1928 */
1929 if (phy == DPIO_PHY1)
1930 val |= OCL2_LDOFUSE_PWR_DIS;
1931 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1932
1933 if (phy == DPIO_PHY0) {
1934 uint32_t grc_code;
1935 /*
1936 * PHY0 isn't connected to an RCOMP resistor so copy over
1937 * the corresponding calibrated value from PHY1, and disable
1938 * the automatic calibration on PHY0.
1939 */
1940 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
1941 grc_code = val << GRC_CODE_FAST_SHIFT |
1942 val << GRC_CODE_SLOW_SHIFT |
1943 val;
1944 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1945
1946 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1947 val |= GRC_DIS | GRC_RDY_OVRD;
1948 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1949 }
1950
1951 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1952 val |= COMMON_RESET_DIS;
1953 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1954
1955 if (phy == DPIO_PHY1)
1956 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
1957 }
1958
1959 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1960 {
1961 uint32_t val;
1962
1963 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1964 val &= ~COMMON_RESET_DIS;
1965 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1966
1967 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1968 val &= ~GT_DISPLAY_POWER_ON(phy);
1969 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1970 }
1971
1972 static bool __printf(6, 7)
1973 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1974 i915_reg_t reg, u32 mask, u32 expected,
1975 const char *reg_fmt, ...)
1976 {
1977 struct va_format vaf;
1978 va_list args;
1979 u32 val;
1980
1981 val = I915_READ(reg);
1982 if ((val & mask) == expected)
1983 return true;
1984
1985 va_start(args, reg_fmt);
1986 vaf.fmt = reg_fmt;
1987 vaf.va = &args;
1988
1989 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1990 "current %08x, expected %08x (mask %08x)\n",
1991 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1992 mask);
1993
1994 va_end(args);
1995
1996 return false;
1997 }
1998
1999 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
2000 enum dpio_phy phy)
2001 {
2002 uint32_t mask;
2003 bool ok;
2004
2005 #define _CHK(reg, mask, exp, fmt, ...) \
2006 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
2007 ## __VA_ARGS__)
2008
2009 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
2010 return false;
2011
2012 ok = true;
2013
2014 /* PLL Rcomp code offset */
2015 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
2016 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
2017 "BXT_PORT_CL1CM_DW9(%d)", phy);
2018 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
2019 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2020 "BXT_PORT_CL1CM_DW10(%d)", phy);
2021
2022 /* Power gating */
2023 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2024 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2025 "BXT_PORT_CL1CM_DW28(%d)", phy);
2026
2027 if (phy == DPIO_PHY0)
2028 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2029 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2030 "BXT_PORT_CL2CM_DW6_BC");
2031
2032 /*
2033 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2034 * at least on stepping A this bit is read-only and fixed at 0.
2035 */
2036
2037 if (phy == DPIO_PHY0) {
2038 u32 grc_code = dev_priv->bxt_phy_grc;
2039
2040 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2041 grc_code << GRC_CODE_SLOW_SHIFT |
2042 grc_code;
2043 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2044 GRC_CODE_NOM_MASK;
2045 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2046 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2047
2048 mask = GRC_DIS | GRC_RDY_OVRD;
2049 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2050 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2051 }
2052
2053 return ok;
2054 #undef _CHK
2055 }
2056
2057 static uint8_t
2058 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2059 struct intel_crtc_state *pipe_config)
2060 {
2061 switch (pipe_config->lane_count) {
2062 case 1:
2063 return 0;
2064 case 2:
2065 return BIT(2) | BIT(0);
2066 case 4:
2067 return BIT(3) | BIT(2) | BIT(0);
2068 default:
2069 MISSING_CASE(pipe_config->lane_count);
2070
2071 return 0;
2072 }
2073 }
2074
2075 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder)
2076 {
2077 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2078 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2079 enum port port = dport->port;
2080 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2081 int lane;
2082
2083 for (lane = 0; lane < 4; lane++) {
2084 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2085
2086 /*
2087 * Note that on CHV this flag is called UPAR, but has
2088 * the same function.
2089 */
2090 val &= ~LATENCY_OPTIM;
2091 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2092 val |= LATENCY_OPTIM;
2093
2094 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2095 }
2096 }
2097
2098 static uint8_t
2099 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2100 {
2101 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2102 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2103 enum port port = dport->port;
2104 int lane;
2105 uint8_t mask;
2106
2107 mask = 0;
2108 for (lane = 0; lane < 4; lane++) {
2109 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2110
2111 if (val & LATENCY_OPTIM)
2112 mask |= BIT(lane);
2113 }
2114
2115 return mask;
2116 }
2117
2118 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2119 {
2120 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2121 struct drm_i915_private *dev_priv =
2122 to_i915(intel_dig_port->base.base.dev);
2123 enum port port = intel_dig_port->port;
2124 uint32_t val;
2125 bool wait = false;
2126
2127 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2128 val = I915_READ(DDI_BUF_CTL(port));
2129 if (val & DDI_BUF_CTL_ENABLE) {
2130 val &= ~DDI_BUF_CTL_ENABLE;
2131 I915_WRITE(DDI_BUF_CTL(port), val);
2132 wait = true;
2133 }
2134
2135 val = I915_READ(DP_TP_CTL(port));
2136 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2137 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2138 I915_WRITE(DP_TP_CTL(port), val);
2139 POSTING_READ(DP_TP_CTL(port));
2140
2141 if (wait)
2142 intel_wait_ddi_buf_idle(dev_priv, port);
2143 }
2144
2145 val = DP_TP_CTL_ENABLE |
2146 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2147 if (intel_dp->is_mst)
2148 val |= DP_TP_CTL_MODE_MST;
2149 else {
2150 val |= DP_TP_CTL_MODE_SST;
2151 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2152 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2153 }
2154 I915_WRITE(DP_TP_CTL(port), val);
2155 POSTING_READ(DP_TP_CTL(port));
2156
2157 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2158 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2159 POSTING_READ(DDI_BUF_CTL(port));
2160
2161 udelay(600);
2162 }
2163
2164 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2165 {
2166 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2167 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2168 uint32_t val;
2169
2170 /*
2171 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2172 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2173 * step 13 is the correct place for it. Step 18 is where it was
2174 * originally before the BUN.
2175 */
2176 val = I915_READ(FDI_RX_CTL(PIPE_A));
2177 val &= ~FDI_RX_ENABLE;
2178 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2179
2180 intel_ddi_post_disable(intel_encoder);
2181
2182 val = I915_READ(FDI_RX_MISC(PIPE_A));
2183 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2184 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2185 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2186
2187 val = I915_READ(FDI_RX_CTL(PIPE_A));
2188 val &= ~FDI_PCDCLK;
2189 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2190
2191 val = I915_READ(FDI_RX_CTL(PIPE_A));
2192 val &= ~FDI_RX_PLL_ENABLE;
2193 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2194 }
2195
2196 void intel_ddi_get_config(struct intel_encoder *encoder,
2197 struct intel_crtc_state *pipe_config)
2198 {
2199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2200 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2201 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2202 struct intel_hdmi *intel_hdmi;
2203 u32 temp, flags = 0;
2204
2205 /* XXX: DSI transcoder paranoia */
2206 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2207 return;
2208
2209 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2210 if (temp & TRANS_DDI_PHSYNC)
2211 flags |= DRM_MODE_FLAG_PHSYNC;
2212 else
2213 flags |= DRM_MODE_FLAG_NHSYNC;
2214 if (temp & TRANS_DDI_PVSYNC)
2215 flags |= DRM_MODE_FLAG_PVSYNC;
2216 else
2217 flags |= DRM_MODE_FLAG_NVSYNC;
2218
2219 pipe_config->base.adjusted_mode.flags |= flags;
2220
2221 switch (temp & TRANS_DDI_BPC_MASK) {
2222 case TRANS_DDI_BPC_6:
2223 pipe_config->pipe_bpp = 18;
2224 break;
2225 case TRANS_DDI_BPC_8:
2226 pipe_config->pipe_bpp = 24;
2227 break;
2228 case TRANS_DDI_BPC_10:
2229 pipe_config->pipe_bpp = 30;
2230 break;
2231 case TRANS_DDI_BPC_12:
2232 pipe_config->pipe_bpp = 36;
2233 break;
2234 default:
2235 break;
2236 }
2237
2238 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2239 case TRANS_DDI_MODE_SELECT_HDMI:
2240 pipe_config->has_hdmi_sink = true;
2241 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2242
2243 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2244 pipe_config->has_infoframe = true;
2245 /* fall through */
2246 case TRANS_DDI_MODE_SELECT_DVI:
2247 pipe_config->lane_count = 4;
2248 break;
2249 case TRANS_DDI_MODE_SELECT_FDI:
2250 break;
2251 case TRANS_DDI_MODE_SELECT_DP_SST:
2252 case TRANS_DDI_MODE_SELECT_DP_MST:
2253 pipe_config->lane_count =
2254 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2255 intel_dp_get_m_n(intel_crtc, pipe_config);
2256 break;
2257 default:
2258 break;
2259 }
2260
2261 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2262 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2263 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2264 pipe_config->has_audio = true;
2265 }
2266
2267 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2268 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2269 /*
2270 * This is a big fat ugly hack.
2271 *
2272 * Some machines in UEFI boot mode provide us a VBT that has 18
2273 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2274 * unknown we fail to light up. Yet the same BIOS boots up with
2275 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2276 * max, not what it tells us to use.
2277 *
2278 * Note: This will still be broken if the eDP panel is not lit
2279 * up by the BIOS, and thus we can't get the mode at module
2280 * load.
2281 */
2282 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2283 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2284 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2285 }
2286
2287 intel_ddi_clock_get(encoder, pipe_config);
2288
2289 if (IS_BROXTON(dev_priv))
2290 pipe_config->lane_lat_optim_mask =
2291 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2292 }
2293
2294 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2295 struct intel_crtc_state *pipe_config)
2296 {
2297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2298 int type = encoder->type;
2299 int port = intel_ddi_get_encoder_port(encoder);
2300 int ret;
2301
2302 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2303
2304 if (port == PORT_A)
2305 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2306
2307 if (type == INTEL_OUTPUT_HDMI)
2308 ret = intel_hdmi_compute_config(encoder, pipe_config);
2309 else
2310 ret = intel_dp_compute_config(encoder, pipe_config);
2311
2312 if (IS_BROXTON(dev_priv) && ret)
2313 pipe_config->lane_lat_optim_mask =
2314 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2315 pipe_config);
2316
2317 return ret;
2318
2319 }
2320
2321 static const struct drm_encoder_funcs intel_ddi_funcs = {
2322 .reset = intel_dp_encoder_reset,
2323 .destroy = intel_dp_encoder_destroy,
2324 };
2325
2326 static struct intel_connector *
2327 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2328 {
2329 struct intel_connector *connector;
2330 enum port port = intel_dig_port->port;
2331
2332 connector = intel_connector_alloc();
2333 if (!connector)
2334 return NULL;
2335
2336 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2337 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2338 kfree(connector);
2339 return NULL;
2340 }
2341
2342 return connector;
2343 }
2344
2345 static struct intel_connector *
2346 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2347 {
2348 struct intel_connector *connector;
2349 enum port port = intel_dig_port->port;
2350
2351 connector = intel_connector_alloc();
2352 if (!connector)
2353 return NULL;
2354
2355 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2356 intel_hdmi_init_connector(intel_dig_port, connector);
2357
2358 return connector;
2359 }
2360
2361 void intel_ddi_init(struct drm_device *dev, enum port port)
2362 {
2363 struct drm_i915_private *dev_priv = to_i915(dev);
2364 struct intel_digital_port *intel_dig_port;
2365 struct intel_encoder *intel_encoder;
2366 struct drm_encoder *encoder;
2367 bool init_hdmi, init_dp;
2368 int max_lanes;
2369
2370 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2371 switch (port) {
2372 case PORT_A:
2373 max_lanes = 4;
2374 break;
2375 case PORT_E:
2376 max_lanes = 0;
2377 break;
2378 default:
2379 max_lanes = 4;
2380 break;
2381 }
2382 } else {
2383 switch (port) {
2384 case PORT_A:
2385 max_lanes = 2;
2386 break;
2387 case PORT_E:
2388 max_lanes = 2;
2389 break;
2390 default:
2391 max_lanes = 4;
2392 break;
2393 }
2394 }
2395
2396 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2397 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2398 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2399 if (!init_dp && !init_hdmi) {
2400 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2401 port_name(port));
2402 return;
2403 }
2404
2405 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2406 if (!intel_dig_port)
2407 return;
2408
2409 intel_encoder = &intel_dig_port->base;
2410 encoder = &intel_encoder->base;
2411
2412 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2413 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2414
2415 intel_encoder->compute_config = intel_ddi_compute_config;
2416 intel_encoder->enable = intel_enable_ddi;
2417 if (IS_BROXTON(dev_priv))
2418 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2419 intel_encoder->pre_enable = intel_ddi_pre_enable;
2420 intel_encoder->disable = intel_disable_ddi;
2421 intel_encoder->post_disable = intel_ddi_post_disable;
2422 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2423 intel_encoder->get_config = intel_ddi_get_config;
2424 intel_encoder->suspend = intel_dp_encoder_suspend;
2425
2426 intel_dig_port->port = port;
2427 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2428 (DDI_BUF_PORT_REVERSAL |
2429 DDI_A_4_LANES);
2430
2431 /*
2432 * Bspec says that DDI_A_4_LANES is the only supported configuration
2433 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2434 * wasn't lit up at boot. Force this bit on in our internal
2435 * configuration so that we use the proper lane count for our
2436 * calculations.
2437 */
2438 if (IS_BROXTON(dev) && port == PORT_A) {
2439 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2440 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2441 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2442 max_lanes = 4;
2443 }
2444 }
2445
2446 intel_dig_port->max_lanes = max_lanes;
2447
2448 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2449 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2450 intel_encoder->cloneable = 0;
2451
2452 if (init_dp) {
2453 if (!intel_ddi_init_dp_connector(intel_dig_port))
2454 goto err;
2455
2456 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2457 /*
2458 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2459 * interrupts to check the external panel connection.
2460 */
2461 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
2462 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2463 else
2464 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2465 }
2466
2467 /* In theory we don't need the encoder->type check, but leave it just in
2468 * case we have some really bad VBTs... */
2469 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2470 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2471 goto err;
2472 }
2473
2474 return;
2475
2476 err:
2477 drm_encoder_cleanup(encoder);
2478 kfree(intel_dig_port);
2479 }
Linux kernel - Deliverables
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