2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
34 u8 i_boost
; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp
[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
152 { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp
[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
165 { 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp
[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp
[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi
[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
248 { 0x00000018, 0x000000C7, 0x0 },
251 struct bxt_ddi_buf_trans
{
252 u32 margin
; /* swing value */
253 u32 scale
; /* scale value */
254 u32 enable
; /* scale enable */
256 bool default_index
; /* true if the entry represents default value */
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp
[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
304 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
305 enum port port
, int type
);
307 static void ddi_get_encoder_port(struct intel_encoder
*intel_encoder
,
308 struct intel_digital_port
**dig_port
,
311 struct drm_encoder
*encoder
= &intel_encoder
->base
;
313 switch (intel_encoder
->type
) {
314 case INTEL_OUTPUT_DP_MST
:
315 *dig_port
= enc_to_mst(encoder
)->primary
;
316 *port
= (*dig_port
)->port
;
318 case INTEL_OUTPUT_DISPLAYPORT
:
319 case INTEL_OUTPUT_EDP
:
320 case INTEL_OUTPUT_HDMI
:
321 case INTEL_OUTPUT_UNKNOWN
:
322 *dig_port
= enc_to_dig_port(encoder
);
323 *port
= (*dig_port
)->port
;
325 case INTEL_OUTPUT_ANALOG
:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder
->type
);
335 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
337 struct intel_digital_port
*dig_port
;
340 ddi_get_encoder_port(intel_encoder
, &dig_port
, &port
);
346 intel_dig_port_supports_hdmi(const struct intel_digital_port
*intel_dig_port
)
348 return i915_mmio_reg_valid(intel_dig_port
->hdmi
.hdmi_reg
);
351 static const struct ddi_buf_trans
*skl_get_buf_trans_dp(struct drm_device
*dev
,
354 const struct ddi_buf_trans
*ddi_translations
;
356 if (IS_SKL_ULX(dev
)) {
357 ddi_translations
= skl_y_ddi_translations_dp
;
358 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_dp
);
359 } else if (IS_SKL_ULT(dev
)) {
360 ddi_translations
= skl_u_ddi_translations_dp
;
361 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
363 ddi_translations
= skl_ddi_translations_dp
;
364 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
367 return ddi_translations
;
370 static const struct ddi_buf_trans
*skl_get_buf_trans_edp(struct drm_device
*dev
,
373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
374 const struct ddi_buf_trans
*ddi_translations
;
376 if (IS_SKL_ULX(dev
)) {
377 if (dev_priv
->edp_low_vswing
) {
378 ddi_translations
= skl_y_ddi_translations_edp
;
379 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_edp
);
381 ddi_translations
= skl_y_ddi_translations_dp
;
382 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_dp
);
384 } else if (IS_SKL_ULT(dev
)) {
385 if (dev_priv
->edp_low_vswing
) {
386 ddi_translations
= skl_u_ddi_translations_edp
;
387 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_edp
);
389 ddi_translations
= skl_u_ddi_translations_dp
;
390 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
393 if (dev_priv
->edp_low_vswing
) {
394 ddi_translations
= skl_ddi_translations_edp
;
395 *n_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
397 ddi_translations
= skl_ddi_translations_dp
;
398 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
402 return ddi_translations
;
405 static const struct ddi_buf_trans
*
406 skl_get_buf_trans_hdmi(struct drm_device
*dev
,
409 const struct ddi_buf_trans
*ddi_translations
;
411 if (IS_SKL_ULX(dev
)) {
412 ddi_translations
= skl_y_ddi_translations_hdmi
;
413 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_hdmi
);
415 ddi_translations
= skl_ddi_translations_hdmi
;
416 *n_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
419 return ddi_translations
;
423 * Starting with Haswell, DDI port buffers must be programmed with correct
424 * values in advance. The buffer values are different for FDI and DP modes,
425 * but the HDMI/DVI fields are shared among those. So we program the DDI
426 * in either FDI or DP modes only, as HDMI connections will work with both
429 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
434 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
436 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
437 const struct ddi_buf_trans
*ddi_translations_fdi
;
438 const struct ddi_buf_trans
*ddi_translations_dp
;
439 const struct ddi_buf_trans
*ddi_translations_edp
;
440 const struct ddi_buf_trans
*ddi_translations_hdmi
;
441 const struct ddi_buf_trans
*ddi_translations
;
443 if (IS_BROXTON(dev
)) {
447 /* Vswing programming for HDMI */
448 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
451 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
452 ddi_translations_fdi
= NULL
;
453 ddi_translations_dp
=
454 skl_get_buf_trans_dp(dev
, &n_dp_entries
);
455 ddi_translations_edp
=
456 skl_get_buf_trans_edp(dev
, &n_edp_entries
);
457 ddi_translations_hdmi
=
458 skl_get_buf_trans_hdmi(dev
, &n_hdmi_entries
);
459 hdmi_default_entry
= 8;
460 /* If we're boosting the current, set bit 31 of trans1 */
461 if (dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
||
462 dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
)
464 } else if (IS_BROADWELL(dev
)) {
465 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
466 ddi_translations_dp
= bdw_ddi_translations_dp
;
467 ddi_translations_edp
= bdw_ddi_translations_edp
;
468 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
469 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
470 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
471 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
472 hdmi_default_entry
= 7;
473 } else if (IS_HASWELL(dev
)) {
474 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
475 ddi_translations_dp
= hsw_ddi_translations_dp
;
476 ddi_translations_edp
= hsw_ddi_translations_dp
;
477 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
478 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
479 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
480 hdmi_default_entry
= 6;
482 WARN(1, "ddi translation table missing\n");
483 ddi_translations_edp
= bdw_ddi_translations_dp
;
484 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
485 ddi_translations_dp
= bdw_ddi_translations_dp
;
486 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
487 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
488 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
489 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
490 hdmi_default_entry
= 7;
495 ddi_translations
= ddi_translations_edp
;
496 size
= n_edp_entries
;
500 ddi_translations
= ddi_translations_dp
;
504 if (intel_dp_is_edp(dev
, PORT_D
)) {
505 ddi_translations
= ddi_translations_edp
;
506 size
= n_edp_entries
;
508 ddi_translations
= ddi_translations_dp
;
513 if (ddi_translations_fdi
)
514 ddi_translations
= ddi_translations_fdi
;
516 ddi_translations
= ddi_translations_dp
;
523 for (i
= 0; i
< size
; i
++) {
524 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
525 ddi_translations
[i
].trans1
| iboost_bit
);
526 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
527 ddi_translations
[i
].trans2
);
533 /* Choose a good default if VBT is badly populated */
534 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
535 hdmi_level
>= n_hdmi_entries
)
536 hdmi_level
= hdmi_default_entry
;
538 /* Entry 9 is for HDMI: */
539 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
540 ddi_translations_hdmi
[hdmi_level
].trans1
| iboost_bit
);
541 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
542 ddi_translations_hdmi
[hdmi_level
].trans2
);
545 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
546 * mode and port E for FDI.
548 void intel_prepare_ddi(struct drm_device
*dev
)
550 struct intel_encoder
*intel_encoder
;
551 bool visited
[I915_MAX_PORTS
] = { 0, };
556 for_each_intel_encoder(dev
, intel_encoder
) {
557 struct intel_digital_port
*intel_dig_port
;
561 if (intel_encoder
->type
== INTEL_OUTPUT_DSI
)
564 ddi_get_encoder_port(intel_encoder
, &intel_dig_port
, &port
);
568 supports_hdmi
= intel_dig_port
&&
569 intel_dig_port_supports_hdmi(intel_dig_port
);
571 intel_prepare_ddi_buffers(dev
, port
, supports_hdmi
);
572 visited
[port
] = true;
576 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
579 i915_reg_t reg
= DDI_BUF_CTL(port
);
582 for (i
= 0; i
< 16; i
++) {
584 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
587 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
590 /* Starting with Haswell, different DDI ports can work in FDI mode for
591 * connection to the PCH-located connectors. For this, it is necessary to train
592 * both the DDI port and PCH receiver for the desired DDI buffer settings.
594 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
595 * please note that when FDI mode is active on DDI E, it shares 2 lines with
596 * DDI A (which is used for eDP)
599 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
601 struct drm_device
*dev
= crtc
->dev
;
602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
603 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
604 u32 temp
, i
, rx_ctl_val
;
606 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
607 * mode set "sequence for CRT port" document:
608 * - TP1 to TP2 time with the default value
611 * WaFDIAutoLinkSetTimingOverrride:hsw
613 I915_WRITE(FDI_RX_MISC(PIPE_A
), FDI_RX_PWRDN_LANE1_VAL(2) |
614 FDI_RX_PWRDN_LANE0_VAL(2) |
615 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
617 /* Enable the PCH Receiver FDI PLL */
618 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
620 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
621 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
622 POSTING_READ(FDI_RX_CTL(PIPE_A
));
625 /* Switch from Rawclk to PCDclk */
626 rx_ctl_val
|= FDI_PCDCLK
;
627 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
629 /* Configure Port Clock Select */
630 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
631 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
633 /* Start the training iterating through available voltages and emphasis,
634 * testing each value twice. */
635 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
636 /* Configure DP_TP_CTL with auto-training */
637 I915_WRITE(DP_TP_CTL(PORT_E
),
638 DP_TP_CTL_FDI_AUTOTRAIN
|
639 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
640 DP_TP_CTL_LINK_TRAIN_PAT1
|
643 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
644 * DDI E does not support port reversal, the functionality is
645 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
646 * port reversal bit */
647 I915_WRITE(DDI_BUF_CTL(PORT_E
),
649 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
650 DDI_BUF_TRANS_SELECT(i
/ 2));
651 POSTING_READ(DDI_BUF_CTL(PORT_E
));
655 /* Program PCH FDI Receiver TU */
656 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A
), TU_SIZE(64));
658 /* Enable PCH FDI Receiver with auto-training */
659 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
660 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
661 POSTING_READ(FDI_RX_CTL(PIPE_A
));
663 /* Wait for FDI receiver lane calibration */
666 /* Unset FDI_RX_MISC pwrdn lanes */
667 temp
= I915_READ(FDI_RX_MISC(PIPE_A
));
668 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
669 I915_WRITE(FDI_RX_MISC(PIPE_A
), temp
);
670 POSTING_READ(FDI_RX_MISC(PIPE_A
));
672 /* Wait for FDI auto training time */
675 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
676 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
677 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
679 /* Enable normal pixel sending for FDI */
680 I915_WRITE(DP_TP_CTL(PORT_E
),
681 DP_TP_CTL_FDI_AUTOTRAIN
|
682 DP_TP_CTL_LINK_TRAIN_NORMAL
|
683 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
689 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
690 temp
&= ~DDI_BUF_CTL_ENABLE
;
691 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
692 POSTING_READ(DDI_BUF_CTL(PORT_E
));
694 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
695 temp
= I915_READ(DP_TP_CTL(PORT_E
));
696 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
697 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
698 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
699 POSTING_READ(DP_TP_CTL(PORT_E
));
701 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
703 rx_ctl_val
&= ~FDI_RX_ENABLE
;
704 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
705 POSTING_READ(FDI_RX_CTL(PIPE_A
));
707 /* Reset FDI_RX_MISC pwrdn lanes */
708 temp
= I915_READ(FDI_RX_MISC(PIPE_A
));
709 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
710 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
711 I915_WRITE(FDI_RX_MISC(PIPE_A
), temp
);
712 POSTING_READ(FDI_RX_MISC(PIPE_A
));
715 DRM_ERROR("FDI link training failed!\n");
718 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
720 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
721 struct intel_digital_port
*intel_dig_port
=
722 enc_to_dig_port(&encoder
->base
);
724 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
725 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
726 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
729 static struct intel_encoder
*
730 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
732 struct drm_device
*dev
= crtc
->dev
;
733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
734 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
735 int num_encoders
= 0;
737 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
742 if (num_encoders
!= 1)
743 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
744 pipe_name(intel_crtc
->pipe
));
750 struct intel_encoder
*
751 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
753 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
754 struct intel_encoder
*ret
= NULL
;
755 struct drm_atomic_state
*state
;
756 struct drm_connector
*connector
;
757 struct drm_connector_state
*connector_state
;
758 int num_encoders
= 0;
761 state
= crtc_state
->base
.state
;
763 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
764 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
767 ret
= to_intel_encoder(connector_state
->best_encoder
);
771 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
772 pipe_name(crtc
->pipe
));
779 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
785 /* Constraints for PLL good behavior */
791 #define abs_diff(a, b) ({ \
792 typeof(a) __a = (a); \
793 typeof(b) __b = (b); \
794 (void) (&__a == &__b); \
795 __a > __b ? (__a - __b) : (__b - __a); })
797 struct hsw_wrpll_rnp
{
801 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
875 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
876 unsigned r2
, unsigned n2
, unsigned p
,
877 struct hsw_wrpll_rnp
*best
)
879 uint64_t a
, b
, c
, d
, diff
, diff_best
;
881 /* No best (r,n,p) yet */
890 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
894 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
897 * and we would like delta <= budget.
899 * If the discrepancy is above the PPM-based budget, always prefer to
900 * improve upon the previous solution. However, if you're within the
901 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
903 a
= freq2k
* budget
* p
* r2
;
904 b
= freq2k
* budget
* best
->p
* best
->r2
;
905 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
906 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
907 LC_FREQ_2K
* best
->n2
);
909 d
= 1000000 * diff_best
;
911 if (a
< c
&& b
< d
) {
912 /* If both are above the budget, pick the closer */
913 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
918 } else if (a
>= c
&& b
< d
) {
919 /* If A is below the threshold but B is above it? Update. */
923 } else if (a
>= c
&& b
>= d
) {
924 /* Both are below the limit, so pick the higher n2/(r2*r2) */
925 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
931 /* Otherwise a < c && b >= d, do nothing */
934 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
937 int refclk
= LC_FREQ
;
941 wrpll
= I915_READ(reg
);
942 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
944 case WRPLL_PLL_NON_SSC
:
946 * We could calculate spread here, but our checking
947 * code only cares about 5% accuracy, and spread is a max of
952 case WRPLL_PLL_LCPLL
:
956 WARN(1, "bad wrpll refclk\n");
960 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
961 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
962 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
964 /* Convert to KHz, p & r have a fixed point portion */
965 return (refclk
* n
* 100) / (p
* r
);
968 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
971 i915_reg_t cfgcr1_reg
, cfgcr2_reg
;
972 uint32_t cfgcr1_val
, cfgcr2_val
;
973 uint32_t p0
, p1
, p2
, dco_freq
;
975 cfgcr1_reg
= DPLL_CFGCR1(dpll
);
976 cfgcr2_reg
= DPLL_CFGCR2(dpll
);
978 cfgcr1_val
= I915_READ(cfgcr1_reg
);
979 cfgcr2_val
= I915_READ(cfgcr2_reg
);
981 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
982 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
984 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
985 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
991 case DPLL_CFGCR2_PDIV_1
:
994 case DPLL_CFGCR2_PDIV_2
:
997 case DPLL_CFGCR2_PDIV_3
:
1000 case DPLL_CFGCR2_PDIV_7
:
1006 case DPLL_CFGCR2_KDIV_5
:
1009 case DPLL_CFGCR2_KDIV_2
:
1012 case DPLL_CFGCR2_KDIV_3
:
1015 case DPLL_CFGCR2_KDIV_1
:
1020 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
1022 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
1025 return dco_freq
/ (p0
* p1
* p2
* 5);
1028 static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config
)
1032 if (pipe_config
->has_pch_encoder
)
1033 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1034 &pipe_config
->fdi_m_n
);
1035 else if (pipe_config
->has_dp_encoder
)
1036 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1037 &pipe_config
->dp_m_n
);
1038 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
== 36)
1039 dotclock
= pipe_config
->port_clock
* 2 / 3;
1041 dotclock
= pipe_config
->port_clock
;
1043 if (pipe_config
->pixel_multiplier
)
1044 dotclock
/= pipe_config
->pixel_multiplier
;
1046 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
1049 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
1050 struct intel_crtc_state
*pipe_config
)
1052 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1054 uint32_t dpll_ctl1
, dpll
;
1056 dpll
= pipe_config
->ddi_pll_sel
;
1058 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
1060 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1061 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
1063 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(dpll
);
1064 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll
);
1066 switch (link_clock
) {
1067 case DPLL_CTRL1_LINK_RATE_810
:
1070 case DPLL_CTRL1_LINK_RATE_1080
:
1071 link_clock
= 108000;
1073 case DPLL_CTRL1_LINK_RATE_1350
:
1074 link_clock
= 135000;
1076 case DPLL_CTRL1_LINK_RATE_1620
:
1077 link_clock
= 162000;
1079 case DPLL_CTRL1_LINK_RATE_2160
:
1080 link_clock
= 216000;
1082 case DPLL_CTRL1_LINK_RATE_2700
:
1083 link_clock
= 270000;
1086 WARN(1, "Unsupported link rate\n");
1092 pipe_config
->port_clock
= link_clock
;
1094 ddi_dotclock_get(pipe_config
);
1097 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
1098 struct intel_crtc_state
*pipe_config
)
1100 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1104 val
= pipe_config
->ddi_pll_sel
;
1105 switch (val
& PORT_CLK_SEL_MASK
) {
1106 case PORT_CLK_SEL_LCPLL_810
:
1109 case PORT_CLK_SEL_LCPLL_1350
:
1110 link_clock
= 135000;
1112 case PORT_CLK_SEL_LCPLL_2700
:
1113 link_clock
= 270000;
1115 case PORT_CLK_SEL_WRPLL1
:
1116 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL(0));
1118 case PORT_CLK_SEL_WRPLL2
:
1119 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL(1));
1121 case PORT_CLK_SEL_SPLL
:
1122 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
1123 if (pll
== SPLL_PLL_FREQ_810MHz
)
1125 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
1126 link_clock
= 135000;
1127 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
1128 link_clock
= 270000;
1130 WARN(1, "bad spll freq\n");
1135 WARN(1, "bad port clock sel\n");
1139 pipe_config
->port_clock
= link_clock
* 2;
1141 ddi_dotclock_get(pipe_config
);
1144 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
1145 enum intel_dpll_id dpll
)
1147 struct intel_shared_dpll
*pll
;
1148 struct intel_dpll_hw_state
*state
;
1149 intel_clock_t clock
;
1151 /* For DDI ports we always use a shared PLL. */
1152 if (WARN_ON(dpll
== DPLL_ID_PRIVATE
))
1155 pll
= &dev_priv
->shared_dplls
[dpll
];
1156 state
= &pll
->config
.hw_state
;
1159 clock
.m2
= (state
->pll0
& PORT_PLL_M2_MASK
) << 22;
1160 if (state
->pll3
& PORT_PLL_M2_FRAC_ENABLE
)
1161 clock
.m2
|= state
->pll2
& PORT_PLL_M2_FRAC_MASK
;
1162 clock
.n
= (state
->pll1
& PORT_PLL_N_MASK
) >> PORT_PLL_N_SHIFT
;
1163 clock
.p1
= (state
->ebb0
& PORT_PLL_P1_MASK
) >> PORT_PLL_P1_SHIFT
;
1164 clock
.p2
= (state
->ebb0
& PORT_PLL_P2_MASK
) >> PORT_PLL_P2_SHIFT
;
1166 return chv_calc_dpll_params(100000, &clock
);
1169 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
1170 struct intel_crtc_state
*pipe_config
)
1172 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1173 enum port port
= intel_ddi_get_encoder_port(encoder
);
1174 uint32_t dpll
= port
;
1176 pipe_config
->port_clock
= bxt_calc_pll_link(dev_priv
, dpll
);
1178 ddi_dotclock_get(pipe_config
);
1181 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1182 struct intel_crtc_state
*pipe_config
)
1184 struct drm_device
*dev
= encoder
->base
.dev
;
1186 if (INTEL_INFO(dev
)->gen
<= 8)
1187 hsw_ddi_clock_get(encoder
, pipe_config
);
1188 else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
1189 skl_ddi_clock_get(encoder
, pipe_config
);
1190 else if (IS_BROXTON(dev
))
1191 bxt_ddi_clock_get(encoder
, pipe_config
);
1195 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
1196 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
1200 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
1203 freq2k
= clock
/ 100;
1205 budget
= hsw_wrpll_get_budget_for_freq(clock
);
1207 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1208 * and directly pass the LC PLL to it. */
1209 if (freq2k
== 5400000) {
1217 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1220 * We want R so that REF_MIN <= Ref <= REF_MAX.
1221 * Injecting R2 = 2 * R gives:
1222 * REF_MAX * r2 > LC_FREQ * 2 and
1223 * REF_MIN * r2 < LC_FREQ * 2
1225 * Which means the desired boundaries for r2 are:
1226 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1229 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
1230 r2
<= LC_FREQ
* 2 / REF_MIN
;
1234 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1236 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1237 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1238 * VCO_MAX * r2 > n2 * LC_FREQ and
1239 * VCO_MIN * r2 < n2 * LC_FREQ)
1241 * Which means the desired boundaries for n2 are:
1242 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1244 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
1245 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
1248 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
1249 hsw_wrpll_update_rnp(freq2k
, budget
,
1260 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1261 struct intel_crtc_state
*crtc_state
,
1262 struct intel_encoder
*intel_encoder
)
1264 int clock
= crtc_state
->port_clock
;
1266 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1267 struct intel_shared_dpll
*pll
;
1271 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
1273 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
1274 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
1275 WRPLL_DIVIDER_POST(p
);
1277 memset(&crtc_state
->dpll_hw_state
, 0,
1278 sizeof(crtc_state
->dpll_hw_state
));
1280 crtc_state
->dpll_hw_state
.wrpll
= val
;
1282 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1284 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1285 pipe_name(intel_crtc
->pipe
));
1289 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
1290 } else if (crtc_state
->ddi_pll_sel
== PORT_CLK_SEL_SPLL
) {
1291 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
1292 struct intel_shared_dpll_config
*spll
=
1293 &intel_atomic_get_shared_dpll_state(state
)[DPLL_ID_SPLL
];
1295 if (spll
->crtc_mask
&&
1296 WARN_ON(spll
->hw_state
.spll
!= crtc_state
->dpll_hw_state
.spll
))
1299 crtc_state
->shared_dpll
= DPLL_ID_SPLL
;
1300 spll
->hw_state
.spll
= crtc_state
->dpll_hw_state
.spll
;
1301 spll
->crtc_mask
|= 1 << intel_crtc
->pipe
;
1307 struct skl_wrpll_context
{
1308 uint64_t min_deviation
; /* current minimal deviation */
1309 uint64_t central_freq
; /* chosen central freq */
1310 uint64_t dco_freq
; /* chosen dco freq */
1311 unsigned int p
; /* chosen divider */
1314 static void skl_wrpll_context_init(struct skl_wrpll_context
*ctx
)
1316 memset(ctx
, 0, sizeof(*ctx
));
1318 ctx
->min_deviation
= U64_MAX
;
1321 /* DCO freq must be within +1%/-6% of the DCO central freq */
1322 #define SKL_DCO_MAX_PDEVIATION 100
1323 #define SKL_DCO_MAX_NDEVIATION 600
1325 static void skl_wrpll_try_divider(struct skl_wrpll_context
*ctx
,
1326 uint64_t central_freq
,
1328 unsigned int divider
)
1332 deviation
= div64_u64(10000 * abs_diff(dco_freq
, central_freq
),
1335 /* positive deviation */
1336 if (dco_freq
>= central_freq
) {
1337 if (deviation
< SKL_DCO_MAX_PDEVIATION
&&
1338 deviation
< ctx
->min_deviation
) {
1339 ctx
->min_deviation
= deviation
;
1340 ctx
->central_freq
= central_freq
;
1341 ctx
->dco_freq
= dco_freq
;
1344 /* negative deviation */
1345 } else if (deviation
< SKL_DCO_MAX_NDEVIATION
&&
1346 deviation
< ctx
->min_deviation
) {
1347 ctx
->min_deviation
= deviation
;
1348 ctx
->central_freq
= central_freq
;
1349 ctx
->dco_freq
= dco_freq
;
1354 static void skl_wrpll_get_multipliers(unsigned int p
,
1355 unsigned int *p0
/* out */,
1356 unsigned int *p1
/* out */,
1357 unsigned int *p2
/* out */)
1361 unsigned int half
= p
/ 2;
1363 if (half
== 1 || half
== 2 || half
== 3 || half
== 5) {
1367 } else if (half
% 2 == 0) {
1371 } else if (half
% 3 == 0) {
1375 } else if (half
% 7 == 0) {
1380 } else if (p
== 3 || p
== 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1384 } else if (p
== 5 || p
== 7) {
1388 } else if (p
== 15) {
1392 } else if (p
== 21) {
1396 } else if (p
== 35) {
1403 struct skl_wrpll_params
{
1404 uint32_t dco_fraction
;
1405 uint32_t dco_integer
;
1406 uint32_t qdiv_ratio
;
1410 uint32_t central_freq
;
1413 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1415 uint64_t central_freq
,
1416 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1420 switch (central_freq
) {
1422 params
->central_freq
= 0;
1425 params
->central_freq
= 1;
1428 params
->central_freq
= 3;
1445 WARN(1, "Incorrect PDiv\n");
1462 WARN(1, "Incorrect KDiv\n");
1465 params
->qdiv_ratio
= p1
;
1466 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1468 dco_freq
= p0
* p1
* p2
* afe_clock
;
1471 * Intermediate values are in Hz.
1472 * Divide by MHz to match bsepc
1474 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1475 params
->dco_fraction
=
1476 div_u64((div_u64(dco_freq
, 24) -
1477 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1481 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1482 struct skl_wrpll_params
*wrpll_params
)
1484 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1485 uint64_t dco_central_freq
[3] = {8400000000ULL,
1488 static const int even_dividers
[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1489 24, 28, 30, 32, 36, 40, 42, 44,
1490 48, 52, 54, 56, 60, 64, 66, 68,
1491 70, 72, 76, 78, 80, 84, 88, 90,
1493 static const int odd_dividers
[] = { 3, 5, 7, 9, 15, 21, 35 };
1494 static const struct {
1498 { even_dividers
, ARRAY_SIZE(even_dividers
) },
1499 { odd_dividers
, ARRAY_SIZE(odd_dividers
) },
1501 struct skl_wrpll_context ctx
;
1502 unsigned int dco
, d
, i
;
1503 unsigned int p0
, p1
, p2
;
1505 skl_wrpll_context_init(&ctx
);
1507 for (d
= 0; d
< ARRAY_SIZE(dividers
); d
++) {
1508 for (dco
= 0; dco
< ARRAY_SIZE(dco_central_freq
); dco
++) {
1509 for (i
= 0; i
< dividers
[d
].n_dividers
; i
++) {
1510 unsigned int p
= dividers
[d
].list
[i
];
1511 uint64_t dco_freq
= p
* afe_clock
;
1513 skl_wrpll_try_divider(&ctx
,
1514 dco_central_freq
[dco
],
1518 * Skip the remaining dividers if we're sure to
1519 * have found the definitive divider, we can't
1520 * improve a 0 deviation.
1522 if (ctx
.min_deviation
== 0)
1523 goto skip_remaining_dividers
;
1527 skip_remaining_dividers
:
1529 * If a solution is found with an even divider, prefer
1532 if (d
== 0 && ctx
.p
)
1537 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock
);
1542 * gcc incorrectly analyses that these can be used without being
1543 * initialized. To be fair, it's hard to guess.
1546 skl_wrpll_get_multipliers(ctx
.p
, &p0
, &p1
, &p2
);
1547 skl_wrpll_params_populate(wrpll_params
, afe_clock
, ctx
.central_freq
,
1554 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1555 struct intel_crtc_state
*crtc_state
,
1556 struct intel_encoder
*intel_encoder
)
1558 struct intel_shared_dpll
*pll
;
1559 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1560 int clock
= crtc_state
->port_clock
;
1563 * See comment in intel_dpll_hw_state to understand why we always use 0
1564 * as the DPLL id in this function.
1567 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1569 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1570 struct skl_wrpll_params wrpll_params
= { 0, };
1572 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1574 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1577 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1578 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1579 wrpll_params
.dco_integer
;
1581 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1582 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1583 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1584 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1585 wrpll_params
.central_freq
;
1586 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1587 switch (crtc_state
->port_clock
/ 2) {
1589 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1592 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1595 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1599 cfgcr1
= cfgcr2
= 0;
1603 memset(&crtc_state
->dpll_hw_state
, 0,
1604 sizeof(crtc_state
->dpll_hw_state
));
1606 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1607 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1608 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1610 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1612 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1613 pipe_name(intel_crtc
->pipe
));
1617 /* shared DPLL id 0 is DPLL 1 */
1618 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1623 /* bxt clock parameters */
1624 struct bxt_clk_div
{
1634 /* pre-calculated values for DP linkrates */
1635 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1636 {162000, 4, 2, 32, 1677722, 1, 1},
1637 {270000, 4, 1, 27, 0, 0, 1},
1638 {540000, 2, 1, 27, 0, 0, 1},
1639 {216000, 3, 2, 32, 1677722, 1, 1},
1640 {243000, 4, 1, 24, 1258291, 1, 1},
1641 {324000, 4, 1, 32, 1677722, 1, 1},
1642 {432000, 3, 1, 32, 1677722, 1, 1}
1646 bxt_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1647 struct intel_crtc_state
*crtc_state
,
1648 struct intel_encoder
*intel_encoder
)
1650 struct intel_shared_dpll
*pll
;
1651 struct bxt_clk_div clk_div
= {0};
1653 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1654 uint32_t lanestagger
;
1655 int clock
= crtc_state
->port_clock
;
1657 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1658 intel_clock_t best_clock
;
1660 /* Calculate HDMI div */
1662 * FIXME: tie the following calculation into
1663 * i9xx_crtc_compute_clock
1665 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1666 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1667 clock
, pipe_name(intel_crtc
->pipe
));
1671 clk_div
.p1
= best_clock
.p1
;
1672 clk_div
.p2
= best_clock
.p2
;
1673 WARN_ON(best_clock
.m1
!= 2);
1674 clk_div
.n
= best_clock
.n
;
1675 clk_div
.m2_int
= best_clock
.m2
>> 22;
1676 clk_div
.m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1677 clk_div
.m2_frac_en
= clk_div
.m2_frac
!= 0;
1679 vco
= best_clock
.vco
;
1680 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1681 intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
1684 clk_div
= bxt_dp_clk_val
[0];
1685 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1686 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1687 clk_div
= bxt_dp_clk_val
[i
];
1691 vco
= clock
* 10 / 2 * clk_div
.p1
* clk_div
.p2
;
1694 if (vco
>= 6200000 && vco
<= 6700000) {
1699 } else if ((vco
> 5400000 && vco
< 6200000) ||
1700 (vco
>= 4800000 && vco
< 5400000)) {
1705 } else if (vco
== 5400000) {
1711 DRM_ERROR("Invalid VCO\n");
1715 memset(&crtc_state
->dpll_hw_state
, 0,
1716 sizeof(crtc_state
->dpll_hw_state
));
1720 else if (clock
> 135000)
1722 else if (clock
> 67000)
1724 else if (clock
> 33000)
1729 crtc_state
->dpll_hw_state
.ebb0
=
1730 PORT_PLL_P1(clk_div
.p1
) | PORT_PLL_P2(clk_div
.p2
);
1731 crtc_state
->dpll_hw_state
.pll0
= clk_div
.m2_int
;
1732 crtc_state
->dpll_hw_state
.pll1
= PORT_PLL_N(clk_div
.n
);
1733 crtc_state
->dpll_hw_state
.pll2
= clk_div
.m2_frac
;
1735 if (clk_div
.m2_frac_en
)
1736 crtc_state
->dpll_hw_state
.pll3
=
1737 PORT_PLL_M2_FRAC_ENABLE
;
1739 crtc_state
->dpll_hw_state
.pll6
=
1740 prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1741 crtc_state
->dpll_hw_state
.pll6
|=
1742 PORT_PLL_GAIN_CTL(gain_ctl
);
1744 crtc_state
->dpll_hw_state
.pll8
= targ_cnt
;
1746 crtc_state
->dpll_hw_state
.pll9
= 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT
;
1748 crtc_state
->dpll_hw_state
.pll10
=
1749 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT
)
1750 | PORT_PLL_DCO_AMP_OVR_EN_H
;
1752 crtc_state
->dpll_hw_state
.ebb4
= PORT_PLL_10BIT_CLK_ENABLE
;
1754 crtc_state
->dpll_hw_state
.pcsdw12
=
1755 LANESTAGGER_STRAP_OVRD
| lanestagger
;
1757 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1759 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1760 pipe_name(intel_crtc
->pipe
));
1764 /* shared DPLL id 0 is DPLL A */
1765 crtc_state
->ddi_pll_sel
= pll
->id
;
1771 * Tries to find a *shared* PLL for the CRTC and store it in
1772 * intel_crtc->ddi_pll_sel.
1774 * For private DPLLs, compute_config() should do the selection for us. This
1775 * function should be folded into compute_config() eventually.
1777 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1778 struct intel_crtc_state
*crtc_state
)
1780 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1781 struct intel_encoder
*intel_encoder
=
1782 intel_ddi_get_crtc_new_encoder(crtc_state
);
1784 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
1785 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1787 else if (IS_BROXTON(dev
))
1788 return bxt_ddi_pll_select(intel_crtc
, crtc_state
,
1791 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1795 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1797 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1799 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1800 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1801 int type
= intel_encoder
->type
;
1804 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1805 temp
= TRANS_MSA_SYNC_CLK
;
1806 switch (intel_crtc
->config
->pipe_bpp
) {
1808 temp
|= TRANS_MSA_6_BPC
;
1811 temp
|= TRANS_MSA_8_BPC
;
1814 temp
|= TRANS_MSA_10_BPC
;
1817 temp
|= TRANS_MSA_12_BPC
;
1822 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1826 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1829 struct drm_device
*dev
= crtc
->dev
;
1830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1831 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1833 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1835 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1837 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1838 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1841 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1843 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1844 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1845 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1846 struct drm_device
*dev
= crtc
->dev
;
1847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1848 enum pipe pipe
= intel_crtc
->pipe
;
1849 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1850 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1851 int type
= intel_encoder
->type
;
1854 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1855 temp
= TRANS_DDI_FUNC_ENABLE
;
1856 temp
|= TRANS_DDI_SELECT_PORT(port
);
1858 switch (intel_crtc
->config
->pipe_bpp
) {
1860 temp
|= TRANS_DDI_BPC_6
;
1863 temp
|= TRANS_DDI_BPC_8
;
1866 temp
|= TRANS_DDI_BPC_10
;
1869 temp
|= TRANS_DDI_BPC_12
;
1875 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1876 temp
|= TRANS_DDI_PVSYNC
;
1877 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1878 temp
|= TRANS_DDI_PHSYNC
;
1880 if (cpu_transcoder
== TRANSCODER_EDP
) {
1883 /* On Haswell, can only use the always-on power well for
1884 * eDP when not using the panel fitter, and when not
1885 * using motion blur mitigation (which we don't
1887 if (IS_HASWELL(dev
) &&
1888 (intel_crtc
->config
->pch_pfit
.enabled
||
1889 intel_crtc
->config
->pch_pfit
.force_thru
))
1890 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1892 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1895 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1898 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1906 if (type
== INTEL_OUTPUT_HDMI
) {
1907 if (intel_crtc
->config
->has_hdmi_sink
)
1908 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1910 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1912 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1913 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1914 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1916 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1917 type
== INTEL_OUTPUT_EDP
) {
1918 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1920 if (intel_dp
->is_mst
) {
1921 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1923 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1925 temp
|= DDI_PORT_WIDTH(intel_crtc
->config
->lane_count
);
1926 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1927 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1929 if (intel_dp
->is_mst
) {
1930 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1932 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1934 temp
|= DDI_PORT_WIDTH(intel_crtc
->config
->lane_count
);
1936 WARN(1, "Invalid encoder type %d for pipe %c\n",
1937 intel_encoder
->type
, pipe_name(pipe
));
1940 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1943 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1944 enum transcoder cpu_transcoder
)
1946 i915_reg_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1947 uint32_t val
= I915_READ(reg
);
1949 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1950 val
|= TRANS_DDI_PORT_NONE
;
1951 I915_WRITE(reg
, val
);
1954 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1956 struct drm_device
*dev
= intel_connector
->base
.dev
;
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1958 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1959 int type
= intel_connector
->base
.connector_type
;
1960 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1962 enum transcoder cpu_transcoder
;
1963 enum intel_display_power_domain power_domain
;
1966 power_domain
= intel_display_port_power_domain(intel_encoder
);
1967 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1970 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1974 cpu_transcoder
= TRANSCODER_EDP
;
1976 cpu_transcoder
= (enum transcoder
) pipe
;
1978 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1980 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1981 case TRANS_DDI_MODE_SELECT_HDMI
:
1982 case TRANS_DDI_MODE_SELECT_DVI
:
1983 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1985 case TRANS_DDI_MODE_SELECT_DP_SST
:
1986 if (type
== DRM_MODE_CONNECTOR_eDP
)
1988 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1989 case TRANS_DDI_MODE_SELECT_DP_MST
:
1990 /* if the transcoder is in MST state then
1991 * connector isn't connected */
1994 case TRANS_DDI_MODE_SELECT_FDI
:
1995 return (type
== DRM_MODE_CONNECTOR_VGA
);
2002 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
2005 struct drm_device
*dev
= encoder
->base
.dev
;
2006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2007 enum port port
= intel_ddi_get_encoder_port(encoder
);
2008 enum intel_display_power_domain power_domain
;
2012 power_domain
= intel_display_port_power_domain(encoder
);
2013 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2016 tmp
= I915_READ(DDI_BUF_CTL(port
));
2018 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
2021 if (port
== PORT_A
) {
2022 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
2024 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
2025 case TRANS_DDI_EDP_INPUT_A_ON
:
2026 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
2029 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
2032 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
2039 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
2040 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
2042 if ((tmp
& TRANS_DDI_PORT_MASK
)
2043 == TRANS_DDI_SELECT_PORT(port
)) {
2044 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
2053 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
2058 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
2060 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2061 struct drm_device
*dev
= crtc
->dev
;
2062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2063 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2064 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2065 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2067 if (cpu_transcoder
!= TRANSCODER_EDP
)
2068 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2069 TRANS_CLK_SEL_PORT(port
));
2072 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
2074 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
2075 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2077 if (cpu_transcoder
!= TRANSCODER_EDP
)
2078 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2079 TRANS_CLK_SEL_DISABLED
);
2082 static void skl_ddi_set_iboost(struct drm_device
*dev
, u32 level
,
2083 enum port port
, int type
)
2085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2086 const struct ddi_buf_trans
*ddi_translations
;
2088 uint8_t dp_iboost
, hdmi_iboost
;
2092 /* VBT may override standard boost values */
2093 dp_iboost
= dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
;
2094 hdmi_iboost
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
;
2096 if (type
== INTEL_OUTPUT_DISPLAYPORT
) {
2100 ddi_translations
= skl_get_buf_trans_dp(dev
, &n_entries
);
2101 iboost
= ddi_translations
[level
].i_boost
;
2103 } else if (type
== INTEL_OUTPUT_EDP
) {
2107 ddi_translations
= skl_get_buf_trans_edp(dev
, &n_entries
);
2108 iboost
= ddi_translations
[level
].i_boost
;
2110 } else if (type
== INTEL_OUTPUT_HDMI
) {
2112 iboost
= hdmi_iboost
;
2114 ddi_translations
= skl_get_buf_trans_hdmi(dev
, &n_entries
);
2115 iboost
= ddi_translations
[level
].i_boost
;
2121 /* Make sure that the requested I_boost is valid */
2122 if (iboost
&& iboost
!= 0x1 && iboost
!= 0x3 && iboost
!= 0x7) {
2123 DRM_ERROR("Invalid I_boost value %u\n", iboost
);
2127 reg
= I915_READ(DISPIO_CR_TX_BMU_CR0
);
2128 reg
&= ~BALANCE_LEG_MASK(port
);
2129 reg
&= ~(1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
));
2132 reg
|= iboost
<< BALANCE_LEG_SHIFT(port
);
2134 reg
|= 1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
);
2136 I915_WRITE(DISPIO_CR_TX_BMU_CR0
, reg
);
2139 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
2140 enum port port
, int type
)
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2143 const struct bxt_ddi_buf_trans
*ddi_translations
;
2147 if (type
== INTEL_OUTPUT_EDP
&& dev_priv
->edp_low_vswing
) {
2148 n_entries
= ARRAY_SIZE(bxt_ddi_translations_edp
);
2149 ddi_translations
= bxt_ddi_translations_edp
;
2150 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
2151 || type
== INTEL_OUTPUT_EDP
) {
2152 n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
2153 ddi_translations
= bxt_ddi_translations_dp
;
2154 } else if (type
== INTEL_OUTPUT_HDMI
) {
2155 n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
2156 ddi_translations
= bxt_ddi_translations_hdmi
;
2158 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2163 /* Check if default value has to be used */
2164 if (level
>= n_entries
||
2165 (type
== INTEL_OUTPUT_HDMI
&& level
== HDMI_LEVEL_SHIFT_UNKNOWN
)) {
2166 for (i
= 0; i
< n_entries
; i
++) {
2167 if (ddi_translations
[i
].default_index
) {
2175 * While we write to the group register to program all lanes at once we
2176 * can read only lane registers and we pick lanes 0/1 for that.
2178 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2179 val
&= ~(TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
);
2180 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2182 val
= I915_READ(BXT_PORT_TX_DW2_LN0(port
));
2183 val
&= ~(MARGIN_000
| UNIQ_TRANS_SCALE
);
2184 val
|= ddi_translations
[level
].margin
<< MARGIN_000_SHIFT
|
2185 ddi_translations
[level
].scale
<< UNIQ_TRANS_SCALE_SHIFT
;
2186 I915_WRITE(BXT_PORT_TX_DW2_GRP(port
), val
);
2188 val
= I915_READ(BXT_PORT_TX_DW3_LN0(port
));
2189 val
&= ~SCALE_DCOMP_METHOD
;
2190 if (ddi_translations
[level
].enable
)
2191 val
|= SCALE_DCOMP_METHOD
;
2193 if ((val
& UNIQUE_TRANGE_EN_METHOD
) && !(val
& SCALE_DCOMP_METHOD
))
2194 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2196 I915_WRITE(BXT_PORT_TX_DW3_GRP(port
), val
);
2198 val
= I915_READ(BXT_PORT_TX_DW4_LN0(port
));
2199 val
&= ~DE_EMPHASIS
;
2200 val
|= ddi_translations
[level
].deemphasis
<< DEEMPH_SHIFT
;
2201 I915_WRITE(BXT_PORT_TX_DW4_GRP(port
), val
);
2203 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2204 val
|= TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
;
2205 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2208 static uint32_t translate_signal_level(int signal_levels
)
2212 switch (signal_levels
) {
2214 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2254 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
)
2256 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2257 struct drm_device
*dev
= dport
->base
.base
.dev
;
2258 struct intel_encoder
*encoder
= &dport
->base
;
2259 uint8_t train_set
= intel_dp
->train_set
[0];
2260 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2261 DP_TRAIN_PRE_EMPHASIS_MASK
);
2262 enum port port
= dport
->port
;
2265 level
= translate_signal_level(signal_levels
);
2267 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
2268 skl_ddi_set_iboost(dev
, level
, port
, encoder
->type
);
2269 else if (IS_BROXTON(dev
))
2270 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
2272 return DDI_BUF_TRANS_SELECT(level
);
2275 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
2276 const struct intel_crtc_state
*pipe_config
)
2278 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2279 enum port port
= intel_ddi_get_encoder_port(encoder
);
2281 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
2282 uint32_t dpll
= pipe_config
->ddi_pll_sel
;
2286 * DPLL0 is used for eDP and is the only "private" DPLL (as
2287 * opposed to shared) on SKL
2289 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
2290 WARN_ON(dpll
!= SKL_DPLL0
);
2292 val
= I915_READ(DPLL_CTRL1
);
2294 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
2295 DPLL_CTRL1_SSC(dpll
) |
2296 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2297 val
|= pipe_config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
2299 I915_WRITE(DPLL_CTRL1
, val
);
2300 POSTING_READ(DPLL_CTRL1
);
2303 /* DDI -> PLL mapping */
2304 val
= I915_READ(DPLL_CTRL2
);
2306 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
2307 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
2308 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
2309 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
2311 I915_WRITE(DPLL_CTRL2
, val
);
2313 } else if (INTEL_INFO(dev_priv
)->gen
< 9) {
2314 WARN_ON(pipe_config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
2315 I915_WRITE(PORT_CLK_SEL(port
), pipe_config
->ddi_pll_sel
);
2319 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
2321 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2322 struct drm_device
*dev
= encoder
->dev
;
2323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2324 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
2325 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2326 int type
= intel_encoder
->type
;
2329 if (type
== INTEL_OUTPUT_EDP
) {
2330 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2331 intel_edp_panel_on(intel_dp
);
2334 intel_ddi_clk_select(intel_encoder
, crtc
->config
);
2336 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2337 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2339 intel_dp_set_link_params(intel_dp
, crtc
->config
);
2341 intel_ddi_init_dp_buf_reg(intel_encoder
);
2343 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2344 intel_dp_start_link_train(intel_dp
);
2345 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
2346 intel_dp_stop_link_train(intel_dp
);
2347 } else if (type
== INTEL_OUTPUT_HDMI
) {
2348 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2350 if (IS_BROXTON(dev
)) {
2351 hdmi_level
= dev_priv
->vbt
.
2352 ddi_port_info
[port
].hdmi_level_shift
;
2353 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
2356 intel_hdmi
->set_infoframes(encoder
,
2357 crtc
->config
->has_hdmi_sink
,
2358 &crtc
->config
->base
.adjusted_mode
);
2362 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
2364 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2365 struct drm_device
*dev
= encoder
->dev
;
2366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2367 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2368 int type
= intel_encoder
->type
;
2372 val
= I915_READ(DDI_BUF_CTL(port
));
2373 if (val
& DDI_BUF_CTL_ENABLE
) {
2374 val
&= ~DDI_BUF_CTL_ENABLE
;
2375 I915_WRITE(DDI_BUF_CTL(port
), val
);
2379 val
= I915_READ(DP_TP_CTL(port
));
2380 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2381 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2382 I915_WRITE(DP_TP_CTL(port
), val
);
2385 intel_wait_ddi_buf_idle(dev_priv
, port
);
2387 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2388 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2389 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2390 intel_edp_panel_vdd_on(intel_dp
);
2391 intel_edp_panel_off(intel_dp
);
2394 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
2395 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
2396 DPLL_CTRL2_DDI_CLK_OFF(port
)));
2397 else if (INTEL_INFO(dev
)->gen
< 9)
2398 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
2401 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
2403 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2404 struct drm_crtc
*crtc
= encoder
->crtc
;
2405 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2406 struct drm_device
*dev
= encoder
->dev
;
2407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2408 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2409 int type
= intel_encoder
->type
;
2411 if (type
== INTEL_OUTPUT_HDMI
) {
2412 struct intel_digital_port
*intel_dig_port
=
2413 enc_to_dig_port(encoder
);
2415 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2416 * are ignored so nothing special needs to be done besides
2417 * enabling the port.
2419 I915_WRITE(DDI_BUF_CTL(port
),
2420 intel_dig_port
->saved_port_bits
|
2421 DDI_BUF_CTL_ENABLE
);
2422 } else if (type
== INTEL_OUTPUT_EDP
) {
2423 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2425 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
2426 intel_dp_stop_link_train(intel_dp
);
2428 intel_edp_backlight_on(intel_dp
);
2429 intel_psr_enable(intel_dp
);
2430 intel_edp_drrs_enable(intel_dp
);
2433 if (intel_crtc
->config
->has_audio
) {
2434 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
2435 intel_audio_codec_enable(intel_encoder
);
2439 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
2441 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2442 struct drm_crtc
*crtc
= encoder
->crtc
;
2443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2444 int type
= intel_encoder
->type
;
2445 struct drm_device
*dev
= encoder
->dev
;
2446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2448 if (intel_crtc
->config
->has_audio
) {
2449 intel_audio_codec_disable(intel_encoder
);
2450 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
2453 if (type
== INTEL_OUTPUT_EDP
) {
2454 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2456 intel_edp_drrs_disable(intel_dp
);
2457 intel_psr_disable(intel_dp
);
2458 intel_edp_backlight_off(intel_dp
);
2462 static void hsw_ddi_wrpll_enable(struct drm_i915_private
*dev_priv
,
2463 struct intel_shared_dpll
*pll
)
2465 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
2466 POSTING_READ(WRPLL_CTL(pll
->id
));
2470 static void hsw_ddi_spll_enable(struct drm_i915_private
*dev_priv
,
2471 struct intel_shared_dpll
*pll
)
2473 I915_WRITE(SPLL_CTL
, pll
->config
.hw_state
.spll
);
2474 POSTING_READ(SPLL_CTL
);
2478 static void hsw_ddi_wrpll_disable(struct drm_i915_private
*dev_priv
,
2479 struct intel_shared_dpll
*pll
)
2483 val
= I915_READ(WRPLL_CTL(pll
->id
));
2484 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
2485 POSTING_READ(WRPLL_CTL(pll
->id
));
2488 static void hsw_ddi_spll_disable(struct drm_i915_private
*dev_priv
,
2489 struct intel_shared_dpll
*pll
)
2493 val
= I915_READ(SPLL_CTL
);
2494 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
2495 POSTING_READ(SPLL_CTL
);
2498 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private
*dev_priv
,
2499 struct intel_shared_dpll
*pll
,
2500 struct intel_dpll_hw_state
*hw_state
)
2504 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2507 val
= I915_READ(WRPLL_CTL(pll
->id
));
2508 hw_state
->wrpll
= val
;
2510 return val
& WRPLL_PLL_ENABLE
;
2513 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private
*dev_priv
,
2514 struct intel_shared_dpll
*pll
,
2515 struct intel_dpll_hw_state
*hw_state
)
2519 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2522 val
= I915_READ(SPLL_CTL
);
2523 hw_state
->spll
= val
;
2525 return val
& SPLL_PLL_ENABLE
;
2529 static const char * const hsw_ddi_pll_names
[] = {
2535 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2539 dev_priv
->num_shared_dpll
= 3;
2541 for (i
= 0; i
< 2; i
++) {
2542 dev_priv
->shared_dplls
[i
].id
= i
;
2543 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
2544 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_wrpll_disable
;
2545 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_wrpll_enable
;
2546 dev_priv
->shared_dplls
[i
].get_hw_state
=
2547 hsw_ddi_wrpll_get_hw_state
;
2550 /* SPLL is special, but needs to be initialized anyway.. */
2551 dev_priv
->shared_dplls
[i
].id
= i
;
2552 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
2553 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_spll_disable
;
2554 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_spll_enable
;
2555 dev_priv
->shared_dplls
[i
].get_hw_state
= hsw_ddi_spll_get_hw_state
;
2559 static const char * const skl_ddi_pll_names
[] = {
2565 struct skl_dpll_regs
{
2566 i915_reg_t ctl
, cfgcr1
, cfgcr2
;
2569 /* this array is indexed by the *shared* pll id */
2570 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
2574 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL1
),
2575 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL1
),
2579 .ctl
= WRPLL_CTL(0),
2580 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL2
),
2581 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL2
),
2585 .ctl
= WRPLL_CTL(1),
2586 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL3
),
2587 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL3
),
2591 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2592 struct intel_shared_dpll
*pll
)
2596 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2598 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2601 val
= I915_READ(DPLL_CTRL1
);
2603 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
2604 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2605 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
2607 I915_WRITE(DPLL_CTRL1
, val
);
2608 POSTING_READ(DPLL_CTRL1
);
2610 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
2611 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
2612 POSTING_READ(regs
[pll
->id
].cfgcr1
);
2613 POSTING_READ(regs
[pll
->id
].cfgcr2
);
2615 /* the enable bit is always bit 31 */
2616 I915_WRITE(regs
[pll
->id
].ctl
,
2617 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
2619 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
2620 DRM_ERROR("DPLL %d not locked\n", dpll
);
2623 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2624 struct intel_shared_dpll
*pll
)
2626 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2628 /* the enable bit is always bit 31 */
2629 I915_WRITE(regs
[pll
->id
].ctl
,
2630 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
2631 POSTING_READ(regs
[pll
->id
].ctl
);
2634 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2635 struct intel_shared_dpll
*pll
,
2636 struct intel_dpll_hw_state
*hw_state
)
2640 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2642 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2645 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2648 val
= I915_READ(regs
[pll
->id
].ctl
);
2649 if (!(val
& LCPLL_PLL_ENABLE
))
2652 val
= I915_READ(DPLL_CTRL1
);
2653 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
2655 /* avoid reading back stale values if HDMI mode is not enabled */
2656 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
2657 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
2658 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
2664 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2668 dev_priv
->num_shared_dpll
= 3;
2670 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2671 dev_priv
->shared_dplls
[i
].id
= i
;
2672 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
2673 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
2674 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
2675 dev_priv
->shared_dplls
[i
].get_hw_state
=
2676 skl_ddi_pll_get_hw_state
;
2680 static void broxton_phy_init(struct drm_i915_private
*dev_priv
,
2686 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
2687 val
|= GT_DISPLAY_POWER_ON(phy
);
2688 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
2690 /* Considering 10ms timeout until BSpec is updated */
2691 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy
)) & PHY_POWER_GOOD
, 10))
2692 DRM_ERROR("timeout during PHY%d power on\n", phy
);
2694 for (port
= (phy
== DPIO_PHY0
? PORT_B
: PORT_A
);
2695 port
<= (phy
== DPIO_PHY0
? PORT_C
: PORT_A
); port
++) {
2698 for (lane
= 0; lane
< 4; lane
++) {
2699 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2701 * Note that on CHV this flag is called UPAR, but has
2702 * the same function.
2704 val
&= ~LATENCY_OPTIM
;
2706 val
|= LATENCY_OPTIM
;
2708 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
2712 /* Program PLL Rcomp code offset */
2713 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
2714 val
&= ~IREF0RC_OFFSET_MASK
;
2715 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
2716 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
2718 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
2719 val
&= ~IREF1RC_OFFSET_MASK
;
2720 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
2721 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
2723 /* Program power gating */
2724 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
2725 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
2727 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
2729 if (phy
== DPIO_PHY0
) {
2730 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
2731 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
2732 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
2735 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
2736 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
2738 * On PHY1 disable power on the second channel, since no port is
2739 * connected there. On PHY0 both channels have a port, so leave it
2741 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2742 * power down the second channel on PHY0 as well.
2744 if (phy
== DPIO_PHY1
)
2745 val
|= OCL2_LDOFUSE_PWR_DIS
;
2746 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
2748 if (phy
== DPIO_PHY0
) {
2751 * PHY0 isn't connected to an RCOMP resistor so copy over
2752 * the corresponding calibrated value from PHY1, and disable
2753 * the automatic calibration on PHY0.
2755 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
,
2757 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2759 val
= I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1
));
2760 val
= (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
2761 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
2762 val
<< GRC_CODE_SLOW_SHIFT
|
2764 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
2766 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
2767 val
|= GRC_DIS
| GRC_RDY_OVRD
;
2768 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
2771 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2772 val
|= COMMON_RESET_DIS
;
2773 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2776 void broxton_ddi_phy_init(struct drm_device
*dev
)
2778 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2779 broxton_phy_init(dev
->dev_private
, DPIO_PHY1
);
2780 broxton_phy_init(dev
->dev_private
, DPIO_PHY0
);
2783 static void broxton_phy_uninit(struct drm_i915_private
*dev_priv
,
2788 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2789 val
&= ~COMMON_RESET_DIS
;
2790 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2793 void broxton_ddi_phy_uninit(struct drm_device
*dev
)
2795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2797 broxton_phy_uninit(dev_priv
, DPIO_PHY1
);
2798 broxton_phy_uninit(dev_priv
, DPIO_PHY0
);
2800 /* FIXME: do this in broxton_phy_uninit per phy */
2801 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, 0);
2804 static const char * const bxt_ddi_pll_names
[] = {
2810 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2811 struct intel_shared_dpll
*pll
)
2814 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2816 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2817 temp
&= ~PORT_PLL_REF_SEL
;
2818 /* Non-SSC reference */
2819 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2821 /* Disable 10 bit clock */
2822 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2823 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2824 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2827 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2828 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
2829 temp
|= pll
->config
.hw_state
.ebb0
;
2830 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
2832 /* Write M2 integer */
2833 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
2834 temp
&= ~PORT_PLL_M2_MASK
;
2835 temp
|= pll
->config
.hw_state
.pll0
;
2836 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
2839 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
2840 temp
&= ~PORT_PLL_N_MASK
;
2841 temp
|= pll
->config
.hw_state
.pll1
;
2842 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
2844 /* Write M2 fraction */
2845 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
2846 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
2847 temp
|= pll
->config
.hw_state
.pll2
;
2848 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
2850 /* Write M2 fraction enable */
2851 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
2852 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
2853 temp
|= pll
->config
.hw_state
.pll3
;
2854 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
2857 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
2858 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
2859 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
2860 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
2861 temp
|= pll
->config
.hw_state
.pll6
;
2862 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
2864 /* Write calibration val */
2865 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
2866 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
2867 temp
|= pll
->config
.hw_state
.pll8
;
2868 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
2870 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
2871 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
2872 temp
|= pll
->config
.hw_state
.pll9
;
2873 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
2875 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
2876 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
2877 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
2878 temp
|= pll
->config
.hw_state
.pll10
;
2879 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
2881 /* Recalibrate with new settings */
2882 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2883 temp
|= PORT_PLL_RECALIBRATE
;
2884 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2885 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2886 temp
|= pll
->config
.hw_state
.ebb4
;
2887 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2890 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2891 temp
|= PORT_PLL_ENABLE
;
2892 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2893 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2895 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
2896 PORT_PLL_LOCK
), 200))
2897 DRM_ERROR("PLL %d not locked\n", port
);
2900 * While we write to the group register to program all lanes at once we
2901 * can read only lane registers and we pick lanes 0/1 for that.
2903 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2904 temp
&= ~LANE_STAGGER_MASK
;
2905 temp
&= ~LANESTAGGER_STRAP_OVRD
;
2906 temp
|= pll
->config
.hw_state
.pcsdw12
;
2907 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
2910 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2911 struct intel_shared_dpll
*pll
)
2913 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2916 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2917 temp
&= ~PORT_PLL_ENABLE
;
2918 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2919 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2922 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2923 struct intel_shared_dpll
*pll
,
2924 struct intel_dpll_hw_state
*hw_state
)
2926 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2929 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2932 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2933 if (!(val
& PORT_PLL_ENABLE
))
2936 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2937 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
2939 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2940 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
2942 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
2943 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
2945 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
2946 hw_state
->pll1
&= PORT_PLL_N_MASK
;
2948 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
2949 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
2951 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
2952 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
2954 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
2955 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
2956 PORT_PLL_INT_COEFF_MASK
|
2957 PORT_PLL_GAIN_CTL_MASK
;
2959 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
2960 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
2962 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(port
, 9));
2963 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
2965 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
2966 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
2967 PORT_PLL_DCO_AMP_MASK
;
2970 * While we write to the group register to program all lanes at once we
2971 * can read only lane registers. We configure all lanes the same way, so
2972 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2974 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2975 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
)) != hw_state
->pcsdw12
)
2976 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2978 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
2979 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
2984 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2988 dev_priv
->num_shared_dpll
= 3;
2990 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2991 dev_priv
->shared_dplls
[i
].id
= i
;
2992 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
2993 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
2994 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
2995 dev_priv
->shared_dplls
[i
].get_hw_state
=
2996 bxt_ddi_pll_get_hw_state
;
3000 void intel_ddi_pll_init(struct drm_device
*dev
)
3002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3003 uint32_t val
= I915_READ(LCPLL_CTL
);
3005 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
3006 skl_shared_dplls_init(dev_priv
);
3007 else if (IS_BROXTON(dev
))
3008 bxt_shared_dplls_init(dev_priv
);
3010 hsw_shared_dplls_init(dev_priv
);
3012 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
3015 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
3016 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
3017 if (skl_sanitize_cdclk(dev_priv
))
3018 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
3019 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
3020 DRM_ERROR("LCPLL1 is disabled\n");
3021 } else if (IS_BROXTON(dev
)) {
3022 broxton_init_cdclk(dev
);
3023 broxton_ddi_phy_init(dev
);
3026 * The LCPLL register should be turned on by the BIOS. For now
3027 * let's just check its state and print errors in case
3028 * something is wrong. Don't even try to turn it on.
3031 if (val
& LCPLL_CD_SOURCE_FCLK
)
3032 DRM_ERROR("CDCLK source is not LCPLL\n");
3034 if (val
& LCPLL_PLL_DISABLE
)
3035 DRM_ERROR("LCPLL is disabled\n");
3039 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
)
3041 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3042 struct drm_i915_private
*dev_priv
=
3043 to_i915(intel_dig_port
->base
.base
.dev
);
3044 enum port port
= intel_dig_port
->port
;
3048 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
3049 val
= I915_READ(DDI_BUF_CTL(port
));
3050 if (val
& DDI_BUF_CTL_ENABLE
) {
3051 val
&= ~DDI_BUF_CTL_ENABLE
;
3052 I915_WRITE(DDI_BUF_CTL(port
), val
);
3056 val
= I915_READ(DP_TP_CTL(port
));
3057 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
3058 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
3059 I915_WRITE(DP_TP_CTL(port
), val
);
3060 POSTING_READ(DP_TP_CTL(port
));
3063 intel_wait_ddi_buf_idle(dev_priv
, port
);
3066 val
= DP_TP_CTL_ENABLE
|
3067 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
3068 if (intel_dp
->is_mst
)
3069 val
|= DP_TP_CTL_MODE_MST
;
3071 val
|= DP_TP_CTL_MODE_SST
;
3072 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3073 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
3075 I915_WRITE(DP_TP_CTL(port
), val
);
3076 POSTING_READ(DP_TP_CTL(port
));
3078 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
3079 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
3080 POSTING_READ(DDI_BUF_CTL(port
));
3085 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
3087 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3088 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
3091 intel_ddi_post_disable(intel_encoder
);
3093 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
3094 val
&= ~FDI_RX_ENABLE
;
3095 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
3097 val
= I915_READ(FDI_RX_MISC(PIPE_A
));
3098 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
3099 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3100 I915_WRITE(FDI_RX_MISC(PIPE_A
), val
);
3102 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
3104 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
3106 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
3107 val
&= ~FDI_RX_PLL_ENABLE
;
3108 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
3111 void intel_ddi_get_config(struct intel_encoder
*encoder
,
3112 struct intel_crtc_state
*pipe_config
)
3114 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
3115 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
3116 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
3117 struct intel_hdmi
*intel_hdmi
;
3118 u32 temp
, flags
= 0;
3120 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3121 if (temp
& TRANS_DDI_PHSYNC
)
3122 flags
|= DRM_MODE_FLAG_PHSYNC
;
3124 flags
|= DRM_MODE_FLAG_NHSYNC
;
3125 if (temp
& TRANS_DDI_PVSYNC
)
3126 flags
|= DRM_MODE_FLAG_PVSYNC
;
3128 flags
|= DRM_MODE_FLAG_NVSYNC
;
3130 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
3132 switch (temp
& TRANS_DDI_BPC_MASK
) {
3133 case TRANS_DDI_BPC_6
:
3134 pipe_config
->pipe_bpp
= 18;
3136 case TRANS_DDI_BPC_8
:
3137 pipe_config
->pipe_bpp
= 24;
3139 case TRANS_DDI_BPC_10
:
3140 pipe_config
->pipe_bpp
= 30;
3142 case TRANS_DDI_BPC_12
:
3143 pipe_config
->pipe_bpp
= 36;
3149 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
3150 case TRANS_DDI_MODE_SELECT_HDMI
:
3151 pipe_config
->has_hdmi_sink
= true;
3152 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
3154 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
3155 pipe_config
->has_infoframe
= true;
3157 case TRANS_DDI_MODE_SELECT_DVI
:
3158 case TRANS_DDI_MODE_SELECT_FDI
:
3160 case TRANS_DDI_MODE_SELECT_DP_SST
:
3161 case TRANS_DDI_MODE_SELECT_DP_MST
:
3162 pipe_config
->has_dp_encoder
= true;
3163 pipe_config
->lane_count
=
3164 ((temp
& DDI_PORT_WIDTH_MASK
) >> DDI_PORT_WIDTH_SHIFT
) + 1;
3165 intel_dp_get_m_n(intel_crtc
, pipe_config
);
3171 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
3172 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
3173 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
3174 pipe_config
->has_audio
= true;
3177 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
3178 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
3180 * This is a big fat ugly hack.
3182 * Some machines in UEFI boot mode provide us a VBT that has 18
3183 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3184 * unknown we fail to light up. Yet the same BIOS boots up with
3185 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3186 * max, not what it tells us to use.
3188 * Note: This will still be broken if the eDP panel is not lit
3189 * up by the BIOS, and thus we can't get the mode at module
3192 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3193 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
3194 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
3197 intel_ddi_clock_get(encoder
, pipe_config
);
3200 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
3202 /* HDMI has nothing special to destroy, so we can go with this. */
3203 intel_dp_encoder_destroy(encoder
);
3206 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
3207 struct intel_crtc_state
*pipe_config
)
3209 int type
= encoder
->type
;
3210 int port
= intel_ddi_get_encoder_port(encoder
);
3212 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
3215 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
3217 if (type
== INTEL_OUTPUT_HDMI
)
3218 return intel_hdmi_compute_config(encoder
, pipe_config
);
3220 return intel_dp_compute_config(encoder
, pipe_config
);
3223 static const struct drm_encoder_funcs intel_ddi_funcs
= {
3224 .destroy
= intel_ddi_destroy
,
3227 static struct intel_connector
*
3228 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
3230 struct intel_connector
*connector
;
3231 enum port port
= intel_dig_port
->port
;
3233 connector
= intel_connector_alloc();
3237 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
3238 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
3246 static struct intel_connector
*
3247 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
3249 struct intel_connector
*connector
;
3250 enum port port
= intel_dig_port
->port
;
3252 connector
= intel_connector_alloc();
3256 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
3257 intel_hdmi_init_connector(intel_dig_port
, connector
);
3262 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
3264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3265 struct intel_digital_port
*intel_dig_port
;
3266 struct intel_encoder
*intel_encoder
;
3267 struct drm_encoder
*encoder
;
3268 bool init_hdmi
, init_dp
;
3270 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
3271 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
3272 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
3273 if (!init_dp
&& !init_hdmi
) {
3274 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3279 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3280 if (!intel_dig_port
)
3283 intel_encoder
= &intel_dig_port
->base
;
3284 encoder
= &intel_encoder
->base
;
3286 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
3287 DRM_MODE_ENCODER_TMDS
, NULL
);
3289 intel_encoder
->compute_config
= intel_ddi_compute_config
;
3290 intel_encoder
->enable
= intel_enable_ddi
;
3291 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
3292 intel_encoder
->disable
= intel_disable_ddi
;
3293 intel_encoder
->post_disable
= intel_ddi_post_disable
;
3294 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
3295 intel_encoder
->get_config
= intel_ddi_get_config
;
3297 intel_dig_port
->port
= port
;
3298 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
3299 (DDI_BUF_PORT_REVERSAL
|
3303 * Bspec says that DDI_A_4_LANES is the only supported configuration
3304 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3305 * wasn't lit up at boot. Force this bit on in our internal
3306 * configuration so that we use the proper lane count for our
3309 if (IS_BROXTON(dev
) && port
== PORT_A
) {
3310 if (!(intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
)) {
3311 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3312 intel_dig_port
->saved_port_bits
|= DDI_A_4_LANES
;
3316 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
3317 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3318 intel_encoder
->cloneable
= 0;
3321 if (!intel_ddi_init_dp_connector(intel_dig_port
))
3324 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
3326 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3327 * interrupts to check the external panel connection.
3329 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
) && port
== PORT_B
)
3330 dev_priv
->hotplug
.irq_port
[PORT_A
] = intel_dig_port
;
3332 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
3335 /* In theory we don't need the encoder->type check, but leave it just in
3336 * case we have some really bad VBTs... */
3337 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
3338 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
3345 drm_encoder_cleanup(encoder
);
3346 kfree(intel_dig_port
);