2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 const u32
*ddi_translations
= ((use_fdi_mode
) ?
94 hsw_ddi_translations_fdi
:
95 hsw_ddi_translations_dp
);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode
? "FDI" : "DP");
101 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
106 I915_WRITE(reg
, ddi_translations
[i
]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device
*dev
)
121 for (port
= PORT_A
; port
< PORT_E
; port
++)
122 intel_prepare_ddi_buffers(dev
, port
, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
131 static const long hsw_ddi_buf_ctl_values
[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW
,
133 DDI_BUF_EMP_400MV_3_5DB_HSW
,
134 DDI_BUF_EMP_400MV_6DB_HSW
,
135 DDI_BUF_EMP_400MV_9_5DB_HSW
,
136 DDI_BUF_EMP_600MV_0DB_HSW
,
137 DDI_BUF_EMP_600MV_3_5DB_HSW
,
138 DDI_BUF_EMP_600MV_6DB_HSW
,
139 DDI_BUF_EMP_800MV_0DB_HSW
,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
146 uint32_t reg
= DDI_BUF_CTL(port
);
149 for (i
= 0; i
< 8; i
++) {
151 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
168 struct drm_device
*dev
= crtc
->dev
;
169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
171 u32 temp
, i
, rx_ctl_val
;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
185 FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
186 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
187 POSTING_READ(_FDI_RXA_CTL
);
190 /* Switch from Rawclk to PCDclk */
191 rx_ctl_val
|= FDI_PCDCLK
;
192 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
194 /* Configure Port Clock Select */
195 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
197 /* Start the training iterating through available voltages and emphasis,
198 * testing each value twice. */
199 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
200 /* Configure DP_TP_CTL with auto-training */
201 I915_WRITE(DP_TP_CTL(PORT_E
),
202 DP_TP_CTL_FDI_AUTOTRAIN
|
203 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
204 DP_TP_CTL_LINK_TRAIN_PAT1
|
207 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
208 * DDI E does not support port reversal, the functionality is
209 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
210 * port reversal bit */
211 I915_WRITE(DDI_BUF_CTL(PORT_E
),
213 ((intel_crtc
->config
.fdi_lanes
- 1) << 1) |
214 hsw_ddi_buf_ctl_values
[i
/ 2]);
215 POSTING_READ(DDI_BUF_CTL(PORT_E
));
219 /* Program PCH FDI Receiver TU */
220 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
222 /* Enable PCH FDI Receiver with auto-training */
223 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
224 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
225 POSTING_READ(_FDI_RXA_CTL
);
227 /* Wait for FDI receiver lane calibration */
230 /* Unset FDI_RX_MISC pwrdn lanes */
231 temp
= I915_READ(_FDI_RXA_MISC
);
232 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
233 I915_WRITE(_FDI_RXA_MISC
, temp
);
234 POSTING_READ(_FDI_RXA_MISC
);
236 /* Wait for FDI auto training time */
239 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
240 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
241 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
243 /* Enable normal pixel sending for FDI */
244 I915_WRITE(DP_TP_CTL(PORT_E
),
245 DP_TP_CTL_FDI_AUTOTRAIN
|
246 DP_TP_CTL_LINK_TRAIN_NORMAL
|
247 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
253 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
254 temp
&= ~DDI_BUF_CTL_ENABLE
;
255 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
256 POSTING_READ(DDI_BUF_CTL(PORT_E
));
258 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
259 temp
= I915_READ(DP_TP_CTL(PORT_E
));
260 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
261 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
262 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
263 POSTING_READ(DP_TP_CTL(PORT_E
));
265 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
267 rx_ctl_val
&= ~FDI_RX_ENABLE
;
268 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
269 POSTING_READ(_FDI_RXA_CTL
);
271 /* Reset FDI_RX_MISC pwrdn lanes */
272 temp
= I915_READ(_FDI_RXA_MISC
);
273 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
274 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
275 I915_WRITE(_FDI_RXA_MISC
, temp
);
276 POSTING_READ(_FDI_RXA_MISC
);
279 DRM_ERROR("FDI link training failed!\n");
282 /* WRPLL clock dividers */
283 struct wrpll_tmds_clock
{
285 u16 p
; /* Post divider */
286 u16 n2
; /* Feedback divider */
287 u16 r2
; /* Reference divider */
290 /* Table of matching values for WRPLL clocks programming for each frequency.
291 * The code assumes this table is sorted. */
292 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
307 {27027, 18, 100, 111},
335 {40541, 22, 147, 89},
345 {44900, 20, 108, 65},
361 {54054, 16, 173, 108},
413 {81081, 6, 100, 111},
458 {108108, 8, 173, 108},
465 {111264, 8, 150, 91},
509 {135250, 6, 167, 111},
532 {148352, 4, 100, 91},
554 {162162, 4, 131, 109},
562 {169000, 4, 104, 83},
609 {202000, 4, 112, 75},
611 {203000, 4, 146, 97},
668 static void intel_ddi_mode_set(struct drm_encoder
*encoder
,
669 struct drm_display_mode
*mode
,
670 struct drm_display_mode
*adjusted_mode
)
672 struct drm_crtc
*crtc
= encoder
->crtc
;
673 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
674 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
675 int port
= intel_ddi_get_encoder_port(intel_encoder
);
676 int pipe
= intel_crtc
->pipe
;
677 int type
= intel_encoder
->type
;
679 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
680 port_name(port
), pipe_name(pipe
));
682 intel_crtc
->eld_vld
= false;
683 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
684 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
685 struct intel_digital_port
*intel_dig_port
=
686 enc_to_dig_port(encoder
);
688 intel_dp
->DP
= intel_dig_port
->port_reversal
|
689 DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
690 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
692 if (intel_dp
->has_audio
) {
693 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
694 pipe_name(intel_crtc
->pipe
));
697 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
698 intel_write_eld(encoder
, adjusted_mode
);
701 intel_dp_init_link_config(intel_dp
);
703 } else if (type
== INTEL_OUTPUT_HDMI
) {
704 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
706 if (intel_hdmi
->has_audio
) {
707 /* Proper support for digital audio needs a new logic
708 * and a new set of registers, so we leave it for future
711 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
712 pipe_name(intel_crtc
->pipe
));
715 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
716 intel_write_eld(encoder
, adjusted_mode
);
719 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
723 static struct intel_encoder
*
724 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
726 struct drm_device
*dev
= crtc
->dev
;
727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
728 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
729 int num_encoders
= 0;
731 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
736 if (num_encoders
!= 1)
737 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
738 pipe_name(intel_crtc
->pipe
));
744 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
746 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
747 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
748 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
751 switch (intel_crtc
->ddi_pll_sel
) {
752 case PORT_CLK_SEL_SPLL
:
753 plls
->spll_refcount
--;
754 if (plls
->spll_refcount
== 0) {
755 DRM_DEBUG_KMS("Disabling SPLL\n");
756 val
= I915_READ(SPLL_CTL
);
757 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
758 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
759 POSTING_READ(SPLL_CTL
);
762 case PORT_CLK_SEL_WRPLL1
:
763 plls
->wrpll1_refcount
--;
764 if (plls
->wrpll1_refcount
== 0) {
765 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
766 val
= I915_READ(WRPLL_CTL1
);
767 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
768 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
769 POSTING_READ(WRPLL_CTL1
);
772 case PORT_CLK_SEL_WRPLL2
:
773 plls
->wrpll2_refcount
--;
774 if (plls
->wrpll2_refcount
== 0) {
775 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
776 val
= I915_READ(WRPLL_CTL2
);
777 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
778 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
779 POSTING_READ(WRPLL_CTL2
);
784 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
785 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
786 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
788 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
791 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
795 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
796 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
799 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
802 *p
= wrpll_tmds_clock_table
[i
].p
;
803 *n2
= wrpll_tmds_clock_table
[i
].n2
;
804 *r2
= wrpll_tmds_clock_table
[i
].r2
;
806 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
807 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
808 wrpll_tmds_clock_table
[i
].clock
, clock
);
810 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
811 clock
, *p
, *n2
, *r2
);
814 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
816 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
817 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
818 struct drm_encoder
*encoder
= &intel_encoder
->base
;
819 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
820 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
821 int type
= intel_encoder
->type
;
822 enum pipe pipe
= intel_crtc
->pipe
;
825 /* TODO: reuse PLLs when possible (compare values) */
827 intel_ddi_put_crtc_pll(crtc
);
829 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
830 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
832 switch (intel_dp
->link_bw
) {
833 case DP_LINK_BW_1_62
:
834 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
837 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
840 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
843 DRM_ERROR("Link bandwidth %d unsupported\n",
848 /* We don't need to turn any PLL on because we'll use LCPLL. */
851 } else if (type
== INTEL_OUTPUT_HDMI
) {
854 if (plls
->wrpll1_refcount
== 0) {
855 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
857 plls
->wrpll1_refcount
++;
859 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
860 } else if (plls
->wrpll2_refcount
== 0) {
861 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
863 plls
->wrpll2_refcount
++;
865 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
867 DRM_ERROR("No WRPLLs available!\n");
871 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
872 "WRPLL already enabled\n");
874 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
876 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
877 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
878 WRPLL_DIVIDER_POST(p
);
880 } else if (type
== INTEL_OUTPUT_ANALOG
) {
881 if (plls
->spll_refcount
== 0) {
882 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
884 plls
->spll_refcount
++;
886 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
888 DRM_ERROR("SPLL already in use\n");
892 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
893 "SPLL already enabled\n");
895 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
898 WARN(1, "Invalid DDI encoder type %d\n", type
);
902 I915_WRITE(reg
, val
);
908 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
910 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
911 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
912 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
913 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
914 int type
= intel_encoder
->type
;
917 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
919 temp
= TRANS_MSA_SYNC_CLK
;
920 switch (intel_crtc
->config
.pipe_bpp
) {
922 temp
|= TRANS_MSA_6_BPC
;
925 temp
|= TRANS_MSA_8_BPC
;
928 temp
|= TRANS_MSA_10_BPC
;
931 temp
|= TRANS_MSA_12_BPC
;
936 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
940 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
942 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
943 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
944 struct drm_encoder
*encoder
= &intel_encoder
->base
;
945 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
946 enum pipe pipe
= intel_crtc
->pipe
;
947 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
948 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
949 int type
= intel_encoder
->type
;
952 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
953 temp
= TRANS_DDI_FUNC_ENABLE
;
954 temp
|= TRANS_DDI_SELECT_PORT(port
);
956 switch (intel_crtc
->config
.pipe_bpp
) {
958 temp
|= TRANS_DDI_BPC_6
;
961 temp
|= TRANS_DDI_BPC_8
;
964 temp
|= TRANS_DDI_BPC_10
;
967 temp
|= TRANS_DDI_BPC_12
;
973 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
974 temp
|= TRANS_DDI_PVSYNC
;
975 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
976 temp
|= TRANS_DDI_PHSYNC
;
978 if (cpu_transcoder
== TRANSCODER_EDP
) {
981 /* Can only use the always-on power well for eDP when
982 * not using the panel fitter, and when not using motion
983 * blur mitigation (which we don't support). */
984 if (intel_crtc
->config
.pch_pfit
.size
)
985 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
987 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
990 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
993 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1001 if (type
== INTEL_OUTPUT_HDMI
) {
1002 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1004 if (intel_hdmi
->has_hdmi_sink
)
1005 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1007 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1009 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1010 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1011 temp
|= (intel_crtc
->config
.fdi_lanes
- 1) << 1;
1013 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1014 type
== INTEL_OUTPUT_EDP
) {
1015 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1017 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1019 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1021 WARN(1, "Invalid encoder type %d for pipe %c\n",
1022 intel_encoder
->type
, pipe_name(pipe
));
1025 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1028 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1029 enum transcoder cpu_transcoder
)
1031 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1032 uint32_t val
= I915_READ(reg
);
1034 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1035 val
|= TRANS_DDI_PORT_NONE
;
1036 I915_WRITE(reg
, val
);
1039 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1041 struct drm_device
*dev
= intel_connector
->base
.dev
;
1042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1043 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1044 int type
= intel_connector
->base
.connector_type
;
1045 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1047 enum transcoder cpu_transcoder
;
1050 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1054 cpu_transcoder
= TRANSCODER_EDP
;
1056 cpu_transcoder
= (enum transcoder
) pipe
;
1058 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1060 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1061 case TRANS_DDI_MODE_SELECT_HDMI
:
1062 case TRANS_DDI_MODE_SELECT_DVI
:
1063 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1065 case TRANS_DDI_MODE_SELECT_DP_SST
:
1066 if (type
== DRM_MODE_CONNECTOR_eDP
)
1068 case TRANS_DDI_MODE_SELECT_DP_MST
:
1069 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1071 case TRANS_DDI_MODE_SELECT_FDI
:
1072 return (type
== DRM_MODE_CONNECTOR_VGA
);
1079 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1082 struct drm_device
*dev
= encoder
->base
.dev
;
1083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1084 enum port port
= intel_ddi_get_encoder_port(encoder
);
1088 tmp
= I915_READ(DDI_BUF_CTL(port
));
1090 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1093 if (port
== PORT_A
) {
1094 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1096 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1097 case TRANS_DDI_EDP_INPUT_A_ON
:
1098 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1101 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1104 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1111 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1112 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1114 if ((tmp
& TRANS_DDI_PORT_MASK
)
1115 == TRANS_DDI_SELECT_PORT(port
)) {
1122 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1127 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1131 enum port port
= I915_MAX_PORTS
;
1132 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1136 if (cpu_transcoder
== TRANSCODER_EDP
) {
1139 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1140 temp
&= TRANS_DDI_PORT_MASK
;
1142 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1143 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1147 if (port
== I915_MAX_PORTS
) {
1148 WARN(1, "Pipe %c enabled on an unknown port\n",
1150 ret
= PORT_CLK_SEL_NONE
;
1152 ret
= I915_READ(PORT_CLK_SEL(port
));
1153 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1154 "0x%08x\n", pipe_name(pipe
), port_name(port
),
1161 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1165 struct intel_crtc
*intel_crtc
;
1167 for_each_pipe(pipe
) {
1169 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1171 if (!intel_crtc
->active
)
1174 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1177 switch (intel_crtc
->ddi_pll_sel
) {
1178 case PORT_CLK_SEL_SPLL
:
1179 dev_priv
->ddi_plls
.spll_refcount
++;
1181 case PORT_CLK_SEL_WRPLL1
:
1182 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1184 case PORT_CLK_SEL_WRPLL2
:
1185 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1191 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1193 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1194 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1195 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1196 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1197 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1199 if (cpu_transcoder
!= TRANSCODER_EDP
)
1200 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1201 TRANS_CLK_SEL_PORT(port
));
1204 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1206 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1207 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1209 if (cpu_transcoder
!= TRANSCODER_EDP
)
1210 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1211 TRANS_CLK_SEL_DISABLED
);
1214 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1216 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1217 struct drm_crtc
*crtc
= encoder
->crtc
;
1218 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1219 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1220 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1221 int type
= intel_encoder
->type
;
1223 if (type
== INTEL_OUTPUT_EDP
) {
1224 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1225 ironlake_edp_panel_vdd_on(intel_dp
);
1226 ironlake_edp_panel_on(intel_dp
);
1227 ironlake_edp_panel_vdd_off(intel_dp
, true);
1230 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1231 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1233 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1234 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1236 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1237 intel_dp_start_link_train(intel_dp
);
1238 intel_dp_complete_link_train(intel_dp
);
1242 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1244 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1245 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1246 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1247 int type
= intel_encoder
->type
;
1251 val
= I915_READ(DDI_BUF_CTL(port
));
1252 if (val
& DDI_BUF_CTL_ENABLE
) {
1253 val
&= ~DDI_BUF_CTL_ENABLE
;
1254 I915_WRITE(DDI_BUF_CTL(port
), val
);
1258 val
= I915_READ(DP_TP_CTL(port
));
1259 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1260 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1261 I915_WRITE(DP_TP_CTL(port
), val
);
1264 intel_wait_ddi_buf_idle(dev_priv
, port
);
1266 if (type
== INTEL_OUTPUT_EDP
) {
1267 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1268 ironlake_edp_panel_vdd_on(intel_dp
);
1269 ironlake_edp_panel_off(intel_dp
);
1272 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1275 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1277 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1278 struct drm_crtc
*crtc
= encoder
->crtc
;
1279 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1280 int pipe
= intel_crtc
->pipe
;
1281 struct drm_device
*dev
= encoder
->dev
;
1282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1283 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1284 int type
= intel_encoder
->type
;
1287 if (type
== INTEL_OUTPUT_HDMI
) {
1288 struct intel_digital_port
*intel_dig_port
=
1289 enc_to_dig_port(encoder
);
1291 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1292 * are ignored so nothing special needs to be done besides
1293 * enabling the port.
1295 I915_WRITE(DDI_BUF_CTL(port
),
1296 intel_dig_port
->port_reversal
| DDI_BUF_CTL_ENABLE
);
1297 } else if (type
== INTEL_OUTPUT_EDP
) {
1298 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1300 ironlake_edp_backlight_on(intel_dp
);
1303 if (intel_crtc
->eld_vld
) {
1304 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1305 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1306 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1310 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1312 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1313 struct drm_crtc
*crtc
= encoder
->crtc
;
1314 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1315 int pipe
= intel_crtc
->pipe
;
1316 int type
= intel_encoder
->type
;
1317 struct drm_device
*dev
= encoder
->dev
;
1318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1321 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1322 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1323 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1325 if (type
== INTEL_OUTPUT_EDP
) {
1326 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1328 ironlake_edp_backlight_off(intel_dp
);
1332 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1334 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1336 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1339 else if (IS_ULT(dev_priv
->dev
))
1345 void intel_ddi_pll_init(struct drm_device
*dev
)
1347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1348 uint32_t val
= I915_READ(LCPLL_CTL
);
1350 /* The LCPLL register should be turned on by the BIOS. For now let's
1351 * just check its state and print errors in case something is wrong.
1352 * Don't even try to turn it on.
1355 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1356 intel_ddi_get_cdclk_freq(dev_priv
));
1358 if (val
& LCPLL_CD_SOURCE_FCLK
)
1359 DRM_ERROR("CDCLK source is not LCPLL\n");
1361 if (val
& LCPLL_PLL_DISABLE
)
1362 DRM_ERROR("LCPLL is disabled\n");
1365 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1367 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1368 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1369 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1370 enum port port
= intel_dig_port
->port
;
1374 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1375 val
= I915_READ(DDI_BUF_CTL(port
));
1376 if (val
& DDI_BUF_CTL_ENABLE
) {
1377 val
&= ~DDI_BUF_CTL_ENABLE
;
1378 I915_WRITE(DDI_BUF_CTL(port
), val
);
1382 val
= I915_READ(DP_TP_CTL(port
));
1383 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1384 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1385 I915_WRITE(DP_TP_CTL(port
), val
);
1386 POSTING_READ(DP_TP_CTL(port
));
1389 intel_wait_ddi_buf_idle(dev_priv
, port
);
1392 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1393 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1394 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1395 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1396 I915_WRITE(DP_TP_CTL(port
), val
);
1397 POSTING_READ(DP_TP_CTL(port
));
1399 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1400 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1401 POSTING_READ(DDI_BUF_CTL(port
));
1406 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1408 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1409 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1412 intel_ddi_post_disable(intel_encoder
);
1414 val
= I915_READ(_FDI_RXA_CTL
);
1415 val
&= ~FDI_RX_ENABLE
;
1416 I915_WRITE(_FDI_RXA_CTL
, val
);
1418 val
= I915_READ(_FDI_RXA_MISC
);
1419 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1420 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1421 I915_WRITE(_FDI_RXA_MISC
, val
);
1423 val
= I915_READ(_FDI_RXA_CTL
);
1425 I915_WRITE(_FDI_RXA_CTL
, val
);
1427 val
= I915_READ(_FDI_RXA_CTL
);
1428 val
&= ~FDI_RX_PLL_ENABLE
;
1429 I915_WRITE(_FDI_RXA_CTL
, val
);
1432 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1434 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1435 int type
= intel_encoder
->type
;
1437 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1438 intel_dp_check_link_status(intel_dp
);
1441 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1443 /* HDMI has nothing special to destroy, so we can go with this. */
1444 intel_dp_encoder_destroy(encoder
);
1447 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1448 struct intel_crtc_config
*pipe_config
)
1450 int type
= encoder
->type
;
1452 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1454 if (type
== INTEL_OUTPUT_HDMI
)
1455 return intel_hdmi_compute_config(encoder
, pipe_config
);
1457 return intel_dp_compute_config(encoder
, pipe_config
);
1460 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1461 .destroy
= intel_ddi_destroy
,
1464 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs
= {
1465 .mode_set
= intel_ddi_mode_set
,
1468 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1471 struct intel_digital_port
*intel_dig_port
;
1472 struct intel_encoder
*intel_encoder
;
1473 struct drm_encoder
*encoder
;
1474 struct intel_connector
*hdmi_connector
= NULL
;
1475 struct intel_connector
*dp_connector
= NULL
;
1477 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1478 if (!intel_dig_port
)
1481 dp_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1482 if (!dp_connector
) {
1483 kfree(intel_dig_port
);
1487 if (port
!= PORT_A
) {
1488 hdmi_connector
= kzalloc(sizeof(struct intel_connector
),
1490 if (!hdmi_connector
) {
1491 kfree(dp_connector
);
1492 kfree(intel_dig_port
);
1497 intel_encoder
= &intel_dig_port
->base
;
1498 encoder
= &intel_encoder
->base
;
1500 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1501 DRM_MODE_ENCODER_TMDS
);
1502 drm_encoder_helper_add(encoder
, &intel_ddi_helper_funcs
);
1504 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1505 intel_encoder
->enable
= intel_enable_ddi
;
1506 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1507 intel_encoder
->disable
= intel_disable_ddi
;
1508 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1509 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1511 intel_dig_port
->port
= port
;
1512 intel_dig_port
->port_reversal
= I915_READ(DDI_BUF_CTL(port
)) &
1513 DDI_BUF_PORT_REVERSAL
;
1515 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1516 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1518 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1519 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1520 intel_encoder
->cloneable
= false;
1521 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1524 intel_hdmi_init_connector(intel_dig_port
, hdmi_connector
);
1525 intel_dp_init_connector(intel_dig_port
, dp_connector
);