2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
40 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
80 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
92 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
130 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000087 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000087 },
142 /* eDP 1.4 low vswing translation parameters */
143 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
157 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
158 /* Idx NT mV T mV db */
159 { 0x00004014, 0x00000087 }, /* 0: 800 1000 2 */
162 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
164 struct drm_encoder
*encoder
= &intel_encoder
->base
;
165 int type
= intel_encoder
->type
;
167 if (type
== INTEL_OUTPUT_DP_MST
) {
168 struct intel_digital_port
*intel_dig_port
= enc_to_mst(encoder
)->primary
;
169 return intel_dig_port
->port
;
170 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
171 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
172 struct intel_digital_port
*intel_dig_port
=
173 enc_to_dig_port(encoder
);
174 return intel_dig_port
->port
;
176 } else if (type
== INTEL_OUTPUT_ANALOG
) {
180 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
186 * Starting with Haswell, DDI port buffers must be programmed with correct
187 * values in advance. The buffer values are different for FDI and DP modes,
188 * but the HDMI/DVI fields are shared among those. So we program the DDI
189 * in either FDI or DP modes only, as HDMI connections will work with both
192 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
198 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
199 const struct ddi_buf_trans
*ddi_translations_fdi
;
200 const struct ddi_buf_trans
*ddi_translations_dp
;
201 const struct ddi_buf_trans
*ddi_translations_edp
;
202 const struct ddi_buf_trans
*ddi_translations_hdmi
;
203 const struct ddi_buf_trans
*ddi_translations
;
205 if (IS_SKYLAKE(dev
)) {
206 ddi_translations_fdi
= NULL
;
207 ddi_translations_dp
= skl_ddi_translations_dp
;
208 n_dp_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
209 if (dev_priv
->vbt
.edp_low_vswing
) {
210 ddi_translations_edp
= skl_ddi_translations_edp
;
211 n_edp_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
213 ddi_translations_edp
= skl_ddi_translations_dp
;
214 n_edp_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
218 * On SKL, the recommendation from the hw team is to always use
219 * a certain type of level shifter (and thus the corresponding
220 * 800mV+2dB entry). Given that's the only validated entry, we
221 * override what is in the VBT, at least until further notice.
224 ddi_translations_hdmi
= skl_ddi_translations_hdmi
;
225 n_hdmi_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
226 hdmi_default_entry
= 0;
227 } else if (IS_BROADWELL(dev
)) {
228 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
229 ddi_translations_dp
= bdw_ddi_translations_dp
;
230 ddi_translations_edp
= bdw_ddi_translations_edp
;
231 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
232 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
233 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
234 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
235 hdmi_default_entry
= 7;
236 } else if (IS_HASWELL(dev
)) {
237 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
238 ddi_translations_dp
= hsw_ddi_translations_dp
;
239 ddi_translations_edp
= hsw_ddi_translations_dp
;
240 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
241 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
242 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
243 hdmi_default_entry
= 6;
245 WARN(1, "ddi translation table missing\n");
246 ddi_translations_edp
= bdw_ddi_translations_dp
;
247 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
248 ddi_translations_dp
= bdw_ddi_translations_dp
;
249 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
250 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
251 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
252 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
253 hdmi_default_entry
= 7;
258 ddi_translations
= ddi_translations_edp
;
259 size
= n_edp_entries
;
263 ddi_translations
= ddi_translations_dp
;
267 if (intel_dp_is_edp(dev
, PORT_D
)) {
268 ddi_translations
= ddi_translations_edp
;
269 size
= n_edp_entries
;
271 ddi_translations
= ddi_translations_dp
;
276 if (ddi_translations_fdi
)
277 ddi_translations
= ddi_translations_fdi
;
279 ddi_translations
= ddi_translations_dp
;
286 for (i
= 0, reg
= DDI_BUF_TRANS(port
); i
< size
; i
++) {
287 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
289 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
293 /* Choose a good default if VBT is badly populated */
294 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
295 hdmi_level
>= n_hdmi_entries
)
296 hdmi_level
= hdmi_default_entry
;
298 /* Entry 9 is for HDMI: */
299 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
301 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
305 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
306 * mode and port E for FDI.
308 void intel_prepare_ddi(struct drm_device
*dev
)
315 for (port
= PORT_A
; port
<= PORT_E
; port
++)
316 intel_prepare_ddi_buffers(dev
, port
);
319 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
322 uint32_t reg
= DDI_BUF_CTL(port
);
325 for (i
= 0; i
< 8; i
++) {
327 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
330 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
333 /* Starting with Haswell, different DDI ports can work in FDI mode for
334 * connection to the PCH-located connectors. For this, it is necessary to train
335 * both the DDI port and PCH receiver for the desired DDI buffer settings.
337 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
338 * please note that when FDI mode is active on DDI E, it shares 2 lines with
339 * DDI A (which is used for eDP)
342 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
344 struct drm_device
*dev
= crtc
->dev
;
345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
346 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
347 u32 temp
, i
, rx_ctl_val
;
349 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
350 * mode set "sequence for CRT port" document:
351 * - TP1 to TP2 time with the default value
354 * WaFDIAutoLinkSetTimingOverrride:hsw
356 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
357 FDI_RX_PWRDN_LANE0_VAL(2) |
358 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
360 /* Enable the PCH Receiver FDI PLL */
361 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
363 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
364 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
365 POSTING_READ(_FDI_RXA_CTL
);
368 /* Switch from Rawclk to PCDclk */
369 rx_ctl_val
|= FDI_PCDCLK
;
370 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
372 /* Configure Port Clock Select */
373 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
374 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
376 /* Start the training iterating through available voltages and emphasis,
377 * testing each value twice. */
378 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
379 /* Configure DP_TP_CTL with auto-training */
380 I915_WRITE(DP_TP_CTL(PORT_E
),
381 DP_TP_CTL_FDI_AUTOTRAIN
|
382 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
383 DP_TP_CTL_LINK_TRAIN_PAT1
|
386 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
387 * DDI E does not support port reversal, the functionality is
388 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
389 * port reversal bit */
390 I915_WRITE(DDI_BUF_CTL(PORT_E
),
392 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
393 DDI_BUF_TRANS_SELECT(i
/ 2));
394 POSTING_READ(DDI_BUF_CTL(PORT_E
));
398 /* Program PCH FDI Receiver TU */
399 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
401 /* Enable PCH FDI Receiver with auto-training */
402 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
403 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
404 POSTING_READ(_FDI_RXA_CTL
);
406 /* Wait for FDI receiver lane calibration */
409 /* Unset FDI_RX_MISC pwrdn lanes */
410 temp
= I915_READ(_FDI_RXA_MISC
);
411 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
412 I915_WRITE(_FDI_RXA_MISC
, temp
);
413 POSTING_READ(_FDI_RXA_MISC
);
415 /* Wait for FDI auto training time */
418 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
419 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
420 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
422 /* Enable normal pixel sending for FDI */
423 I915_WRITE(DP_TP_CTL(PORT_E
),
424 DP_TP_CTL_FDI_AUTOTRAIN
|
425 DP_TP_CTL_LINK_TRAIN_NORMAL
|
426 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
432 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
433 temp
&= ~DDI_BUF_CTL_ENABLE
;
434 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
435 POSTING_READ(DDI_BUF_CTL(PORT_E
));
437 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
438 temp
= I915_READ(DP_TP_CTL(PORT_E
));
439 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
440 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
441 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
442 POSTING_READ(DP_TP_CTL(PORT_E
));
444 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
446 rx_ctl_val
&= ~FDI_RX_ENABLE
;
447 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
448 POSTING_READ(_FDI_RXA_CTL
);
450 /* Reset FDI_RX_MISC pwrdn lanes */
451 temp
= I915_READ(_FDI_RXA_MISC
);
452 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
453 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
454 I915_WRITE(_FDI_RXA_MISC
, temp
);
455 POSTING_READ(_FDI_RXA_MISC
);
458 DRM_ERROR("FDI link training failed!\n");
461 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
463 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
464 struct intel_digital_port
*intel_dig_port
=
465 enc_to_dig_port(&encoder
->base
);
467 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
468 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
469 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
473 static struct intel_encoder
*
474 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
476 struct drm_device
*dev
= crtc
->dev
;
477 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
478 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
479 int num_encoders
= 0;
481 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
486 if (num_encoders
!= 1)
487 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
488 pipe_name(intel_crtc
->pipe
));
494 static struct intel_encoder
*
495 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
497 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
498 struct intel_encoder
*ret
= NULL
;
499 struct drm_atomic_state
*state
;
500 int num_encoders
= 0;
503 state
= crtc_state
->base
.state
;
505 for (i
= 0; i
< state
->num_connector
; i
++) {
506 if (!state
->connectors
[i
] ||
507 state
->connector_states
[i
]->crtc
!= crtc_state
->base
.crtc
)
510 ret
= to_intel_encoder(state
->connector_states
[i
]->best_encoder
);
514 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
515 pipe_name(crtc
->pipe
));
522 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
528 /* Constraints for PLL good behavior */
534 #define abs_diff(a, b) ({ \
535 typeof(a) __a = (a); \
536 typeof(b) __b = (b); \
537 (void) (&__a == &__b); \
538 __a > __b ? (__a - __b) : (__b - __a); })
544 static unsigned wrpll_get_budget_for_freq(int clock
)
618 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
619 unsigned r2
, unsigned n2
, unsigned p
,
620 struct wrpll_rnp
*best
)
622 uint64_t a
, b
, c
, d
, diff
, diff_best
;
624 /* No best (r,n,p) yet */
633 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
637 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
640 * and we would like delta <= budget.
642 * If the discrepancy is above the PPM-based budget, always prefer to
643 * improve upon the previous solution. However, if you're within the
644 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
646 a
= freq2k
* budget
* p
* r2
;
647 b
= freq2k
* budget
* best
->p
* best
->r2
;
648 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
649 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
650 LC_FREQ_2K
* best
->n2
);
652 d
= 1000000 * diff_best
;
654 if (a
< c
&& b
< d
) {
655 /* If both are above the budget, pick the closer */
656 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
661 } else if (a
>= c
&& b
< d
) {
662 /* If A is below the threshold but B is above it? Update. */
666 } else if (a
>= c
&& b
>= d
) {
667 /* Both are below the limit, so pick the higher n2/(r2*r2) */
668 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
674 /* Otherwise a < c && b >= d, do nothing */
677 static int intel_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
680 int refclk
= LC_FREQ
;
684 wrpll
= I915_READ(reg
);
685 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
687 case WRPLL_PLL_NON_SSC
:
689 * We could calculate spread here, but our checking
690 * code only cares about 5% accuracy, and spread is a max of
695 case WRPLL_PLL_LCPLL
:
699 WARN(1, "bad wrpll refclk\n");
703 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
704 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
705 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
707 /* Convert to KHz, p & r have a fixed point portion */
708 return (refclk
* n
* 100) / (p
* r
);
711 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
714 uint32_t cfgcr1_reg
, cfgcr2_reg
;
715 uint32_t cfgcr1_val
, cfgcr2_val
;
716 uint32_t p0
, p1
, p2
, dco_freq
;
718 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
719 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
721 cfgcr1_val
= I915_READ(cfgcr1_reg
);
722 cfgcr2_val
= I915_READ(cfgcr2_reg
);
724 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
725 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
727 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
728 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
734 case DPLL_CFGCR2_PDIV_1
:
737 case DPLL_CFGCR2_PDIV_2
:
740 case DPLL_CFGCR2_PDIV_3
:
743 case DPLL_CFGCR2_PDIV_7
:
749 case DPLL_CFGCR2_KDIV_5
:
752 case DPLL_CFGCR2_KDIV_2
:
755 case DPLL_CFGCR2_KDIV_3
:
758 case DPLL_CFGCR2_KDIV_1
:
763 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
765 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
768 return dco_freq
/ (p0
* p1
* p2
* 5);
772 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
773 struct intel_crtc_state
*pipe_config
)
775 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
777 uint32_t dpll_ctl1
, dpll
;
779 dpll
= pipe_config
->ddi_pll_sel
;
781 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
783 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
784 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
786 link_clock
= dpll_ctl1
& DPLL_CRTL1_LINK_RATE_MASK(dpll
);
787 link_clock
>>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll
);
789 switch (link_clock
) {
790 case DPLL_CRTL1_LINK_RATE_810
:
793 case DPLL_CRTL1_LINK_RATE_1080
:
796 case DPLL_CRTL1_LINK_RATE_1350
:
799 case DPLL_CRTL1_LINK_RATE_1620
:
802 case DPLL_CRTL1_LINK_RATE_2160
:
805 case DPLL_CRTL1_LINK_RATE_2700
:
809 WARN(1, "Unsupported link rate\n");
815 pipe_config
->port_clock
= link_clock
;
817 if (pipe_config
->has_dp_encoder
)
818 pipe_config
->base
.adjusted_mode
.crtc_clock
=
819 intel_dotclock_calculate(pipe_config
->port_clock
,
820 &pipe_config
->dp_m_n
);
822 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
825 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
826 struct intel_crtc_state
*pipe_config
)
828 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
832 val
= pipe_config
->ddi_pll_sel
;
833 switch (val
& PORT_CLK_SEL_MASK
) {
834 case PORT_CLK_SEL_LCPLL_810
:
837 case PORT_CLK_SEL_LCPLL_1350
:
840 case PORT_CLK_SEL_LCPLL_2700
:
843 case PORT_CLK_SEL_WRPLL1
:
844 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
846 case PORT_CLK_SEL_WRPLL2
:
847 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
849 case PORT_CLK_SEL_SPLL
:
850 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
851 if (pll
== SPLL_PLL_FREQ_810MHz
)
853 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
855 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
858 WARN(1, "bad spll freq\n");
863 WARN(1, "bad port clock sel\n");
867 pipe_config
->port_clock
= link_clock
* 2;
869 if (pipe_config
->has_pch_encoder
)
870 pipe_config
->base
.adjusted_mode
.crtc_clock
=
871 intel_dotclock_calculate(pipe_config
->port_clock
,
872 &pipe_config
->fdi_m_n
);
873 else if (pipe_config
->has_dp_encoder
)
874 pipe_config
->base
.adjusted_mode
.crtc_clock
=
875 intel_dotclock_calculate(pipe_config
->port_clock
,
876 &pipe_config
->dp_m_n
);
878 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
881 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
882 struct intel_crtc_state
*pipe_config
)
884 struct drm_device
*dev
= encoder
->base
.dev
;
886 if (INTEL_INFO(dev
)->gen
<= 8)
887 hsw_ddi_clock_get(encoder
, pipe_config
);
889 skl_ddi_clock_get(encoder
, pipe_config
);
893 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
894 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
898 struct wrpll_rnp best
= { 0, 0, 0 };
901 freq2k
= clock
/ 100;
903 budget
= wrpll_get_budget_for_freq(clock
);
905 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
906 * and directly pass the LC PLL to it. */
907 if (freq2k
== 5400000) {
915 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
918 * We want R so that REF_MIN <= Ref <= REF_MAX.
919 * Injecting R2 = 2 * R gives:
920 * REF_MAX * r2 > LC_FREQ * 2 and
921 * REF_MIN * r2 < LC_FREQ * 2
923 * Which means the desired boundaries for r2 are:
924 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
927 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
928 r2
<= LC_FREQ
* 2 / REF_MIN
;
932 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
934 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
935 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
936 * VCO_MAX * r2 > n2 * LC_FREQ and
937 * VCO_MIN * r2 < n2 * LC_FREQ)
939 * Which means the desired boundaries for n2 are:
940 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
942 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
943 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
946 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
947 wrpll_update_rnp(freq2k
, budget
,
958 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
959 struct intel_crtc_state
*crtc_state
,
960 struct intel_encoder
*intel_encoder
,
963 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
964 struct intel_shared_dpll
*pll
;
968 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
970 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
971 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
972 WRPLL_DIVIDER_POST(p
);
974 crtc_state
->dpll_hw_state
.wrpll
= val
;
976 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
978 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
979 pipe_name(intel_crtc
->pipe
));
983 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
989 struct skl_wrpll_params
{
990 uint32_t dco_fraction
;
991 uint32_t dco_integer
;
996 uint32_t central_freq
;
1000 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1001 struct skl_wrpll_params
*wrpll_params
)
1003 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1004 uint64_t dco_central_freq
[3] = {8400000000ULL,
1007 uint32_t min_dco_deviation
= 400;
1008 uint32_t min_dco_index
= 3;
1009 uint32_t P0
[4] = {1, 2, 3, 7};
1010 uint32_t P2
[4] = {1, 2, 3, 5};
1012 uint32_t candidate_p
= 0;
1013 uint32_t candidate_p0
[3] = {0}, candidate_p1
[3] = {0};
1014 uint32_t candidate_p2
[3] = {0};
1015 uint32_t dco_central_freq_deviation
[3];
1016 uint32_t i
, P1
, k
, dco_count
;
1017 bool retry_with_odd
= false;
1020 /* Determine P0, P1 or P2 */
1021 for (dco_count
= 0; dco_count
< 3; dco_count
++) {
1024 div64_u64(dco_central_freq
[dco_count
], afe_clock
);
1025 if (retry_with_odd
== false)
1026 candidate_p
= (candidate_p
% 2 == 0 ?
1027 candidate_p
: candidate_p
+ 1);
1029 for (P1
= 1; P1
< candidate_p
; P1
++) {
1030 for (i
= 0; i
< 4; i
++) {
1031 if (!(P0
[i
] != 1 || P1
== 1))
1034 for (k
= 0; k
< 4; k
++) {
1035 if (P1
!= 1 && P2
[k
] != 2)
1038 if (candidate_p
== P0
[i
] * P1
* P2
[k
]) {
1039 /* Found possible P0, P1, P2 */
1041 candidate_p0
[dco_count
] = P0
[i
];
1042 candidate_p1
[dco_count
] = P1
;
1043 candidate_p2
[dco_count
] = P2
[k
];
1053 dco_central_freq_deviation
[dco_count
] =
1055 abs_diff((candidate_p
* afe_clock
),
1056 dco_central_freq
[dco_count
]),
1057 dco_central_freq
[dco_count
]);
1059 if (dco_central_freq_deviation
[dco_count
] <
1060 min_dco_deviation
) {
1062 dco_central_freq_deviation
[dco_count
];
1063 min_dco_index
= dco_count
;
1067 if (min_dco_index
> 2 && dco_count
== 2) {
1068 retry_with_odd
= true;
1073 if (min_dco_index
> 2) {
1074 WARN(1, "No valid values found for the given pixel clock\n");
1076 wrpll_params
->central_freq
= dco_central_freq
[min_dco_index
];
1078 switch (dco_central_freq
[min_dco_index
]) {
1080 wrpll_params
->central_freq
= 0;
1083 wrpll_params
->central_freq
= 1;
1086 wrpll_params
->central_freq
= 3;
1089 switch (candidate_p0
[min_dco_index
]) {
1091 wrpll_params
->pdiv
= 0;
1094 wrpll_params
->pdiv
= 1;
1097 wrpll_params
->pdiv
= 2;
1100 wrpll_params
->pdiv
= 4;
1103 WARN(1, "Incorrect PDiv\n");
1106 switch (candidate_p2
[min_dco_index
]) {
1108 wrpll_params
->kdiv
= 0;
1111 wrpll_params
->kdiv
= 1;
1114 wrpll_params
->kdiv
= 2;
1117 wrpll_params
->kdiv
= 3;
1120 WARN(1, "Incorrect KDiv\n");
1123 wrpll_params
->qdiv_ratio
= candidate_p1
[min_dco_index
];
1124 wrpll_params
->qdiv_mode
=
1125 (wrpll_params
->qdiv_ratio
== 1) ? 0 : 1;
1127 dco_freq
= candidate_p0
[min_dco_index
] *
1128 candidate_p1
[min_dco_index
] *
1129 candidate_p2
[min_dco_index
] * afe_clock
;
1132 * Intermediate values are in Hz.
1133 * Divide by MHz to match bsepc
1135 wrpll_params
->dco_integer
= div_u64(dco_freq
, (24 * MHz(1)));
1136 wrpll_params
->dco_fraction
=
1137 div_u64(((div_u64(dco_freq
, 24) -
1138 wrpll_params
->dco_integer
* MHz(1)) * 0x8000), MHz(1));
1145 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1146 struct intel_crtc_state
*crtc_state
,
1147 struct intel_encoder
*intel_encoder
,
1150 struct intel_shared_dpll
*pll
;
1151 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1154 * See comment in intel_dpll_hw_state to understand why we always use 0
1155 * as the DPLL id in this function.
1158 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1160 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1161 struct skl_wrpll_params wrpll_params
= { 0, };
1163 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1165 skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
);
1167 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1168 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1169 wrpll_params
.dco_integer
;
1171 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1172 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1173 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1174 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1175 wrpll_params
.central_freq
;
1176 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1177 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1178 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1180 switch (intel_dp
->link_bw
) {
1181 case DP_LINK_BW_1_62
:
1182 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
, 0);
1184 case DP_LINK_BW_2_7
:
1185 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
, 0);
1187 case DP_LINK_BW_5_4
:
1188 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
, 0);
1192 cfgcr1
= cfgcr2
= 0;
1196 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1197 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1198 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1200 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1202 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1203 pipe_name(intel_crtc
->pipe
));
1207 /* shared DPLL id 0 is DPLL 1 */
1208 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1214 * Tries to find a *shared* PLL for the CRTC and store it in
1215 * intel_crtc->ddi_pll_sel.
1217 * For private DPLLs, compute_config() should do the selection for us. This
1218 * function should be folded into compute_config() eventually.
1220 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1221 struct intel_crtc_state
*crtc_state
)
1223 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1224 struct intel_encoder
*intel_encoder
=
1225 intel_ddi_get_crtc_new_encoder(crtc_state
);
1226 int clock
= crtc_state
->port_clock
;
1228 if (IS_SKYLAKE(dev
))
1229 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1230 intel_encoder
, clock
);
1232 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1233 intel_encoder
, clock
);
1236 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1238 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1239 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1240 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1241 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1242 int type
= intel_encoder
->type
;
1245 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1246 temp
= TRANS_MSA_SYNC_CLK
;
1247 switch (intel_crtc
->config
->pipe_bpp
) {
1249 temp
|= TRANS_MSA_6_BPC
;
1252 temp
|= TRANS_MSA_8_BPC
;
1255 temp
|= TRANS_MSA_10_BPC
;
1258 temp
|= TRANS_MSA_12_BPC
;
1263 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1267 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1269 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1270 struct drm_device
*dev
= crtc
->dev
;
1271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1272 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1274 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1276 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1278 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1279 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1282 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1285 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1286 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1287 struct drm_device
*dev
= crtc
->dev
;
1288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1289 enum pipe pipe
= intel_crtc
->pipe
;
1290 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1291 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1292 int type
= intel_encoder
->type
;
1295 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1296 temp
= TRANS_DDI_FUNC_ENABLE
;
1297 temp
|= TRANS_DDI_SELECT_PORT(port
);
1299 switch (intel_crtc
->config
->pipe_bpp
) {
1301 temp
|= TRANS_DDI_BPC_6
;
1304 temp
|= TRANS_DDI_BPC_8
;
1307 temp
|= TRANS_DDI_BPC_10
;
1310 temp
|= TRANS_DDI_BPC_12
;
1316 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1317 temp
|= TRANS_DDI_PVSYNC
;
1318 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1319 temp
|= TRANS_DDI_PHSYNC
;
1321 if (cpu_transcoder
== TRANSCODER_EDP
) {
1324 /* On Haswell, can only use the always-on power well for
1325 * eDP when not using the panel fitter, and when not
1326 * using motion blur mitigation (which we don't
1328 if (IS_HASWELL(dev
) &&
1329 (intel_crtc
->config
->pch_pfit
.enabled
||
1330 intel_crtc
->config
->pch_pfit
.force_thru
))
1331 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1333 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1336 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1339 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1347 if (type
== INTEL_OUTPUT_HDMI
) {
1348 if (intel_crtc
->config
->has_hdmi_sink
)
1349 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1351 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1353 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1354 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1355 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1357 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1358 type
== INTEL_OUTPUT_EDP
) {
1359 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1361 if (intel_dp
->is_mst
) {
1362 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1364 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1366 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1367 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1368 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1370 if (intel_dp
->is_mst
) {
1371 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1373 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1375 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1377 WARN(1, "Invalid encoder type %d for pipe %c\n",
1378 intel_encoder
->type
, pipe_name(pipe
));
1381 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1384 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1385 enum transcoder cpu_transcoder
)
1387 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1388 uint32_t val
= I915_READ(reg
);
1390 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1391 val
|= TRANS_DDI_PORT_NONE
;
1392 I915_WRITE(reg
, val
);
1395 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1397 struct drm_device
*dev
= intel_connector
->base
.dev
;
1398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1399 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1400 int type
= intel_connector
->base
.connector_type
;
1401 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1403 enum transcoder cpu_transcoder
;
1404 enum intel_display_power_domain power_domain
;
1407 power_domain
= intel_display_port_power_domain(intel_encoder
);
1408 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1411 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1415 cpu_transcoder
= TRANSCODER_EDP
;
1417 cpu_transcoder
= (enum transcoder
) pipe
;
1419 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1421 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1422 case TRANS_DDI_MODE_SELECT_HDMI
:
1423 case TRANS_DDI_MODE_SELECT_DVI
:
1424 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1426 case TRANS_DDI_MODE_SELECT_DP_SST
:
1427 if (type
== DRM_MODE_CONNECTOR_eDP
)
1429 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1430 case TRANS_DDI_MODE_SELECT_DP_MST
:
1431 /* if the transcoder is in MST state then
1432 * connector isn't connected */
1435 case TRANS_DDI_MODE_SELECT_FDI
:
1436 return (type
== DRM_MODE_CONNECTOR_VGA
);
1443 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1446 struct drm_device
*dev
= encoder
->base
.dev
;
1447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1448 enum port port
= intel_ddi_get_encoder_port(encoder
);
1449 enum intel_display_power_domain power_domain
;
1453 power_domain
= intel_display_port_power_domain(encoder
);
1454 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1457 tmp
= I915_READ(DDI_BUF_CTL(port
));
1459 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1462 if (port
== PORT_A
) {
1463 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1465 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1466 case TRANS_DDI_EDP_INPUT_A_ON
:
1467 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1470 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1473 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1480 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1481 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1483 if ((tmp
& TRANS_DDI_PORT_MASK
)
1484 == TRANS_DDI_SELECT_PORT(port
)) {
1485 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
1494 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1499 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1501 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1502 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1503 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1504 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1505 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1507 if (cpu_transcoder
!= TRANSCODER_EDP
)
1508 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1509 TRANS_CLK_SEL_PORT(port
));
1512 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1514 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1515 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1517 if (cpu_transcoder
!= TRANSCODER_EDP
)
1518 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1519 TRANS_CLK_SEL_DISABLED
);
1522 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1524 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1525 struct drm_device
*dev
= encoder
->dev
;
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1528 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1529 int type
= intel_encoder
->type
;
1531 if (type
== INTEL_OUTPUT_EDP
) {
1532 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1533 intel_edp_panel_on(intel_dp
);
1536 if (IS_SKYLAKE(dev
)) {
1537 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
1541 * DPLL0 is used for eDP and is the only "private" DPLL (as
1542 * opposed to shared) on SKL
1544 if (type
== INTEL_OUTPUT_EDP
) {
1545 WARN_ON(dpll
!= SKL_DPLL0
);
1547 val
= I915_READ(DPLL_CTRL1
);
1549 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
1550 DPLL_CTRL1_SSC(dpll
) |
1551 DPLL_CRTL1_LINK_RATE_MASK(dpll
));
1552 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
1554 I915_WRITE(DPLL_CTRL1
, val
);
1555 POSTING_READ(DPLL_CTRL1
);
1558 /* DDI -> PLL mapping */
1559 val
= I915_READ(DPLL_CTRL2
);
1561 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
1562 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
1563 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
1564 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
1566 I915_WRITE(DPLL_CTRL2
, val
);
1569 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1570 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
1573 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1574 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1576 intel_ddi_init_dp_buf_reg(intel_encoder
);
1578 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1579 intel_dp_start_link_train(intel_dp
);
1580 intel_dp_complete_link_train(intel_dp
);
1581 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
1582 intel_dp_stop_link_train(intel_dp
);
1583 } else if (type
== INTEL_OUTPUT_HDMI
) {
1584 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1586 intel_hdmi
->set_infoframes(encoder
,
1587 crtc
->config
->has_hdmi_sink
,
1588 &crtc
->config
->base
.adjusted_mode
);
1592 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1594 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1595 struct drm_device
*dev
= encoder
->dev
;
1596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1597 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1598 int type
= intel_encoder
->type
;
1602 val
= I915_READ(DDI_BUF_CTL(port
));
1603 if (val
& DDI_BUF_CTL_ENABLE
) {
1604 val
&= ~DDI_BUF_CTL_ENABLE
;
1605 I915_WRITE(DDI_BUF_CTL(port
), val
);
1609 val
= I915_READ(DP_TP_CTL(port
));
1610 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1611 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1612 I915_WRITE(DP_TP_CTL(port
), val
);
1615 intel_wait_ddi_buf_idle(dev_priv
, port
);
1617 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1618 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1619 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1620 intel_edp_panel_vdd_on(intel_dp
);
1621 intel_edp_panel_off(intel_dp
);
1624 if (IS_SKYLAKE(dev
))
1625 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
1626 DPLL_CTRL2_DDI_CLK_OFF(port
)));
1628 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1631 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1633 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1634 struct drm_crtc
*crtc
= encoder
->crtc
;
1635 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1636 struct drm_device
*dev
= encoder
->dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1639 int type
= intel_encoder
->type
;
1641 if (type
== INTEL_OUTPUT_HDMI
) {
1642 struct intel_digital_port
*intel_dig_port
=
1643 enc_to_dig_port(encoder
);
1645 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1646 * are ignored so nothing special needs to be done besides
1647 * enabling the port.
1649 I915_WRITE(DDI_BUF_CTL(port
),
1650 intel_dig_port
->saved_port_bits
|
1651 DDI_BUF_CTL_ENABLE
);
1652 } else if (type
== INTEL_OUTPUT_EDP
) {
1653 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1655 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
1656 intel_dp_stop_link_train(intel_dp
);
1658 intel_edp_backlight_on(intel_dp
);
1659 intel_psr_enable(intel_dp
);
1660 intel_edp_drrs_enable(intel_dp
);
1663 if (intel_crtc
->config
->has_audio
) {
1664 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1665 intel_audio_codec_enable(intel_encoder
);
1669 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1671 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1672 struct drm_crtc
*crtc
= encoder
->crtc
;
1673 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1674 int type
= intel_encoder
->type
;
1675 struct drm_device
*dev
= encoder
->dev
;
1676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1678 if (intel_crtc
->config
->has_audio
) {
1679 intel_audio_codec_disable(intel_encoder
);
1680 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1683 if (type
== INTEL_OUTPUT_EDP
) {
1684 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1686 intel_edp_drrs_disable(intel_dp
);
1687 intel_psr_disable(intel_dp
);
1688 intel_edp_backlight_off(intel_dp
);
1692 static int skl_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1694 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
1695 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
1698 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
1699 WARN(1, "LCPLL1 not enabled\n");
1700 return 24000; /* 24MHz is the cd freq with NSSC ref */
1703 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
1706 linkrate
= (I915_READ(DPLL_CTRL1
) &
1707 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
1709 if (linkrate
== DPLL_CRTL1_LINK_RATE_2160
||
1710 linkrate
== DPLL_CRTL1_LINK_RATE_1080
) {
1712 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
1713 case CDCLK_FREQ_450_432
:
1715 case CDCLK_FREQ_337_308
:
1717 case CDCLK_FREQ_675_617
:
1720 WARN(1, "Unknown cd freq selection\n");
1724 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
1725 case CDCLK_FREQ_450_432
:
1727 case CDCLK_FREQ_337_308
:
1729 case CDCLK_FREQ_675_617
:
1732 WARN(1, "Unknown cd freq selection\n");
1736 /* error case, do as if DPLL0 isn't enabled */
1740 static int bdw_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1742 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1743 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1745 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
1747 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1749 else if (freq
== LCPLL_CLK_FREQ_450
)
1751 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
1753 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
1759 static int hsw_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1761 struct drm_device
*dev
= dev_priv
->dev
;
1762 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1763 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1765 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
1767 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1769 else if (freq
== LCPLL_CLK_FREQ_450
)
1771 else if (IS_HSW_ULT(dev
))
1777 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1779 struct drm_device
*dev
= dev_priv
->dev
;
1781 if (IS_SKYLAKE(dev
))
1782 return skl_get_cdclk_freq(dev_priv
);
1784 if (IS_BROADWELL(dev
))
1785 return bdw_get_cdclk_freq(dev_priv
);
1788 return hsw_get_cdclk_freq(dev_priv
);
1791 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1792 struct intel_shared_dpll
*pll
)
1794 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
1795 POSTING_READ(WRPLL_CTL(pll
->id
));
1799 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1800 struct intel_shared_dpll
*pll
)
1804 val
= I915_READ(WRPLL_CTL(pll
->id
));
1805 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
1806 POSTING_READ(WRPLL_CTL(pll
->id
));
1809 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1810 struct intel_shared_dpll
*pll
,
1811 struct intel_dpll_hw_state
*hw_state
)
1815 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1818 val
= I915_READ(WRPLL_CTL(pll
->id
));
1819 hw_state
->wrpll
= val
;
1821 return val
& WRPLL_PLL_ENABLE
;
1824 static const char * const hsw_ddi_pll_names
[] = {
1829 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1833 dev_priv
->num_shared_dpll
= 2;
1835 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1836 dev_priv
->shared_dplls
[i
].id
= i
;
1837 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
1838 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
1839 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
1840 dev_priv
->shared_dplls
[i
].get_hw_state
=
1841 hsw_ddi_pll_get_hw_state
;
1845 static const char * const skl_ddi_pll_names
[] = {
1851 struct skl_dpll_regs
{
1852 u32 ctl
, cfgcr1
, cfgcr2
;
1855 /* this array is indexed by the *shared* pll id */
1856 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
1860 .cfgcr1
= DPLL1_CFGCR1
,
1861 .cfgcr2
= DPLL1_CFGCR2
,
1866 .cfgcr1
= DPLL2_CFGCR1
,
1867 .cfgcr2
= DPLL2_CFGCR2
,
1872 .cfgcr1
= DPLL3_CFGCR1
,
1873 .cfgcr2
= DPLL3_CFGCR2
,
1877 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1878 struct intel_shared_dpll
*pll
)
1882 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1884 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1887 val
= I915_READ(DPLL_CTRL1
);
1889 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
1890 DPLL_CRTL1_LINK_RATE_MASK(dpll
));
1891 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
1893 I915_WRITE(DPLL_CTRL1
, val
);
1894 POSTING_READ(DPLL_CTRL1
);
1896 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
1897 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
1898 POSTING_READ(regs
[pll
->id
].cfgcr1
);
1899 POSTING_READ(regs
[pll
->id
].cfgcr2
);
1901 /* the enable bit is always bit 31 */
1902 I915_WRITE(regs
[pll
->id
].ctl
,
1903 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
1905 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
1906 DRM_ERROR("DPLL %d not locked\n", dpll
);
1909 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1910 struct intel_shared_dpll
*pll
)
1912 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1914 /* the enable bit is always bit 31 */
1915 I915_WRITE(regs
[pll
->id
].ctl
,
1916 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
1917 POSTING_READ(regs
[pll
->id
].ctl
);
1920 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1921 struct intel_shared_dpll
*pll
,
1922 struct intel_dpll_hw_state
*hw_state
)
1926 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1928 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1931 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1934 val
= I915_READ(regs
[pll
->id
].ctl
);
1935 if (!(val
& LCPLL_PLL_ENABLE
))
1938 val
= I915_READ(DPLL_CTRL1
);
1939 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
1941 /* avoid reading back stale values if HDMI mode is not enabled */
1942 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1943 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
1944 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
1950 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1954 dev_priv
->num_shared_dpll
= 3;
1956 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1957 dev_priv
->shared_dplls
[i
].id
= i
;
1958 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
1959 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
1960 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
1961 dev_priv
->shared_dplls
[i
].get_hw_state
=
1962 skl_ddi_pll_get_hw_state
;
1966 void intel_ddi_pll_init(struct drm_device
*dev
)
1968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1969 uint32_t val
= I915_READ(LCPLL_CTL
);
1971 if (IS_SKYLAKE(dev
))
1972 skl_shared_dplls_init(dev_priv
);
1974 hsw_shared_dplls_init(dev_priv
);
1976 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1977 intel_ddi_get_cdclk_freq(dev_priv
));
1979 if (IS_SKYLAKE(dev
)) {
1980 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
1981 DRM_ERROR("LCPLL1 is disabled\n");
1984 * The LCPLL register should be turned on by the BIOS. For now
1985 * let's just check its state and print errors in case
1986 * something is wrong. Don't even try to turn it on.
1989 if (val
& LCPLL_CD_SOURCE_FCLK
)
1990 DRM_ERROR("CDCLK source is not LCPLL\n");
1992 if (val
& LCPLL_PLL_DISABLE
)
1993 DRM_ERROR("LCPLL is disabled\n");
1997 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1999 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2000 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2001 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
2002 enum port port
= intel_dig_port
->port
;
2006 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2007 val
= I915_READ(DDI_BUF_CTL(port
));
2008 if (val
& DDI_BUF_CTL_ENABLE
) {
2009 val
&= ~DDI_BUF_CTL_ENABLE
;
2010 I915_WRITE(DDI_BUF_CTL(port
), val
);
2014 val
= I915_READ(DP_TP_CTL(port
));
2015 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2016 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2017 I915_WRITE(DP_TP_CTL(port
), val
);
2018 POSTING_READ(DP_TP_CTL(port
));
2021 intel_wait_ddi_buf_idle(dev_priv
, port
);
2024 val
= DP_TP_CTL_ENABLE
|
2025 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2026 if (intel_dp
->is_mst
)
2027 val
|= DP_TP_CTL_MODE_MST
;
2029 val
|= DP_TP_CTL_MODE_SST
;
2030 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2031 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2033 I915_WRITE(DP_TP_CTL(port
), val
);
2034 POSTING_READ(DP_TP_CTL(port
));
2036 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2037 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
2038 POSTING_READ(DDI_BUF_CTL(port
));
2043 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
2045 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2046 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2049 intel_ddi_post_disable(intel_encoder
);
2051 val
= I915_READ(_FDI_RXA_CTL
);
2052 val
&= ~FDI_RX_ENABLE
;
2053 I915_WRITE(_FDI_RXA_CTL
, val
);
2055 val
= I915_READ(_FDI_RXA_MISC
);
2056 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
2057 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2058 I915_WRITE(_FDI_RXA_MISC
, val
);
2060 val
= I915_READ(_FDI_RXA_CTL
);
2062 I915_WRITE(_FDI_RXA_CTL
, val
);
2064 val
= I915_READ(_FDI_RXA_CTL
);
2065 val
&= ~FDI_RX_PLL_ENABLE
;
2066 I915_WRITE(_FDI_RXA_CTL
, val
);
2069 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
2071 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
2072 int type
= intel_dig_port
->base
.type
;
2074 if (type
!= INTEL_OUTPUT_DISPLAYPORT
&&
2075 type
!= INTEL_OUTPUT_EDP
&&
2076 type
!= INTEL_OUTPUT_UNKNOWN
) {
2080 intel_dp_hot_plug(intel_encoder
);
2083 void intel_ddi_get_config(struct intel_encoder
*encoder
,
2084 struct intel_crtc_state
*pipe_config
)
2086 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
2087 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2088 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2089 struct intel_hdmi
*intel_hdmi
;
2090 u32 temp
, flags
= 0;
2092 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
2093 if (temp
& TRANS_DDI_PHSYNC
)
2094 flags
|= DRM_MODE_FLAG_PHSYNC
;
2096 flags
|= DRM_MODE_FLAG_NHSYNC
;
2097 if (temp
& TRANS_DDI_PVSYNC
)
2098 flags
|= DRM_MODE_FLAG_PVSYNC
;
2100 flags
|= DRM_MODE_FLAG_NVSYNC
;
2102 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2104 switch (temp
& TRANS_DDI_BPC_MASK
) {
2105 case TRANS_DDI_BPC_6
:
2106 pipe_config
->pipe_bpp
= 18;
2108 case TRANS_DDI_BPC_8
:
2109 pipe_config
->pipe_bpp
= 24;
2111 case TRANS_DDI_BPC_10
:
2112 pipe_config
->pipe_bpp
= 30;
2114 case TRANS_DDI_BPC_12
:
2115 pipe_config
->pipe_bpp
= 36;
2121 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
2122 case TRANS_DDI_MODE_SELECT_HDMI
:
2123 pipe_config
->has_hdmi_sink
= true;
2124 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2126 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
2127 pipe_config
->has_infoframe
= true;
2129 case TRANS_DDI_MODE_SELECT_DVI
:
2130 case TRANS_DDI_MODE_SELECT_FDI
:
2132 case TRANS_DDI_MODE_SELECT_DP_SST
:
2133 case TRANS_DDI_MODE_SELECT_DP_MST
:
2134 pipe_config
->has_dp_encoder
= true;
2135 intel_dp_get_m_n(intel_crtc
, pipe_config
);
2141 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
2142 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
2143 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
2144 pipe_config
->has_audio
= true;
2147 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
2148 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2150 * This is a big fat ugly hack.
2152 * Some machines in UEFI boot mode provide us a VBT that has 18
2153 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2154 * unknown we fail to light up. Yet the same BIOS boots up with
2155 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2156 * max, not what it tells us to use.
2158 * Note: This will still be broken if the eDP panel is not lit
2159 * up by the BIOS, and thus we can't get the mode at module
2162 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2163 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2164 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2167 intel_ddi_clock_get(encoder
, pipe_config
);
2170 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
2172 /* HDMI has nothing special to destroy, so we can go with this. */
2173 intel_dp_encoder_destroy(encoder
);
2176 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
2177 struct intel_crtc_state
*pipe_config
)
2179 int type
= encoder
->type
;
2180 int port
= intel_ddi_get_encoder_port(encoder
);
2182 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
2185 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
2187 if (type
== INTEL_OUTPUT_HDMI
)
2188 return intel_hdmi_compute_config(encoder
, pipe_config
);
2190 return intel_dp_compute_config(encoder
, pipe_config
);
2193 static const struct drm_encoder_funcs intel_ddi_funcs
= {
2194 .destroy
= intel_ddi_destroy
,
2197 static struct intel_connector
*
2198 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
2200 struct intel_connector
*connector
;
2201 enum port port
= intel_dig_port
->port
;
2203 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
2207 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
2208 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
2216 static struct intel_connector
*
2217 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
2219 struct intel_connector
*connector
;
2220 enum port port
= intel_dig_port
->port
;
2222 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
2226 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
2227 intel_hdmi_init_connector(intel_dig_port
, connector
);
2232 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
2234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 struct intel_digital_port
*intel_dig_port
;
2236 struct intel_encoder
*intel_encoder
;
2237 struct drm_encoder
*encoder
;
2238 bool init_hdmi
, init_dp
;
2240 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
2241 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
2242 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
2243 if (!init_dp
&& !init_hdmi
) {
2244 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2250 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2251 if (!intel_dig_port
)
2254 intel_encoder
= &intel_dig_port
->base
;
2255 encoder
= &intel_encoder
->base
;
2257 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
2258 DRM_MODE_ENCODER_TMDS
);
2260 intel_encoder
->compute_config
= intel_ddi_compute_config
;
2261 intel_encoder
->enable
= intel_enable_ddi
;
2262 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2263 intel_encoder
->disable
= intel_disable_ddi
;
2264 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2265 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2266 intel_encoder
->get_config
= intel_ddi_get_config
;
2268 intel_dig_port
->port
= port
;
2269 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
2270 (DDI_BUF_PORT_REVERSAL
|
2273 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
2274 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2275 intel_encoder
->cloneable
= 0;
2276 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
2279 if (!intel_ddi_init_dp_connector(intel_dig_port
))
2282 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
2283 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
2286 /* In theory we don't need the encoder->type check, but leave it just in
2287 * case we have some really bad VBTs... */
2288 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
2289 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
2296 drm_encoder_cleanup(encoder
);
2297 kfree(intel_dig_port
);