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6d5b09f2a8a6d82ef83f4b7ae4abd0d567e85f9c
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
51 };
52
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
63 };
64
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
79 };
80
81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
91 };
92
93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
103 };
104
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
115 };
116
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
129 };
130
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 },
142 };
143
144 /* Skylake U */
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x80007011, 0x000000CD, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake Y */
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x0 },
162 { 0x80009010, 0x000000C0, 0x3 },
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 },
168 };
169
170 /*
171 * Skylake H and S
172 * eDP 1.4 low vswing translation parameters
173 */
174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185 };
186
187 /*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
202 };
203
204 /*
205 * Skylake Y
206 * eDP 1.4 low vswing translation parameters
207 */
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219 };
220
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x80006012, 0x000000CD, 0x1 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
234 };
235
236 /* Skylake Y */
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x80007011, 0x000000CB, 0x3 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x80006013, 0x000000C0, 0x3 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
249 };
250
251 struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257 };
258
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
271 };
272
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285 };
286
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302 };
303
304 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
306
307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
310 {
311 struct drm_encoder *encoder = &intel_encoder->base;
312
313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
324 break;
325 case INTEL_OUTPUT_ANALOG:
326 *dig_port = NULL;
327 *port = PORT_E;
328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
332 }
333 }
334
335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336 {
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343 }
344
345 static const struct ddi_buf_trans *
346 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
347 {
348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
350 return skl_y_ddi_translations_dp;
351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
353 return skl_u_ddi_translations_dp;
354 } else {
355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
356 return skl_ddi_translations_dp;
357 }
358 }
359
360 static const struct ddi_buf_trans *
361 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
362 {
363 if (dev_priv->edp_low_vswing) {
364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
366 return skl_y_ddi_translations_edp;
367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
369 return skl_u_ddi_translations_edp;
370 } else {
371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
372 return skl_ddi_translations_edp;
373 }
374 }
375
376 return skl_get_buf_trans_dp(dev_priv, n_entries);
377 }
378
379 static const struct ddi_buf_trans *
380 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
381 {
382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
384 return skl_y_ddi_translations_hdmi;
385 } else {
386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
387 return skl_ddi_translations_hdmi;
388 }
389 }
390
391 /*
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
396 * of those
397 */
398 void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
399 {
400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
401 u32 iboost_bit = 0;
402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
403 size;
404 int hdmi_level;
405 enum port port;
406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
411
412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
414
415 if (IS_BROXTON(dev_priv)) {
416 if (encoder->type != INTEL_OUTPUT_HDMI)
417 return;
418
419 /* Vswing programming for HDMI */
420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
421 INTEL_OUTPUT_HDMI);
422 return;
423 }
424
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
426 ddi_translations_fdi = NULL;
427 ddi_translations_dp =
428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
429 ddi_translations_edp =
430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
431 ddi_translations_hdmi =
432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
433 hdmi_default_entry = 8;
434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
438
439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
441 n_edp_entries > 9))
442 n_edp_entries = 9;
443 } else if (IS_BROADWELL(dev_priv)) {
444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
446 ddi_translations_edp = bdw_ddi_translations_edp;
447 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
448 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
449 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
450 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
451 hdmi_default_entry = 7;
452 } else if (IS_HASWELL(dev_priv)) {
453 ddi_translations_fdi = hsw_ddi_translations_fdi;
454 ddi_translations_dp = hsw_ddi_translations_dp;
455 ddi_translations_edp = hsw_ddi_translations_dp;
456 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
458 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
459 hdmi_default_entry = 6;
460 } else {
461 WARN(1, "ddi translation table missing\n");
462 ddi_translations_edp = bdw_ddi_translations_dp;
463 ddi_translations_fdi = bdw_ddi_translations_fdi;
464 ddi_translations_dp = bdw_ddi_translations_dp;
465 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
466 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
467 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
468 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
469 hdmi_default_entry = 7;
470 }
471
472 switch (encoder->type) {
473 case INTEL_OUTPUT_EDP:
474 ddi_translations = ddi_translations_edp;
475 size = n_edp_entries;
476 break;
477 case INTEL_OUTPUT_DISPLAYPORT:
478 case INTEL_OUTPUT_HDMI:
479 ddi_translations = ddi_translations_dp;
480 size = n_dp_entries;
481 break;
482 case INTEL_OUTPUT_ANALOG:
483 ddi_translations = ddi_translations_fdi;
484 size = n_dp_entries;
485 break;
486 default:
487 BUG();
488 }
489
490 for (i = 0; i < size; i++) {
491 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
492 ddi_translations[i].trans1 | iboost_bit);
493 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
494 ddi_translations[i].trans2);
495 }
496
497 if (encoder->type != INTEL_OUTPUT_HDMI)
498 return;
499
500 /* Choose a good default if VBT is badly populated */
501 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
502 hdmi_level >= n_hdmi_entries)
503 hdmi_level = hdmi_default_entry;
504
505 /* Entry 9 is for HDMI: */
506 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
507 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
508 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
509 ddi_translations_hdmi[hdmi_level].trans2);
510 }
511
512 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
513 enum port port)
514 {
515 i915_reg_t reg = DDI_BUF_CTL(port);
516 int i;
517
518 for (i = 0; i < 16; i++) {
519 udelay(1);
520 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
521 return;
522 }
523 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
524 }
525
526 /* Starting with Haswell, different DDI ports can work in FDI mode for
527 * connection to the PCH-located connectors. For this, it is necessary to train
528 * both the DDI port and PCH receiver for the desired DDI buffer settings.
529 *
530 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
531 * please note that when FDI mode is active on DDI E, it shares 2 lines with
532 * DDI A (which is used for eDP)
533 */
534
535 void hsw_fdi_link_train(struct drm_crtc *crtc)
536 {
537 struct drm_device *dev = crtc->dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
540 struct intel_encoder *encoder;
541 u32 temp, i, rx_ctl_val;
542
543 for_each_encoder_on_crtc(dev, crtc, encoder) {
544 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
545 intel_prepare_ddi_buffer(encoder);
546 }
547
548 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
549 * mode set "sequence for CRT port" document:
550 * - TP1 to TP2 time with the default value
551 * - FDI delay to 90h
552 *
553 * WaFDIAutoLinkSetTimingOverrride:hsw
554 */
555 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
556 FDI_RX_PWRDN_LANE0_VAL(2) |
557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
558
559 /* Enable the PCH Receiver FDI PLL */
560 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
561 FDI_RX_PLL_ENABLE |
562 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
563 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
564 POSTING_READ(FDI_RX_CTL(PIPE_A));
565 udelay(220);
566
567 /* Switch from Rawclk to PCDclk */
568 rx_ctl_val |= FDI_PCDCLK;
569 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
570
571 /* Configure Port Clock Select */
572 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
573 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
574
575 /* Start the training iterating through available voltages and emphasis,
576 * testing each value twice. */
577 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
578 /* Configure DP_TP_CTL with auto-training */
579 I915_WRITE(DP_TP_CTL(PORT_E),
580 DP_TP_CTL_FDI_AUTOTRAIN |
581 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
582 DP_TP_CTL_LINK_TRAIN_PAT1 |
583 DP_TP_CTL_ENABLE);
584
585 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
586 * DDI E does not support port reversal, the functionality is
587 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
588 * port reversal bit */
589 I915_WRITE(DDI_BUF_CTL(PORT_E),
590 DDI_BUF_CTL_ENABLE |
591 ((intel_crtc->config->fdi_lanes - 1) << 1) |
592 DDI_BUF_TRANS_SELECT(i / 2));
593 POSTING_READ(DDI_BUF_CTL(PORT_E));
594
595 udelay(600);
596
597 /* Program PCH FDI Receiver TU */
598 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
599
600 /* Enable PCH FDI Receiver with auto-training */
601 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603 POSTING_READ(FDI_RX_CTL(PIPE_A));
604
605 /* Wait for FDI receiver lane calibration */
606 udelay(30);
607
608 /* Unset FDI_RX_MISC pwrdn lanes */
609 temp = I915_READ(FDI_RX_MISC(PIPE_A));
610 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
611 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
612 POSTING_READ(FDI_RX_MISC(PIPE_A));
613
614 /* Wait for FDI auto training time */
615 udelay(5);
616
617 temp = I915_READ(DP_TP_STATUS(PORT_E));
618 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
619 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
620 break;
621 }
622
623 /*
624 * Leave things enabled even if we failed to train FDI.
625 * Results in less fireworks from the state checker.
626 */
627 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
628 DRM_ERROR("FDI link training failed!\n");
629 break;
630 }
631
632 temp = I915_READ(DDI_BUF_CTL(PORT_E));
633 temp &= ~DDI_BUF_CTL_ENABLE;
634 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
635 POSTING_READ(DDI_BUF_CTL(PORT_E));
636
637 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
638 temp = I915_READ(DP_TP_CTL(PORT_E));
639 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
640 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
641 I915_WRITE(DP_TP_CTL(PORT_E), temp);
642 POSTING_READ(DP_TP_CTL(PORT_E));
643
644 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
645
646 rx_ctl_val &= ~FDI_RX_ENABLE;
647 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
648 POSTING_READ(FDI_RX_CTL(PIPE_A));
649
650 /* Reset FDI_RX_MISC pwrdn lanes */
651 temp = I915_READ(FDI_RX_MISC(PIPE_A));
652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
653 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
654 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
655 POSTING_READ(FDI_RX_MISC(PIPE_A));
656 }
657
658 /* Enable normal pixel sending for FDI */
659 I915_WRITE(DP_TP_CTL(PORT_E),
660 DP_TP_CTL_FDI_AUTOTRAIN |
661 DP_TP_CTL_LINK_TRAIN_NORMAL |
662 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
663 DP_TP_CTL_ENABLE);
664 }
665
666 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
667 {
668 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
669 struct intel_digital_port *intel_dig_port =
670 enc_to_dig_port(&encoder->base);
671
672 intel_dp->DP = intel_dig_port->saved_port_bits |
673 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
674 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
675 }
676
677 static struct intel_encoder *
678 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
679 {
680 struct drm_device *dev = crtc->dev;
681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
682 struct intel_encoder *intel_encoder, *ret = NULL;
683 int num_encoders = 0;
684
685 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
686 ret = intel_encoder;
687 num_encoders++;
688 }
689
690 if (num_encoders != 1)
691 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
692 pipe_name(intel_crtc->pipe));
693
694 BUG_ON(ret == NULL);
695 return ret;
696 }
697
698 struct intel_encoder *
699 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
700 {
701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
702 struct intel_encoder *ret = NULL;
703 struct drm_atomic_state *state;
704 struct drm_connector *connector;
705 struct drm_connector_state *connector_state;
706 int num_encoders = 0;
707 int i;
708
709 state = crtc_state->base.state;
710
711 for_each_connector_in_state(state, connector, connector_state, i) {
712 if (connector_state->crtc != crtc_state->base.crtc)
713 continue;
714
715 ret = to_intel_encoder(connector_state->best_encoder);
716 num_encoders++;
717 }
718
719 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
720 pipe_name(crtc->pipe));
721
722 BUG_ON(ret == NULL);
723 return ret;
724 }
725
726 #define LC_FREQ 2700
727 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
728
729 #define P_MIN 2
730 #define P_MAX 64
731 #define P_INC 2
732
733 /* Constraints for PLL good behavior */
734 #define REF_MIN 48
735 #define REF_MAX 400
736 #define VCO_MIN 2400
737 #define VCO_MAX 4800
738
739 #define abs_diff(a, b) ({ \
740 typeof(a) __a = (a); \
741 typeof(b) __b = (b); \
742 (void) (&__a == &__b); \
743 __a > __b ? (__a - __b) : (__b - __a); })
744
745 struct hsw_wrpll_rnp {
746 unsigned p, n2, r2;
747 };
748
749 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
750 {
751 unsigned budget;
752
753 switch (clock) {
754 case 25175000:
755 case 25200000:
756 case 27000000:
757 case 27027000:
758 case 37762500:
759 case 37800000:
760 case 40500000:
761 case 40541000:
762 case 54000000:
763 case 54054000:
764 case 59341000:
765 case 59400000:
766 case 72000000:
767 case 74176000:
768 case 74250000:
769 case 81000000:
770 case 81081000:
771 case 89012000:
772 case 89100000:
773 case 108000000:
774 case 108108000:
775 case 111264000:
776 case 111375000:
777 case 148352000:
778 case 148500000:
779 case 162000000:
780 case 162162000:
781 case 222525000:
782 case 222750000:
783 case 296703000:
784 case 297000000:
785 budget = 0;
786 break;
787 case 233500000:
788 case 245250000:
789 case 247750000:
790 case 253250000:
791 case 298000000:
792 budget = 1500;
793 break;
794 case 169128000:
795 case 169500000:
796 case 179500000:
797 case 202000000:
798 budget = 2000;
799 break;
800 case 256250000:
801 case 262500000:
802 case 270000000:
803 case 272500000:
804 case 273750000:
805 case 280750000:
806 case 281250000:
807 case 286000000:
808 case 291750000:
809 budget = 4000;
810 break;
811 case 267250000:
812 case 268500000:
813 budget = 5000;
814 break;
815 default:
816 budget = 1000;
817 break;
818 }
819
820 return budget;
821 }
822
823 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
824 unsigned r2, unsigned n2, unsigned p,
825 struct hsw_wrpll_rnp *best)
826 {
827 uint64_t a, b, c, d, diff, diff_best;
828
829 /* No best (r,n,p) yet */
830 if (best->p == 0) {
831 best->p = p;
832 best->n2 = n2;
833 best->r2 = r2;
834 return;
835 }
836
837 /*
838 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
839 * freq2k.
840 *
841 * delta = 1e6 *
842 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
843 * freq2k;
844 *
845 * and we would like delta <= budget.
846 *
847 * If the discrepancy is above the PPM-based budget, always prefer to
848 * improve upon the previous solution. However, if you're within the
849 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
850 */
851 a = freq2k * budget * p * r2;
852 b = freq2k * budget * best->p * best->r2;
853 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
854 diff_best = abs_diff(freq2k * best->p * best->r2,
855 LC_FREQ_2K * best->n2);
856 c = 1000000 * diff;
857 d = 1000000 * diff_best;
858
859 if (a < c && b < d) {
860 /* If both are above the budget, pick the closer */
861 if (best->p * best->r2 * diff < p * r2 * diff_best) {
862 best->p = p;
863 best->n2 = n2;
864 best->r2 = r2;
865 }
866 } else if (a >= c && b < d) {
867 /* If A is below the threshold but B is above it? Update. */
868 best->p = p;
869 best->n2 = n2;
870 best->r2 = r2;
871 } else if (a >= c && b >= d) {
872 /* Both are below the limit, so pick the higher n2/(r2*r2) */
873 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
874 best->p = p;
875 best->n2 = n2;
876 best->r2 = r2;
877 }
878 }
879 /* Otherwise a < c && b >= d, do nothing */
880 }
881
882 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
883 i915_reg_t reg)
884 {
885 int refclk = LC_FREQ;
886 int n, p, r;
887 u32 wrpll;
888
889 wrpll = I915_READ(reg);
890 switch (wrpll & WRPLL_PLL_REF_MASK) {
891 case WRPLL_PLL_SSC:
892 case WRPLL_PLL_NON_SSC:
893 /*
894 * We could calculate spread here, but our checking
895 * code only cares about 5% accuracy, and spread is a max of
896 * 0.5% downspread.
897 */
898 refclk = 135;
899 break;
900 case WRPLL_PLL_LCPLL:
901 refclk = LC_FREQ;
902 break;
903 default:
904 WARN(1, "bad wrpll refclk\n");
905 return 0;
906 }
907
908 r = wrpll & WRPLL_DIVIDER_REF_MASK;
909 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
910 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
911
912 /* Convert to KHz, p & r have a fixed point portion */
913 return (refclk * n * 100) / (p * r);
914 }
915
916 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
917 uint32_t dpll)
918 {
919 i915_reg_t cfgcr1_reg, cfgcr2_reg;
920 uint32_t cfgcr1_val, cfgcr2_val;
921 uint32_t p0, p1, p2, dco_freq;
922
923 cfgcr1_reg = DPLL_CFGCR1(dpll);
924 cfgcr2_reg = DPLL_CFGCR2(dpll);
925
926 cfgcr1_val = I915_READ(cfgcr1_reg);
927 cfgcr2_val = I915_READ(cfgcr2_reg);
928
929 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
930 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
931
932 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
933 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
934 else
935 p1 = 1;
936
937
938 switch (p0) {
939 case DPLL_CFGCR2_PDIV_1:
940 p0 = 1;
941 break;
942 case DPLL_CFGCR2_PDIV_2:
943 p0 = 2;
944 break;
945 case DPLL_CFGCR2_PDIV_3:
946 p0 = 3;
947 break;
948 case DPLL_CFGCR2_PDIV_7:
949 p0 = 7;
950 break;
951 }
952
953 switch (p2) {
954 case DPLL_CFGCR2_KDIV_5:
955 p2 = 5;
956 break;
957 case DPLL_CFGCR2_KDIV_2:
958 p2 = 2;
959 break;
960 case DPLL_CFGCR2_KDIV_3:
961 p2 = 3;
962 break;
963 case DPLL_CFGCR2_KDIV_1:
964 p2 = 1;
965 break;
966 }
967
968 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
969
970 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
971 1000) / 0x8000;
972
973 return dco_freq / (p0 * p1 * p2 * 5);
974 }
975
976 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
977 {
978 int dotclock;
979
980 if (pipe_config->has_pch_encoder)
981 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
982 &pipe_config->fdi_m_n);
983 else if (pipe_config->has_dp_encoder)
984 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
985 &pipe_config->dp_m_n);
986 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
987 dotclock = pipe_config->port_clock * 2 / 3;
988 else
989 dotclock = pipe_config->port_clock;
990
991 if (pipe_config->pixel_multiplier)
992 dotclock /= pipe_config->pixel_multiplier;
993
994 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
995 }
996
997 static void skl_ddi_clock_get(struct intel_encoder *encoder,
998 struct intel_crtc_state *pipe_config)
999 {
1000 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1001 int link_clock = 0;
1002 uint32_t dpll_ctl1, dpll;
1003
1004 dpll = pipe_config->ddi_pll_sel;
1005
1006 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1007
1008 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1009 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1010 } else {
1011 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1012 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1013
1014 switch (link_clock) {
1015 case DPLL_CTRL1_LINK_RATE_810:
1016 link_clock = 81000;
1017 break;
1018 case DPLL_CTRL1_LINK_RATE_1080:
1019 link_clock = 108000;
1020 break;
1021 case DPLL_CTRL1_LINK_RATE_1350:
1022 link_clock = 135000;
1023 break;
1024 case DPLL_CTRL1_LINK_RATE_1620:
1025 link_clock = 162000;
1026 break;
1027 case DPLL_CTRL1_LINK_RATE_2160:
1028 link_clock = 216000;
1029 break;
1030 case DPLL_CTRL1_LINK_RATE_2700:
1031 link_clock = 270000;
1032 break;
1033 default:
1034 WARN(1, "Unsupported link rate\n");
1035 break;
1036 }
1037 link_clock *= 2;
1038 }
1039
1040 pipe_config->port_clock = link_clock;
1041
1042 ddi_dotclock_get(pipe_config);
1043 }
1044
1045 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1046 struct intel_crtc_state *pipe_config)
1047 {
1048 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1049 int link_clock = 0;
1050 u32 val, pll;
1051
1052 val = pipe_config->ddi_pll_sel;
1053 switch (val & PORT_CLK_SEL_MASK) {
1054 case PORT_CLK_SEL_LCPLL_810:
1055 link_clock = 81000;
1056 break;
1057 case PORT_CLK_SEL_LCPLL_1350:
1058 link_clock = 135000;
1059 break;
1060 case PORT_CLK_SEL_LCPLL_2700:
1061 link_clock = 270000;
1062 break;
1063 case PORT_CLK_SEL_WRPLL1:
1064 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1065 break;
1066 case PORT_CLK_SEL_WRPLL2:
1067 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1068 break;
1069 case PORT_CLK_SEL_SPLL:
1070 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1071 if (pll == SPLL_PLL_FREQ_810MHz)
1072 link_clock = 81000;
1073 else if (pll == SPLL_PLL_FREQ_1350MHz)
1074 link_clock = 135000;
1075 else if (pll == SPLL_PLL_FREQ_2700MHz)
1076 link_clock = 270000;
1077 else {
1078 WARN(1, "bad spll freq\n");
1079 return;
1080 }
1081 break;
1082 default:
1083 WARN(1, "bad port clock sel\n");
1084 return;
1085 }
1086
1087 pipe_config->port_clock = link_clock * 2;
1088
1089 ddi_dotclock_get(pipe_config);
1090 }
1091
1092 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1093 enum intel_dpll_id dpll)
1094 {
1095 struct intel_shared_dpll *pll;
1096 struct intel_dpll_hw_state *state;
1097 intel_clock_t clock;
1098
1099 /* For DDI ports we always use a shared PLL. */
1100 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1101 return 0;
1102
1103 pll = &dev_priv->shared_dplls[dpll];
1104 state = &pll->config.hw_state;
1105
1106 clock.m1 = 2;
1107 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1108 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1109 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1110 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1111 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1112 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1113
1114 return chv_calc_dpll_params(100000, &clock);
1115 }
1116
1117 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1118 struct intel_crtc_state *pipe_config)
1119 {
1120 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1121 enum port port = intel_ddi_get_encoder_port(encoder);
1122 uint32_t dpll = port;
1123
1124 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1125
1126 ddi_dotclock_get(pipe_config);
1127 }
1128
1129 void intel_ddi_clock_get(struct intel_encoder *encoder,
1130 struct intel_crtc_state *pipe_config)
1131 {
1132 struct drm_device *dev = encoder->base.dev;
1133
1134 if (INTEL_INFO(dev)->gen <= 8)
1135 hsw_ddi_clock_get(encoder, pipe_config);
1136 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1137 skl_ddi_clock_get(encoder, pipe_config);
1138 else if (IS_BROXTON(dev))
1139 bxt_ddi_clock_get(encoder, pipe_config);
1140 }
1141
1142 static void
1143 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1144 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1145 {
1146 uint64_t freq2k;
1147 unsigned p, n2, r2;
1148 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1149 unsigned budget;
1150
1151 freq2k = clock / 100;
1152
1153 budget = hsw_wrpll_get_budget_for_freq(clock);
1154
1155 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1156 * and directly pass the LC PLL to it. */
1157 if (freq2k == 5400000) {
1158 *n2_out = 2;
1159 *p_out = 1;
1160 *r2_out = 2;
1161 return;
1162 }
1163
1164 /*
1165 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1166 * the WR PLL.
1167 *
1168 * We want R so that REF_MIN <= Ref <= REF_MAX.
1169 * Injecting R2 = 2 * R gives:
1170 * REF_MAX * r2 > LC_FREQ * 2 and
1171 * REF_MIN * r2 < LC_FREQ * 2
1172 *
1173 * Which means the desired boundaries for r2 are:
1174 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1175 *
1176 */
1177 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1178 r2 <= LC_FREQ * 2 / REF_MIN;
1179 r2++) {
1180
1181 /*
1182 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1183 *
1184 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1185 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1186 * VCO_MAX * r2 > n2 * LC_FREQ and
1187 * VCO_MIN * r2 < n2 * LC_FREQ)
1188 *
1189 * Which means the desired boundaries for n2 are:
1190 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1191 */
1192 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1193 n2 <= VCO_MAX * r2 / LC_FREQ;
1194 n2++) {
1195
1196 for (p = P_MIN; p <= P_MAX; p += P_INC)
1197 hsw_wrpll_update_rnp(freq2k, budget,
1198 r2, n2, p, &best);
1199 }
1200 }
1201
1202 *n2_out = best.n2;
1203 *p_out = best.p;
1204 *r2_out = best.r2;
1205 }
1206
1207 static bool
1208 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1209 struct intel_crtc_state *crtc_state,
1210 struct intel_encoder *intel_encoder)
1211 {
1212 int clock = crtc_state->port_clock;
1213
1214 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1215 struct intel_shared_dpll *pll;
1216 uint32_t val;
1217 unsigned p, n2, r2;
1218
1219 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1220
1221 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1222 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1223 WRPLL_DIVIDER_POST(p);
1224
1225 memset(&crtc_state->dpll_hw_state, 0,
1226 sizeof(crtc_state->dpll_hw_state));
1227
1228 crtc_state->dpll_hw_state.wrpll = val;
1229
1230 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1231 if (pll == NULL) {
1232 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1233 pipe_name(intel_crtc->pipe));
1234 return false;
1235 }
1236
1237 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1238 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1239 struct drm_atomic_state *state = crtc_state->base.state;
1240 struct intel_shared_dpll_config *spll =
1241 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1242
1243 if (spll->crtc_mask &&
1244 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1245 return false;
1246
1247 crtc_state->shared_dpll = DPLL_ID_SPLL;
1248 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1249 spll->crtc_mask |= 1 << intel_crtc->pipe;
1250 }
1251
1252 return true;
1253 }
1254
1255 struct skl_wrpll_context {
1256 uint64_t min_deviation; /* current minimal deviation */
1257 uint64_t central_freq; /* chosen central freq */
1258 uint64_t dco_freq; /* chosen dco freq */
1259 unsigned int p; /* chosen divider */
1260 };
1261
1262 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1263 {
1264 memset(ctx, 0, sizeof(*ctx));
1265
1266 ctx->min_deviation = U64_MAX;
1267 }
1268
1269 /* DCO freq must be within +1%/-6% of the DCO central freq */
1270 #define SKL_DCO_MAX_PDEVIATION 100
1271 #define SKL_DCO_MAX_NDEVIATION 600
1272
1273 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1274 uint64_t central_freq,
1275 uint64_t dco_freq,
1276 unsigned int divider)
1277 {
1278 uint64_t deviation;
1279
1280 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1281 central_freq);
1282
1283 /* positive deviation */
1284 if (dco_freq >= central_freq) {
1285 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1286 deviation < ctx->min_deviation) {
1287 ctx->min_deviation = deviation;
1288 ctx->central_freq = central_freq;
1289 ctx->dco_freq = dco_freq;
1290 ctx->p = divider;
1291 }
1292 /* negative deviation */
1293 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1294 deviation < ctx->min_deviation) {
1295 ctx->min_deviation = deviation;
1296 ctx->central_freq = central_freq;
1297 ctx->dco_freq = dco_freq;
1298 ctx->p = divider;
1299 }
1300 }
1301
1302 static void skl_wrpll_get_multipliers(unsigned int p,
1303 unsigned int *p0 /* out */,
1304 unsigned int *p1 /* out */,
1305 unsigned int *p2 /* out */)
1306 {
1307 /* even dividers */
1308 if (p % 2 == 0) {
1309 unsigned int half = p / 2;
1310
1311 if (half == 1 || half == 2 || half == 3 || half == 5) {
1312 *p0 = 2;
1313 *p1 = 1;
1314 *p2 = half;
1315 } else if (half % 2 == 0) {
1316 *p0 = 2;
1317 *p1 = half / 2;
1318 *p2 = 2;
1319 } else if (half % 3 == 0) {
1320 *p0 = 3;
1321 *p1 = half / 3;
1322 *p2 = 2;
1323 } else if (half % 7 == 0) {
1324 *p0 = 7;
1325 *p1 = half / 7;
1326 *p2 = 2;
1327 }
1328 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1329 *p0 = 3;
1330 *p1 = 1;
1331 *p2 = p / 3;
1332 } else if (p == 5 || p == 7) {
1333 *p0 = p;
1334 *p1 = 1;
1335 *p2 = 1;
1336 } else if (p == 15) {
1337 *p0 = 3;
1338 *p1 = 1;
1339 *p2 = 5;
1340 } else if (p == 21) {
1341 *p0 = 7;
1342 *p1 = 1;
1343 *p2 = 3;
1344 } else if (p == 35) {
1345 *p0 = 7;
1346 *p1 = 1;
1347 *p2 = 5;
1348 }
1349 }
1350
1351 struct skl_wrpll_params {
1352 uint32_t dco_fraction;
1353 uint32_t dco_integer;
1354 uint32_t qdiv_ratio;
1355 uint32_t qdiv_mode;
1356 uint32_t kdiv;
1357 uint32_t pdiv;
1358 uint32_t central_freq;
1359 };
1360
1361 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1362 uint64_t afe_clock,
1363 uint64_t central_freq,
1364 uint32_t p0, uint32_t p1, uint32_t p2)
1365 {
1366 uint64_t dco_freq;
1367
1368 switch (central_freq) {
1369 case 9600000000ULL:
1370 params->central_freq = 0;
1371 break;
1372 case 9000000000ULL:
1373 params->central_freq = 1;
1374 break;
1375 case 8400000000ULL:
1376 params->central_freq = 3;
1377 }
1378
1379 switch (p0) {
1380 case 1:
1381 params->pdiv = 0;
1382 break;
1383 case 2:
1384 params->pdiv = 1;
1385 break;
1386 case 3:
1387 params->pdiv = 2;
1388 break;
1389 case 7:
1390 params->pdiv = 4;
1391 break;
1392 default:
1393 WARN(1, "Incorrect PDiv\n");
1394 }
1395
1396 switch (p2) {
1397 case 5:
1398 params->kdiv = 0;
1399 break;
1400 case 2:
1401 params->kdiv = 1;
1402 break;
1403 case 3:
1404 params->kdiv = 2;
1405 break;
1406 case 1:
1407 params->kdiv = 3;
1408 break;
1409 default:
1410 WARN(1, "Incorrect KDiv\n");
1411 }
1412
1413 params->qdiv_ratio = p1;
1414 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1415
1416 dco_freq = p0 * p1 * p2 * afe_clock;
1417
1418 /*
1419 * Intermediate values are in Hz.
1420 * Divide by MHz to match bsepc
1421 */
1422 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1423 params->dco_fraction =
1424 div_u64((div_u64(dco_freq, 24) -
1425 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1426 }
1427
1428 static bool
1429 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1430 struct skl_wrpll_params *wrpll_params)
1431 {
1432 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1433 uint64_t dco_central_freq[3] = {8400000000ULL,
1434 9000000000ULL,
1435 9600000000ULL};
1436 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1437 24, 28, 30, 32, 36, 40, 42, 44,
1438 48, 52, 54, 56, 60, 64, 66, 68,
1439 70, 72, 76, 78, 80, 84, 88, 90,
1440 92, 96, 98 };
1441 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1442 static const struct {
1443 const int *list;
1444 int n_dividers;
1445 } dividers[] = {
1446 { even_dividers, ARRAY_SIZE(even_dividers) },
1447 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1448 };
1449 struct skl_wrpll_context ctx;
1450 unsigned int dco, d, i;
1451 unsigned int p0, p1, p2;
1452
1453 skl_wrpll_context_init(&ctx);
1454
1455 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1456 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1457 for (i = 0; i < dividers[d].n_dividers; i++) {
1458 unsigned int p = dividers[d].list[i];
1459 uint64_t dco_freq = p * afe_clock;
1460
1461 skl_wrpll_try_divider(&ctx,
1462 dco_central_freq[dco],
1463 dco_freq,
1464 p);
1465 /*
1466 * Skip the remaining dividers if we're sure to
1467 * have found the definitive divider, we can't
1468 * improve a 0 deviation.
1469 */
1470 if (ctx.min_deviation == 0)
1471 goto skip_remaining_dividers;
1472 }
1473 }
1474
1475 skip_remaining_dividers:
1476 /*
1477 * If a solution is found with an even divider, prefer
1478 * this one.
1479 */
1480 if (d == 0 && ctx.p)
1481 break;
1482 }
1483
1484 if (!ctx.p) {
1485 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1486 return false;
1487 }
1488
1489 /*
1490 * gcc incorrectly analyses that these can be used without being
1491 * initialized. To be fair, it's hard to guess.
1492 */
1493 p0 = p1 = p2 = 0;
1494 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1495 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1496 p0, p1, p2);
1497
1498 return true;
1499 }
1500
1501 static bool
1502 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1503 struct intel_crtc_state *crtc_state,
1504 struct intel_encoder *intel_encoder)
1505 {
1506 struct intel_shared_dpll *pll;
1507 uint32_t ctrl1, cfgcr1, cfgcr2;
1508 int clock = crtc_state->port_clock;
1509
1510 /*
1511 * See comment in intel_dpll_hw_state to understand why we always use 0
1512 * as the DPLL id in this function.
1513 */
1514
1515 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1516
1517 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1518 struct skl_wrpll_params wrpll_params = { 0, };
1519
1520 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1521
1522 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1523 return false;
1524
1525 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1526 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1527 wrpll_params.dco_integer;
1528
1529 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1530 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1531 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1532 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1533 wrpll_params.central_freq;
1534 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1535 switch (crtc_state->port_clock / 2) {
1536 case 81000:
1537 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1538 break;
1539 case 135000:
1540 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1541 break;
1542 case 270000:
1543 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1544 break;
1545 }
1546
1547 cfgcr1 = cfgcr2 = 0;
1548 } else /* eDP */
1549 return true;
1550
1551 memset(&crtc_state->dpll_hw_state, 0,
1552 sizeof(crtc_state->dpll_hw_state));
1553
1554 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1555 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1556 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1557
1558 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1559 if (pll == NULL) {
1560 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1561 pipe_name(intel_crtc->pipe));
1562 return false;
1563 }
1564
1565 /* shared DPLL id 0 is DPLL 1 */
1566 crtc_state->ddi_pll_sel = pll->id + 1;
1567
1568 return true;
1569 }
1570
1571 /* bxt clock parameters */
1572 struct bxt_clk_div {
1573 int clock;
1574 uint32_t p1;
1575 uint32_t p2;
1576 uint32_t m2_int;
1577 uint32_t m2_frac;
1578 bool m2_frac_en;
1579 uint32_t n;
1580 };
1581
1582 /* pre-calculated values for DP linkrates */
1583 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1584 {162000, 4, 2, 32, 1677722, 1, 1},
1585 {270000, 4, 1, 27, 0, 0, 1},
1586 {540000, 2, 1, 27, 0, 0, 1},
1587 {216000, 3, 2, 32, 1677722, 1, 1},
1588 {243000, 4, 1, 24, 1258291, 1, 1},
1589 {324000, 4, 1, 32, 1677722, 1, 1},
1590 {432000, 3, 1, 32, 1677722, 1, 1}
1591 };
1592
1593 static bool
1594 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1595 struct intel_crtc_state *crtc_state,
1596 struct intel_encoder *intel_encoder)
1597 {
1598 struct intel_shared_dpll *pll;
1599 struct bxt_clk_div clk_div = {0};
1600 int vco = 0;
1601 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1602 uint32_t lanestagger;
1603 int clock = crtc_state->port_clock;
1604
1605 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1606 intel_clock_t best_clock;
1607
1608 /* Calculate HDMI div */
1609 /*
1610 * FIXME: tie the following calculation into
1611 * i9xx_crtc_compute_clock
1612 */
1613 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1614 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1615 clock, pipe_name(intel_crtc->pipe));
1616 return false;
1617 }
1618
1619 clk_div.p1 = best_clock.p1;
1620 clk_div.p2 = best_clock.p2;
1621 WARN_ON(best_clock.m1 != 2);
1622 clk_div.n = best_clock.n;
1623 clk_div.m2_int = best_clock.m2 >> 22;
1624 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1625 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1626
1627 vco = best_clock.vco;
1628 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1629 intel_encoder->type == INTEL_OUTPUT_EDP) {
1630 int i;
1631
1632 clk_div = bxt_dp_clk_val[0];
1633 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1634 if (bxt_dp_clk_val[i].clock == clock) {
1635 clk_div = bxt_dp_clk_val[i];
1636 break;
1637 }
1638 }
1639 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1640 }
1641
1642 if (vco >= 6200000 && vco <= 6700000) {
1643 prop_coef = 4;
1644 int_coef = 9;
1645 gain_ctl = 3;
1646 targ_cnt = 8;
1647 } else if ((vco > 5400000 && vco < 6200000) ||
1648 (vco >= 4800000 && vco < 5400000)) {
1649 prop_coef = 5;
1650 int_coef = 11;
1651 gain_ctl = 3;
1652 targ_cnt = 9;
1653 } else if (vco == 5400000) {
1654 prop_coef = 3;
1655 int_coef = 8;
1656 gain_ctl = 1;
1657 targ_cnt = 9;
1658 } else {
1659 DRM_ERROR("Invalid VCO\n");
1660 return false;
1661 }
1662
1663 memset(&crtc_state->dpll_hw_state, 0,
1664 sizeof(crtc_state->dpll_hw_state));
1665
1666 if (clock > 270000)
1667 lanestagger = 0x18;
1668 else if (clock > 135000)
1669 lanestagger = 0x0d;
1670 else if (clock > 67000)
1671 lanestagger = 0x07;
1672 else if (clock > 33000)
1673 lanestagger = 0x04;
1674 else
1675 lanestagger = 0x02;
1676
1677 crtc_state->dpll_hw_state.ebb0 =
1678 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1679 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1680 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1681 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1682
1683 if (clk_div.m2_frac_en)
1684 crtc_state->dpll_hw_state.pll3 =
1685 PORT_PLL_M2_FRAC_ENABLE;
1686
1687 crtc_state->dpll_hw_state.pll6 =
1688 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1689 crtc_state->dpll_hw_state.pll6 |=
1690 PORT_PLL_GAIN_CTL(gain_ctl);
1691
1692 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1693
1694 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1695
1696 crtc_state->dpll_hw_state.pll10 =
1697 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1698 | PORT_PLL_DCO_AMP_OVR_EN_H;
1699
1700 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1701
1702 crtc_state->dpll_hw_state.pcsdw12 =
1703 LANESTAGGER_STRAP_OVRD | lanestagger;
1704
1705 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1706 if (pll == NULL) {
1707 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1708 pipe_name(intel_crtc->pipe));
1709 return false;
1710 }
1711
1712 /* shared DPLL id 0 is DPLL A */
1713 crtc_state->ddi_pll_sel = pll->id;
1714
1715 return true;
1716 }
1717
1718 /*
1719 * Tries to find a *shared* PLL for the CRTC and store it in
1720 * intel_crtc->ddi_pll_sel.
1721 *
1722 * For private DPLLs, compute_config() should do the selection for us. This
1723 * function should be folded into compute_config() eventually.
1724 */
1725 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1726 struct intel_crtc_state *crtc_state)
1727 {
1728 struct drm_device *dev = intel_crtc->base.dev;
1729 struct intel_encoder *intel_encoder =
1730 intel_ddi_get_crtc_new_encoder(crtc_state);
1731
1732 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1733 return skl_ddi_pll_select(intel_crtc, crtc_state,
1734 intel_encoder);
1735 else if (IS_BROXTON(dev))
1736 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1737 intel_encoder);
1738 else
1739 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1740 intel_encoder);
1741 }
1742
1743 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1744 {
1745 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1747 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1748 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1749 int type = intel_encoder->type;
1750 uint32_t temp;
1751
1752 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1753 temp = TRANS_MSA_SYNC_CLK;
1754 switch (intel_crtc->config->pipe_bpp) {
1755 case 18:
1756 temp |= TRANS_MSA_6_BPC;
1757 break;
1758 case 24:
1759 temp |= TRANS_MSA_8_BPC;
1760 break;
1761 case 30:
1762 temp |= TRANS_MSA_10_BPC;
1763 break;
1764 case 36:
1765 temp |= TRANS_MSA_12_BPC;
1766 break;
1767 default:
1768 BUG();
1769 }
1770 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1771 }
1772 }
1773
1774 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1775 {
1776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1777 struct drm_device *dev = crtc->dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1780 uint32_t temp;
1781 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1782 if (state == true)
1783 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1784 else
1785 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1786 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1787 }
1788
1789 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1790 {
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1793 struct drm_encoder *encoder = &intel_encoder->base;
1794 struct drm_device *dev = crtc->dev;
1795 struct drm_i915_private *dev_priv = dev->dev_private;
1796 enum pipe pipe = intel_crtc->pipe;
1797 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1798 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1799 int type = intel_encoder->type;
1800 uint32_t temp;
1801
1802 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1803 temp = TRANS_DDI_FUNC_ENABLE;
1804 temp |= TRANS_DDI_SELECT_PORT(port);
1805
1806 switch (intel_crtc->config->pipe_bpp) {
1807 case 18:
1808 temp |= TRANS_DDI_BPC_6;
1809 break;
1810 case 24:
1811 temp |= TRANS_DDI_BPC_8;
1812 break;
1813 case 30:
1814 temp |= TRANS_DDI_BPC_10;
1815 break;
1816 case 36:
1817 temp |= TRANS_DDI_BPC_12;
1818 break;
1819 default:
1820 BUG();
1821 }
1822
1823 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1824 temp |= TRANS_DDI_PVSYNC;
1825 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1826 temp |= TRANS_DDI_PHSYNC;
1827
1828 if (cpu_transcoder == TRANSCODER_EDP) {
1829 switch (pipe) {
1830 case PIPE_A:
1831 /* On Haswell, can only use the always-on power well for
1832 * eDP when not using the panel fitter, and when not
1833 * using motion blur mitigation (which we don't
1834 * support). */
1835 if (IS_HASWELL(dev) &&
1836 (intel_crtc->config->pch_pfit.enabled ||
1837 intel_crtc->config->pch_pfit.force_thru))
1838 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1839 else
1840 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1841 break;
1842 case PIPE_B:
1843 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1844 break;
1845 case PIPE_C:
1846 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1847 break;
1848 default:
1849 BUG();
1850 break;
1851 }
1852 }
1853
1854 if (type == INTEL_OUTPUT_HDMI) {
1855 if (intel_crtc->config->has_hdmi_sink)
1856 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1857 else
1858 temp |= TRANS_DDI_MODE_SELECT_DVI;
1859
1860 } else if (type == INTEL_OUTPUT_ANALOG) {
1861 temp |= TRANS_DDI_MODE_SELECT_FDI;
1862 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1863
1864 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1865 type == INTEL_OUTPUT_EDP) {
1866 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1867
1868 if (intel_dp->is_mst) {
1869 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1870 } else
1871 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1872
1873 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1874 } else if (type == INTEL_OUTPUT_DP_MST) {
1875 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1876
1877 if (intel_dp->is_mst) {
1878 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1879 } else
1880 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1881
1882 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1883 } else {
1884 WARN(1, "Invalid encoder type %d for pipe %c\n",
1885 intel_encoder->type, pipe_name(pipe));
1886 }
1887
1888 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1889 }
1890
1891 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1892 enum transcoder cpu_transcoder)
1893 {
1894 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1895 uint32_t val = I915_READ(reg);
1896
1897 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1898 val |= TRANS_DDI_PORT_NONE;
1899 I915_WRITE(reg, val);
1900 }
1901
1902 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1903 {
1904 struct drm_device *dev = intel_connector->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_encoder *intel_encoder = intel_connector->encoder;
1907 int type = intel_connector->base.connector_type;
1908 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1909 enum pipe pipe = 0;
1910 enum transcoder cpu_transcoder;
1911 enum intel_display_power_domain power_domain;
1912 uint32_t tmp;
1913
1914 power_domain = intel_display_port_power_domain(intel_encoder);
1915 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1916 return false;
1917
1918 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1919 return false;
1920
1921 if (port == PORT_A)
1922 cpu_transcoder = TRANSCODER_EDP;
1923 else
1924 cpu_transcoder = (enum transcoder) pipe;
1925
1926 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1927
1928 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1929 case TRANS_DDI_MODE_SELECT_HDMI:
1930 case TRANS_DDI_MODE_SELECT_DVI:
1931 return (type == DRM_MODE_CONNECTOR_HDMIA);
1932
1933 case TRANS_DDI_MODE_SELECT_DP_SST:
1934 if (type == DRM_MODE_CONNECTOR_eDP)
1935 return true;
1936 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1937 case TRANS_DDI_MODE_SELECT_DP_MST:
1938 /* if the transcoder is in MST state then
1939 * connector isn't connected */
1940 return false;
1941
1942 case TRANS_DDI_MODE_SELECT_FDI:
1943 return (type == DRM_MODE_CONNECTOR_VGA);
1944
1945 default:
1946 return false;
1947 }
1948 }
1949
1950 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1951 enum pipe *pipe)
1952 {
1953 struct drm_device *dev = encoder->base.dev;
1954 struct drm_i915_private *dev_priv = dev->dev_private;
1955 enum port port = intel_ddi_get_encoder_port(encoder);
1956 enum intel_display_power_domain power_domain;
1957 u32 tmp;
1958 int i;
1959
1960 power_domain = intel_display_port_power_domain(encoder);
1961 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1962 return false;
1963
1964 tmp = I915_READ(DDI_BUF_CTL(port));
1965
1966 if (!(tmp & DDI_BUF_CTL_ENABLE))
1967 return false;
1968
1969 if (port == PORT_A) {
1970 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1971
1972 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1973 case TRANS_DDI_EDP_INPUT_A_ON:
1974 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1975 *pipe = PIPE_A;
1976 break;
1977 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1978 *pipe = PIPE_B;
1979 break;
1980 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1981 *pipe = PIPE_C;
1982 break;
1983 }
1984
1985 return true;
1986 } else {
1987 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1988 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1989
1990 if ((tmp & TRANS_DDI_PORT_MASK)
1991 == TRANS_DDI_SELECT_PORT(port)) {
1992 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1993 return false;
1994
1995 *pipe = i;
1996 return true;
1997 }
1998 }
1999 }
2000
2001 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2002
2003 return false;
2004 }
2005
2006 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2007 {
2008 struct drm_crtc *crtc = &intel_crtc->base;
2009 struct drm_device *dev = crtc->dev;
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2012 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2013 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2014
2015 if (cpu_transcoder != TRANSCODER_EDP)
2016 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2017 TRANS_CLK_SEL_PORT(port));
2018 }
2019
2020 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2021 {
2022 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2023 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2024
2025 if (cpu_transcoder != TRANSCODER_EDP)
2026 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2027 TRANS_CLK_SEL_DISABLED);
2028 }
2029
2030 static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2031 u32 level, enum port port, int type)
2032 {
2033 const struct ddi_buf_trans *ddi_translations;
2034 uint8_t iboost;
2035 uint8_t dp_iboost, hdmi_iboost;
2036 int n_entries;
2037 u32 reg;
2038
2039 /* VBT may override standard boost values */
2040 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2041 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2042
2043 if (type == INTEL_OUTPUT_DISPLAYPORT) {
2044 if (dp_iboost) {
2045 iboost = dp_iboost;
2046 } else {
2047 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
2048 iboost = ddi_translations[level].i_boost;
2049 }
2050 } else if (type == INTEL_OUTPUT_EDP) {
2051 if (dp_iboost) {
2052 iboost = dp_iboost;
2053 } else {
2054 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
2055
2056 if (WARN_ON(port != PORT_A &&
2057 port != PORT_E && n_entries > 9))
2058 n_entries = 9;
2059
2060 iboost = ddi_translations[level].i_boost;
2061 }
2062 } else if (type == INTEL_OUTPUT_HDMI) {
2063 if (hdmi_iboost) {
2064 iboost = hdmi_iboost;
2065 } else {
2066 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
2067 iboost = ddi_translations[level].i_boost;
2068 }
2069 } else {
2070 return;
2071 }
2072
2073 /* Make sure that the requested I_boost is valid */
2074 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2075 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2076 return;
2077 }
2078
2079 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2080 reg &= ~BALANCE_LEG_MASK(port);
2081 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2082
2083 if (iboost)
2084 reg |= iboost << BALANCE_LEG_SHIFT(port);
2085 else
2086 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2087
2088 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2089 }
2090
2091 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
2092 u32 level, enum port port, int type)
2093 {
2094 const struct bxt_ddi_buf_trans *ddi_translations;
2095 u32 n_entries, i;
2096 uint32_t val;
2097
2098 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2099 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2100 ddi_translations = bxt_ddi_translations_edp;
2101 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2102 || type == INTEL_OUTPUT_EDP) {
2103 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2104 ddi_translations = bxt_ddi_translations_dp;
2105 } else if (type == INTEL_OUTPUT_HDMI) {
2106 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2107 ddi_translations = bxt_ddi_translations_hdmi;
2108 } else {
2109 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2110 type);
2111 return;
2112 }
2113
2114 /* Check if default value has to be used */
2115 if (level >= n_entries ||
2116 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2117 for (i = 0; i < n_entries; i++) {
2118 if (ddi_translations[i].default_index) {
2119 level = i;
2120 break;
2121 }
2122 }
2123 }
2124
2125 /*
2126 * While we write to the group register to program all lanes at once we
2127 * can read only lane registers and we pick lanes 0/1 for that.
2128 */
2129 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2130 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2131 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2132
2133 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2134 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2135 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2136 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2137 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2138
2139 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2140 val &= ~SCALE_DCOMP_METHOD;
2141 if (ddi_translations[level].enable)
2142 val |= SCALE_DCOMP_METHOD;
2143
2144 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2145 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2146
2147 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2148
2149 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2150 val &= ~DE_EMPHASIS;
2151 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2152 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2153
2154 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2155 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2156 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2157 }
2158
2159 static uint32_t translate_signal_level(int signal_levels)
2160 {
2161 uint32_t level;
2162
2163 switch (signal_levels) {
2164 default:
2165 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2166 signal_levels);
2167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2168 level = 0;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2171 level = 1;
2172 break;
2173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2174 level = 2;
2175 break;
2176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2177 level = 3;
2178 break;
2179
2180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2181 level = 4;
2182 break;
2183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2184 level = 5;
2185 break;
2186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2187 level = 6;
2188 break;
2189
2190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2191 level = 7;
2192 break;
2193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2194 level = 8;
2195 break;
2196
2197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2198 level = 9;
2199 break;
2200 }
2201
2202 return level;
2203 }
2204
2205 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2206 {
2207 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2208 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2209 struct intel_encoder *encoder = &dport->base;
2210 uint8_t train_set = intel_dp->train_set[0];
2211 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2212 DP_TRAIN_PRE_EMPHASIS_MASK);
2213 enum port port = dport->port;
2214 uint32_t level;
2215
2216 level = translate_signal_level(signal_levels);
2217
2218 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2219 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
2220 else if (IS_BROXTON(dev_priv))
2221 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2222
2223 return DDI_BUF_TRANS_SELECT(level);
2224 }
2225
2226 void intel_ddi_clk_select(struct intel_encoder *encoder,
2227 const struct intel_crtc_state *pipe_config)
2228 {
2229 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2230 enum port port = intel_ddi_get_encoder_port(encoder);
2231
2232 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2233 uint32_t dpll = pipe_config->ddi_pll_sel;
2234 uint32_t val;
2235
2236 /*
2237 * DPLL0 is used for eDP and is the only "private" DPLL (as
2238 * opposed to shared) on SKL
2239 */
2240 if (encoder->type == INTEL_OUTPUT_EDP) {
2241 WARN_ON(dpll != SKL_DPLL0);
2242
2243 val = I915_READ(DPLL_CTRL1);
2244
2245 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2246 DPLL_CTRL1_SSC(dpll) |
2247 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2248 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
2249
2250 I915_WRITE(DPLL_CTRL1, val);
2251 POSTING_READ(DPLL_CTRL1);
2252 }
2253
2254 /* DDI -> PLL mapping */
2255 val = I915_READ(DPLL_CTRL2);
2256
2257 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2258 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2259 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2260 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2261
2262 I915_WRITE(DPLL_CTRL2, val);
2263
2264 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2265 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2266 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
2267 }
2268 }
2269
2270 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2271 {
2272 struct drm_encoder *encoder = &intel_encoder->base;
2273 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2274 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2275 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2276 int type = intel_encoder->type;
2277
2278 intel_prepare_ddi_buffer(intel_encoder);
2279
2280 if (type == INTEL_OUTPUT_EDP) {
2281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2282 intel_edp_panel_on(intel_dp);
2283 }
2284
2285 intel_ddi_clk_select(intel_encoder, crtc->config);
2286
2287 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2288 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2289
2290 intel_dp_set_link_params(intel_dp, crtc->config);
2291
2292 intel_ddi_init_dp_buf_reg(intel_encoder);
2293
2294 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2295 intel_dp_start_link_train(intel_dp);
2296 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
2297 intel_dp_stop_link_train(intel_dp);
2298 } else if (type == INTEL_OUTPUT_HDMI) {
2299 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2300
2301 intel_hdmi->set_infoframes(encoder,
2302 crtc->config->has_hdmi_sink,
2303 &crtc->config->base.adjusted_mode);
2304 }
2305 }
2306
2307 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2308 {
2309 struct drm_encoder *encoder = &intel_encoder->base;
2310 struct drm_device *dev = encoder->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2313 int type = intel_encoder->type;
2314 uint32_t val;
2315 bool wait = false;
2316
2317 val = I915_READ(DDI_BUF_CTL(port));
2318 if (val & DDI_BUF_CTL_ENABLE) {
2319 val &= ~DDI_BUF_CTL_ENABLE;
2320 I915_WRITE(DDI_BUF_CTL(port), val);
2321 wait = true;
2322 }
2323
2324 val = I915_READ(DP_TP_CTL(port));
2325 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2326 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2327 I915_WRITE(DP_TP_CTL(port), val);
2328
2329 if (wait)
2330 intel_wait_ddi_buf_idle(dev_priv, port);
2331
2332 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2333 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2334 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2335 intel_edp_panel_vdd_on(intel_dp);
2336 intel_edp_panel_off(intel_dp);
2337 }
2338
2339 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2340 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2341 DPLL_CTRL2_DDI_CLK_OFF(port)));
2342 else if (INTEL_INFO(dev)->gen < 9)
2343 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2344 }
2345
2346 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2347 {
2348 struct drm_encoder *encoder = &intel_encoder->base;
2349 struct drm_crtc *crtc = encoder->crtc;
2350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2351 struct drm_device *dev = encoder->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2354 int type = intel_encoder->type;
2355
2356 if (type == INTEL_OUTPUT_HDMI) {
2357 struct intel_digital_port *intel_dig_port =
2358 enc_to_dig_port(encoder);
2359
2360 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2361 * are ignored so nothing special needs to be done besides
2362 * enabling the port.
2363 */
2364 I915_WRITE(DDI_BUF_CTL(port),
2365 intel_dig_port->saved_port_bits |
2366 DDI_BUF_CTL_ENABLE);
2367 } else if (type == INTEL_OUTPUT_EDP) {
2368 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2369
2370 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2371 intel_dp_stop_link_train(intel_dp);
2372
2373 intel_edp_backlight_on(intel_dp);
2374 intel_psr_enable(intel_dp);
2375 intel_edp_drrs_enable(intel_dp);
2376 }
2377
2378 if (intel_crtc->config->has_audio) {
2379 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2380 intel_audio_codec_enable(intel_encoder);
2381 }
2382 }
2383
2384 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2385 {
2386 struct drm_encoder *encoder = &intel_encoder->base;
2387 struct drm_crtc *crtc = encoder->crtc;
2388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2389 int type = intel_encoder->type;
2390 struct drm_device *dev = encoder->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392
2393 if (intel_crtc->config->has_audio) {
2394 intel_audio_codec_disable(intel_encoder);
2395 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2396 }
2397
2398 if (type == INTEL_OUTPUT_EDP) {
2399 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2400
2401 intel_edp_drrs_disable(intel_dp);
2402 intel_psr_disable(intel_dp);
2403 intel_edp_backlight_off(intel_dp);
2404 }
2405 }
2406
2407 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
2408 struct intel_shared_dpll *pll)
2409 {
2410 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2411 POSTING_READ(WRPLL_CTL(pll->id));
2412 udelay(20);
2413 }
2414
2415 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
2416 struct intel_shared_dpll *pll)
2417 {
2418 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2419 POSTING_READ(SPLL_CTL);
2420 udelay(20);
2421 }
2422
2423 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2424 struct intel_shared_dpll *pll)
2425 {
2426 uint32_t val;
2427
2428 val = I915_READ(WRPLL_CTL(pll->id));
2429 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2430 POSTING_READ(WRPLL_CTL(pll->id));
2431 }
2432
2433 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2434 struct intel_shared_dpll *pll)
2435 {
2436 uint32_t val;
2437
2438 val = I915_READ(SPLL_CTL);
2439 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2440 POSTING_READ(SPLL_CTL);
2441 }
2442
2443 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2444 struct intel_shared_dpll *pll,
2445 struct intel_dpll_hw_state *hw_state)
2446 {
2447 uint32_t val;
2448
2449 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2450 return false;
2451
2452 val = I915_READ(WRPLL_CTL(pll->id));
2453 hw_state->wrpll = val;
2454
2455 return val & WRPLL_PLL_ENABLE;
2456 }
2457
2458 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2459 struct intel_shared_dpll *pll,
2460 struct intel_dpll_hw_state *hw_state)
2461 {
2462 uint32_t val;
2463
2464 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2465 return false;
2466
2467 val = I915_READ(SPLL_CTL);
2468 hw_state->spll = val;
2469
2470 return val & SPLL_PLL_ENABLE;
2471 }
2472
2473
2474 static const char * const hsw_ddi_pll_names[] = {
2475 "WRPLL 1",
2476 "WRPLL 2",
2477 "SPLL"
2478 };
2479
2480 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2481 {
2482 int i;
2483
2484 dev_priv->num_shared_dpll = 3;
2485
2486 for (i = 0; i < 2; i++) {
2487 dev_priv->shared_dplls[i].id = i;
2488 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2489 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2490 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
2491 dev_priv->shared_dplls[i].get_hw_state =
2492 hsw_ddi_wrpll_get_hw_state;
2493 }
2494
2495 /* SPLL is special, but needs to be initialized anyway.. */
2496 dev_priv->shared_dplls[i].id = i;
2497 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2498 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2499 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2500 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2501
2502 }
2503
2504 static const char * const skl_ddi_pll_names[] = {
2505 "DPLL 1",
2506 "DPLL 2",
2507 "DPLL 3",
2508 };
2509
2510 struct skl_dpll_regs {
2511 i915_reg_t ctl, cfgcr1, cfgcr2;
2512 };
2513
2514 /* this array is indexed by the *shared* pll id */
2515 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2516 {
2517 /* DPLL 1 */
2518 .ctl = LCPLL2_CTL,
2519 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2520 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2521 },
2522 {
2523 /* DPLL 2 */
2524 .ctl = WRPLL_CTL(0),
2525 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2526 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2527 },
2528 {
2529 /* DPLL 3 */
2530 .ctl = WRPLL_CTL(1),
2531 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2532 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2533 },
2534 };
2535
2536 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2537 struct intel_shared_dpll *pll)
2538 {
2539 uint32_t val;
2540 unsigned int dpll;
2541 const struct skl_dpll_regs *regs = skl_dpll_regs;
2542
2543 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2544 dpll = pll->id + 1;
2545
2546 val = I915_READ(DPLL_CTRL1);
2547
2548 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2549 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2550 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2551
2552 I915_WRITE(DPLL_CTRL1, val);
2553 POSTING_READ(DPLL_CTRL1);
2554
2555 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2556 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2557 POSTING_READ(regs[pll->id].cfgcr1);
2558 POSTING_READ(regs[pll->id].cfgcr2);
2559
2560 /* the enable bit is always bit 31 */
2561 I915_WRITE(regs[pll->id].ctl,
2562 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2563
2564 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2565 DRM_ERROR("DPLL %d not locked\n", dpll);
2566 }
2567
2568 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2569 struct intel_shared_dpll *pll)
2570 {
2571 const struct skl_dpll_regs *regs = skl_dpll_regs;
2572
2573 /* the enable bit is always bit 31 */
2574 I915_WRITE(regs[pll->id].ctl,
2575 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2576 POSTING_READ(regs[pll->id].ctl);
2577 }
2578
2579 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2580 struct intel_shared_dpll *pll,
2581 struct intel_dpll_hw_state *hw_state)
2582 {
2583 uint32_t val;
2584 unsigned int dpll;
2585 const struct skl_dpll_regs *regs = skl_dpll_regs;
2586
2587 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2588 return false;
2589
2590 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2591 dpll = pll->id + 1;
2592
2593 val = I915_READ(regs[pll->id].ctl);
2594 if (!(val & LCPLL_PLL_ENABLE))
2595 return false;
2596
2597 val = I915_READ(DPLL_CTRL1);
2598 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2599
2600 /* avoid reading back stale values if HDMI mode is not enabled */
2601 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2602 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2603 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2604 }
2605
2606 return true;
2607 }
2608
2609 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2610 {
2611 int i;
2612
2613 dev_priv->num_shared_dpll = 3;
2614
2615 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2616 dev_priv->shared_dplls[i].id = i;
2617 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2618 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2619 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2620 dev_priv->shared_dplls[i].get_hw_state =
2621 skl_ddi_pll_get_hw_state;
2622 }
2623 }
2624
2625 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2626 enum dpio_phy phy)
2627 {
2628 enum port port;
2629 uint32_t val;
2630
2631 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2632 val |= GT_DISPLAY_POWER_ON(phy);
2633 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2634
2635 /* Considering 10ms timeout until BSpec is updated */
2636 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2637 DRM_ERROR("timeout during PHY%d power on\n", phy);
2638
2639 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2640 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2641 int lane;
2642
2643 for (lane = 0; lane < 4; lane++) {
2644 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2645 /*
2646 * Note that on CHV this flag is called UPAR, but has
2647 * the same function.
2648 */
2649 val &= ~LATENCY_OPTIM;
2650 if (lane != 1)
2651 val |= LATENCY_OPTIM;
2652
2653 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2654 }
2655 }
2656
2657 /* Program PLL Rcomp code offset */
2658 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2659 val &= ~IREF0RC_OFFSET_MASK;
2660 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2661 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2662
2663 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2664 val &= ~IREF1RC_OFFSET_MASK;
2665 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2666 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2667
2668 /* Program power gating */
2669 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2670 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2671 SUS_CLK_CONFIG;
2672 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2673
2674 if (phy == DPIO_PHY0) {
2675 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2676 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2677 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2678 }
2679
2680 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2681 val &= ~OCL2_LDOFUSE_PWR_DIS;
2682 /*
2683 * On PHY1 disable power on the second channel, since no port is
2684 * connected there. On PHY0 both channels have a port, so leave it
2685 * enabled.
2686 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2687 * power down the second channel on PHY0 as well.
2688 */
2689 if (phy == DPIO_PHY1)
2690 val |= OCL2_LDOFUSE_PWR_DIS;
2691 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2692
2693 if (phy == DPIO_PHY0) {
2694 uint32_t grc_code;
2695 /*
2696 * PHY0 isn't connected to an RCOMP resistor so copy over
2697 * the corresponding calibrated value from PHY1, and disable
2698 * the automatic calibration on PHY0.
2699 */
2700 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2701 10))
2702 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2703
2704 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2705 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2706 grc_code = val << GRC_CODE_FAST_SHIFT |
2707 val << GRC_CODE_SLOW_SHIFT |
2708 val;
2709 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2710
2711 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2712 val |= GRC_DIS | GRC_RDY_OVRD;
2713 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2714 }
2715
2716 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2717 val |= COMMON_RESET_DIS;
2718 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2719 }
2720
2721 void broxton_ddi_phy_init(struct drm_device *dev)
2722 {
2723 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2724 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2725 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2726 }
2727
2728 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2729 enum dpio_phy phy)
2730 {
2731 uint32_t val;
2732
2733 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2734 val &= ~COMMON_RESET_DIS;
2735 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2736 }
2737
2738 void broxton_ddi_phy_uninit(struct drm_device *dev)
2739 {
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741
2742 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2743 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2744
2745 /* FIXME: do this in broxton_phy_uninit per phy */
2746 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2747 }
2748
2749 static const char * const bxt_ddi_pll_names[] = {
2750 "PORT PLL A",
2751 "PORT PLL B",
2752 "PORT PLL C",
2753 };
2754
2755 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2756 struct intel_shared_dpll *pll)
2757 {
2758 uint32_t temp;
2759 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2760
2761 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2762 temp &= ~PORT_PLL_REF_SEL;
2763 /* Non-SSC reference */
2764 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2765
2766 /* Disable 10 bit clock */
2767 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2768 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2769 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2770
2771 /* Write P1 & P2 */
2772 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2773 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2774 temp |= pll->config.hw_state.ebb0;
2775 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2776
2777 /* Write M2 integer */
2778 temp = I915_READ(BXT_PORT_PLL(port, 0));
2779 temp &= ~PORT_PLL_M2_MASK;
2780 temp |= pll->config.hw_state.pll0;
2781 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2782
2783 /* Write N */
2784 temp = I915_READ(BXT_PORT_PLL(port, 1));
2785 temp &= ~PORT_PLL_N_MASK;
2786 temp |= pll->config.hw_state.pll1;
2787 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2788
2789 /* Write M2 fraction */
2790 temp = I915_READ(BXT_PORT_PLL(port, 2));
2791 temp &= ~PORT_PLL_M2_FRAC_MASK;
2792 temp |= pll->config.hw_state.pll2;
2793 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2794
2795 /* Write M2 fraction enable */
2796 temp = I915_READ(BXT_PORT_PLL(port, 3));
2797 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2798 temp |= pll->config.hw_state.pll3;
2799 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2800
2801 /* Write coeff */
2802 temp = I915_READ(BXT_PORT_PLL(port, 6));
2803 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2804 temp &= ~PORT_PLL_INT_COEFF_MASK;
2805 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2806 temp |= pll->config.hw_state.pll6;
2807 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2808
2809 /* Write calibration val */
2810 temp = I915_READ(BXT_PORT_PLL(port, 8));
2811 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2812 temp |= pll->config.hw_state.pll8;
2813 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2814
2815 temp = I915_READ(BXT_PORT_PLL(port, 9));
2816 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2817 temp |= pll->config.hw_state.pll9;
2818 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2819
2820 temp = I915_READ(BXT_PORT_PLL(port, 10));
2821 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2822 temp &= ~PORT_PLL_DCO_AMP_MASK;
2823 temp |= pll->config.hw_state.pll10;
2824 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2825
2826 /* Recalibrate with new settings */
2827 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2828 temp |= PORT_PLL_RECALIBRATE;
2829 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2830 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2831 temp |= pll->config.hw_state.ebb4;
2832 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2833
2834 /* Enable PLL */
2835 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2836 temp |= PORT_PLL_ENABLE;
2837 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2838 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2839
2840 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2841 PORT_PLL_LOCK), 200))
2842 DRM_ERROR("PLL %d not locked\n", port);
2843
2844 /*
2845 * While we write to the group register to program all lanes at once we
2846 * can read only lane registers and we pick lanes 0/1 for that.
2847 */
2848 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2849 temp &= ~LANE_STAGGER_MASK;
2850 temp &= ~LANESTAGGER_STRAP_OVRD;
2851 temp |= pll->config.hw_state.pcsdw12;
2852 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2853 }
2854
2855 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2856 struct intel_shared_dpll *pll)
2857 {
2858 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2859 uint32_t temp;
2860
2861 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2862 temp &= ~PORT_PLL_ENABLE;
2863 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2864 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2865 }
2866
2867 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2868 struct intel_shared_dpll *pll,
2869 struct intel_dpll_hw_state *hw_state)
2870 {
2871 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2872 uint32_t val;
2873
2874 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2875 return false;
2876
2877 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2878 if (!(val & PORT_PLL_ENABLE))
2879 return false;
2880
2881 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2882 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2883
2884 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2885 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2886
2887 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2888 hw_state->pll0 &= PORT_PLL_M2_MASK;
2889
2890 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2891 hw_state->pll1 &= PORT_PLL_N_MASK;
2892
2893 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2894 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2895
2896 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2897 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2898
2899 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2900 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2901 PORT_PLL_INT_COEFF_MASK |
2902 PORT_PLL_GAIN_CTL_MASK;
2903
2904 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2905 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2906
2907 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2908 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2909
2910 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2911 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2912 PORT_PLL_DCO_AMP_MASK;
2913
2914 /*
2915 * While we write to the group register to program all lanes at once we
2916 * can read only lane registers. We configure all lanes the same way, so
2917 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2918 */
2919 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2920 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
2921 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2922 hw_state->pcsdw12,
2923 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2924 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2925
2926 return true;
2927 }
2928
2929 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2930 {
2931 int i;
2932
2933 dev_priv->num_shared_dpll = 3;
2934
2935 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2936 dev_priv->shared_dplls[i].id = i;
2937 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2938 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2939 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2940 dev_priv->shared_dplls[i].get_hw_state =
2941 bxt_ddi_pll_get_hw_state;
2942 }
2943 }
2944
2945 void intel_ddi_pll_init(struct drm_device *dev)
2946 {
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948 uint32_t val = I915_READ(LCPLL_CTL);
2949
2950 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2951 skl_shared_dplls_init(dev_priv);
2952 else if (IS_BROXTON(dev))
2953 bxt_shared_dplls_init(dev_priv);
2954 else
2955 hsw_shared_dplls_init(dev_priv);
2956
2957 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2958 int cdclk_freq;
2959
2960 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2961 dev_priv->skl_boot_cdclk = cdclk_freq;
2962 if (skl_sanitize_cdclk(dev_priv))
2963 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
2964 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2965 DRM_ERROR("LCPLL1 is disabled\n");
2966 } else if (IS_BROXTON(dev)) {
2967 broxton_init_cdclk(dev);
2968 broxton_ddi_phy_init(dev);
2969 } else {
2970 /*
2971 * The LCPLL register should be turned on by the BIOS. For now
2972 * let's just check its state and print errors in case
2973 * something is wrong. Don't even try to turn it on.
2974 */
2975
2976 if (val & LCPLL_CD_SOURCE_FCLK)
2977 DRM_ERROR("CDCLK source is not LCPLL\n");
2978
2979 if (val & LCPLL_PLL_DISABLE)
2980 DRM_ERROR("LCPLL is disabled\n");
2981 }
2982 }
2983
2984 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2985 {
2986 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2987 struct drm_i915_private *dev_priv =
2988 to_i915(intel_dig_port->base.base.dev);
2989 enum port port = intel_dig_port->port;
2990 uint32_t val;
2991 bool wait = false;
2992
2993 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2994 val = I915_READ(DDI_BUF_CTL(port));
2995 if (val & DDI_BUF_CTL_ENABLE) {
2996 val &= ~DDI_BUF_CTL_ENABLE;
2997 I915_WRITE(DDI_BUF_CTL(port), val);
2998 wait = true;
2999 }
3000
3001 val = I915_READ(DP_TP_CTL(port));
3002 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3003 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3004 I915_WRITE(DP_TP_CTL(port), val);
3005 POSTING_READ(DP_TP_CTL(port));
3006
3007 if (wait)
3008 intel_wait_ddi_buf_idle(dev_priv, port);
3009 }
3010
3011 val = DP_TP_CTL_ENABLE |
3012 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3013 if (intel_dp->is_mst)
3014 val |= DP_TP_CTL_MODE_MST;
3015 else {
3016 val |= DP_TP_CTL_MODE_SST;
3017 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3018 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3019 }
3020 I915_WRITE(DP_TP_CTL(port), val);
3021 POSTING_READ(DP_TP_CTL(port));
3022
3023 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3024 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3025 POSTING_READ(DDI_BUF_CTL(port));
3026
3027 udelay(600);
3028 }
3029
3030 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3031 {
3032 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3033 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3034 uint32_t val;
3035
3036 intel_ddi_post_disable(intel_encoder);
3037
3038 val = I915_READ(FDI_RX_CTL(PIPE_A));
3039 val &= ~FDI_RX_ENABLE;
3040 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3041
3042 val = I915_READ(FDI_RX_MISC(PIPE_A));
3043 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3044 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3045 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3046
3047 val = I915_READ(FDI_RX_CTL(PIPE_A));
3048 val &= ~FDI_PCDCLK;
3049 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3050
3051 val = I915_READ(FDI_RX_CTL(PIPE_A));
3052 val &= ~FDI_RX_PLL_ENABLE;
3053 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3054 }
3055
3056 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3057 struct intel_crtc *intel_crtc)
3058 {
3059 u32 temp;
3060
3061 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3062 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3063 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3064 return true;
3065 }
3066 return false;
3067 }
3068
3069 void intel_ddi_get_config(struct intel_encoder *encoder,
3070 struct intel_crtc_state *pipe_config)
3071 {
3072 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3073 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3074 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3075 struct intel_hdmi *intel_hdmi;
3076 u32 temp, flags = 0;
3077
3078 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3079 if (temp & TRANS_DDI_PHSYNC)
3080 flags |= DRM_MODE_FLAG_PHSYNC;
3081 else
3082 flags |= DRM_MODE_FLAG_NHSYNC;
3083 if (temp & TRANS_DDI_PVSYNC)
3084 flags |= DRM_MODE_FLAG_PVSYNC;
3085 else
3086 flags |= DRM_MODE_FLAG_NVSYNC;
3087
3088 pipe_config->base.adjusted_mode.flags |= flags;
3089
3090 switch (temp & TRANS_DDI_BPC_MASK) {
3091 case TRANS_DDI_BPC_6:
3092 pipe_config->pipe_bpp = 18;
3093 break;
3094 case TRANS_DDI_BPC_8:
3095 pipe_config->pipe_bpp = 24;
3096 break;
3097 case TRANS_DDI_BPC_10:
3098 pipe_config->pipe_bpp = 30;
3099 break;
3100 case TRANS_DDI_BPC_12:
3101 pipe_config->pipe_bpp = 36;
3102 break;
3103 default:
3104 break;
3105 }
3106
3107 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3108 case TRANS_DDI_MODE_SELECT_HDMI:
3109 pipe_config->has_hdmi_sink = true;
3110 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3111
3112 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
3113 pipe_config->has_infoframe = true;
3114 break;
3115 case TRANS_DDI_MODE_SELECT_DVI:
3116 case TRANS_DDI_MODE_SELECT_FDI:
3117 break;
3118 case TRANS_DDI_MODE_SELECT_DP_SST:
3119 case TRANS_DDI_MODE_SELECT_DP_MST:
3120 pipe_config->has_dp_encoder = true;
3121 pipe_config->lane_count =
3122 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3123 intel_dp_get_m_n(intel_crtc, pipe_config);
3124 break;
3125 default:
3126 break;
3127 }
3128
3129 pipe_config->has_audio =
3130 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
3131
3132 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3133 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3134 /*
3135 * This is a big fat ugly hack.
3136 *
3137 * Some machines in UEFI boot mode provide us a VBT that has 18
3138 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3139 * unknown we fail to light up. Yet the same BIOS boots up with
3140 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3141 * max, not what it tells us to use.
3142 *
3143 * Note: This will still be broken if the eDP panel is not lit
3144 * up by the BIOS, and thus we can't get the mode at module
3145 * load.
3146 */
3147 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3148 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3149 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3150 }
3151
3152 intel_ddi_clock_get(encoder, pipe_config);
3153 }
3154
3155 static void intel_ddi_destroy(struct drm_encoder *encoder)
3156 {
3157 /* HDMI has nothing special to destroy, so we can go with this. */
3158 intel_dp_encoder_destroy(encoder);
3159 }
3160
3161 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3162 struct intel_crtc_state *pipe_config)
3163 {
3164 int type = encoder->type;
3165 int port = intel_ddi_get_encoder_port(encoder);
3166
3167 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3168
3169 if (port == PORT_A)
3170 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3171
3172 if (type == INTEL_OUTPUT_HDMI)
3173 return intel_hdmi_compute_config(encoder, pipe_config);
3174 else
3175 return intel_dp_compute_config(encoder, pipe_config);
3176 }
3177
3178 static const struct drm_encoder_funcs intel_ddi_funcs = {
3179 .destroy = intel_ddi_destroy,
3180 };
3181
3182 static struct intel_connector *
3183 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3184 {
3185 struct intel_connector *connector;
3186 enum port port = intel_dig_port->port;
3187
3188 connector = intel_connector_alloc();
3189 if (!connector)
3190 return NULL;
3191
3192 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3193 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3194 kfree(connector);
3195 return NULL;
3196 }
3197
3198 return connector;
3199 }
3200
3201 static struct intel_connector *
3202 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3203 {
3204 struct intel_connector *connector;
3205 enum port port = intel_dig_port->port;
3206
3207 connector = intel_connector_alloc();
3208 if (!connector)
3209 return NULL;
3210
3211 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3212 intel_hdmi_init_connector(intel_dig_port, connector);
3213
3214 return connector;
3215 }
3216
3217 void intel_ddi_init(struct drm_device *dev, enum port port)
3218 {
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_digital_port *intel_dig_port;
3221 struct intel_encoder *intel_encoder;
3222 struct drm_encoder *encoder;
3223 bool init_hdmi, init_dp;
3224 int max_lanes;
3225
3226 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
3227 switch (port) {
3228 case PORT_A:
3229 max_lanes = 4;
3230 break;
3231 case PORT_E:
3232 max_lanes = 0;
3233 break;
3234 default:
3235 max_lanes = 4;
3236 break;
3237 }
3238 } else {
3239 switch (port) {
3240 case PORT_A:
3241 max_lanes = 2;
3242 break;
3243 case PORT_E:
3244 max_lanes = 2;
3245 break;
3246 default:
3247 max_lanes = 4;
3248 break;
3249 }
3250 }
3251
3252 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3253 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3254 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3255 if (!init_dp && !init_hdmi) {
3256 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3257 port_name(port));
3258 return;
3259 }
3260
3261 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3262 if (!intel_dig_port)
3263 return;
3264
3265 intel_encoder = &intel_dig_port->base;
3266 encoder = &intel_encoder->base;
3267
3268 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3269 DRM_MODE_ENCODER_TMDS, NULL);
3270
3271 intel_encoder->compute_config = intel_ddi_compute_config;
3272 intel_encoder->enable = intel_enable_ddi;
3273 intel_encoder->pre_enable = intel_ddi_pre_enable;
3274 intel_encoder->disable = intel_disable_ddi;
3275 intel_encoder->post_disable = intel_ddi_post_disable;
3276 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3277 intel_encoder->get_config = intel_ddi_get_config;
3278
3279 intel_dig_port->port = port;
3280 dev_priv->dig_port_map[port] = intel_encoder;
3281 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3282 (DDI_BUF_PORT_REVERSAL |
3283 DDI_A_4_LANES);
3284
3285 /*
3286 * Bspec says that DDI_A_4_LANES is the only supported configuration
3287 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3288 * wasn't lit up at boot. Force this bit on in our internal
3289 * configuration so that we use the proper lane count for our
3290 * calculations.
3291 */
3292 if (IS_BROXTON(dev) && port == PORT_A) {
3293 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3294 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3295 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3296 max_lanes = 4;
3297 }
3298 }
3299
3300 intel_dig_port->max_lanes = max_lanes;
3301
3302 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3303 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3304 intel_encoder->cloneable = 0;
3305
3306 if (init_dp) {
3307 if (!intel_ddi_init_dp_connector(intel_dig_port))
3308 goto err;
3309
3310 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3311 /*
3312 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3313 * interrupts to check the external panel connection.
3314 */
3315 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
3316 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3317 else
3318 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3319 }
3320
3321 /* In theory we don't need the encoder->type check, but leave it just in
3322 * case we have some really bad VBTs... */
3323 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3324 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3325 goto err;
3326 }
3327
3328 return;
3329
3330 err:
3331 drm_encoder_cleanup(encoder);
3332 kfree(intel_dig_port);
3333 }
Linux kernel - Deliverables
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