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drm/i915: Track hdmi mode in the pipe config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35 static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 };
46
47 static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
57 };
58
59 static const u32 hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
73 };
74
75 static const u32 bdw_ddi_translations_edp[] = {
76 0x00FFFFFF, 0x00000012, /* eDP parameters */
77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00FFFFFF, 0x00020011,
80 0x00DB6FFF, 0x0005000F,
81 0x00BEEFFF, 0x000A000C,
82 0x00FFFFFF, 0x0005000F,
83 0x00DB6FFF, 0x000A000C,
84 0x00FFFFFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
86 };
87
88 static const u32 bdw_ddi_translations_dp[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x00FFFFFF, 0x000E000A,
93 0x00D75FFF, 0x00180004,
94 0x80CB2FFF, 0x001B0002,
95 0x00F7DFFF, 0x00180004,
96 0x80D75FFF, 0x001B0002,
97 0x80FFFFFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
99 };
100
101 static const u32 bdw_ddi_translations_fdi[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
112 };
113
114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
115 {
116 struct drm_encoder *encoder = &intel_encoder->base;
117 int type = intel_encoder->type;
118
119 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
120 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
121 struct intel_digital_port *intel_dig_port =
122 enc_to_dig_port(encoder);
123 return intel_dig_port->port;
124
125 } else if (type == INTEL_OUTPUT_ANALOG) {
126 return PORT_E;
127
128 } else {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type);
130 BUG();
131 }
132 }
133
134 /*
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
139 * of those
140 */
141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
142 {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 u32 reg;
145 int i;
146 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
147 const u32 *ddi_translations_fdi;
148 const u32 *ddi_translations_dp;
149 const u32 *ddi_translations_edp;
150 const u32 *ddi_translations;
151
152 if (IS_BROADWELL(dev)) {
153 ddi_translations_fdi = bdw_ddi_translations_fdi;
154 ddi_translations_dp = bdw_ddi_translations_dp;
155 ddi_translations_edp = bdw_ddi_translations_edp;
156 } else if (IS_HASWELL(dev)) {
157 ddi_translations_fdi = hsw_ddi_translations_fdi;
158 ddi_translations_dp = hsw_ddi_translations_dp;
159 ddi_translations_edp = hsw_ddi_translations_dp;
160 } else {
161 WARN(1, "ddi translation table missing\n");
162 ddi_translations_edp = bdw_ddi_translations_dp;
163 ddi_translations_fdi = bdw_ddi_translations_fdi;
164 ddi_translations_dp = bdw_ddi_translations_dp;
165 }
166
167 switch (port) {
168 case PORT_A:
169 ddi_translations = ddi_translations_edp;
170 break;
171 case PORT_B:
172 case PORT_C:
173 ddi_translations = ddi_translations_dp;
174 break;
175 case PORT_D:
176 if (intel_dp_is_edp(dev, PORT_D))
177 ddi_translations = ddi_translations_edp;
178 else
179 ddi_translations = ddi_translations_dp;
180 break;
181 case PORT_E:
182 ddi_translations = ddi_translations_fdi;
183 break;
184 default:
185 BUG();
186 }
187
188 for (i = 0, reg = DDI_BUF_TRANS(port);
189 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
190 I915_WRITE(reg, ddi_translations[i]);
191 reg += 4;
192 }
193 /* Entry 9 is for HDMI: */
194 for (i = 0; i < 2; i++) {
195 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
196 reg += 4;
197 }
198 }
199
200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
202 */
203 void intel_prepare_ddi(struct drm_device *dev)
204 {
205 int port;
206
207 if (!HAS_DDI(dev))
208 return;
209
210 for (port = PORT_A; port <= PORT_E; port++)
211 intel_prepare_ddi_buffers(dev, port);
212 }
213
214 static const long hsw_ddi_buf_ctl_values[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW,
216 DDI_BUF_EMP_400MV_3_5DB_HSW,
217 DDI_BUF_EMP_400MV_6DB_HSW,
218 DDI_BUF_EMP_400MV_9_5DB_HSW,
219 DDI_BUF_EMP_600MV_0DB_HSW,
220 DDI_BUF_EMP_600MV_3_5DB_HSW,
221 DDI_BUF_EMP_600MV_6DB_HSW,
222 DDI_BUF_EMP_800MV_0DB_HSW,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
224 };
225
226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
227 enum port port)
228 {
229 uint32_t reg = DDI_BUF_CTL(port);
230 int i;
231
232 for (i = 0; i < 8; i++) {
233 udelay(1);
234 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
235 return;
236 }
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
238 }
239
240 /* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
243 *
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
247 */
248
249 void hsw_fdi_link_train(struct drm_crtc *crtc)
250 {
251 struct drm_device *dev = crtc->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
254 u32 temp, i, rx_ctl_val;
255
256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
259 * - FDI delay to 90h
260 *
261 * WaFDIAutoLinkSetTimingOverrride:hsw
262 */
263 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
266
267 /* Enable the PCH Receiver FDI PLL */
268 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
269 FDI_RX_PLL_ENABLE |
270 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
271 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
272 POSTING_READ(_FDI_RXA_CTL);
273 udelay(220);
274
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val |= FDI_PCDCLK;
277 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
278
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
281
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E),
287 DP_TP_CTL_FDI_AUTOTRAIN |
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
289 DP_TP_CTL_LINK_TRAIN_PAT1 |
290 DP_TP_CTL_ENABLE);
291
292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
296 I915_WRITE(DDI_BUF_CTL(PORT_E),
297 DDI_BUF_CTL_ENABLE |
298 ((intel_crtc->config.fdi_lanes - 1) << 1) |
299 hsw_ddi_buf_ctl_values[i / 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E));
301
302 udelay(600);
303
304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
306
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
309 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
310 POSTING_READ(_FDI_RXA_CTL);
311
312 /* Wait for FDI receiver lane calibration */
313 udelay(30);
314
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp = I915_READ(_FDI_RXA_MISC);
317 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
318 I915_WRITE(_FDI_RXA_MISC, temp);
319 POSTING_READ(_FDI_RXA_MISC);
320
321 /* Wait for FDI auto training time */
322 udelay(5);
323
324 temp = I915_READ(DP_TP_STATUS(PORT_E));
325 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
327
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E),
330 DP_TP_CTL_FDI_AUTOTRAIN |
331 DP_TP_CTL_LINK_TRAIN_NORMAL |
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
333 DP_TP_CTL_ENABLE);
334
335 return;
336 }
337
338 temp = I915_READ(DDI_BUF_CTL(PORT_E));
339 temp &= ~DDI_BUF_CTL_ENABLE;
340 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
341 POSTING_READ(DDI_BUF_CTL(PORT_E));
342
343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
344 temp = I915_READ(DP_TP_CTL(PORT_E));
345 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
346 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
347 I915_WRITE(DP_TP_CTL(PORT_E), temp);
348 POSTING_READ(DP_TP_CTL(PORT_E));
349
350 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
351
352 rx_ctl_val &= ~FDI_RX_ENABLE;
353 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
354 POSTING_READ(_FDI_RXA_CTL);
355
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp = I915_READ(_FDI_RXA_MISC);
358 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
359 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC, temp);
361 POSTING_READ(_FDI_RXA_MISC);
362 }
363
364 DRM_ERROR("FDI link training failed!\n");
365 }
366
367 static void intel_ddi_mode_set(struct intel_encoder *encoder)
368 {
369 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
370 int port = intel_ddi_get_encoder_port(encoder);
371 int pipe = crtc->pipe;
372 int type = encoder->type;
373 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
374
375 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
376 port_name(port), pipe_name(pipe));
377
378 crtc->eld_vld = false;
379 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
381 struct intel_digital_port *intel_dig_port =
382 enc_to_dig_port(&encoder->base);
383
384 intel_dp->DP = intel_dig_port->saved_port_bits |
385 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
386 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
387
388 if (intel_dp->has_audio) {
389 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
390 pipe_name(crtc->pipe));
391
392 /* write eld */
393 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
394 intel_write_eld(&encoder->base, adjusted_mode);
395 }
396 } else if (type == INTEL_OUTPUT_HDMI) {
397 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
398
399 if (intel_hdmi->has_audio) {
400 /* Proper support for digital audio needs a new logic
401 * and a new set of registers, so we leave it for future
402 * patch bombing.
403 */
404 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
405 pipe_name(crtc->pipe));
406
407 /* write eld */
408 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
409 intel_write_eld(&encoder->base, adjusted_mode);
410 }
411
412 intel_hdmi->set_infoframes(&encoder->base,
413 crtc->config.has_hdmi_sink,
414 adjusted_mode);
415 }
416 }
417
418 static struct intel_encoder *
419 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
420 {
421 struct drm_device *dev = crtc->dev;
422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
423 struct intel_encoder *intel_encoder, *ret = NULL;
424 int num_encoders = 0;
425
426 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
427 ret = intel_encoder;
428 num_encoders++;
429 }
430
431 if (num_encoders != 1)
432 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
433 pipe_name(intel_crtc->pipe));
434
435 BUG_ON(ret == NULL);
436 return ret;
437 }
438
439 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
440 {
441 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
442 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
444 uint32_t val;
445
446 switch (intel_crtc->ddi_pll_sel) {
447 case PORT_CLK_SEL_SPLL:
448 plls->spll_refcount--;
449 if (plls->spll_refcount == 0) {
450 DRM_DEBUG_KMS("Disabling SPLL\n");
451 val = I915_READ(SPLL_CTL);
452 WARN_ON(!(val & SPLL_PLL_ENABLE));
453 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
454 POSTING_READ(SPLL_CTL);
455 }
456 break;
457 case PORT_CLK_SEL_WRPLL1:
458 plls->wrpll1_refcount--;
459 if (plls->wrpll1_refcount == 0) {
460 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
461 val = I915_READ(WRPLL_CTL1);
462 WARN_ON(!(val & WRPLL_PLL_ENABLE));
463 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
464 POSTING_READ(WRPLL_CTL1);
465 }
466 break;
467 case PORT_CLK_SEL_WRPLL2:
468 plls->wrpll2_refcount--;
469 if (plls->wrpll2_refcount == 0) {
470 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
471 val = I915_READ(WRPLL_CTL2);
472 WARN_ON(!(val & WRPLL_PLL_ENABLE));
473 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
474 POSTING_READ(WRPLL_CTL2);
475 }
476 break;
477 }
478
479 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
480 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
481 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
482
483 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
484 }
485
486 #define LC_FREQ 2700
487 #define LC_FREQ_2K (LC_FREQ * 2000)
488
489 #define P_MIN 2
490 #define P_MAX 64
491 #define P_INC 2
492
493 /* Constraints for PLL good behavior */
494 #define REF_MIN 48
495 #define REF_MAX 400
496 #define VCO_MIN 2400
497 #define VCO_MAX 4800
498
499 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
500
501 struct wrpll_rnp {
502 unsigned p, n2, r2;
503 };
504
505 static unsigned wrpll_get_budget_for_freq(int clock)
506 {
507 unsigned budget;
508
509 switch (clock) {
510 case 25175000:
511 case 25200000:
512 case 27000000:
513 case 27027000:
514 case 37762500:
515 case 37800000:
516 case 40500000:
517 case 40541000:
518 case 54000000:
519 case 54054000:
520 case 59341000:
521 case 59400000:
522 case 72000000:
523 case 74176000:
524 case 74250000:
525 case 81000000:
526 case 81081000:
527 case 89012000:
528 case 89100000:
529 case 108000000:
530 case 108108000:
531 case 111264000:
532 case 111375000:
533 case 148352000:
534 case 148500000:
535 case 162000000:
536 case 162162000:
537 case 222525000:
538 case 222750000:
539 case 296703000:
540 case 297000000:
541 budget = 0;
542 break;
543 case 233500000:
544 case 245250000:
545 case 247750000:
546 case 253250000:
547 case 298000000:
548 budget = 1500;
549 break;
550 case 169128000:
551 case 169500000:
552 case 179500000:
553 case 202000000:
554 budget = 2000;
555 break;
556 case 256250000:
557 case 262500000:
558 case 270000000:
559 case 272500000:
560 case 273750000:
561 case 280750000:
562 case 281250000:
563 case 286000000:
564 case 291750000:
565 budget = 4000;
566 break;
567 case 267250000:
568 case 268500000:
569 budget = 5000;
570 break;
571 default:
572 budget = 1000;
573 break;
574 }
575
576 return budget;
577 }
578
579 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
580 unsigned r2, unsigned n2, unsigned p,
581 struct wrpll_rnp *best)
582 {
583 uint64_t a, b, c, d, diff, diff_best;
584
585 /* No best (r,n,p) yet */
586 if (best->p == 0) {
587 best->p = p;
588 best->n2 = n2;
589 best->r2 = r2;
590 return;
591 }
592
593 /*
594 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
595 * freq2k.
596 *
597 * delta = 1e6 *
598 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
599 * freq2k;
600 *
601 * and we would like delta <= budget.
602 *
603 * If the discrepancy is above the PPM-based budget, always prefer to
604 * improve upon the previous solution. However, if you're within the
605 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
606 */
607 a = freq2k * budget * p * r2;
608 b = freq2k * budget * best->p * best->r2;
609 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
610 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
611 (LC_FREQ_2K * best->n2));
612 c = 1000000 * diff;
613 d = 1000000 * diff_best;
614
615 if (a < c && b < d) {
616 /* If both are above the budget, pick the closer */
617 if (best->p * best->r2 * diff < p * r2 * diff_best) {
618 best->p = p;
619 best->n2 = n2;
620 best->r2 = r2;
621 }
622 } else if (a >= c && b < d) {
623 /* If A is below the threshold but B is above it? Update. */
624 best->p = p;
625 best->n2 = n2;
626 best->r2 = r2;
627 } else if (a >= c && b >= d) {
628 /* Both are below the limit, so pick the higher n2/(r2*r2) */
629 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
630 best->p = p;
631 best->n2 = n2;
632 best->r2 = r2;
633 }
634 }
635 /* Otherwise a < c && b >= d, do nothing */
636 }
637
638 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
639 int reg)
640 {
641 int refclk = LC_FREQ;
642 int n, p, r;
643 u32 wrpll;
644
645 wrpll = I915_READ(reg);
646 switch (wrpll & SPLL_PLL_REF_MASK) {
647 case SPLL_PLL_SSC:
648 case SPLL_PLL_NON_SSC:
649 /*
650 * We could calculate spread here, but our checking
651 * code only cares about 5% accuracy, and spread is a max of
652 * 0.5% downspread.
653 */
654 refclk = 135;
655 break;
656 case SPLL_PLL_LCPLL:
657 refclk = LC_FREQ;
658 break;
659 default:
660 WARN(1, "bad wrpll refclk\n");
661 return 0;
662 }
663
664 r = wrpll & WRPLL_DIVIDER_REF_MASK;
665 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
666 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
667
668 /* Convert to KHz, p & r have a fixed point portion */
669 return (refclk * n * 100) / (p * r);
670 }
671
672 static void intel_ddi_clock_get(struct intel_encoder *encoder,
673 struct intel_crtc_config *pipe_config)
674 {
675 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
676 enum port port = intel_ddi_get_encoder_port(encoder);
677 int link_clock = 0;
678 u32 val, pll;
679
680 val = I915_READ(PORT_CLK_SEL(port));
681 switch (val & PORT_CLK_SEL_MASK) {
682 case PORT_CLK_SEL_LCPLL_810:
683 link_clock = 81000;
684 break;
685 case PORT_CLK_SEL_LCPLL_1350:
686 link_clock = 135000;
687 break;
688 case PORT_CLK_SEL_LCPLL_2700:
689 link_clock = 270000;
690 break;
691 case PORT_CLK_SEL_WRPLL1:
692 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
693 break;
694 case PORT_CLK_SEL_WRPLL2:
695 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
696 break;
697 case PORT_CLK_SEL_SPLL:
698 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
699 if (pll == SPLL_PLL_FREQ_810MHz)
700 link_clock = 81000;
701 else if (pll == SPLL_PLL_FREQ_1350MHz)
702 link_clock = 135000;
703 else if (pll == SPLL_PLL_FREQ_2700MHz)
704 link_clock = 270000;
705 else {
706 WARN(1, "bad spll freq\n");
707 return;
708 }
709 break;
710 default:
711 WARN(1, "bad port clock sel\n");
712 return;
713 }
714
715 pipe_config->port_clock = link_clock * 2;
716
717 if (pipe_config->has_pch_encoder)
718 pipe_config->adjusted_mode.crtc_clock =
719 intel_dotclock_calculate(pipe_config->port_clock,
720 &pipe_config->fdi_m_n);
721 else if (pipe_config->has_dp_encoder)
722 pipe_config->adjusted_mode.crtc_clock =
723 intel_dotclock_calculate(pipe_config->port_clock,
724 &pipe_config->dp_m_n);
725 else
726 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
727 }
728
729 static void
730 intel_ddi_calculate_wrpll(int clock /* in Hz */,
731 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
732 {
733 uint64_t freq2k;
734 unsigned p, n2, r2;
735 struct wrpll_rnp best = { 0, 0, 0 };
736 unsigned budget;
737
738 freq2k = clock / 100;
739
740 budget = wrpll_get_budget_for_freq(clock);
741
742 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
743 * and directly pass the LC PLL to it. */
744 if (freq2k == 5400000) {
745 *n2_out = 2;
746 *p_out = 1;
747 *r2_out = 2;
748 return;
749 }
750
751 /*
752 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
753 * the WR PLL.
754 *
755 * We want R so that REF_MIN <= Ref <= REF_MAX.
756 * Injecting R2 = 2 * R gives:
757 * REF_MAX * r2 > LC_FREQ * 2 and
758 * REF_MIN * r2 < LC_FREQ * 2
759 *
760 * Which means the desired boundaries for r2 are:
761 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
762 *
763 */
764 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
765 r2 <= LC_FREQ * 2 / REF_MIN;
766 r2++) {
767
768 /*
769 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
770 *
771 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
772 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
773 * VCO_MAX * r2 > n2 * LC_FREQ and
774 * VCO_MIN * r2 < n2 * LC_FREQ)
775 *
776 * Which means the desired boundaries for n2 are:
777 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
778 */
779 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
780 n2 <= VCO_MAX * r2 / LC_FREQ;
781 n2++) {
782
783 for (p = P_MIN; p <= P_MAX; p += P_INC)
784 wrpll_update_rnp(freq2k, budget,
785 r2, n2, p, &best);
786 }
787 }
788
789 *n2_out = best.n2;
790 *p_out = best.p;
791 *r2_out = best.r2;
792 }
793
794 /*
795 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
796 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
797 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
798 * enable the PLL.
799 */
800 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
801 {
802 struct drm_crtc *crtc = &intel_crtc->base;
803 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
804 struct drm_encoder *encoder = &intel_encoder->base;
805 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
806 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
807 int type = intel_encoder->type;
808 enum pipe pipe = intel_crtc->pipe;
809 int clock = intel_crtc->config.port_clock;
810
811 intel_ddi_put_crtc_pll(crtc);
812
813 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
814 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
815
816 switch (intel_dp->link_bw) {
817 case DP_LINK_BW_1_62:
818 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
819 break;
820 case DP_LINK_BW_2_7:
821 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
822 break;
823 case DP_LINK_BW_5_4:
824 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
825 break;
826 default:
827 DRM_ERROR("Link bandwidth %d unsupported\n",
828 intel_dp->link_bw);
829 return false;
830 }
831
832 } else if (type == INTEL_OUTPUT_HDMI) {
833 uint32_t reg, val;
834 unsigned p, n2, r2;
835
836 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
837
838 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
839 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
840 WRPLL_DIVIDER_POST(p);
841
842 if (val == I915_READ(WRPLL_CTL1)) {
843 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
844 pipe_name(pipe));
845 reg = WRPLL_CTL1;
846 } else if (val == I915_READ(WRPLL_CTL2)) {
847 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
848 pipe_name(pipe));
849 reg = WRPLL_CTL2;
850 } else if (plls->wrpll1_refcount == 0) {
851 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
852 pipe_name(pipe));
853 reg = WRPLL_CTL1;
854 } else if (plls->wrpll2_refcount == 0) {
855 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
856 pipe_name(pipe));
857 reg = WRPLL_CTL2;
858 } else {
859 DRM_ERROR("No WRPLLs available!\n");
860 return false;
861 }
862
863 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
864 clock, p, n2, r2);
865
866 if (reg == WRPLL_CTL1) {
867 plls->wrpll1_refcount++;
868 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
869 } else {
870 plls->wrpll2_refcount++;
871 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
872 }
873
874 } else if (type == INTEL_OUTPUT_ANALOG) {
875 if (plls->spll_refcount == 0) {
876 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
877 pipe_name(pipe));
878 plls->spll_refcount++;
879 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
880 } else {
881 DRM_ERROR("SPLL already in use\n");
882 return false;
883 }
884
885 } else {
886 WARN(1, "Invalid DDI encoder type %d\n", type);
887 return false;
888 }
889
890 return true;
891 }
892
893 /*
894 * To be called after intel_ddi_pll_select(). That one selects the PLL to be
895 * used, this one actually enables the PLL.
896 */
897 void intel_ddi_pll_enable(struct intel_crtc *crtc)
898 {
899 struct drm_device *dev = crtc->base.dev;
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
902 int clock = crtc->config.port_clock;
903 uint32_t reg, cur_val, new_val;
904 int refcount;
905 const char *pll_name;
906 uint32_t enable_bit = (1 << 31);
907 unsigned int p, n2, r2;
908
909 BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
910 BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
911
912 switch (crtc->ddi_pll_sel) {
913 case PORT_CLK_SEL_LCPLL_2700:
914 case PORT_CLK_SEL_LCPLL_1350:
915 case PORT_CLK_SEL_LCPLL_810:
916 /*
917 * LCPLL should always be enabled at this point of the mode set
918 * sequence, so nothing to do.
919 */
920 return;
921
922 case PORT_CLK_SEL_SPLL:
923 pll_name = "SPLL";
924 reg = SPLL_CTL;
925 refcount = plls->spll_refcount;
926 new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
927 SPLL_PLL_SSC;
928 break;
929
930 case PORT_CLK_SEL_WRPLL1:
931 case PORT_CLK_SEL_WRPLL2:
932 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
933 pll_name = "WRPLL1";
934 reg = WRPLL_CTL1;
935 refcount = plls->wrpll1_refcount;
936 } else {
937 pll_name = "WRPLL2";
938 reg = WRPLL_CTL2;
939 refcount = plls->wrpll2_refcount;
940 }
941
942 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
943
944 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
945 WRPLL_DIVIDER_REFERENCE(r2) |
946 WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
947
948 break;
949
950 case PORT_CLK_SEL_NONE:
951 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
952 return;
953 default:
954 WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
955 return;
956 }
957
958 cur_val = I915_READ(reg);
959
960 WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
961 if (refcount == 1) {
962 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
963 I915_WRITE(reg, new_val);
964 POSTING_READ(reg);
965 udelay(20);
966 } else {
967 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
968 }
969 }
970
971 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
972 {
973 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
975 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
976 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
977 int type = intel_encoder->type;
978 uint32_t temp;
979
980 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
981
982 temp = TRANS_MSA_SYNC_CLK;
983 switch (intel_crtc->config.pipe_bpp) {
984 case 18:
985 temp |= TRANS_MSA_6_BPC;
986 break;
987 case 24:
988 temp |= TRANS_MSA_8_BPC;
989 break;
990 case 30:
991 temp |= TRANS_MSA_10_BPC;
992 break;
993 case 36:
994 temp |= TRANS_MSA_12_BPC;
995 break;
996 default:
997 BUG();
998 }
999 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1000 }
1001 }
1002
1003 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1004 {
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1007 struct drm_encoder *encoder = &intel_encoder->base;
1008 struct drm_device *dev = crtc->dev;
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 enum pipe pipe = intel_crtc->pipe;
1011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1012 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1013 int type = intel_encoder->type;
1014 uint32_t temp;
1015
1016 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1017 temp = TRANS_DDI_FUNC_ENABLE;
1018 temp |= TRANS_DDI_SELECT_PORT(port);
1019
1020 switch (intel_crtc->config.pipe_bpp) {
1021 case 18:
1022 temp |= TRANS_DDI_BPC_6;
1023 break;
1024 case 24:
1025 temp |= TRANS_DDI_BPC_8;
1026 break;
1027 case 30:
1028 temp |= TRANS_DDI_BPC_10;
1029 break;
1030 case 36:
1031 temp |= TRANS_DDI_BPC_12;
1032 break;
1033 default:
1034 BUG();
1035 }
1036
1037 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1038 temp |= TRANS_DDI_PVSYNC;
1039 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1040 temp |= TRANS_DDI_PHSYNC;
1041
1042 if (cpu_transcoder == TRANSCODER_EDP) {
1043 switch (pipe) {
1044 case PIPE_A:
1045 /* On Haswell, can only use the always-on power well for
1046 * eDP when not using the panel fitter, and when not
1047 * using motion blur mitigation (which we don't
1048 * support). */
1049 if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
1050 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1051 else
1052 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1053 break;
1054 case PIPE_B:
1055 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1056 break;
1057 case PIPE_C:
1058 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1059 break;
1060 default:
1061 BUG();
1062 break;
1063 }
1064 }
1065
1066 if (type == INTEL_OUTPUT_HDMI) {
1067 if (intel_crtc->config.has_hdmi_sink)
1068 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1069 else
1070 temp |= TRANS_DDI_MODE_SELECT_DVI;
1071
1072 } else if (type == INTEL_OUTPUT_ANALOG) {
1073 temp |= TRANS_DDI_MODE_SELECT_FDI;
1074 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1075
1076 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1077 type == INTEL_OUTPUT_EDP) {
1078 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1079
1080 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1081
1082 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1083 } else {
1084 WARN(1, "Invalid encoder type %d for pipe %c\n",
1085 intel_encoder->type, pipe_name(pipe));
1086 }
1087
1088 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1089 }
1090
1091 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1092 enum transcoder cpu_transcoder)
1093 {
1094 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1095 uint32_t val = I915_READ(reg);
1096
1097 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1098 val |= TRANS_DDI_PORT_NONE;
1099 I915_WRITE(reg, val);
1100 }
1101
1102 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1103 {
1104 struct drm_device *dev = intel_connector->base.dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 struct intel_encoder *intel_encoder = intel_connector->encoder;
1107 int type = intel_connector->base.connector_type;
1108 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1109 enum pipe pipe = 0;
1110 enum transcoder cpu_transcoder;
1111 enum intel_display_power_domain power_domain;
1112 uint32_t tmp;
1113
1114 power_domain = intel_display_port_power_domain(intel_encoder);
1115 if (!intel_display_power_enabled(dev_priv, power_domain))
1116 return false;
1117
1118 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1119 return false;
1120
1121 if (port == PORT_A)
1122 cpu_transcoder = TRANSCODER_EDP;
1123 else
1124 cpu_transcoder = (enum transcoder) pipe;
1125
1126 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1127
1128 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1129 case TRANS_DDI_MODE_SELECT_HDMI:
1130 case TRANS_DDI_MODE_SELECT_DVI:
1131 return (type == DRM_MODE_CONNECTOR_HDMIA);
1132
1133 case TRANS_DDI_MODE_SELECT_DP_SST:
1134 if (type == DRM_MODE_CONNECTOR_eDP)
1135 return true;
1136 case TRANS_DDI_MODE_SELECT_DP_MST:
1137 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1138
1139 case TRANS_DDI_MODE_SELECT_FDI:
1140 return (type == DRM_MODE_CONNECTOR_VGA);
1141
1142 default:
1143 return false;
1144 }
1145 }
1146
1147 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1148 enum pipe *pipe)
1149 {
1150 struct drm_device *dev = encoder->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 enum port port = intel_ddi_get_encoder_port(encoder);
1153 enum intel_display_power_domain power_domain;
1154 u32 tmp;
1155 int i;
1156
1157 power_domain = intel_display_port_power_domain(encoder);
1158 if (!intel_display_power_enabled(dev_priv, power_domain))
1159 return false;
1160
1161 tmp = I915_READ(DDI_BUF_CTL(port));
1162
1163 if (!(tmp & DDI_BUF_CTL_ENABLE))
1164 return false;
1165
1166 if (port == PORT_A) {
1167 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1168
1169 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1170 case TRANS_DDI_EDP_INPUT_A_ON:
1171 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1172 *pipe = PIPE_A;
1173 break;
1174 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1175 *pipe = PIPE_B;
1176 break;
1177 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1178 *pipe = PIPE_C;
1179 break;
1180 }
1181
1182 return true;
1183 } else {
1184 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1185 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1186
1187 if ((tmp & TRANS_DDI_PORT_MASK)
1188 == TRANS_DDI_SELECT_PORT(port)) {
1189 *pipe = i;
1190 return true;
1191 }
1192 }
1193 }
1194
1195 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1196
1197 return false;
1198 }
1199
1200 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202 {
1203 uint32_t temp, ret;
1204 enum port port = I915_MAX_PORTS;
1205 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1206 pipe);
1207 int i;
1208
1209 if (cpu_transcoder == TRANSCODER_EDP) {
1210 port = PORT_A;
1211 } else {
1212 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1213 temp &= TRANS_DDI_PORT_MASK;
1214
1215 for (i = PORT_B; i <= PORT_E; i++)
1216 if (temp == TRANS_DDI_SELECT_PORT(i))
1217 port = i;
1218 }
1219
1220 if (port == I915_MAX_PORTS) {
1221 WARN(1, "Pipe %c enabled on an unknown port\n",
1222 pipe_name(pipe));
1223 ret = PORT_CLK_SEL_NONE;
1224 } else {
1225 ret = I915_READ(PORT_CLK_SEL(port));
1226 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1227 "0x%08x\n", pipe_name(pipe), port_name(port),
1228 ret);
1229 }
1230
1231 return ret;
1232 }
1233
1234 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1235 {
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 enum pipe pipe;
1238 struct intel_crtc *intel_crtc;
1239
1240 dev_priv->ddi_plls.spll_refcount = 0;
1241 dev_priv->ddi_plls.wrpll1_refcount = 0;
1242 dev_priv->ddi_plls.wrpll2_refcount = 0;
1243
1244 for_each_pipe(pipe) {
1245 intel_crtc =
1246 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1247
1248 if (!intel_crtc->active) {
1249 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
1250 continue;
1251 }
1252
1253 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1254 pipe);
1255
1256 switch (intel_crtc->ddi_pll_sel) {
1257 case PORT_CLK_SEL_SPLL:
1258 dev_priv->ddi_plls.spll_refcount++;
1259 break;
1260 case PORT_CLK_SEL_WRPLL1:
1261 dev_priv->ddi_plls.wrpll1_refcount++;
1262 break;
1263 case PORT_CLK_SEL_WRPLL2:
1264 dev_priv->ddi_plls.wrpll2_refcount++;
1265 break;
1266 }
1267 }
1268 }
1269
1270 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1271 {
1272 struct drm_crtc *crtc = &intel_crtc->base;
1273 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1274 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1275 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1276 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1277
1278 if (cpu_transcoder != TRANSCODER_EDP)
1279 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1280 TRANS_CLK_SEL_PORT(port));
1281 }
1282
1283 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1284 {
1285 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1286 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1287
1288 if (cpu_transcoder != TRANSCODER_EDP)
1289 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1290 TRANS_CLK_SEL_DISABLED);
1291 }
1292
1293 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1294 {
1295 struct drm_encoder *encoder = &intel_encoder->base;
1296 struct drm_crtc *crtc = encoder->crtc;
1297 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1299 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1300 int type = intel_encoder->type;
1301
1302 if (type == INTEL_OUTPUT_EDP) {
1303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1304 intel_edp_panel_on(intel_dp);
1305 }
1306
1307 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1308 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1309
1310 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1311 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1312
1313 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1314 intel_dp_start_link_train(intel_dp);
1315 intel_dp_complete_link_train(intel_dp);
1316 if (port != PORT_A)
1317 intel_dp_stop_link_train(intel_dp);
1318 }
1319 }
1320
1321 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1322 {
1323 struct drm_encoder *encoder = &intel_encoder->base;
1324 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1325 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1326 int type = intel_encoder->type;
1327 uint32_t val;
1328 bool wait = false;
1329
1330 val = I915_READ(DDI_BUF_CTL(port));
1331 if (val & DDI_BUF_CTL_ENABLE) {
1332 val &= ~DDI_BUF_CTL_ENABLE;
1333 I915_WRITE(DDI_BUF_CTL(port), val);
1334 wait = true;
1335 }
1336
1337 val = I915_READ(DP_TP_CTL(port));
1338 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1339 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1340 I915_WRITE(DP_TP_CTL(port), val);
1341
1342 if (wait)
1343 intel_wait_ddi_buf_idle(dev_priv, port);
1344
1345 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1346 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1347 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1348 intel_edp_panel_vdd_on(intel_dp);
1349 intel_edp_panel_off(intel_dp);
1350 }
1351
1352 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1353 }
1354
1355 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1356 {
1357 struct drm_encoder *encoder = &intel_encoder->base;
1358 struct drm_crtc *crtc = encoder->crtc;
1359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1360 int pipe = intel_crtc->pipe;
1361 struct drm_device *dev = encoder->dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1364 int type = intel_encoder->type;
1365 uint32_t tmp;
1366
1367 if (type == INTEL_OUTPUT_HDMI) {
1368 struct intel_digital_port *intel_dig_port =
1369 enc_to_dig_port(encoder);
1370
1371 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1372 * are ignored so nothing special needs to be done besides
1373 * enabling the port.
1374 */
1375 I915_WRITE(DDI_BUF_CTL(port),
1376 intel_dig_port->saved_port_bits |
1377 DDI_BUF_CTL_ENABLE);
1378 } else if (type == INTEL_OUTPUT_EDP) {
1379 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1380
1381 if (port == PORT_A)
1382 intel_dp_stop_link_train(intel_dp);
1383
1384 intel_edp_backlight_on(intel_dp);
1385 intel_edp_psr_enable(intel_dp);
1386 }
1387
1388 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1389 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1390 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1391 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1392 }
1393 }
1394
1395 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1396 {
1397 struct drm_encoder *encoder = &intel_encoder->base;
1398 struct drm_crtc *crtc = encoder->crtc;
1399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1400 int pipe = intel_crtc->pipe;
1401 int type = intel_encoder->type;
1402 struct drm_device *dev = encoder->dev;
1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404 uint32_t tmp;
1405
1406 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1407 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1408 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1409 (pipe * 4));
1410 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1411 }
1412
1413 if (type == INTEL_OUTPUT_EDP) {
1414 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1415
1416 intel_edp_psr_disable(intel_dp);
1417 intel_edp_backlight_off(intel_dp);
1418 }
1419 }
1420
1421 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1422 {
1423 struct drm_device *dev = dev_priv->dev;
1424 uint32_t lcpll = I915_READ(LCPLL_CTL);
1425 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1426
1427 if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1428 return 800000;
1429 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1430 return 450000;
1431 } else if (freq == LCPLL_CLK_FREQ_450) {
1432 return 450000;
1433 } else if (IS_HASWELL(dev)) {
1434 if (IS_ULT(dev))
1435 return 337500;
1436 else
1437 return 540000;
1438 } else {
1439 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1440 return 540000;
1441 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1442 return 337500;
1443 else
1444 return 675000;
1445 }
1446 }
1447
1448 void intel_ddi_pll_init(struct drm_device *dev)
1449 {
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 uint32_t val = I915_READ(LCPLL_CTL);
1452
1453 /* The LCPLL register should be turned on by the BIOS. For now let's
1454 * just check its state and print errors in case something is wrong.
1455 * Don't even try to turn it on.
1456 */
1457
1458 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1459 intel_ddi_get_cdclk_freq(dev_priv));
1460
1461 if (val & LCPLL_CD_SOURCE_FCLK)
1462 DRM_ERROR("CDCLK source is not LCPLL\n");
1463
1464 if (val & LCPLL_PLL_DISABLE)
1465 DRM_ERROR("LCPLL is disabled\n");
1466 }
1467
1468 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1469 {
1470 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1471 struct intel_dp *intel_dp = &intel_dig_port->dp;
1472 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1473 enum port port = intel_dig_port->port;
1474 uint32_t val;
1475 bool wait = false;
1476
1477 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1478 val = I915_READ(DDI_BUF_CTL(port));
1479 if (val & DDI_BUF_CTL_ENABLE) {
1480 val &= ~DDI_BUF_CTL_ENABLE;
1481 I915_WRITE(DDI_BUF_CTL(port), val);
1482 wait = true;
1483 }
1484
1485 val = I915_READ(DP_TP_CTL(port));
1486 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1487 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1488 I915_WRITE(DP_TP_CTL(port), val);
1489 POSTING_READ(DP_TP_CTL(port));
1490
1491 if (wait)
1492 intel_wait_ddi_buf_idle(dev_priv, port);
1493 }
1494
1495 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1496 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1497 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1498 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1499 I915_WRITE(DP_TP_CTL(port), val);
1500 POSTING_READ(DP_TP_CTL(port));
1501
1502 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1503 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1504 POSTING_READ(DDI_BUF_CTL(port));
1505
1506 udelay(600);
1507 }
1508
1509 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1510 {
1511 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1512 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1513 uint32_t val;
1514
1515 intel_ddi_post_disable(intel_encoder);
1516
1517 val = I915_READ(_FDI_RXA_CTL);
1518 val &= ~FDI_RX_ENABLE;
1519 I915_WRITE(_FDI_RXA_CTL, val);
1520
1521 val = I915_READ(_FDI_RXA_MISC);
1522 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1523 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1524 I915_WRITE(_FDI_RXA_MISC, val);
1525
1526 val = I915_READ(_FDI_RXA_CTL);
1527 val &= ~FDI_PCDCLK;
1528 I915_WRITE(_FDI_RXA_CTL, val);
1529
1530 val = I915_READ(_FDI_RXA_CTL);
1531 val &= ~FDI_RX_PLL_ENABLE;
1532 I915_WRITE(_FDI_RXA_CTL, val);
1533 }
1534
1535 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1536 {
1537 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1538 int type = intel_encoder->type;
1539
1540 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1541 intel_dp_check_link_status(intel_dp);
1542 }
1543
1544 void intel_ddi_get_config(struct intel_encoder *encoder,
1545 struct intel_crtc_config *pipe_config)
1546 {
1547 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1548 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1549 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1550 u32 temp, flags = 0;
1551
1552 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1553 if (temp & TRANS_DDI_PHSYNC)
1554 flags |= DRM_MODE_FLAG_PHSYNC;
1555 else
1556 flags |= DRM_MODE_FLAG_NHSYNC;
1557 if (temp & TRANS_DDI_PVSYNC)
1558 flags |= DRM_MODE_FLAG_PVSYNC;
1559 else
1560 flags |= DRM_MODE_FLAG_NVSYNC;
1561
1562 pipe_config->adjusted_mode.flags |= flags;
1563
1564 switch (temp & TRANS_DDI_BPC_MASK) {
1565 case TRANS_DDI_BPC_6:
1566 pipe_config->pipe_bpp = 18;
1567 break;
1568 case TRANS_DDI_BPC_8:
1569 pipe_config->pipe_bpp = 24;
1570 break;
1571 case TRANS_DDI_BPC_10:
1572 pipe_config->pipe_bpp = 30;
1573 break;
1574 case TRANS_DDI_BPC_12:
1575 pipe_config->pipe_bpp = 36;
1576 break;
1577 default:
1578 break;
1579 }
1580
1581 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1582 case TRANS_DDI_MODE_SELECT_HDMI:
1583 pipe_config->has_hdmi_sink = true;
1584 case TRANS_DDI_MODE_SELECT_DVI:
1585 case TRANS_DDI_MODE_SELECT_FDI:
1586 break;
1587 case TRANS_DDI_MODE_SELECT_DP_SST:
1588 case TRANS_DDI_MODE_SELECT_DP_MST:
1589 pipe_config->has_dp_encoder = true;
1590 intel_dp_get_m_n(intel_crtc, pipe_config);
1591 break;
1592 default:
1593 break;
1594 }
1595
1596 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1597 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1598 /*
1599 * This is a big fat ugly hack.
1600 *
1601 * Some machines in UEFI boot mode provide us a VBT that has 18
1602 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1603 * unknown we fail to light up. Yet the same BIOS boots up with
1604 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1605 * max, not what it tells us to use.
1606 *
1607 * Note: This will still be broken if the eDP panel is not lit
1608 * up by the BIOS, and thus we can't get the mode at module
1609 * load.
1610 */
1611 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1612 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1613 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1614 }
1615
1616 intel_ddi_clock_get(encoder, pipe_config);
1617 }
1618
1619 static void intel_ddi_destroy(struct drm_encoder *encoder)
1620 {
1621 /* HDMI has nothing special to destroy, so we can go with this. */
1622 intel_dp_encoder_destroy(encoder);
1623 }
1624
1625 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1626 struct intel_crtc_config *pipe_config)
1627 {
1628 int type = encoder->type;
1629 int port = intel_ddi_get_encoder_port(encoder);
1630
1631 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1632
1633 if (port == PORT_A)
1634 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1635
1636 if (type == INTEL_OUTPUT_HDMI)
1637 return intel_hdmi_compute_config(encoder, pipe_config);
1638 else
1639 return intel_dp_compute_config(encoder, pipe_config);
1640 }
1641
1642 static const struct drm_encoder_funcs intel_ddi_funcs = {
1643 .destroy = intel_ddi_destroy,
1644 };
1645
1646 static struct intel_connector *
1647 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1648 {
1649 struct intel_connector *connector;
1650 enum port port = intel_dig_port->port;
1651
1652 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1653 if (!connector)
1654 return NULL;
1655
1656 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1657 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1658 kfree(connector);
1659 return NULL;
1660 }
1661
1662 return connector;
1663 }
1664
1665 static struct intel_connector *
1666 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1667 {
1668 struct intel_connector *connector;
1669 enum port port = intel_dig_port->port;
1670
1671 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1672 if (!connector)
1673 return NULL;
1674
1675 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1676 intel_hdmi_init_connector(intel_dig_port, connector);
1677
1678 return connector;
1679 }
1680
1681 void intel_ddi_init(struct drm_device *dev, enum port port)
1682 {
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684 struct intel_digital_port *intel_dig_port;
1685 struct intel_encoder *intel_encoder;
1686 struct drm_encoder *encoder;
1687 struct intel_connector *hdmi_connector = NULL;
1688 struct intel_connector *dp_connector = NULL;
1689 bool init_hdmi, init_dp;
1690
1691 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1692 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1693 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1694 if (!init_dp && !init_hdmi) {
1695 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1696 port_name(port));
1697 init_hdmi = true;
1698 init_dp = true;
1699 }
1700
1701 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1702 if (!intel_dig_port)
1703 return;
1704
1705 intel_encoder = &intel_dig_port->base;
1706 encoder = &intel_encoder->base;
1707
1708 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1709 DRM_MODE_ENCODER_TMDS);
1710
1711 intel_encoder->compute_config = intel_ddi_compute_config;
1712 intel_encoder->mode_set = intel_ddi_mode_set;
1713 intel_encoder->enable = intel_enable_ddi;
1714 intel_encoder->pre_enable = intel_ddi_pre_enable;
1715 intel_encoder->disable = intel_disable_ddi;
1716 intel_encoder->post_disable = intel_ddi_post_disable;
1717 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1718 intel_encoder->get_config = intel_ddi_get_config;
1719
1720 intel_dig_port->port = port;
1721 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1722 (DDI_BUF_PORT_REVERSAL |
1723 DDI_A_4_LANES);
1724
1725 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1726 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1727 intel_encoder->cloneable = 0;
1728 intel_encoder->hot_plug = intel_ddi_hot_plug;
1729
1730 if (init_dp)
1731 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
1732
1733 /* In theory we don't need the encoder->type check, but leave it just in
1734 * case we have some really bad VBTs... */
1735 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1736 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
1737
1738 if (!dp_connector && !hdmi_connector) {
1739 drm_encoder_cleanup(encoder);
1740 kfree(intel_dig_port);
1741 }
1742 }
Linux kernel - Deliverables
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