2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 const u32
*ddi_translations
= ((use_fdi_mode
) ?
94 hsw_ddi_translations_fdi
:
95 hsw_ddi_translations_dp
);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode
? "FDI" : "DP");
101 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
106 I915_WRITE(reg
, ddi_translations
[i
]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device
*dev
)
121 for (port
= PORT_A
; port
< PORT_E
; port
++)
122 intel_prepare_ddi_buffers(dev
, port
, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
131 static const long hsw_ddi_buf_ctl_values
[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW
,
133 DDI_BUF_EMP_400MV_3_5DB_HSW
,
134 DDI_BUF_EMP_400MV_6DB_HSW
,
135 DDI_BUF_EMP_400MV_9_5DB_HSW
,
136 DDI_BUF_EMP_600MV_0DB_HSW
,
137 DDI_BUF_EMP_600MV_3_5DB_HSW
,
138 DDI_BUF_EMP_600MV_6DB_HSW
,
139 DDI_BUF_EMP_800MV_0DB_HSW
,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
146 uint32_t reg
= DDI_BUF_CTL(port
);
149 for (i
= 0; i
< 8; i
++) {
151 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
168 struct drm_device
*dev
= crtc
->dev
;
169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
171 u32 temp
, i
, rx_ctl_val
;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 * WaFDIAutoLinkSetTimingOverrride:hsw
180 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
181 FDI_RX_PWRDN_LANE0_VAL(2) |
182 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
184 /* Enable the PCH Receiver FDI PLL */
185 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
187 FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
188 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
189 POSTING_READ(_FDI_RXA_CTL
);
192 /* Switch from Rawclk to PCDclk */
193 rx_ctl_val
|= FDI_PCDCLK
;
194 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
196 /* Configure Port Clock Select */
197 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
199 /* Start the training iterating through available voltages and emphasis,
200 * testing each value twice. */
201 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
202 /* Configure DP_TP_CTL with auto-training */
203 I915_WRITE(DP_TP_CTL(PORT_E
),
204 DP_TP_CTL_FDI_AUTOTRAIN
|
205 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
206 DP_TP_CTL_LINK_TRAIN_PAT1
|
209 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
210 * DDI E does not support port reversal, the functionality is
211 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
212 * port reversal bit */
213 I915_WRITE(DDI_BUF_CTL(PORT_E
),
215 ((intel_crtc
->config
.fdi_lanes
- 1) << 1) |
216 hsw_ddi_buf_ctl_values
[i
/ 2]);
217 POSTING_READ(DDI_BUF_CTL(PORT_E
));
221 /* Program PCH FDI Receiver TU */
222 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
224 /* Enable PCH FDI Receiver with auto-training */
225 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
226 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
227 POSTING_READ(_FDI_RXA_CTL
);
229 /* Wait for FDI receiver lane calibration */
232 /* Unset FDI_RX_MISC pwrdn lanes */
233 temp
= I915_READ(_FDI_RXA_MISC
);
234 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
235 I915_WRITE(_FDI_RXA_MISC
, temp
);
236 POSTING_READ(_FDI_RXA_MISC
);
238 /* Wait for FDI auto training time */
241 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
242 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
243 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
245 /* Enable normal pixel sending for FDI */
246 I915_WRITE(DP_TP_CTL(PORT_E
),
247 DP_TP_CTL_FDI_AUTOTRAIN
|
248 DP_TP_CTL_LINK_TRAIN_NORMAL
|
249 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
255 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
256 temp
&= ~DDI_BUF_CTL_ENABLE
;
257 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
258 POSTING_READ(DDI_BUF_CTL(PORT_E
));
260 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
261 temp
= I915_READ(DP_TP_CTL(PORT_E
));
262 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
263 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
264 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
265 POSTING_READ(DP_TP_CTL(PORT_E
));
267 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
269 rx_ctl_val
&= ~FDI_RX_ENABLE
;
270 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
271 POSTING_READ(_FDI_RXA_CTL
);
273 /* Reset FDI_RX_MISC pwrdn lanes */
274 temp
= I915_READ(_FDI_RXA_MISC
);
275 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
276 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
277 I915_WRITE(_FDI_RXA_MISC
, temp
);
278 POSTING_READ(_FDI_RXA_MISC
);
281 DRM_ERROR("FDI link training failed!\n");
284 static void intel_ddi_mode_set(struct drm_encoder
*encoder
,
285 struct drm_display_mode
*mode
,
286 struct drm_display_mode
*adjusted_mode
)
288 struct drm_crtc
*crtc
= encoder
->crtc
;
289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
290 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
291 int port
= intel_ddi_get_encoder_port(intel_encoder
);
292 int pipe
= intel_crtc
->pipe
;
293 int type
= intel_encoder
->type
;
295 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
296 port_name(port
), pipe_name(pipe
));
298 intel_crtc
->eld_vld
= false;
299 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
300 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
301 struct intel_digital_port
*intel_dig_port
=
302 enc_to_dig_port(encoder
);
304 intel_dp
->DP
= intel_dig_port
->port_reversal
|
305 DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
306 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
308 if (intel_dp
->has_audio
) {
309 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
310 pipe_name(intel_crtc
->pipe
));
313 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
314 intel_write_eld(encoder
, adjusted_mode
);
317 intel_dp_init_link_config(intel_dp
);
319 } else if (type
== INTEL_OUTPUT_HDMI
) {
320 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
322 if (intel_hdmi
->has_audio
) {
323 /* Proper support for digital audio needs a new logic
324 * and a new set of registers, so we leave it for future
327 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
328 pipe_name(intel_crtc
->pipe
));
331 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
332 intel_write_eld(encoder
, adjusted_mode
);
335 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
339 static struct intel_encoder
*
340 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
342 struct drm_device
*dev
= crtc
->dev
;
343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
344 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
345 int num_encoders
= 0;
347 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
352 if (num_encoders
!= 1)
353 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
354 pipe_name(intel_crtc
->pipe
));
360 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
362 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
363 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
364 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
367 switch (intel_crtc
->ddi_pll_sel
) {
368 case PORT_CLK_SEL_SPLL
:
369 plls
->spll_refcount
--;
370 if (plls
->spll_refcount
== 0) {
371 DRM_DEBUG_KMS("Disabling SPLL\n");
372 val
= I915_READ(SPLL_CTL
);
373 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
374 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
375 POSTING_READ(SPLL_CTL
);
378 case PORT_CLK_SEL_WRPLL1
:
379 plls
->wrpll1_refcount
--;
380 if (plls
->wrpll1_refcount
== 0) {
381 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
382 val
= I915_READ(WRPLL_CTL1
);
383 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
384 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
385 POSTING_READ(WRPLL_CTL1
);
388 case PORT_CLK_SEL_WRPLL2
:
389 plls
->wrpll2_refcount
--;
390 if (plls
->wrpll2_refcount
== 0) {
391 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
392 val
= I915_READ(WRPLL_CTL2
);
393 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
394 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
395 POSTING_READ(WRPLL_CTL2
);
400 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
401 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
402 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
404 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
408 #define LC_FREQ_2K (LC_FREQ * 2000)
414 /* Constraints for PLL good behavior */
420 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
426 static unsigned wrpll_get_budget_for_freq(int clock
)
500 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
501 unsigned r2
, unsigned n2
, unsigned p
,
502 struct wrpll_rnp
*best
)
504 uint64_t a
, b
, c
, d
, diff
, diff_best
;
506 /* No best (r,n,p) yet */
515 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
519 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
522 * and we would like delta <= budget.
524 * If the discrepancy is above the PPM-based budget, always prefer to
525 * improve upon the previous solution. However, if you're within the
526 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
528 a
= freq2k
* budget
* p
* r2
;
529 b
= freq2k
* budget
* best
->p
* best
->r2
;
530 diff
= ABS_DIFF((freq2k
* p
* r2
), (LC_FREQ_2K
* n2
));
531 diff_best
= ABS_DIFF((freq2k
* best
->p
* best
->r2
),
532 (LC_FREQ_2K
* best
->n2
));
534 d
= 1000000 * diff_best
;
536 if (a
< c
&& b
< d
) {
537 /* If both are above the budget, pick the closer */
538 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
543 } else if (a
>= c
&& b
< d
) {
544 /* If A is below the threshold but B is above it? Update. */
548 } else if (a
>= c
&& b
>= d
) {
549 /* Both are below the limit, so pick the higher n2/(r2*r2) */
550 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
556 /* Otherwise a < c && b >= d, do nothing */
560 intel_ddi_calculate_wrpll(int clock
/* in Hz */,
561 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
565 struct wrpll_rnp best
= { 0, 0, 0 };
568 freq2k
= clock
/ 100;
570 budget
= wrpll_get_budget_for_freq(clock
);
572 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
573 * and directly pass the LC PLL to it. */
574 if (freq2k
== 5400000) {
582 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
585 * We want R so that REF_MIN <= Ref <= REF_MAX.
586 * Injecting R2 = 2 * R gives:
587 * REF_MAX * r2 > LC_FREQ * 2 and
588 * REF_MIN * r2 < LC_FREQ * 2
590 * Which means the desired boundaries for r2 are:
591 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
594 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
595 r2
<= LC_FREQ
* 2 / REF_MIN
;
599 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
601 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
602 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
603 * VCO_MAX * r2 > n2 * LC_FREQ and
604 * VCO_MIN * r2 < n2 * LC_FREQ)
606 * Which means the desired boundaries for n2 are:
607 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
609 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
610 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
613 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
614 wrpll_update_rnp(freq2k
, budget
,
623 DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
624 clock
, *p_out
, *n2_out
, *r2_out
);
627 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
629 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
630 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
631 struct drm_encoder
*encoder
= &intel_encoder
->base
;
632 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
633 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
634 int type
= intel_encoder
->type
;
635 enum pipe pipe
= intel_crtc
->pipe
;
638 /* TODO: reuse PLLs when possible (compare values) */
640 intel_ddi_put_crtc_pll(crtc
);
642 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
643 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
645 switch (intel_dp
->link_bw
) {
646 case DP_LINK_BW_1_62
:
647 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
650 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
653 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
656 DRM_ERROR("Link bandwidth %d unsupported\n",
661 /* We don't need to turn any PLL on because we'll use LCPLL. */
664 } else if (type
== INTEL_OUTPUT_HDMI
) {
667 if (plls
->wrpll1_refcount
== 0) {
668 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
670 plls
->wrpll1_refcount
++;
672 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
673 } else if (plls
->wrpll2_refcount
== 0) {
674 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
676 plls
->wrpll2_refcount
++;
678 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
680 DRM_ERROR("No WRPLLs available!\n");
684 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
685 "WRPLL already enabled\n");
687 intel_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
689 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
690 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
691 WRPLL_DIVIDER_POST(p
);
693 } else if (type
== INTEL_OUTPUT_ANALOG
) {
694 if (plls
->spll_refcount
== 0) {
695 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
697 plls
->spll_refcount
++;
699 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
701 DRM_ERROR("SPLL already in use\n");
705 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
706 "SPLL already enabled\n");
708 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
711 WARN(1, "Invalid DDI encoder type %d\n", type
);
715 I915_WRITE(reg
, val
);
721 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
723 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
724 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
725 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
726 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
727 int type
= intel_encoder
->type
;
730 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
732 temp
= TRANS_MSA_SYNC_CLK
;
733 switch (intel_crtc
->config
.pipe_bpp
) {
735 temp
|= TRANS_MSA_6_BPC
;
738 temp
|= TRANS_MSA_8_BPC
;
741 temp
|= TRANS_MSA_10_BPC
;
744 temp
|= TRANS_MSA_12_BPC
;
749 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
753 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
755 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
756 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
757 struct drm_encoder
*encoder
= &intel_encoder
->base
;
758 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
759 enum pipe pipe
= intel_crtc
->pipe
;
760 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
761 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
762 int type
= intel_encoder
->type
;
765 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
766 temp
= TRANS_DDI_FUNC_ENABLE
;
767 temp
|= TRANS_DDI_SELECT_PORT(port
);
769 switch (intel_crtc
->config
.pipe_bpp
) {
771 temp
|= TRANS_DDI_BPC_6
;
774 temp
|= TRANS_DDI_BPC_8
;
777 temp
|= TRANS_DDI_BPC_10
;
780 temp
|= TRANS_DDI_BPC_12
;
786 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
787 temp
|= TRANS_DDI_PVSYNC
;
788 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
789 temp
|= TRANS_DDI_PHSYNC
;
791 if (cpu_transcoder
== TRANSCODER_EDP
) {
794 /* Can only use the always-on power well for eDP when
795 * not using the panel fitter, and when not using motion
796 * blur mitigation (which we don't support). */
797 if (intel_crtc
->config
.pch_pfit
.size
)
798 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
800 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
803 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
806 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
814 if (type
== INTEL_OUTPUT_HDMI
) {
815 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
817 if (intel_hdmi
->has_hdmi_sink
)
818 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
820 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
822 } else if (type
== INTEL_OUTPUT_ANALOG
) {
823 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
824 temp
|= (intel_crtc
->config
.fdi_lanes
- 1) << 1;
826 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
827 type
== INTEL_OUTPUT_EDP
) {
828 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
830 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
832 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
834 WARN(1, "Invalid encoder type %d for pipe %c\n",
835 intel_encoder
->type
, pipe_name(pipe
));
838 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
841 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
842 enum transcoder cpu_transcoder
)
844 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
845 uint32_t val
= I915_READ(reg
);
847 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
848 val
|= TRANS_DDI_PORT_NONE
;
849 I915_WRITE(reg
, val
);
852 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
854 struct drm_device
*dev
= intel_connector
->base
.dev
;
855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
856 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
857 int type
= intel_connector
->base
.connector_type
;
858 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
860 enum transcoder cpu_transcoder
;
863 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
867 cpu_transcoder
= TRANSCODER_EDP
;
869 cpu_transcoder
= (enum transcoder
) pipe
;
871 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
873 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
874 case TRANS_DDI_MODE_SELECT_HDMI
:
875 case TRANS_DDI_MODE_SELECT_DVI
:
876 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
878 case TRANS_DDI_MODE_SELECT_DP_SST
:
879 if (type
== DRM_MODE_CONNECTOR_eDP
)
881 case TRANS_DDI_MODE_SELECT_DP_MST
:
882 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
884 case TRANS_DDI_MODE_SELECT_FDI
:
885 return (type
== DRM_MODE_CONNECTOR_VGA
);
892 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
895 struct drm_device
*dev
= encoder
->base
.dev
;
896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
897 enum port port
= intel_ddi_get_encoder_port(encoder
);
901 tmp
= I915_READ(DDI_BUF_CTL(port
));
903 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
906 if (port
== PORT_A
) {
907 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
909 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
910 case TRANS_DDI_EDP_INPUT_A_ON
:
911 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
914 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
917 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
924 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
925 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
927 if ((tmp
& TRANS_DDI_PORT_MASK
)
928 == TRANS_DDI_SELECT_PORT(port
)) {
935 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
940 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
944 enum port port
= I915_MAX_PORTS
;
945 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
949 if (cpu_transcoder
== TRANSCODER_EDP
) {
952 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
953 temp
&= TRANS_DDI_PORT_MASK
;
955 for (i
= PORT_B
; i
<= PORT_E
; i
++)
956 if (temp
== TRANS_DDI_SELECT_PORT(i
))
960 if (port
== I915_MAX_PORTS
) {
961 WARN(1, "Pipe %c enabled on an unknown port\n",
963 ret
= PORT_CLK_SEL_NONE
;
965 ret
= I915_READ(PORT_CLK_SEL(port
));
966 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
967 "0x%08x\n", pipe_name(pipe
), port_name(port
),
974 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
978 struct intel_crtc
*intel_crtc
;
980 for_each_pipe(pipe
) {
982 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
984 if (!intel_crtc
->active
)
987 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
990 switch (intel_crtc
->ddi_pll_sel
) {
991 case PORT_CLK_SEL_SPLL
:
992 dev_priv
->ddi_plls
.spll_refcount
++;
994 case PORT_CLK_SEL_WRPLL1
:
995 dev_priv
->ddi_plls
.wrpll1_refcount
++;
997 case PORT_CLK_SEL_WRPLL2
:
998 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1004 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1006 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1007 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1008 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1009 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1010 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1012 if (cpu_transcoder
!= TRANSCODER_EDP
)
1013 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1014 TRANS_CLK_SEL_PORT(port
));
1017 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1019 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1020 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1022 if (cpu_transcoder
!= TRANSCODER_EDP
)
1023 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1024 TRANS_CLK_SEL_DISABLED
);
1027 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1029 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1030 struct drm_crtc
*crtc
= encoder
->crtc
;
1031 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1032 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1033 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1034 int type
= intel_encoder
->type
;
1036 if (type
== INTEL_OUTPUT_EDP
) {
1037 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1038 ironlake_edp_panel_vdd_on(intel_dp
);
1039 ironlake_edp_panel_on(intel_dp
);
1040 ironlake_edp_panel_vdd_off(intel_dp
, true);
1043 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1044 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1046 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1047 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1049 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1050 intel_dp_start_link_train(intel_dp
);
1051 intel_dp_complete_link_train(intel_dp
);
1053 intel_dp_stop_link_train(intel_dp
);
1057 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1059 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1060 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1061 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1062 int type
= intel_encoder
->type
;
1066 val
= I915_READ(DDI_BUF_CTL(port
));
1067 if (val
& DDI_BUF_CTL_ENABLE
) {
1068 val
&= ~DDI_BUF_CTL_ENABLE
;
1069 I915_WRITE(DDI_BUF_CTL(port
), val
);
1073 val
= I915_READ(DP_TP_CTL(port
));
1074 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1075 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1076 I915_WRITE(DP_TP_CTL(port
), val
);
1079 intel_wait_ddi_buf_idle(dev_priv
, port
);
1081 if (type
== INTEL_OUTPUT_EDP
) {
1082 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1083 ironlake_edp_panel_vdd_on(intel_dp
);
1084 ironlake_edp_panel_off(intel_dp
);
1087 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1090 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1092 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1093 struct drm_crtc
*crtc
= encoder
->crtc
;
1094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1095 int pipe
= intel_crtc
->pipe
;
1096 struct drm_device
*dev
= encoder
->dev
;
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1099 int type
= intel_encoder
->type
;
1102 if (type
== INTEL_OUTPUT_HDMI
) {
1103 struct intel_digital_port
*intel_dig_port
=
1104 enc_to_dig_port(encoder
);
1106 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1107 * are ignored so nothing special needs to be done besides
1108 * enabling the port.
1110 I915_WRITE(DDI_BUF_CTL(port
),
1111 intel_dig_port
->port_reversal
| DDI_BUF_CTL_ENABLE
);
1112 } else if (type
== INTEL_OUTPUT_EDP
) {
1113 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1116 intel_dp_stop_link_train(intel_dp
);
1118 ironlake_edp_backlight_on(intel_dp
);
1121 if (intel_crtc
->eld_vld
&& type
!= INTEL_OUTPUT_EDP
) {
1122 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1123 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1124 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1128 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1130 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1131 struct drm_crtc
*crtc
= encoder
->crtc
;
1132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1133 int pipe
= intel_crtc
->pipe
;
1134 int type
= intel_encoder
->type
;
1135 struct drm_device
*dev
= encoder
->dev
;
1136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1139 if (intel_crtc
->eld_vld
&& type
!= INTEL_OUTPUT_EDP
) {
1140 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1141 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) <<
1143 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1146 if (type
== INTEL_OUTPUT_EDP
) {
1147 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1149 ironlake_edp_backlight_off(intel_dp
);
1153 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1155 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1157 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1160 else if (IS_ULT(dev_priv
->dev
))
1166 void intel_ddi_pll_init(struct drm_device
*dev
)
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 uint32_t val
= I915_READ(LCPLL_CTL
);
1171 /* The LCPLL register should be turned on by the BIOS. For now let's
1172 * just check its state and print errors in case something is wrong.
1173 * Don't even try to turn it on.
1176 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1177 intel_ddi_get_cdclk_freq(dev_priv
));
1179 if (val
& LCPLL_CD_SOURCE_FCLK
)
1180 DRM_ERROR("CDCLK source is not LCPLL\n");
1182 if (val
& LCPLL_PLL_DISABLE
)
1183 DRM_ERROR("LCPLL is disabled\n");
1186 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1188 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1189 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1190 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1191 enum port port
= intel_dig_port
->port
;
1195 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1196 val
= I915_READ(DDI_BUF_CTL(port
));
1197 if (val
& DDI_BUF_CTL_ENABLE
) {
1198 val
&= ~DDI_BUF_CTL_ENABLE
;
1199 I915_WRITE(DDI_BUF_CTL(port
), val
);
1203 val
= I915_READ(DP_TP_CTL(port
));
1204 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1205 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1206 I915_WRITE(DP_TP_CTL(port
), val
);
1207 POSTING_READ(DP_TP_CTL(port
));
1210 intel_wait_ddi_buf_idle(dev_priv
, port
);
1213 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1214 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1215 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1216 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1217 I915_WRITE(DP_TP_CTL(port
), val
);
1218 POSTING_READ(DP_TP_CTL(port
));
1220 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1221 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1222 POSTING_READ(DDI_BUF_CTL(port
));
1227 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1229 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1230 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1233 intel_ddi_post_disable(intel_encoder
);
1235 val
= I915_READ(_FDI_RXA_CTL
);
1236 val
&= ~FDI_RX_ENABLE
;
1237 I915_WRITE(_FDI_RXA_CTL
, val
);
1239 val
= I915_READ(_FDI_RXA_MISC
);
1240 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1241 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1242 I915_WRITE(_FDI_RXA_MISC
, val
);
1244 val
= I915_READ(_FDI_RXA_CTL
);
1246 I915_WRITE(_FDI_RXA_CTL
, val
);
1248 val
= I915_READ(_FDI_RXA_CTL
);
1249 val
&= ~FDI_RX_PLL_ENABLE
;
1250 I915_WRITE(_FDI_RXA_CTL
, val
);
1253 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1255 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1256 int type
= intel_encoder
->type
;
1258 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1259 intel_dp_check_link_status(intel_dp
);
1262 static void intel_ddi_get_config(struct intel_encoder
*encoder
,
1263 struct intel_crtc_config
*pipe_config
)
1265 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1266 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1267 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1268 u32 temp
, flags
= 0;
1270 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1271 if (temp
& TRANS_DDI_PHSYNC
)
1272 flags
|= DRM_MODE_FLAG_PHSYNC
;
1274 flags
|= DRM_MODE_FLAG_NHSYNC
;
1275 if (temp
& TRANS_DDI_PVSYNC
)
1276 flags
|= DRM_MODE_FLAG_PVSYNC
;
1278 flags
|= DRM_MODE_FLAG_NVSYNC
;
1280 pipe_config
->adjusted_mode
.flags
|= flags
;
1281 pipe_config
->pixel_multiplier
= 1;
1284 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1286 /* HDMI has nothing special to destroy, so we can go with this. */
1287 intel_dp_encoder_destroy(encoder
);
1290 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1291 struct intel_crtc_config
*pipe_config
)
1293 int type
= encoder
->type
;
1294 int port
= intel_ddi_get_encoder_port(encoder
);
1296 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1299 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
1301 if (type
== INTEL_OUTPUT_HDMI
)
1302 return intel_hdmi_compute_config(encoder
, pipe_config
);
1304 return intel_dp_compute_config(encoder
, pipe_config
);
1307 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1308 .destroy
= intel_ddi_destroy
,
1311 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs
= {
1312 .mode_set
= intel_ddi_mode_set
,
1315 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1318 struct intel_digital_port
*intel_dig_port
;
1319 struct intel_encoder
*intel_encoder
;
1320 struct drm_encoder
*encoder
;
1321 struct intel_connector
*hdmi_connector
= NULL
;
1322 struct intel_connector
*dp_connector
= NULL
;
1324 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1325 if (!intel_dig_port
)
1328 dp_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1329 if (!dp_connector
) {
1330 kfree(intel_dig_port
);
1334 intel_encoder
= &intel_dig_port
->base
;
1335 encoder
= &intel_encoder
->base
;
1337 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1338 DRM_MODE_ENCODER_TMDS
);
1339 drm_encoder_helper_add(encoder
, &intel_ddi_helper_funcs
);
1341 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1342 intel_encoder
->enable
= intel_enable_ddi
;
1343 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1344 intel_encoder
->disable
= intel_disable_ddi
;
1345 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1346 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1347 intel_encoder
->get_config
= intel_ddi_get_config
;
1349 intel_dig_port
->port
= port
;
1350 intel_dig_port
->port_reversal
= I915_READ(DDI_BUF_CTL(port
)) &
1351 DDI_BUF_PORT_REVERSAL
;
1352 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1354 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1355 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1356 intel_encoder
->cloneable
= false;
1357 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1359 intel_dp_init_connector(intel_dig_port
, dp_connector
);
1361 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
) {
1362 hdmi_connector
= kzalloc(sizeof(struct intel_connector
),
1364 if (!hdmi_connector
) {
1368 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1369 intel_hdmi_init_connector(intel_dig_port
, hdmi_connector
);