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drm/i915/skl: Program the DDB allocation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 };
35
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
50 };
51
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
62 };
63
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
78 };
79
80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
90 };
91
92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
102 };
103
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
114 };
115
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
128 };
129
130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
131 { 0x00000018, 0x000000a0 },
132 { 0x00004014, 0x00000098 },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000080 },
135 { 0x00000018, 0x00000098 },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000080 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000080 },
140 };
141
142 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
154 };
155
156 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
157 {
158 struct drm_encoder *encoder = &intel_encoder->base;
159 int type = intel_encoder->type;
160
161 if (type == INTEL_OUTPUT_DP_MST) {
162 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
163 return intel_dig_port->port;
164 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
165 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
166 struct intel_digital_port *intel_dig_port =
167 enc_to_dig_port(encoder);
168 return intel_dig_port->port;
169
170 } else if (type == INTEL_OUTPUT_ANALOG) {
171 return PORT_E;
172
173 } else {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type);
175 BUG();
176 }
177 }
178
179 /*
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
184 * of those
185 */
186 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 u32 reg;
190 int i, n_hdmi_entries, hdmi_800mV_0dB;
191 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
192 const struct ddi_buf_trans *ddi_translations_fdi;
193 const struct ddi_buf_trans *ddi_translations_dp;
194 const struct ddi_buf_trans *ddi_translations_edp;
195 const struct ddi_buf_trans *ddi_translations_hdmi;
196 const struct ddi_buf_trans *ddi_translations;
197
198 if (IS_SKYLAKE(dev)) {
199 ddi_translations_fdi = NULL;
200 ddi_translations_dp = skl_ddi_translations_dp;
201 ddi_translations_edp = skl_ddi_translations_dp;
202 ddi_translations_hdmi = skl_ddi_translations_hdmi;
203 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
204 hdmi_800mV_0dB = 7;
205 } else if (IS_BROADWELL(dev)) {
206 ddi_translations_fdi = bdw_ddi_translations_fdi;
207 ddi_translations_dp = bdw_ddi_translations_dp;
208 ddi_translations_edp = bdw_ddi_translations_edp;
209 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
210 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
211 hdmi_800mV_0dB = 7;
212 } else if (IS_HASWELL(dev)) {
213 ddi_translations_fdi = hsw_ddi_translations_fdi;
214 ddi_translations_dp = hsw_ddi_translations_dp;
215 ddi_translations_edp = hsw_ddi_translations_dp;
216 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
217 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
218 hdmi_800mV_0dB = 6;
219 } else {
220 WARN(1, "ddi translation table missing\n");
221 ddi_translations_edp = bdw_ddi_translations_dp;
222 ddi_translations_fdi = bdw_ddi_translations_fdi;
223 ddi_translations_dp = bdw_ddi_translations_dp;
224 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
225 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
226 hdmi_800mV_0dB = 7;
227 }
228
229 switch (port) {
230 case PORT_A:
231 ddi_translations = ddi_translations_edp;
232 break;
233 case PORT_B:
234 case PORT_C:
235 ddi_translations = ddi_translations_dp;
236 break;
237 case PORT_D:
238 if (intel_dp_is_edp(dev, PORT_D))
239 ddi_translations = ddi_translations_edp;
240 else
241 ddi_translations = ddi_translations_dp;
242 break;
243 case PORT_E:
244 if (ddi_translations_fdi)
245 ddi_translations = ddi_translations_fdi;
246 else
247 ddi_translations = ddi_translations_dp;
248 break;
249 default:
250 BUG();
251 }
252
253 for (i = 0, reg = DDI_BUF_TRANS(port);
254 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
255 I915_WRITE(reg, ddi_translations[i].trans1);
256 reg += 4;
257 I915_WRITE(reg, ddi_translations[i].trans2);
258 reg += 4;
259 }
260
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
263 hdmi_level >= n_hdmi_entries)
264 hdmi_level = hdmi_800mV_0dB;
265
266 /* Entry 9 is for HDMI: */
267 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
268 reg += 4;
269 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
270 reg += 4;
271 }
272
273 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
275 */
276 void intel_prepare_ddi(struct drm_device *dev)
277 {
278 int port;
279
280 if (!HAS_DDI(dev))
281 return;
282
283 for (port = PORT_A; port <= PORT_E; port++)
284 intel_prepare_ddi_buffers(dev, port);
285 }
286
287 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
288 enum port port)
289 {
290 uint32_t reg = DDI_BUF_CTL(port);
291 int i;
292
293 for (i = 0; i < 8; i++) {
294 udelay(1);
295 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
296 return;
297 }
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
299 }
300
301 /* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
304 *
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
308 */
309
310 void hsw_fdi_link_train(struct drm_crtc *crtc)
311 {
312 struct drm_device *dev = crtc->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
315 u32 temp, i, rx_ctl_val;
316
317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
320 * - FDI delay to 90h
321 *
322 * WaFDIAutoLinkSetTimingOverrride:hsw
323 */
324 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
327
328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
330 FDI_RX_PLL_ENABLE |
331 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL);
334 udelay(220);
335
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val |= FDI_PCDCLK;
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
339
340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
342 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
343
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
346 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E),
349 DP_TP_CTL_FDI_AUTOTRAIN |
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
351 DP_TP_CTL_LINK_TRAIN_PAT1 |
352 DP_TP_CTL_ENABLE);
353
354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E),
359 DDI_BUF_CTL_ENABLE |
360 ((intel_crtc->config.fdi_lanes - 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i / 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E));
363
364 udelay(600);
365
366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
368
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
372 POSTING_READ(_FDI_RXA_CTL);
373
374 /* Wait for FDI receiver lane calibration */
375 udelay(30);
376
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp = I915_READ(_FDI_RXA_MISC);
379 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
380 I915_WRITE(_FDI_RXA_MISC, temp);
381 POSTING_READ(_FDI_RXA_MISC);
382
383 /* Wait for FDI auto training time */
384 udelay(5);
385
386 temp = I915_READ(DP_TP_STATUS(PORT_E));
387 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
389
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E),
392 DP_TP_CTL_FDI_AUTOTRAIN |
393 DP_TP_CTL_LINK_TRAIN_NORMAL |
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
395 DP_TP_CTL_ENABLE);
396
397 return;
398 }
399
400 temp = I915_READ(DDI_BUF_CTL(PORT_E));
401 temp &= ~DDI_BUF_CTL_ENABLE;
402 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
403 POSTING_READ(DDI_BUF_CTL(PORT_E));
404
405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 temp = I915_READ(DP_TP_CTL(PORT_E));
407 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
408 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
409 I915_WRITE(DP_TP_CTL(PORT_E), temp);
410 POSTING_READ(DP_TP_CTL(PORT_E));
411
412 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
413
414 rx_ctl_val &= ~FDI_RX_ENABLE;
415 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
416 POSTING_READ(_FDI_RXA_CTL);
417
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp = I915_READ(_FDI_RXA_MISC);
420 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC, temp);
423 POSTING_READ(_FDI_RXA_MISC);
424 }
425
426 DRM_ERROR("FDI link training failed!\n");
427 }
428
429 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
430 {
431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
432 struct intel_digital_port *intel_dig_port =
433 enc_to_dig_port(&encoder->base);
434
435 intel_dp->DP = intel_dig_port->saved_port_bits |
436 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
437 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
438
439 }
440
441 static struct intel_encoder *
442 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
443 {
444 struct drm_device *dev = crtc->dev;
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
446 struct intel_encoder *intel_encoder, *ret = NULL;
447 int num_encoders = 0;
448
449 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
450 ret = intel_encoder;
451 num_encoders++;
452 }
453
454 if (num_encoders != 1)
455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
456 pipe_name(intel_crtc->pipe));
457
458 BUG_ON(ret == NULL);
459 return ret;
460 }
461
462 static struct intel_encoder *
463 intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
464 {
465 struct drm_device *dev = crtc->base.dev;
466 struct intel_encoder *intel_encoder, *ret = NULL;
467 int num_encoders = 0;
468
469 for_each_intel_encoder(dev, intel_encoder) {
470 if (intel_encoder->new_crtc == crtc) {
471 ret = intel_encoder;
472 num_encoders++;
473 }
474 }
475
476 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
477 pipe_name(crtc->pipe));
478
479 BUG_ON(ret == NULL);
480 return ret;
481 }
482
483 #define LC_FREQ 2700
484 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
485
486 #define P_MIN 2
487 #define P_MAX 64
488 #define P_INC 2
489
490 /* Constraints for PLL good behavior */
491 #define REF_MIN 48
492 #define REF_MAX 400
493 #define VCO_MIN 2400
494 #define VCO_MAX 4800
495
496 #define abs_diff(a, b) ({ \
497 typeof(a) __a = (a); \
498 typeof(b) __b = (b); \
499 (void) (&__a == &__b); \
500 __a > __b ? (__a - __b) : (__b - __a); })
501
502 struct wrpll_rnp {
503 unsigned p, n2, r2;
504 };
505
506 static unsigned wrpll_get_budget_for_freq(int clock)
507 {
508 unsigned budget;
509
510 switch (clock) {
511 case 25175000:
512 case 25200000:
513 case 27000000:
514 case 27027000:
515 case 37762500:
516 case 37800000:
517 case 40500000:
518 case 40541000:
519 case 54000000:
520 case 54054000:
521 case 59341000:
522 case 59400000:
523 case 72000000:
524 case 74176000:
525 case 74250000:
526 case 81000000:
527 case 81081000:
528 case 89012000:
529 case 89100000:
530 case 108000000:
531 case 108108000:
532 case 111264000:
533 case 111375000:
534 case 148352000:
535 case 148500000:
536 case 162000000:
537 case 162162000:
538 case 222525000:
539 case 222750000:
540 case 296703000:
541 case 297000000:
542 budget = 0;
543 break;
544 case 233500000:
545 case 245250000:
546 case 247750000:
547 case 253250000:
548 case 298000000:
549 budget = 1500;
550 break;
551 case 169128000:
552 case 169500000:
553 case 179500000:
554 case 202000000:
555 budget = 2000;
556 break;
557 case 256250000:
558 case 262500000:
559 case 270000000:
560 case 272500000:
561 case 273750000:
562 case 280750000:
563 case 281250000:
564 case 286000000:
565 case 291750000:
566 budget = 4000;
567 break;
568 case 267250000:
569 case 268500000:
570 budget = 5000;
571 break;
572 default:
573 budget = 1000;
574 break;
575 }
576
577 return budget;
578 }
579
580 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
581 unsigned r2, unsigned n2, unsigned p,
582 struct wrpll_rnp *best)
583 {
584 uint64_t a, b, c, d, diff, diff_best;
585
586 /* No best (r,n,p) yet */
587 if (best->p == 0) {
588 best->p = p;
589 best->n2 = n2;
590 best->r2 = r2;
591 return;
592 }
593
594 /*
595 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
596 * freq2k.
597 *
598 * delta = 1e6 *
599 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
600 * freq2k;
601 *
602 * and we would like delta <= budget.
603 *
604 * If the discrepancy is above the PPM-based budget, always prefer to
605 * improve upon the previous solution. However, if you're within the
606 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
607 */
608 a = freq2k * budget * p * r2;
609 b = freq2k * budget * best->p * best->r2;
610 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
611 diff_best = abs_diff(freq2k * best->p * best->r2,
612 LC_FREQ_2K * best->n2);
613 c = 1000000 * diff;
614 d = 1000000 * diff_best;
615
616 if (a < c && b < d) {
617 /* If both are above the budget, pick the closer */
618 if (best->p * best->r2 * diff < p * r2 * diff_best) {
619 best->p = p;
620 best->n2 = n2;
621 best->r2 = r2;
622 }
623 } else if (a >= c && b < d) {
624 /* If A is below the threshold but B is above it? Update. */
625 best->p = p;
626 best->n2 = n2;
627 best->r2 = r2;
628 } else if (a >= c && b >= d) {
629 /* Both are below the limit, so pick the higher n2/(r2*r2) */
630 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
631 best->p = p;
632 best->n2 = n2;
633 best->r2 = r2;
634 }
635 }
636 /* Otherwise a < c && b >= d, do nothing */
637 }
638
639 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
640 int reg)
641 {
642 int refclk = LC_FREQ;
643 int n, p, r;
644 u32 wrpll;
645
646 wrpll = I915_READ(reg);
647 switch (wrpll & WRPLL_PLL_REF_MASK) {
648 case WRPLL_PLL_SSC:
649 case WRPLL_PLL_NON_SSC:
650 /*
651 * We could calculate spread here, but our checking
652 * code only cares about 5% accuracy, and spread is a max of
653 * 0.5% downspread.
654 */
655 refclk = 135;
656 break;
657 case WRPLL_PLL_LCPLL:
658 refclk = LC_FREQ;
659 break;
660 default:
661 WARN(1, "bad wrpll refclk\n");
662 return 0;
663 }
664
665 r = wrpll & WRPLL_DIVIDER_REF_MASK;
666 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
667 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
668
669 /* Convert to KHz, p & r have a fixed point portion */
670 return (refclk * n * 100) / (p * r);
671 }
672
673 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
674 struct intel_crtc_config *pipe_config)
675 {
676 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
677 int link_clock = 0;
678 u32 val, pll;
679
680 val = pipe_config->ddi_pll_sel;
681 switch (val & PORT_CLK_SEL_MASK) {
682 case PORT_CLK_SEL_LCPLL_810:
683 link_clock = 81000;
684 break;
685 case PORT_CLK_SEL_LCPLL_1350:
686 link_clock = 135000;
687 break;
688 case PORT_CLK_SEL_LCPLL_2700:
689 link_clock = 270000;
690 break;
691 case PORT_CLK_SEL_WRPLL1:
692 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
693 break;
694 case PORT_CLK_SEL_WRPLL2:
695 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
696 break;
697 case PORT_CLK_SEL_SPLL:
698 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
699 if (pll == SPLL_PLL_FREQ_810MHz)
700 link_clock = 81000;
701 else if (pll == SPLL_PLL_FREQ_1350MHz)
702 link_clock = 135000;
703 else if (pll == SPLL_PLL_FREQ_2700MHz)
704 link_clock = 270000;
705 else {
706 WARN(1, "bad spll freq\n");
707 return;
708 }
709 break;
710 default:
711 WARN(1, "bad port clock sel\n");
712 return;
713 }
714
715 pipe_config->port_clock = link_clock * 2;
716
717 if (pipe_config->has_pch_encoder)
718 pipe_config->adjusted_mode.crtc_clock =
719 intel_dotclock_calculate(pipe_config->port_clock,
720 &pipe_config->fdi_m_n);
721 else if (pipe_config->has_dp_encoder)
722 pipe_config->adjusted_mode.crtc_clock =
723 intel_dotclock_calculate(pipe_config->port_clock,
724 &pipe_config->dp_m_n);
725 else
726 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
727 }
728
729 void intel_ddi_clock_get(struct intel_encoder *encoder,
730 struct intel_crtc_config *pipe_config)
731 {
732 hsw_ddi_clock_get(encoder, pipe_config);
733 }
734
735 static void
736 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
737 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
738 {
739 uint64_t freq2k;
740 unsigned p, n2, r2;
741 struct wrpll_rnp best = { 0, 0, 0 };
742 unsigned budget;
743
744 freq2k = clock / 100;
745
746 budget = wrpll_get_budget_for_freq(clock);
747
748 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
749 * and directly pass the LC PLL to it. */
750 if (freq2k == 5400000) {
751 *n2_out = 2;
752 *p_out = 1;
753 *r2_out = 2;
754 return;
755 }
756
757 /*
758 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
759 * the WR PLL.
760 *
761 * We want R so that REF_MIN <= Ref <= REF_MAX.
762 * Injecting R2 = 2 * R gives:
763 * REF_MAX * r2 > LC_FREQ * 2 and
764 * REF_MIN * r2 < LC_FREQ * 2
765 *
766 * Which means the desired boundaries for r2 are:
767 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
768 *
769 */
770 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
771 r2 <= LC_FREQ * 2 / REF_MIN;
772 r2++) {
773
774 /*
775 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
776 *
777 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
778 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
779 * VCO_MAX * r2 > n2 * LC_FREQ and
780 * VCO_MIN * r2 < n2 * LC_FREQ)
781 *
782 * Which means the desired boundaries for n2 are:
783 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
784 */
785 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
786 n2 <= VCO_MAX * r2 / LC_FREQ;
787 n2++) {
788
789 for (p = P_MIN; p <= P_MAX; p += P_INC)
790 wrpll_update_rnp(freq2k, budget,
791 r2, n2, p, &best);
792 }
793 }
794
795 *n2_out = best.n2;
796 *p_out = best.p;
797 *r2_out = best.r2;
798 }
799
800 static bool
801 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
802 struct intel_encoder *intel_encoder,
803 int clock)
804 {
805 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
806 struct intel_shared_dpll *pll;
807 uint32_t val;
808 unsigned p, n2, r2;
809
810 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
811
812 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
813 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
814 WRPLL_DIVIDER_POST(p);
815
816 intel_crtc->new_config->dpll_hw_state.wrpll = val;
817
818 pll = intel_get_shared_dpll(intel_crtc);
819 if (pll == NULL) {
820 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
821 pipe_name(intel_crtc->pipe));
822 return false;
823 }
824
825 intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
826 }
827
828 return true;
829 }
830
831
832 /*
833 * Tries to find a *shared* PLL for the CRTC and store it in
834 * intel_crtc->ddi_pll_sel.
835 *
836 * For private DPLLs, compute_config() should do the selection for us. This
837 * function should be folded into compute_config() eventually.
838 */
839 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
840 {
841 struct intel_encoder *intel_encoder =
842 intel_ddi_get_crtc_new_encoder(intel_crtc);
843 int clock = intel_crtc->new_config->port_clock;
844
845 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
846 }
847
848 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
849 {
850 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
852 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
853 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
854 int type = intel_encoder->type;
855 uint32_t temp;
856
857 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
858 temp = TRANS_MSA_SYNC_CLK;
859 switch (intel_crtc->config.pipe_bpp) {
860 case 18:
861 temp |= TRANS_MSA_6_BPC;
862 break;
863 case 24:
864 temp |= TRANS_MSA_8_BPC;
865 break;
866 case 30:
867 temp |= TRANS_MSA_10_BPC;
868 break;
869 case 36:
870 temp |= TRANS_MSA_12_BPC;
871 break;
872 default:
873 BUG();
874 }
875 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
876 }
877 }
878
879 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
880 {
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882 struct drm_device *dev = crtc->dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
885 uint32_t temp;
886 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
887 if (state == true)
888 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
889 else
890 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
891 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
892 }
893
894 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
895 {
896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
897 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
898 struct drm_encoder *encoder = &intel_encoder->base;
899 struct drm_device *dev = crtc->dev;
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 enum pipe pipe = intel_crtc->pipe;
902 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
903 enum port port = intel_ddi_get_encoder_port(intel_encoder);
904 int type = intel_encoder->type;
905 uint32_t temp;
906
907 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
908 temp = TRANS_DDI_FUNC_ENABLE;
909 temp |= TRANS_DDI_SELECT_PORT(port);
910
911 switch (intel_crtc->config.pipe_bpp) {
912 case 18:
913 temp |= TRANS_DDI_BPC_6;
914 break;
915 case 24:
916 temp |= TRANS_DDI_BPC_8;
917 break;
918 case 30:
919 temp |= TRANS_DDI_BPC_10;
920 break;
921 case 36:
922 temp |= TRANS_DDI_BPC_12;
923 break;
924 default:
925 BUG();
926 }
927
928 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
929 temp |= TRANS_DDI_PVSYNC;
930 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
931 temp |= TRANS_DDI_PHSYNC;
932
933 if (cpu_transcoder == TRANSCODER_EDP) {
934 switch (pipe) {
935 case PIPE_A:
936 /* On Haswell, can only use the always-on power well for
937 * eDP when not using the panel fitter, and when not
938 * using motion blur mitigation (which we don't
939 * support). */
940 if (IS_HASWELL(dev) &&
941 (intel_crtc->config.pch_pfit.enabled ||
942 intel_crtc->config.pch_pfit.force_thru))
943 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
944 else
945 temp |= TRANS_DDI_EDP_INPUT_A_ON;
946 break;
947 case PIPE_B:
948 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
949 break;
950 case PIPE_C:
951 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
952 break;
953 default:
954 BUG();
955 break;
956 }
957 }
958
959 if (type == INTEL_OUTPUT_HDMI) {
960 if (intel_crtc->config.has_hdmi_sink)
961 temp |= TRANS_DDI_MODE_SELECT_HDMI;
962 else
963 temp |= TRANS_DDI_MODE_SELECT_DVI;
964
965 } else if (type == INTEL_OUTPUT_ANALOG) {
966 temp |= TRANS_DDI_MODE_SELECT_FDI;
967 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
968
969 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
970 type == INTEL_OUTPUT_EDP) {
971 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
972
973 if (intel_dp->is_mst) {
974 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
975 } else
976 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
977
978 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
979 } else if (type == INTEL_OUTPUT_DP_MST) {
980 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
981
982 if (intel_dp->is_mst) {
983 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
984 } else
985 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
986
987 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
988 } else {
989 WARN(1, "Invalid encoder type %d for pipe %c\n",
990 intel_encoder->type, pipe_name(pipe));
991 }
992
993 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
994 }
995
996 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
997 enum transcoder cpu_transcoder)
998 {
999 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1000 uint32_t val = I915_READ(reg);
1001
1002 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1003 val |= TRANS_DDI_PORT_NONE;
1004 I915_WRITE(reg, val);
1005 }
1006
1007 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1008 {
1009 struct drm_device *dev = intel_connector->base.dev;
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct intel_encoder *intel_encoder = intel_connector->encoder;
1012 int type = intel_connector->base.connector_type;
1013 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1014 enum pipe pipe = 0;
1015 enum transcoder cpu_transcoder;
1016 enum intel_display_power_domain power_domain;
1017 uint32_t tmp;
1018
1019 power_domain = intel_display_port_power_domain(intel_encoder);
1020 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1021 return false;
1022
1023 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1024 return false;
1025
1026 if (port == PORT_A)
1027 cpu_transcoder = TRANSCODER_EDP;
1028 else
1029 cpu_transcoder = (enum transcoder) pipe;
1030
1031 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1032
1033 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1034 case TRANS_DDI_MODE_SELECT_HDMI:
1035 case TRANS_DDI_MODE_SELECT_DVI:
1036 return (type == DRM_MODE_CONNECTOR_HDMIA);
1037
1038 case TRANS_DDI_MODE_SELECT_DP_SST:
1039 if (type == DRM_MODE_CONNECTOR_eDP)
1040 return true;
1041 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1042 case TRANS_DDI_MODE_SELECT_DP_MST:
1043 /* if the transcoder is in MST state then
1044 * connector isn't connected */
1045 return false;
1046
1047 case TRANS_DDI_MODE_SELECT_FDI:
1048 return (type == DRM_MODE_CONNECTOR_VGA);
1049
1050 default:
1051 return false;
1052 }
1053 }
1054
1055 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1056 enum pipe *pipe)
1057 {
1058 struct drm_device *dev = encoder->base.dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 enum port port = intel_ddi_get_encoder_port(encoder);
1061 enum intel_display_power_domain power_domain;
1062 u32 tmp;
1063 int i;
1064
1065 power_domain = intel_display_port_power_domain(encoder);
1066 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1067 return false;
1068
1069 tmp = I915_READ(DDI_BUF_CTL(port));
1070
1071 if (!(tmp & DDI_BUF_CTL_ENABLE))
1072 return false;
1073
1074 if (port == PORT_A) {
1075 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1076
1077 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1078 case TRANS_DDI_EDP_INPUT_A_ON:
1079 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1080 *pipe = PIPE_A;
1081 break;
1082 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1083 *pipe = PIPE_B;
1084 break;
1085 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1086 *pipe = PIPE_C;
1087 break;
1088 }
1089
1090 return true;
1091 } else {
1092 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1093 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1094
1095 if ((tmp & TRANS_DDI_PORT_MASK)
1096 == TRANS_DDI_SELECT_PORT(port)) {
1097 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1098 return false;
1099
1100 *pipe = i;
1101 return true;
1102 }
1103 }
1104 }
1105
1106 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1107
1108 return false;
1109 }
1110
1111 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1112 {
1113 struct drm_crtc *crtc = &intel_crtc->base;
1114 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1115 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1116 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1117 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1118
1119 if (cpu_transcoder != TRANSCODER_EDP)
1120 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1121 TRANS_CLK_SEL_PORT(port));
1122 }
1123
1124 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1125 {
1126 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1128
1129 if (cpu_transcoder != TRANSCODER_EDP)
1130 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1131 TRANS_CLK_SEL_DISABLED);
1132 }
1133
1134 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1135 {
1136 struct drm_encoder *encoder = &intel_encoder->base;
1137 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1138 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1139 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1140 int type = intel_encoder->type;
1141
1142 if (type == INTEL_OUTPUT_EDP) {
1143 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1144 intel_edp_panel_on(intel_dp);
1145 }
1146
1147 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1148 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1149
1150 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1151 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1152
1153 intel_ddi_init_dp_buf_reg(intel_encoder);
1154
1155 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1156 intel_dp_start_link_train(intel_dp);
1157 intel_dp_complete_link_train(intel_dp);
1158 if (port != PORT_A)
1159 intel_dp_stop_link_train(intel_dp);
1160 } else if (type == INTEL_OUTPUT_HDMI) {
1161 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1162
1163 intel_hdmi->set_infoframes(encoder,
1164 crtc->config.has_hdmi_sink,
1165 &crtc->config.adjusted_mode);
1166 }
1167 }
1168
1169 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1170 {
1171 struct drm_encoder *encoder = &intel_encoder->base;
1172 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1173 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1174 int type = intel_encoder->type;
1175 uint32_t val;
1176 bool wait = false;
1177
1178 val = I915_READ(DDI_BUF_CTL(port));
1179 if (val & DDI_BUF_CTL_ENABLE) {
1180 val &= ~DDI_BUF_CTL_ENABLE;
1181 I915_WRITE(DDI_BUF_CTL(port), val);
1182 wait = true;
1183 }
1184
1185 val = I915_READ(DP_TP_CTL(port));
1186 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1187 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1188 I915_WRITE(DP_TP_CTL(port), val);
1189
1190 if (wait)
1191 intel_wait_ddi_buf_idle(dev_priv, port);
1192
1193 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1194 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1195 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1196 intel_edp_panel_vdd_on(intel_dp);
1197 intel_edp_panel_off(intel_dp);
1198 }
1199
1200 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1201 }
1202
1203 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1204 {
1205 struct drm_encoder *encoder = &intel_encoder->base;
1206 struct drm_crtc *crtc = encoder->crtc;
1207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1208 struct drm_device *dev = encoder->dev;
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1211 int type = intel_encoder->type;
1212
1213 if (type == INTEL_OUTPUT_HDMI) {
1214 struct intel_digital_port *intel_dig_port =
1215 enc_to_dig_port(encoder);
1216
1217 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1218 * are ignored so nothing special needs to be done besides
1219 * enabling the port.
1220 */
1221 I915_WRITE(DDI_BUF_CTL(port),
1222 intel_dig_port->saved_port_bits |
1223 DDI_BUF_CTL_ENABLE);
1224 } else if (type == INTEL_OUTPUT_EDP) {
1225 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1226
1227 if (port == PORT_A)
1228 intel_dp_stop_link_train(intel_dp);
1229
1230 intel_edp_backlight_on(intel_dp);
1231 intel_edp_psr_enable(intel_dp);
1232 }
1233
1234 if (intel_crtc->config.has_audio) {
1235 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1236 intel_audio_codec_enable(intel_encoder);
1237 }
1238 }
1239
1240 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1241 {
1242 struct drm_encoder *encoder = &intel_encoder->base;
1243 struct drm_crtc *crtc = encoder->crtc;
1244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1245 int type = intel_encoder->type;
1246 struct drm_device *dev = encoder->dev;
1247 struct drm_i915_private *dev_priv = dev->dev_private;
1248
1249 if (intel_crtc->config.has_audio) {
1250 intel_audio_codec_disable(intel_encoder);
1251 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1252 }
1253
1254 if (type == INTEL_OUTPUT_EDP) {
1255 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1256
1257 intel_edp_psr_disable(intel_dp);
1258 intel_edp_backlight_off(intel_dp);
1259 }
1260 }
1261
1262 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1263 {
1264 uint32_t lcpll = I915_READ(LCPLL_CTL);
1265 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1266
1267 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1268 return 800000;
1269 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1270 return 450000;
1271 else if (freq == LCPLL_CLK_FREQ_450)
1272 return 450000;
1273 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1274 return 540000;
1275 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1276 return 337500;
1277 else
1278 return 675000;
1279 }
1280
1281 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 uint32_t lcpll = I915_READ(LCPLL_CTL);
1285 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1286
1287 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1288 return 800000;
1289 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1290 return 450000;
1291 else if (freq == LCPLL_CLK_FREQ_450)
1292 return 450000;
1293 else if (IS_HSW_ULT(dev))
1294 return 337500;
1295 else
1296 return 540000;
1297 }
1298
1299 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1300 {
1301 struct drm_device *dev = dev_priv->dev;
1302
1303 if (IS_BROADWELL(dev))
1304 return bdw_get_cdclk_freq(dev_priv);
1305
1306 /* Haswell */
1307 return hsw_get_cdclk_freq(dev_priv);
1308 }
1309
1310 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1311 struct intel_shared_dpll *pll)
1312 {
1313 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1314 POSTING_READ(WRPLL_CTL(pll->id));
1315 udelay(20);
1316 }
1317
1318 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1319 struct intel_shared_dpll *pll)
1320 {
1321 uint32_t val;
1322
1323 val = I915_READ(WRPLL_CTL(pll->id));
1324 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1325 POSTING_READ(WRPLL_CTL(pll->id));
1326 }
1327
1328 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1329 struct intel_shared_dpll *pll,
1330 struct intel_dpll_hw_state *hw_state)
1331 {
1332 uint32_t val;
1333
1334 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1335 return false;
1336
1337 val = I915_READ(WRPLL_CTL(pll->id));
1338 hw_state->wrpll = val;
1339
1340 return val & WRPLL_PLL_ENABLE;
1341 }
1342
1343 static const char * const hsw_ddi_pll_names[] = {
1344 "WRPLL 1",
1345 "WRPLL 2",
1346 };
1347
1348 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1349 {
1350 int i;
1351
1352 dev_priv->num_shared_dpll = 2;
1353
1354 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1355 dev_priv->shared_dplls[i].id = i;
1356 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1357 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1358 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1359 dev_priv->shared_dplls[i].get_hw_state =
1360 hsw_ddi_pll_get_hw_state;
1361 }
1362 }
1363
1364 void intel_ddi_pll_init(struct drm_device *dev)
1365 {
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 uint32_t val = I915_READ(LCPLL_CTL);
1368
1369 hsw_shared_dplls_init(dev_priv);
1370
1371 /* The LCPLL register should be turned on by the BIOS. For now let's
1372 * just check its state and print errors in case something is wrong.
1373 * Don't even try to turn it on.
1374 */
1375
1376 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1377 intel_ddi_get_cdclk_freq(dev_priv));
1378
1379 if (val & LCPLL_CD_SOURCE_FCLK)
1380 DRM_ERROR("CDCLK source is not LCPLL\n");
1381
1382 if (val & LCPLL_PLL_DISABLE)
1383 DRM_ERROR("LCPLL is disabled\n");
1384 }
1385
1386 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1387 {
1388 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1389 struct intel_dp *intel_dp = &intel_dig_port->dp;
1390 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1391 enum port port = intel_dig_port->port;
1392 uint32_t val;
1393 bool wait = false;
1394
1395 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1396 val = I915_READ(DDI_BUF_CTL(port));
1397 if (val & DDI_BUF_CTL_ENABLE) {
1398 val &= ~DDI_BUF_CTL_ENABLE;
1399 I915_WRITE(DDI_BUF_CTL(port), val);
1400 wait = true;
1401 }
1402
1403 val = I915_READ(DP_TP_CTL(port));
1404 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1405 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1406 I915_WRITE(DP_TP_CTL(port), val);
1407 POSTING_READ(DP_TP_CTL(port));
1408
1409 if (wait)
1410 intel_wait_ddi_buf_idle(dev_priv, port);
1411 }
1412
1413 val = DP_TP_CTL_ENABLE |
1414 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1415 if (intel_dp->is_mst)
1416 val |= DP_TP_CTL_MODE_MST;
1417 else {
1418 val |= DP_TP_CTL_MODE_SST;
1419 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1420 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1421 }
1422 I915_WRITE(DP_TP_CTL(port), val);
1423 POSTING_READ(DP_TP_CTL(port));
1424
1425 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1426 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1427 POSTING_READ(DDI_BUF_CTL(port));
1428
1429 udelay(600);
1430 }
1431
1432 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1433 {
1434 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1435 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1436 uint32_t val;
1437
1438 intel_ddi_post_disable(intel_encoder);
1439
1440 val = I915_READ(_FDI_RXA_CTL);
1441 val &= ~FDI_RX_ENABLE;
1442 I915_WRITE(_FDI_RXA_CTL, val);
1443
1444 val = I915_READ(_FDI_RXA_MISC);
1445 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1446 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1447 I915_WRITE(_FDI_RXA_MISC, val);
1448
1449 val = I915_READ(_FDI_RXA_CTL);
1450 val &= ~FDI_PCDCLK;
1451 I915_WRITE(_FDI_RXA_CTL, val);
1452
1453 val = I915_READ(_FDI_RXA_CTL);
1454 val &= ~FDI_RX_PLL_ENABLE;
1455 I915_WRITE(_FDI_RXA_CTL, val);
1456 }
1457
1458 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1459 {
1460 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1461 int type = intel_dig_port->base.type;
1462
1463 if (type != INTEL_OUTPUT_DISPLAYPORT &&
1464 type != INTEL_OUTPUT_EDP &&
1465 type != INTEL_OUTPUT_UNKNOWN) {
1466 return;
1467 }
1468
1469 intel_dp_hot_plug(intel_encoder);
1470 }
1471
1472 void intel_ddi_get_config(struct intel_encoder *encoder,
1473 struct intel_crtc_config *pipe_config)
1474 {
1475 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1476 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1477 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1478 u32 temp, flags = 0;
1479
1480 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1481 if (temp & TRANS_DDI_PHSYNC)
1482 flags |= DRM_MODE_FLAG_PHSYNC;
1483 else
1484 flags |= DRM_MODE_FLAG_NHSYNC;
1485 if (temp & TRANS_DDI_PVSYNC)
1486 flags |= DRM_MODE_FLAG_PVSYNC;
1487 else
1488 flags |= DRM_MODE_FLAG_NVSYNC;
1489
1490 pipe_config->adjusted_mode.flags |= flags;
1491
1492 switch (temp & TRANS_DDI_BPC_MASK) {
1493 case TRANS_DDI_BPC_6:
1494 pipe_config->pipe_bpp = 18;
1495 break;
1496 case TRANS_DDI_BPC_8:
1497 pipe_config->pipe_bpp = 24;
1498 break;
1499 case TRANS_DDI_BPC_10:
1500 pipe_config->pipe_bpp = 30;
1501 break;
1502 case TRANS_DDI_BPC_12:
1503 pipe_config->pipe_bpp = 36;
1504 break;
1505 default:
1506 break;
1507 }
1508
1509 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1510 case TRANS_DDI_MODE_SELECT_HDMI:
1511 pipe_config->has_hdmi_sink = true;
1512 case TRANS_DDI_MODE_SELECT_DVI:
1513 case TRANS_DDI_MODE_SELECT_FDI:
1514 break;
1515 case TRANS_DDI_MODE_SELECT_DP_SST:
1516 case TRANS_DDI_MODE_SELECT_DP_MST:
1517 pipe_config->has_dp_encoder = true;
1518 intel_dp_get_m_n(intel_crtc, pipe_config);
1519 break;
1520 default:
1521 break;
1522 }
1523
1524 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1525 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1526 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1527 pipe_config->has_audio = true;
1528 }
1529
1530 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1531 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1532 /*
1533 * This is a big fat ugly hack.
1534 *
1535 * Some machines in UEFI boot mode provide us a VBT that has 18
1536 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1537 * unknown we fail to light up. Yet the same BIOS boots up with
1538 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1539 * max, not what it tells us to use.
1540 *
1541 * Note: This will still be broken if the eDP panel is not lit
1542 * up by the BIOS, and thus we can't get the mode at module
1543 * load.
1544 */
1545 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1546 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1547 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1548 }
1549
1550 hsw_ddi_clock_get(encoder, pipe_config);
1551 }
1552
1553 static void intel_ddi_destroy(struct drm_encoder *encoder)
1554 {
1555 /* HDMI has nothing special to destroy, so we can go with this. */
1556 intel_dp_encoder_destroy(encoder);
1557 }
1558
1559 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1560 struct intel_crtc_config *pipe_config)
1561 {
1562 int type = encoder->type;
1563 int port = intel_ddi_get_encoder_port(encoder);
1564
1565 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1566
1567 if (port == PORT_A)
1568 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1569
1570 if (type == INTEL_OUTPUT_HDMI)
1571 return intel_hdmi_compute_config(encoder, pipe_config);
1572 else
1573 return intel_dp_compute_config(encoder, pipe_config);
1574 }
1575
1576 static const struct drm_encoder_funcs intel_ddi_funcs = {
1577 .destroy = intel_ddi_destroy,
1578 };
1579
1580 static struct intel_connector *
1581 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1582 {
1583 struct intel_connector *connector;
1584 enum port port = intel_dig_port->port;
1585
1586 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1587 if (!connector)
1588 return NULL;
1589
1590 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1591 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1592 kfree(connector);
1593 return NULL;
1594 }
1595
1596 return connector;
1597 }
1598
1599 static struct intel_connector *
1600 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1601 {
1602 struct intel_connector *connector;
1603 enum port port = intel_dig_port->port;
1604
1605 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1606 if (!connector)
1607 return NULL;
1608
1609 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1610 intel_hdmi_init_connector(intel_dig_port, connector);
1611
1612 return connector;
1613 }
1614
1615 void intel_ddi_init(struct drm_device *dev, enum port port)
1616 {
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 struct intel_digital_port *intel_dig_port;
1619 struct intel_encoder *intel_encoder;
1620 struct drm_encoder *encoder;
1621 bool init_hdmi, init_dp;
1622
1623 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1624 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1625 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1626 if (!init_dp && !init_hdmi) {
1627 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1628 port_name(port));
1629 init_hdmi = true;
1630 init_dp = true;
1631 }
1632
1633 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1634 if (!intel_dig_port)
1635 return;
1636
1637 intel_encoder = &intel_dig_port->base;
1638 encoder = &intel_encoder->base;
1639
1640 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1641 DRM_MODE_ENCODER_TMDS);
1642
1643 intel_encoder->compute_config = intel_ddi_compute_config;
1644 intel_encoder->enable = intel_enable_ddi;
1645 intel_encoder->pre_enable = intel_ddi_pre_enable;
1646 intel_encoder->disable = intel_disable_ddi;
1647 intel_encoder->post_disable = intel_ddi_post_disable;
1648 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1649 intel_encoder->get_config = intel_ddi_get_config;
1650
1651 intel_dig_port->port = port;
1652 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1653 (DDI_BUF_PORT_REVERSAL |
1654 DDI_A_4_LANES);
1655
1656 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1657 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1658 intel_encoder->cloneable = 0;
1659 intel_encoder->hot_plug = intel_ddi_hot_plug;
1660
1661 if (init_dp) {
1662 if (!intel_ddi_init_dp_connector(intel_dig_port))
1663 goto err;
1664
1665 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1666 dev_priv->hpd_irq_port[port] = intel_dig_port;
1667 }
1668
1669 /* In theory we don't need the encoder->type check, but leave it just in
1670 * case we have some really bad VBTs... */
1671 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1672 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1673 goto err;
1674 }
1675
1676 return;
1677
1678 err:
1679 drm_encoder_cleanup(encoder);
1680 kfree(intel_dig_port);
1681 }
Linux kernel - Deliverables
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