2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
40 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
80 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
92 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
130 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000087 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000087 },
142 /* eDP 1.4 low vswing translation parameters */
143 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
157 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
171 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
173 struct drm_encoder
*encoder
= &intel_encoder
->base
;
174 int type
= intel_encoder
->type
;
176 if (type
== INTEL_OUTPUT_DP_MST
) {
177 struct intel_digital_port
*intel_dig_port
= enc_to_mst(encoder
)->primary
;
178 return intel_dig_port
->port
;
179 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
180 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
181 struct intel_digital_port
*intel_dig_port
=
182 enc_to_dig_port(encoder
);
183 return intel_dig_port
->port
;
185 } else if (type
== INTEL_OUTPUT_ANALOG
) {
189 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
195 * Starting with Haswell, DDI port buffers must be programmed with correct
196 * values in advance. The buffer values are different for FDI and DP modes,
197 * but the HDMI/DVI fields are shared among those. So we program the DDI
198 * in either FDI or DP modes only, as HDMI connections will work with both
201 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
205 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
207 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
208 const struct ddi_buf_trans
*ddi_translations_fdi
;
209 const struct ddi_buf_trans
*ddi_translations_dp
;
210 const struct ddi_buf_trans
*ddi_translations_edp
;
211 const struct ddi_buf_trans
*ddi_translations_hdmi
;
212 const struct ddi_buf_trans
*ddi_translations
;
214 if (IS_SKYLAKE(dev
)) {
215 ddi_translations_fdi
= NULL
;
216 ddi_translations_dp
= skl_ddi_translations_dp
;
217 n_dp_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
218 if (dev_priv
->vbt
.edp_low_vswing
) {
219 ddi_translations_edp
= skl_ddi_translations_edp
;
220 n_edp_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
222 ddi_translations_edp
= skl_ddi_translations_dp
;
223 n_edp_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
226 ddi_translations_hdmi
= skl_ddi_translations_hdmi
;
227 n_hdmi_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
228 hdmi_default_entry
= 7;
229 } else if (IS_BROADWELL(dev
)) {
230 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
231 ddi_translations_dp
= bdw_ddi_translations_dp
;
232 ddi_translations_edp
= bdw_ddi_translations_edp
;
233 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
234 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
235 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
236 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
237 hdmi_default_entry
= 7;
238 } else if (IS_HASWELL(dev
)) {
239 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
240 ddi_translations_dp
= hsw_ddi_translations_dp
;
241 ddi_translations_edp
= hsw_ddi_translations_dp
;
242 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
243 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
244 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
245 hdmi_default_entry
= 6;
247 WARN(1, "ddi translation table missing\n");
248 ddi_translations_edp
= bdw_ddi_translations_dp
;
249 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
250 ddi_translations_dp
= bdw_ddi_translations_dp
;
251 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
252 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
253 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
254 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
255 hdmi_default_entry
= 7;
260 ddi_translations
= ddi_translations_edp
;
261 size
= n_edp_entries
;
265 ddi_translations
= ddi_translations_dp
;
269 if (intel_dp_is_edp(dev
, PORT_D
)) {
270 ddi_translations
= ddi_translations_edp
;
271 size
= n_edp_entries
;
273 ddi_translations
= ddi_translations_dp
;
278 if (ddi_translations_fdi
)
279 ddi_translations
= ddi_translations_fdi
;
281 ddi_translations
= ddi_translations_dp
;
288 for (i
= 0, reg
= DDI_BUF_TRANS(port
); i
< size
; i
++) {
289 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
291 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
295 /* Choose a good default if VBT is badly populated */
296 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
297 hdmi_level
>= n_hdmi_entries
)
298 hdmi_level
= hdmi_default_entry
;
300 /* Entry 9 is for HDMI: */
301 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
303 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
307 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
308 * mode and port E for FDI.
310 void intel_prepare_ddi(struct drm_device
*dev
)
317 for (port
= PORT_A
; port
<= PORT_E
; port
++)
318 intel_prepare_ddi_buffers(dev
, port
);
321 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
324 uint32_t reg
= DDI_BUF_CTL(port
);
327 for (i
= 0; i
< 16; i
++) {
329 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
332 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
335 /* Starting with Haswell, different DDI ports can work in FDI mode for
336 * connection to the PCH-located connectors. For this, it is necessary to train
337 * both the DDI port and PCH receiver for the desired DDI buffer settings.
339 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
340 * please note that when FDI mode is active on DDI E, it shares 2 lines with
341 * DDI A (which is used for eDP)
344 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
346 struct drm_device
*dev
= crtc
->dev
;
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
349 u32 temp
, i
, rx_ctl_val
;
351 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
352 * mode set "sequence for CRT port" document:
353 * - TP1 to TP2 time with the default value
356 * WaFDIAutoLinkSetTimingOverrride:hsw
358 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
359 FDI_RX_PWRDN_LANE0_VAL(2) |
360 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
362 /* Enable the PCH Receiver FDI PLL */
363 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
365 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
366 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
367 POSTING_READ(_FDI_RXA_CTL
);
370 /* Switch from Rawclk to PCDclk */
371 rx_ctl_val
|= FDI_PCDCLK
;
372 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
374 /* Configure Port Clock Select */
375 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
376 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
378 /* Start the training iterating through available voltages and emphasis,
379 * testing each value twice. */
380 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
381 /* Configure DP_TP_CTL with auto-training */
382 I915_WRITE(DP_TP_CTL(PORT_E
),
383 DP_TP_CTL_FDI_AUTOTRAIN
|
384 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
385 DP_TP_CTL_LINK_TRAIN_PAT1
|
388 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
389 * DDI E does not support port reversal, the functionality is
390 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
391 * port reversal bit */
392 I915_WRITE(DDI_BUF_CTL(PORT_E
),
394 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
395 DDI_BUF_TRANS_SELECT(i
/ 2));
396 POSTING_READ(DDI_BUF_CTL(PORT_E
));
400 /* Program PCH FDI Receiver TU */
401 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
403 /* Enable PCH FDI Receiver with auto-training */
404 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
405 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
406 POSTING_READ(_FDI_RXA_CTL
);
408 /* Wait for FDI receiver lane calibration */
411 /* Unset FDI_RX_MISC pwrdn lanes */
412 temp
= I915_READ(_FDI_RXA_MISC
);
413 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
414 I915_WRITE(_FDI_RXA_MISC
, temp
);
415 POSTING_READ(_FDI_RXA_MISC
);
417 /* Wait for FDI auto training time */
420 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
421 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
422 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
424 /* Enable normal pixel sending for FDI */
425 I915_WRITE(DP_TP_CTL(PORT_E
),
426 DP_TP_CTL_FDI_AUTOTRAIN
|
427 DP_TP_CTL_LINK_TRAIN_NORMAL
|
428 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
434 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
435 temp
&= ~DDI_BUF_CTL_ENABLE
;
436 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
437 POSTING_READ(DDI_BUF_CTL(PORT_E
));
439 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
440 temp
= I915_READ(DP_TP_CTL(PORT_E
));
441 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
442 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
443 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
444 POSTING_READ(DP_TP_CTL(PORT_E
));
446 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
448 rx_ctl_val
&= ~FDI_RX_ENABLE
;
449 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
450 POSTING_READ(_FDI_RXA_CTL
);
452 /* Reset FDI_RX_MISC pwrdn lanes */
453 temp
= I915_READ(_FDI_RXA_MISC
);
454 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
455 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
456 I915_WRITE(_FDI_RXA_MISC
, temp
);
457 POSTING_READ(_FDI_RXA_MISC
);
460 DRM_ERROR("FDI link training failed!\n");
463 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
465 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
466 struct intel_digital_port
*intel_dig_port
=
467 enc_to_dig_port(&encoder
->base
);
469 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
470 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
471 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
475 static struct intel_encoder
*
476 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
478 struct drm_device
*dev
= crtc
->dev
;
479 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
480 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
481 int num_encoders
= 0;
483 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
488 if (num_encoders
!= 1)
489 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
490 pipe_name(intel_crtc
->pipe
));
496 static struct intel_encoder
*
497 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
499 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
500 struct intel_encoder
*ret
= NULL
;
501 struct drm_atomic_state
*state
;
502 int num_encoders
= 0;
505 state
= crtc_state
->base
.state
;
507 for (i
= 0; i
< state
->num_connector
; i
++) {
508 if (!state
->connectors
[i
] ||
509 state
->connector_states
[i
]->crtc
!= crtc_state
->base
.crtc
)
512 ret
= to_intel_encoder(state
->connector_states
[i
]->best_encoder
);
516 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
517 pipe_name(crtc
->pipe
));
524 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
530 /* Constraints for PLL good behavior */
536 #define abs_diff(a, b) ({ \
537 typeof(a) __a = (a); \
538 typeof(b) __b = (b); \
539 (void) (&__a == &__b); \
540 __a > __b ? (__a - __b) : (__b - __a); })
546 static unsigned wrpll_get_budget_for_freq(int clock
)
620 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
621 unsigned r2
, unsigned n2
, unsigned p
,
622 struct wrpll_rnp
*best
)
624 uint64_t a
, b
, c
, d
, diff
, diff_best
;
626 /* No best (r,n,p) yet */
635 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
639 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
642 * and we would like delta <= budget.
644 * If the discrepancy is above the PPM-based budget, always prefer to
645 * improve upon the previous solution. However, if you're within the
646 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
648 a
= freq2k
* budget
* p
* r2
;
649 b
= freq2k
* budget
* best
->p
* best
->r2
;
650 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
651 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
652 LC_FREQ_2K
* best
->n2
);
654 d
= 1000000 * diff_best
;
656 if (a
< c
&& b
< d
) {
657 /* If both are above the budget, pick the closer */
658 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
663 } else if (a
>= c
&& b
< d
) {
664 /* If A is below the threshold but B is above it? Update. */
668 } else if (a
>= c
&& b
>= d
) {
669 /* Both are below the limit, so pick the higher n2/(r2*r2) */
670 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
676 /* Otherwise a < c && b >= d, do nothing */
679 static int intel_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
682 int refclk
= LC_FREQ
;
686 wrpll
= I915_READ(reg
);
687 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
689 case WRPLL_PLL_NON_SSC
:
691 * We could calculate spread here, but our checking
692 * code only cares about 5% accuracy, and spread is a max of
697 case WRPLL_PLL_LCPLL
:
701 WARN(1, "bad wrpll refclk\n");
705 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
706 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
707 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
709 /* Convert to KHz, p & r have a fixed point portion */
710 return (refclk
* n
* 100) / (p
* r
);
713 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
716 uint32_t cfgcr1_reg
, cfgcr2_reg
;
717 uint32_t cfgcr1_val
, cfgcr2_val
;
718 uint32_t p0
, p1
, p2
, dco_freq
;
720 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
721 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
723 cfgcr1_val
= I915_READ(cfgcr1_reg
);
724 cfgcr2_val
= I915_READ(cfgcr2_reg
);
726 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
727 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
729 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
730 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
736 case DPLL_CFGCR2_PDIV_1
:
739 case DPLL_CFGCR2_PDIV_2
:
742 case DPLL_CFGCR2_PDIV_3
:
745 case DPLL_CFGCR2_PDIV_7
:
751 case DPLL_CFGCR2_KDIV_5
:
754 case DPLL_CFGCR2_KDIV_2
:
757 case DPLL_CFGCR2_KDIV_3
:
760 case DPLL_CFGCR2_KDIV_1
:
765 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
767 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
770 return dco_freq
/ (p0
* p1
* p2
* 5);
774 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
775 struct intel_crtc_state
*pipe_config
)
777 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
779 uint32_t dpll_ctl1
, dpll
;
781 dpll
= pipe_config
->ddi_pll_sel
;
783 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
785 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
786 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
788 link_clock
= dpll_ctl1
& DPLL_CRTL1_LINK_RATE_MASK(dpll
);
789 link_clock
>>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll
);
791 switch (link_clock
) {
792 case DPLL_CRTL1_LINK_RATE_810
:
795 case DPLL_CRTL1_LINK_RATE_1080
:
798 case DPLL_CRTL1_LINK_RATE_1350
:
801 case DPLL_CRTL1_LINK_RATE_1620
:
804 case DPLL_CRTL1_LINK_RATE_2160
:
807 case DPLL_CRTL1_LINK_RATE_2700
:
811 WARN(1, "Unsupported link rate\n");
817 pipe_config
->port_clock
= link_clock
;
819 if (pipe_config
->has_dp_encoder
)
820 pipe_config
->base
.adjusted_mode
.crtc_clock
=
821 intel_dotclock_calculate(pipe_config
->port_clock
,
822 &pipe_config
->dp_m_n
);
824 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
827 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
828 struct intel_crtc_state
*pipe_config
)
830 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
834 val
= pipe_config
->ddi_pll_sel
;
835 switch (val
& PORT_CLK_SEL_MASK
) {
836 case PORT_CLK_SEL_LCPLL_810
:
839 case PORT_CLK_SEL_LCPLL_1350
:
842 case PORT_CLK_SEL_LCPLL_2700
:
845 case PORT_CLK_SEL_WRPLL1
:
846 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
848 case PORT_CLK_SEL_WRPLL2
:
849 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
851 case PORT_CLK_SEL_SPLL
:
852 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
853 if (pll
== SPLL_PLL_FREQ_810MHz
)
855 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
857 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
860 WARN(1, "bad spll freq\n");
865 WARN(1, "bad port clock sel\n");
869 pipe_config
->port_clock
= link_clock
* 2;
871 if (pipe_config
->has_pch_encoder
)
872 pipe_config
->base
.adjusted_mode
.crtc_clock
=
873 intel_dotclock_calculate(pipe_config
->port_clock
,
874 &pipe_config
->fdi_m_n
);
875 else if (pipe_config
->has_dp_encoder
)
876 pipe_config
->base
.adjusted_mode
.crtc_clock
=
877 intel_dotclock_calculate(pipe_config
->port_clock
,
878 &pipe_config
->dp_m_n
);
880 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
883 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
884 struct intel_crtc_state
*pipe_config
)
886 struct drm_device
*dev
= encoder
->base
.dev
;
888 if (INTEL_INFO(dev
)->gen
<= 8)
889 hsw_ddi_clock_get(encoder
, pipe_config
);
891 skl_ddi_clock_get(encoder
, pipe_config
);
895 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
896 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
900 struct wrpll_rnp best
= { 0, 0, 0 };
903 freq2k
= clock
/ 100;
905 budget
= wrpll_get_budget_for_freq(clock
);
907 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
908 * and directly pass the LC PLL to it. */
909 if (freq2k
== 5400000) {
917 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
920 * We want R so that REF_MIN <= Ref <= REF_MAX.
921 * Injecting R2 = 2 * R gives:
922 * REF_MAX * r2 > LC_FREQ * 2 and
923 * REF_MIN * r2 < LC_FREQ * 2
925 * Which means the desired boundaries for r2 are:
926 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
929 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
930 r2
<= LC_FREQ
* 2 / REF_MIN
;
934 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
936 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
937 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
938 * VCO_MAX * r2 > n2 * LC_FREQ and
939 * VCO_MIN * r2 < n2 * LC_FREQ)
941 * Which means the desired boundaries for n2 are:
942 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
944 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
945 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
948 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
949 wrpll_update_rnp(freq2k
, budget
,
960 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
961 struct intel_crtc_state
*crtc_state
,
962 struct intel_encoder
*intel_encoder
,
965 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
966 struct intel_shared_dpll
*pll
;
970 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
972 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
973 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
974 WRPLL_DIVIDER_POST(p
);
976 crtc_state
->dpll_hw_state
.wrpll
= val
;
978 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
980 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
981 pipe_name(intel_crtc
->pipe
));
985 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
991 struct skl_wrpll_params
{
992 uint32_t dco_fraction
;
993 uint32_t dco_integer
;
998 uint32_t central_freq
;
1002 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1003 struct skl_wrpll_params
*wrpll_params
)
1005 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1006 uint64_t dco_central_freq
[3] = {8400000000ULL,
1009 uint32_t min_dco_deviation
= 400;
1010 uint32_t min_dco_index
= 3;
1011 uint32_t P0
[4] = {1, 2, 3, 7};
1012 uint32_t P2
[4] = {1, 2, 3, 5};
1014 uint32_t candidate_p
= 0;
1015 uint32_t candidate_p0
[3] = {0}, candidate_p1
[3] = {0};
1016 uint32_t candidate_p2
[3] = {0};
1017 uint32_t dco_central_freq_deviation
[3];
1018 uint32_t i
, P1
, k
, dco_count
;
1019 bool retry_with_odd
= false;
1022 /* Determine P0, P1 or P2 */
1023 for (dco_count
= 0; dco_count
< 3; dco_count
++) {
1026 div64_u64(dco_central_freq
[dco_count
], afe_clock
);
1027 if (retry_with_odd
== false)
1028 candidate_p
= (candidate_p
% 2 == 0 ?
1029 candidate_p
: candidate_p
+ 1);
1031 for (P1
= 1; P1
< candidate_p
; P1
++) {
1032 for (i
= 0; i
< 4; i
++) {
1033 if (!(P0
[i
] != 1 || P1
== 1))
1036 for (k
= 0; k
< 4; k
++) {
1037 if (P1
!= 1 && P2
[k
] != 2)
1040 if (candidate_p
== P0
[i
] * P1
* P2
[k
]) {
1041 /* Found possible P0, P1, P2 */
1043 candidate_p0
[dco_count
] = P0
[i
];
1044 candidate_p1
[dco_count
] = P1
;
1045 candidate_p2
[dco_count
] = P2
[k
];
1055 dco_central_freq_deviation
[dco_count
] =
1057 abs_diff((candidate_p
* afe_clock
),
1058 dco_central_freq
[dco_count
]),
1059 dco_central_freq
[dco_count
]);
1061 if (dco_central_freq_deviation
[dco_count
] <
1062 min_dco_deviation
) {
1064 dco_central_freq_deviation
[dco_count
];
1065 min_dco_index
= dco_count
;
1069 if (min_dco_index
> 2 && dco_count
== 2) {
1070 retry_with_odd
= true;
1075 if (min_dco_index
> 2) {
1076 WARN(1, "No valid values found for the given pixel clock\n");
1078 wrpll_params
->central_freq
= dco_central_freq
[min_dco_index
];
1080 switch (dco_central_freq
[min_dco_index
]) {
1082 wrpll_params
->central_freq
= 0;
1085 wrpll_params
->central_freq
= 1;
1088 wrpll_params
->central_freq
= 3;
1091 switch (candidate_p0
[min_dco_index
]) {
1093 wrpll_params
->pdiv
= 0;
1096 wrpll_params
->pdiv
= 1;
1099 wrpll_params
->pdiv
= 2;
1102 wrpll_params
->pdiv
= 4;
1105 WARN(1, "Incorrect PDiv\n");
1108 switch (candidate_p2
[min_dco_index
]) {
1110 wrpll_params
->kdiv
= 0;
1113 wrpll_params
->kdiv
= 1;
1116 wrpll_params
->kdiv
= 2;
1119 wrpll_params
->kdiv
= 3;
1122 WARN(1, "Incorrect KDiv\n");
1125 wrpll_params
->qdiv_ratio
= candidate_p1
[min_dco_index
];
1126 wrpll_params
->qdiv_mode
=
1127 (wrpll_params
->qdiv_ratio
== 1) ? 0 : 1;
1129 dco_freq
= candidate_p0
[min_dco_index
] *
1130 candidate_p1
[min_dco_index
] *
1131 candidate_p2
[min_dco_index
] * afe_clock
;
1134 * Intermediate values are in Hz.
1135 * Divide by MHz to match bsepc
1137 wrpll_params
->dco_integer
= div_u64(dco_freq
, (24 * MHz(1)));
1138 wrpll_params
->dco_fraction
=
1139 div_u64(((div_u64(dco_freq
, 24) -
1140 wrpll_params
->dco_integer
* MHz(1)) * 0x8000), MHz(1));
1147 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1148 struct intel_crtc_state
*crtc_state
,
1149 struct intel_encoder
*intel_encoder
,
1152 struct intel_shared_dpll
*pll
;
1153 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1156 * See comment in intel_dpll_hw_state to understand why we always use 0
1157 * as the DPLL id in this function.
1160 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1162 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1163 struct skl_wrpll_params wrpll_params
= { 0, };
1165 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1167 skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
);
1169 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1170 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1171 wrpll_params
.dco_integer
;
1173 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1174 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1175 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1176 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1177 wrpll_params
.central_freq
;
1178 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1179 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1180 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1182 switch (intel_dp
->link_bw
) {
1183 case DP_LINK_BW_1_62
:
1184 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
, 0);
1186 case DP_LINK_BW_2_7
:
1187 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
, 0);
1189 case DP_LINK_BW_5_4
:
1190 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
, 0);
1194 cfgcr1
= cfgcr2
= 0;
1198 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1199 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1200 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1202 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1204 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1205 pipe_name(intel_crtc
->pipe
));
1209 /* shared DPLL id 0 is DPLL 1 */
1210 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1216 * Tries to find a *shared* PLL for the CRTC and store it in
1217 * intel_crtc->ddi_pll_sel.
1219 * For private DPLLs, compute_config() should do the selection for us. This
1220 * function should be folded into compute_config() eventually.
1222 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1223 struct intel_crtc_state
*crtc_state
)
1225 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1226 struct intel_encoder
*intel_encoder
=
1227 intel_ddi_get_crtc_new_encoder(crtc_state
);
1228 int clock
= crtc_state
->port_clock
;
1230 if (IS_SKYLAKE(dev
))
1231 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1232 intel_encoder
, clock
);
1234 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1235 intel_encoder
, clock
);
1238 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1240 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1242 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1243 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1244 int type
= intel_encoder
->type
;
1247 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1248 temp
= TRANS_MSA_SYNC_CLK
;
1249 switch (intel_crtc
->config
->pipe_bpp
) {
1251 temp
|= TRANS_MSA_6_BPC
;
1254 temp
|= TRANS_MSA_8_BPC
;
1257 temp
|= TRANS_MSA_10_BPC
;
1260 temp
|= TRANS_MSA_12_BPC
;
1265 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1269 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1271 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1272 struct drm_device
*dev
= crtc
->dev
;
1273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1274 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1276 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1278 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1280 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1281 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1284 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1286 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1287 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1288 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1289 struct drm_device
*dev
= crtc
->dev
;
1290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1291 enum pipe pipe
= intel_crtc
->pipe
;
1292 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1293 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1294 int type
= intel_encoder
->type
;
1297 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1298 temp
= TRANS_DDI_FUNC_ENABLE
;
1299 temp
|= TRANS_DDI_SELECT_PORT(port
);
1301 switch (intel_crtc
->config
->pipe_bpp
) {
1303 temp
|= TRANS_DDI_BPC_6
;
1306 temp
|= TRANS_DDI_BPC_8
;
1309 temp
|= TRANS_DDI_BPC_10
;
1312 temp
|= TRANS_DDI_BPC_12
;
1318 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1319 temp
|= TRANS_DDI_PVSYNC
;
1320 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1321 temp
|= TRANS_DDI_PHSYNC
;
1323 if (cpu_transcoder
== TRANSCODER_EDP
) {
1326 /* On Haswell, can only use the always-on power well for
1327 * eDP when not using the panel fitter, and when not
1328 * using motion blur mitigation (which we don't
1330 if (IS_HASWELL(dev
) &&
1331 (intel_crtc
->config
->pch_pfit
.enabled
||
1332 intel_crtc
->config
->pch_pfit
.force_thru
))
1333 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1335 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1338 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1341 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1349 if (type
== INTEL_OUTPUT_HDMI
) {
1350 if (intel_crtc
->config
->has_hdmi_sink
)
1351 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1353 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1355 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1356 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1357 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1359 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1360 type
== INTEL_OUTPUT_EDP
) {
1361 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1363 if (intel_dp
->is_mst
) {
1364 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1366 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1368 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1369 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1370 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1372 if (intel_dp
->is_mst
) {
1373 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1375 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1377 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1379 WARN(1, "Invalid encoder type %d for pipe %c\n",
1380 intel_encoder
->type
, pipe_name(pipe
));
1383 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1386 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1387 enum transcoder cpu_transcoder
)
1389 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1390 uint32_t val
= I915_READ(reg
);
1392 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1393 val
|= TRANS_DDI_PORT_NONE
;
1394 I915_WRITE(reg
, val
);
1397 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1399 struct drm_device
*dev
= intel_connector
->base
.dev
;
1400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1401 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1402 int type
= intel_connector
->base
.connector_type
;
1403 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1405 enum transcoder cpu_transcoder
;
1406 enum intel_display_power_domain power_domain
;
1409 power_domain
= intel_display_port_power_domain(intel_encoder
);
1410 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1413 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1417 cpu_transcoder
= TRANSCODER_EDP
;
1419 cpu_transcoder
= (enum transcoder
) pipe
;
1421 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1423 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1424 case TRANS_DDI_MODE_SELECT_HDMI
:
1425 case TRANS_DDI_MODE_SELECT_DVI
:
1426 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1428 case TRANS_DDI_MODE_SELECT_DP_SST
:
1429 if (type
== DRM_MODE_CONNECTOR_eDP
)
1431 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1432 case TRANS_DDI_MODE_SELECT_DP_MST
:
1433 /* if the transcoder is in MST state then
1434 * connector isn't connected */
1437 case TRANS_DDI_MODE_SELECT_FDI
:
1438 return (type
== DRM_MODE_CONNECTOR_VGA
);
1445 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1448 struct drm_device
*dev
= encoder
->base
.dev
;
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1450 enum port port
= intel_ddi_get_encoder_port(encoder
);
1451 enum intel_display_power_domain power_domain
;
1455 power_domain
= intel_display_port_power_domain(encoder
);
1456 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1459 tmp
= I915_READ(DDI_BUF_CTL(port
));
1461 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1464 if (port
== PORT_A
) {
1465 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1467 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1468 case TRANS_DDI_EDP_INPUT_A_ON
:
1469 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1472 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1475 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1482 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1483 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1485 if ((tmp
& TRANS_DDI_PORT_MASK
)
1486 == TRANS_DDI_SELECT_PORT(port
)) {
1487 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
1496 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1501 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1503 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1504 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1505 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1506 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1507 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1509 if (cpu_transcoder
!= TRANSCODER_EDP
)
1510 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1511 TRANS_CLK_SEL_PORT(port
));
1514 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1516 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1517 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1519 if (cpu_transcoder
!= TRANSCODER_EDP
)
1520 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1521 TRANS_CLK_SEL_DISABLED
);
1524 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1526 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1527 struct drm_device
*dev
= encoder
->dev
;
1528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1529 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1530 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1531 int type
= intel_encoder
->type
;
1533 if (type
== INTEL_OUTPUT_EDP
) {
1534 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1535 intel_edp_panel_on(intel_dp
);
1538 if (IS_SKYLAKE(dev
)) {
1539 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
1543 * DPLL0 is used for eDP and is the only "private" DPLL (as
1544 * opposed to shared) on SKL
1546 if (type
== INTEL_OUTPUT_EDP
) {
1547 WARN_ON(dpll
!= SKL_DPLL0
);
1549 val
= I915_READ(DPLL_CTRL1
);
1551 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
1552 DPLL_CTRL1_SSC(dpll
) |
1553 DPLL_CRTL1_LINK_RATE_MASK(dpll
));
1554 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
1556 I915_WRITE(DPLL_CTRL1
, val
);
1557 POSTING_READ(DPLL_CTRL1
);
1560 /* DDI -> PLL mapping */
1561 val
= I915_READ(DPLL_CTRL2
);
1563 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
1564 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
1565 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
1566 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
1568 I915_WRITE(DPLL_CTRL2
, val
);
1570 } else if (INTEL_INFO(dev
)->gen
< 9) {
1571 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1572 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
1575 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1576 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1578 intel_ddi_init_dp_buf_reg(intel_encoder
);
1580 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1581 intel_dp_start_link_train(intel_dp
);
1582 intel_dp_complete_link_train(intel_dp
);
1583 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
1584 intel_dp_stop_link_train(intel_dp
);
1585 } else if (type
== INTEL_OUTPUT_HDMI
) {
1586 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1588 intel_hdmi
->set_infoframes(encoder
,
1589 crtc
->config
->has_hdmi_sink
,
1590 &crtc
->config
->base
.adjusted_mode
);
1594 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1596 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1597 struct drm_device
*dev
= encoder
->dev
;
1598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1599 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1600 int type
= intel_encoder
->type
;
1604 val
= I915_READ(DDI_BUF_CTL(port
));
1605 if (val
& DDI_BUF_CTL_ENABLE
) {
1606 val
&= ~DDI_BUF_CTL_ENABLE
;
1607 I915_WRITE(DDI_BUF_CTL(port
), val
);
1611 val
= I915_READ(DP_TP_CTL(port
));
1612 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1613 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1614 I915_WRITE(DP_TP_CTL(port
), val
);
1617 intel_wait_ddi_buf_idle(dev_priv
, port
);
1619 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1620 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1621 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1622 intel_edp_panel_vdd_on(intel_dp
);
1623 intel_edp_panel_off(intel_dp
);
1626 if (IS_SKYLAKE(dev
))
1627 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
1628 DPLL_CTRL2_DDI_CLK_OFF(port
)));
1629 else if (INTEL_INFO(dev
)->gen
< 9)
1630 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1633 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1635 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1636 struct drm_crtc
*crtc
= encoder
->crtc
;
1637 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1638 struct drm_device
*dev
= encoder
->dev
;
1639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1640 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1641 int type
= intel_encoder
->type
;
1643 if (type
== INTEL_OUTPUT_HDMI
) {
1644 struct intel_digital_port
*intel_dig_port
=
1645 enc_to_dig_port(encoder
);
1647 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1648 * are ignored so nothing special needs to be done besides
1649 * enabling the port.
1651 I915_WRITE(DDI_BUF_CTL(port
),
1652 intel_dig_port
->saved_port_bits
|
1653 DDI_BUF_CTL_ENABLE
);
1654 } else if (type
== INTEL_OUTPUT_EDP
) {
1655 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1657 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
1658 intel_dp_stop_link_train(intel_dp
);
1660 intel_edp_backlight_on(intel_dp
);
1661 intel_psr_enable(intel_dp
);
1662 intel_edp_drrs_enable(intel_dp
);
1665 if (intel_crtc
->config
->has_audio
) {
1666 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1667 intel_audio_codec_enable(intel_encoder
);
1671 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1673 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1674 struct drm_crtc
*crtc
= encoder
->crtc
;
1675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1676 int type
= intel_encoder
->type
;
1677 struct drm_device
*dev
= encoder
->dev
;
1678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 if (intel_crtc
->config
->has_audio
) {
1681 intel_audio_codec_disable(intel_encoder
);
1682 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1685 if (type
== INTEL_OUTPUT_EDP
) {
1686 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1688 intel_edp_drrs_disable(intel_dp
);
1689 intel_psr_disable(intel_dp
);
1690 intel_edp_backlight_off(intel_dp
);
1694 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1695 struct intel_shared_dpll
*pll
)
1697 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
1698 POSTING_READ(WRPLL_CTL(pll
->id
));
1702 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1703 struct intel_shared_dpll
*pll
)
1707 val
= I915_READ(WRPLL_CTL(pll
->id
));
1708 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
1709 POSTING_READ(WRPLL_CTL(pll
->id
));
1712 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1713 struct intel_shared_dpll
*pll
,
1714 struct intel_dpll_hw_state
*hw_state
)
1718 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1721 val
= I915_READ(WRPLL_CTL(pll
->id
));
1722 hw_state
->wrpll
= val
;
1724 return val
& WRPLL_PLL_ENABLE
;
1727 static const char * const hsw_ddi_pll_names
[] = {
1732 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1736 dev_priv
->num_shared_dpll
= 2;
1738 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1739 dev_priv
->shared_dplls
[i
].id
= i
;
1740 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
1741 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
1742 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
1743 dev_priv
->shared_dplls
[i
].get_hw_state
=
1744 hsw_ddi_pll_get_hw_state
;
1748 static const char * const skl_ddi_pll_names
[] = {
1754 struct skl_dpll_regs
{
1755 u32 ctl
, cfgcr1
, cfgcr2
;
1758 /* this array is indexed by the *shared* pll id */
1759 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
1763 .cfgcr1
= DPLL1_CFGCR1
,
1764 .cfgcr2
= DPLL1_CFGCR2
,
1769 .cfgcr1
= DPLL2_CFGCR1
,
1770 .cfgcr2
= DPLL2_CFGCR2
,
1775 .cfgcr1
= DPLL3_CFGCR1
,
1776 .cfgcr2
= DPLL3_CFGCR2
,
1780 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1781 struct intel_shared_dpll
*pll
)
1785 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1787 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1790 val
= I915_READ(DPLL_CTRL1
);
1792 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
1793 DPLL_CRTL1_LINK_RATE_MASK(dpll
));
1794 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
1796 I915_WRITE(DPLL_CTRL1
, val
);
1797 POSTING_READ(DPLL_CTRL1
);
1799 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
1800 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
1801 POSTING_READ(regs
[pll
->id
].cfgcr1
);
1802 POSTING_READ(regs
[pll
->id
].cfgcr2
);
1804 /* the enable bit is always bit 31 */
1805 I915_WRITE(regs
[pll
->id
].ctl
,
1806 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
1808 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
1809 DRM_ERROR("DPLL %d not locked\n", dpll
);
1812 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1813 struct intel_shared_dpll
*pll
)
1815 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1817 /* the enable bit is always bit 31 */
1818 I915_WRITE(regs
[pll
->id
].ctl
,
1819 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
1820 POSTING_READ(regs
[pll
->id
].ctl
);
1823 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1824 struct intel_shared_dpll
*pll
,
1825 struct intel_dpll_hw_state
*hw_state
)
1829 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1831 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1834 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1837 val
= I915_READ(regs
[pll
->id
].ctl
);
1838 if (!(val
& LCPLL_PLL_ENABLE
))
1841 val
= I915_READ(DPLL_CTRL1
);
1842 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
1844 /* avoid reading back stale values if HDMI mode is not enabled */
1845 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1846 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
1847 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
1853 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1857 dev_priv
->num_shared_dpll
= 3;
1859 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1860 dev_priv
->shared_dplls
[i
].id
= i
;
1861 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
1862 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
1863 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
1864 dev_priv
->shared_dplls
[i
].get_hw_state
=
1865 skl_ddi_pll_get_hw_state
;
1869 static void broxton_phy_init(struct drm_i915_private
*dev_priv
,
1875 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
1876 val
|= GT_DISPLAY_POWER_ON(phy
);
1877 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
1879 /* Considering 10ms timeout until BSpec is updated */
1880 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy
)) & PHY_POWER_GOOD
, 10))
1881 DRM_ERROR("timeout during PHY%d power on\n", phy
);
1883 for (port
= (phy
== DPIO_PHY0
? PORT_B
: PORT_A
);
1884 port
<= (phy
== DPIO_PHY0
? PORT_C
: PORT_A
); port
++) {
1887 for (lane
= 0; lane
< 4; lane
++) {
1888 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
1890 * Note that on CHV this flag is called UPAR, but has
1891 * the same function.
1893 val
&= ~LATENCY_OPTIM
;
1895 val
|= LATENCY_OPTIM
;
1897 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
1901 /* Program PLL Rcomp code offset */
1902 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
1903 val
&= ~IREF0RC_OFFSET_MASK
;
1904 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
1905 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
1907 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
1908 val
&= ~IREF1RC_OFFSET_MASK
;
1909 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
1910 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
1912 /* Program power gating */
1913 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
1914 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
1916 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
1918 if (phy
== DPIO_PHY0
) {
1919 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
1920 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
1921 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
1924 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
1925 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
1927 * On PHY1 disable power on the second channel, since no port is
1928 * connected there. On PHY0 both channels have a port, so leave it
1930 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1931 * power down the second channel on PHY0 as well.
1933 if (phy
== DPIO_PHY1
)
1934 val
|= OCL2_LDOFUSE_PWR_DIS
;
1935 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
1937 if (phy
== DPIO_PHY0
) {
1940 * PHY0 isn't connected to an RCOMP resistor so copy over
1941 * the corresponding calibrated value from PHY1, and disable
1942 * the automatic calibration on PHY0.
1944 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
,
1946 DRM_ERROR("timeout waiting for PHY1 GRC\n");
1948 val
= I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1
));
1949 val
= (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
1950 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
1951 val
<< GRC_CODE_SLOW_SHIFT
|
1953 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
1955 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
1956 val
|= GRC_DIS
| GRC_RDY_OVRD
;
1957 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
1960 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
1961 val
|= COMMON_RESET_DIS
;
1962 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
1965 void broxton_ddi_phy_init(struct drm_device
*dev
)
1967 /* Enable PHY1 first since it provides Rcomp for PHY0 */
1968 broxton_phy_init(dev
->dev_private
, DPIO_PHY1
);
1969 broxton_phy_init(dev
->dev_private
, DPIO_PHY0
);
1972 static void broxton_phy_uninit(struct drm_i915_private
*dev_priv
,
1977 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
1978 val
&= ~COMMON_RESET_DIS
;
1979 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
1982 void broxton_ddi_phy_uninit(struct drm_device
*dev
)
1984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 broxton_phy_uninit(dev_priv
, DPIO_PHY1
);
1987 broxton_phy_uninit(dev_priv
, DPIO_PHY0
);
1989 /* FIXME: do this in broxton_phy_uninit per phy */
1990 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, 0);
1993 static const char * const bxt_ddi_pll_names
[] = {
1999 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2000 struct intel_shared_dpll
*pll
)
2003 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2005 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2006 temp
&= ~PORT_PLL_REF_SEL
;
2007 /* Non-SSC reference */
2008 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2010 /* Disable 10 bit clock */
2011 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2012 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2013 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2016 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2017 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
2018 temp
|= pll
->config
.hw_state
.ebb0
;
2019 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
2021 /* Write M2 integer */
2022 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
2023 temp
&= ~PORT_PLL_M2_MASK
;
2024 temp
|= pll
->config
.hw_state
.pll0
;
2025 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
2028 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
2029 temp
&= ~PORT_PLL_N_MASK
;
2030 temp
|= pll
->config
.hw_state
.pll1
;
2031 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
2033 /* Write M2 fraction */
2034 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
2035 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
2036 temp
|= pll
->config
.hw_state
.pll2
;
2037 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
2039 /* Write M2 fraction enable */
2040 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
2041 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
2042 temp
|= pll
->config
.hw_state
.pll3
;
2043 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
2046 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
2047 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
2048 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
2049 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
2050 temp
|= pll
->config
.hw_state
.pll6
;
2051 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
2053 /* Write calibration val */
2054 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
2055 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
2056 temp
|= pll
->config
.hw_state
.pll8
;
2057 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
2060 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
2061 * specification update.
2064 /* Recalibrate with new settings */
2065 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2066 temp
|= PORT_PLL_RECALIBRATE
;
2067 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2068 /* Enable 10 bit clock */
2069 temp
|= PORT_PLL_10BIT_CLK_ENABLE
;
2070 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2073 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2074 temp
|= PORT_PLL_ENABLE
;
2075 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2076 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2078 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
2079 PORT_PLL_LOCK
), 200))
2080 DRM_ERROR("PLL %d not locked\n", port
);
2083 * While we write to the group register to program all lanes at once we
2084 * can read only lane registers and we pick lanes 0/1 for that.
2086 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2087 temp
&= ~LANE_STAGGER_MASK
;
2088 temp
&= ~LANESTAGGER_STRAP_OVRD
;
2089 temp
|= pll
->config
.hw_state
.pcsdw12
;
2090 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
2093 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2094 struct intel_shared_dpll
*pll
)
2096 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2099 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2100 temp
&= ~PORT_PLL_ENABLE
;
2101 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2102 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2105 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2106 struct intel_shared_dpll
*pll
,
2107 struct intel_dpll_hw_state
*hw_state
)
2109 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2112 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2115 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2116 if (!(val
& PORT_PLL_ENABLE
))
2119 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2120 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
2121 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
2122 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
2123 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
2124 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
2125 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
2127 * While we write to the group register to program all lanes at once we
2128 * can read only lane registers. We configure all lanes the same way, so
2129 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2131 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2132 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
) != hw_state
->pcsdw12
))
2133 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2135 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
2140 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2144 dev_priv
->num_shared_dpll
= 3;
2146 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2147 dev_priv
->shared_dplls
[i
].id
= i
;
2148 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
2149 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
2150 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
2151 dev_priv
->shared_dplls
[i
].get_hw_state
=
2152 bxt_ddi_pll_get_hw_state
;
2156 void intel_ddi_pll_init(struct drm_device
*dev
)
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2159 uint32_t val
= I915_READ(LCPLL_CTL
);
2161 if (IS_SKYLAKE(dev
))
2162 skl_shared_dplls_init(dev_priv
);
2163 else if (IS_BROXTON(dev
))
2164 bxt_shared_dplls_init(dev_priv
);
2166 hsw_shared_dplls_init(dev_priv
);
2168 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
2169 dev_priv
->display
.get_display_clock_speed(dev
));
2171 if (IS_SKYLAKE(dev
)) {
2172 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
2173 DRM_ERROR("LCPLL1 is disabled\n");
2174 } else if (IS_BROXTON(dev
)) {
2175 broxton_init_cdclk(dev
);
2176 broxton_ddi_phy_init(dev
);
2179 * The LCPLL register should be turned on by the BIOS. For now
2180 * let's just check its state and print errors in case
2181 * something is wrong. Don't even try to turn it on.
2184 if (val
& LCPLL_CD_SOURCE_FCLK
)
2185 DRM_ERROR("CDCLK source is not LCPLL\n");
2187 if (val
& LCPLL_PLL_DISABLE
)
2188 DRM_ERROR("LCPLL is disabled\n");
2192 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
2194 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2195 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2196 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
2197 enum port port
= intel_dig_port
->port
;
2201 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2202 val
= I915_READ(DDI_BUF_CTL(port
));
2203 if (val
& DDI_BUF_CTL_ENABLE
) {
2204 val
&= ~DDI_BUF_CTL_ENABLE
;
2205 I915_WRITE(DDI_BUF_CTL(port
), val
);
2209 val
= I915_READ(DP_TP_CTL(port
));
2210 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2211 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2212 I915_WRITE(DP_TP_CTL(port
), val
);
2213 POSTING_READ(DP_TP_CTL(port
));
2216 intel_wait_ddi_buf_idle(dev_priv
, port
);
2219 val
= DP_TP_CTL_ENABLE
|
2220 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2221 if (intel_dp
->is_mst
)
2222 val
|= DP_TP_CTL_MODE_MST
;
2224 val
|= DP_TP_CTL_MODE_SST
;
2225 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2226 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2228 I915_WRITE(DP_TP_CTL(port
), val
);
2229 POSTING_READ(DP_TP_CTL(port
));
2231 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2232 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
2233 POSTING_READ(DDI_BUF_CTL(port
));
2238 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
2240 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2241 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2244 intel_ddi_post_disable(intel_encoder
);
2246 val
= I915_READ(_FDI_RXA_CTL
);
2247 val
&= ~FDI_RX_ENABLE
;
2248 I915_WRITE(_FDI_RXA_CTL
, val
);
2250 val
= I915_READ(_FDI_RXA_MISC
);
2251 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
2252 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2253 I915_WRITE(_FDI_RXA_MISC
, val
);
2255 val
= I915_READ(_FDI_RXA_CTL
);
2257 I915_WRITE(_FDI_RXA_CTL
, val
);
2259 val
= I915_READ(_FDI_RXA_CTL
);
2260 val
&= ~FDI_RX_PLL_ENABLE
;
2261 I915_WRITE(_FDI_RXA_CTL
, val
);
2264 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
2266 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
2267 int type
= intel_dig_port
->base
.type
;
2269 if (type
!= INTEL_OUTPUT_DISPLAYPORT
&&
2270 type
!= INTEL_OUTPUT_EDP
&&
2271 type
!= INTEL_OUTPUT_UNKNOWN
) {
2275 intel_dp_hot_plug(intel_encoder
);
2278 void intel_ddi_get_config(struct intel_encoder
*encoder
,
2279 struct intel_crtc_state
*pipe_config
)
2281 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
2282 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2283 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2284 struct intel_hdmi
*intel_hdmi
;
2285 u32 temp
, flags
= 0;
2287 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
2288 if (temp
& TRANS_DDI_PHSYNC
)
2289 flags
|= DRM_MODE_FLAG_PHSYNC
;
2291 flags
|= DRM_MODE_FLAG_NHSYNC
;
2292 if (temp
& TRANS_DDI_PVSYNC
)
2293 flags
|= DRM_MODE_FLAG_PVSYNC
;
2295 flags
|= DRM_MODE_FLAG_NVSYNC
;
2297 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2299 switch (temp
& TRANS_DDI_BPC_MASK
) {
2300 case TRANS_DDI_BPC_6
:
2301 pipe_config
->pipe_bpp
= 18;
2303 case TRANS_DDI_BPC_8
:
2304 pipe_config
->pipe_bpp
= 24;
2306 case TRANS_DDI_BPC_10
:
2307 pipe_config
->pipe_bpp
= 30;
2309 case TRANS_DDI_BPC_12
:
2310 pipe_config
->pipe_bpp
= 36;
2316 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
2317 case TRANS_DDI_MODE_SELECT_HDMI
:
2318 pipe_config
->has_hdmi_sink
= true;
2319 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2321 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
2322 pipe_config
->has_infoframe
= true;
2324 case TRANS_DDI_MODE_SELECT_DVI
:
2325 case TRANS_DDI_MODE_SELECT_FDI
:
2327 case TRANS_DDI_MODE_SELECT_DP_SST
:
2328 case TRANS_DDI_MODE_SELECT_DP_MST
:
2329 pipe_config
->has_dp_encoder
= true;
2330 intel_dp_get_m_n(intel_crtc
, pipe_config
);
2336 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
2337 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
2338 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
2339 pipe_config
->has_audio
= true;
2342 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
2343 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2345 * This is a big fat ugly hack.
2347 * Some machines in UEFI boot mode provide us a VBT that has 18
2348 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2349 * unknown we fail to light up. Yet the same BIOS boots up with
2350 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2351 * max, not what it tells us to use.
2353 * Note: This will still be broken if the eDP panel is not lit
2354 * up by the BIOS, and thus we can't get the mode at module
2357 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2358 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2359 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2362 intel_ddi_clock_get(encoder
, pipe_config
);
2365 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
2367 /* HDMI has nothing special to destroy, so we can go with this. */
2368 intel_dp_encoder_destroy(encoder
);
2371 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
2372 struct intel_crtc_state
*pipe_config
)
2374 int type
= encoder
->type
;
2375 int port
= intel_ddi_get_encoder_port(encoder
);
2377 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
2380 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
2382 if (type
== INTEL_OUTPUT_HDMI
)
2383 return intel_hdmi_compute_config(encoder
, pipe_config
);
2385 return intel_dp_compute_config(encoder
, pipe_config
);
2388 static const struct drm_encoder_funcs intel_ddi_funcs
= {
2389 .destroy
= intel_ddi_destroy
,
2392 static struct intel_connector
*
2393 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
2395 struct intel_connector
*connector
;
2396 enum port port
= intel_dig_port
->port
;
2398 connector
= intel_connector_alloc();
2402 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
2403 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
2411 static struct intel_connector
*
2412 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
2414 struct intel_connector
*connector
;
2415 enum port port
= intel_dig_port
->port
;
2417 connector
= intel_connector_alloc();
2421 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
2422 intel_hdmi_init_connector(intel_dig_port
, connector
);
2427 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
2429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2430 struct intel_digital_port
*intel_dig_port
;
2431 struct intel_encoder
*intel_encoder
;
2432 struct drm_encoder
*encoder
;
2433 bool init_hdmi
, init_dp
;
2435 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
2436 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
2437 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
2438 if (!init_dp
&& !init_hdmi
) {
2439 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2445 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2446 if (!intel_dig_port
)
2449 intel_encoder
= &intel_dig_port
->base
;
2450 encoder
= &intel_encoder
->base
;
2452 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
2453 DRM_MODE_ENCODER_TMDS
);
2455 intel_encoder
->compute_config
= intel_ddi_compute_config
;
2456 intel_encoder
->enable
= intel_enable_ddi
;
2457 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2458 intel_encoder
->disable
= intel_disable_ddi
;
2459 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2460 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2461 intel_encoder
->get_config
= intel_ddi_get_config
;
2463 intel_dig_port
->port
= port
;
2464 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
2465 (DDI_BUF_PORT_REVERSAL
|
2468 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
2469 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2470 intel_encoder
->cloneable
= 0;
2471 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
2474 if (!intel_ddi_init_dp_connector(intel_dig_port
))
2477 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
2478 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
2481 /* In theory we don't need the encoder->type check, but leave it just in
2482 * case we have some really bad VBTs... */
2483 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
2484 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
2491 drm_encoder_cleanup(encoder
);
2492 kfree(intel_dig_port
);