2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
34 u8 i_boost
; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 },
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp
[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x80007011, 0x000000CD, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp
[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x0 },
162 { 0x80009010, 0x000000C0, 0x3 },
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 },
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp
[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp
[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x80006012, 0x000000CD, 0x1 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi
[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x80007011, 0x000000CB, 0x3 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x80006013, 0x000000C0, 0x3 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
251 struct bxt_ddi_buf_trans
{
252 u32 margin
; /* swing value */
253 u32 scale
; /* scale value */
254 u32 enable
; /* scale enable */
256 bool default_index
; /* true if the entry represents default value */
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp
[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
304 static void bxt_ddi_vswing_sequence(struct drm_i915_private
*dev_priv
,
305 u32 level
, enum port port
, int type
);
307 static void ddi_get_encoder_port(struct intel_encoder
*intel_encoder
,
308 struct intel_digital_port
**dig_port
,
311 struct drm_encoder
*encoder
= &intel_encoder
->base
;
313 switch (intel_encoder
->type
) {
314 case INTEL_OUTPUT_DP_MST
:
315 *dig_port
= enc_to_mst(encoder
)->primary
;
316 *port
= (*dig_port
)->port
;
319 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder
->type
);
320 /* fallthrough and treat as unknown */
321 case INTEL_OUTPUT_DISPLAYPORT
:
322 case INTEL_OUTPUT_EDP
:
323 case INTEL_OUTPUT_HDMI
:
324 case INTEL_OUTPUT_UNKNOWN
:
325 *dig_port
= enc_to_dig_port(encoder
);
326 *port
= (*dig_port
)->port
;
328 case INTEL_OUTPUT_ANALOG
:
335 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
337 struct intel_digital_port
*dig_port
;
340 ddi_get_encoder_port(intel_encoder
, &dig_port
, &port
);
345 static const struct ddi_buf_trans
*
346 skl_get_buf_trans_dp(struct drm_i915_private
*dev_priv
, int *n_entries
)
348 if (IS_SKL_ULX(dev_priv
) || IS_KBL_ULX(dev_priv
)) {
349 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_dp
);
350 return skl_y_ddi_translations_dp
;
351 } else if (IS_SKL_ULT(dev_priv
) || IS_KBL_ULT(dev_priv
)) {
352 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
353 return skl_u_ddi_translations_dp
;
355 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
356 return skl_ddi_translations_dp
;
360 static const struct ddi_buf_trans
*
361 skl_get_buf_trans_edp(struct drm_i915_private
*dev_priv
, int *n_entries
)
363 if (dev_priv
->vbt
.edp
.low_vswing
) {
364 if (IS_SKL_ULX(dev_priv
) || IS_KBL_ULX(dev_priv
)) {
365 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_edp
);
366 return skl_y_ddi_translations_edp
;
367 } else if (IS_SKL_ULT(dev_priv
) || IS_KBL_ULT(dev_priv
)) {
368 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_edp
);
369 return skl_u_ddi_translations_edp
;
371 *n_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
372 return skl_ddi_translations_edp
;
376 return skl_get_buf_trans_dp(dev_priv
, n_entries
);
379 static const struct ddi_buf_trans
*
380 skl_get_buf_trans_hdmi(struct drm_i915_private
*dev_priv
, int *n_entries
)
382 if (IS_SKL_ULX(dev_priv
) || IS_KBL_ULX(dev_priv
)) {
383 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_hdmi
);
384 return skl_y_ddi_translations_hdmi
;
386 *n_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
387 return skl_ddi_translations_hdmi
;
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
398 void intel_prepare_ddi_buffer(struct intel_encoder
*encoder
)
400 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
402 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
406 const struct ddi_buf_trans
*ddi_translations_fdi
;
407 const struct ddi_buf_trans
*ddi_translations_dp
;
408 const struct ddi_buf_trans
*ddi_translations_edp
;
409 const struct ddi_buf_trans
*ddi_translations_hdmi
;
410 const struct ddi_buf_trans
*ddi_translations
;
412 port
= intel_ddi_get_encoder_port(encoder
);
413 hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
415 if (IS_BROXTON(dev_priv
)) {
416 if (encoder
->type
!= INTEL_OUTPUT_HDMI
)
419 /* Vswing programming for HDMI */
420 bxt_ddi_vswing_sequence(dev_priv
, hdmi_level
, port
,
425 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
426 ddi_translations_fdi
= NULL
;
427 ddi_translations_dp
=
428 skl_get_buf_trans_dp(dev_priv
, &n_dp_entries
);
429 ddi_translations_edp
=
430 skl_get_buf_trans_edp(dev_priv
, &n_edp_entries
);
431 ddi_translations_hdmi
=
432 skl_get_buf_trans_hdmi(dev_priv
, &n_hdmi_entries
);
433 hdmi_default_entry
= 8;
434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
||
436 dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
)
439 if (WARN_ON(encoder
->type
== INTEL_OUTPUT_EDP
&&
440 port
!= PORT_A
&& port
!= PORT_E
&&
443 } else if (IS_BROADWELL(dev_priv
)) {
444 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
445 ddi_translations_dp
= bdw_ddi_translations_dp
;
447 if (dev_priv
->vbt
.edp
.low_vswing
) {
448 ddi_translations_edp
= bdw_ddi_translations_edp
;
449 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
451 ddi_translations_edp
= bdw_ddi_translations_dp
;
452 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
455 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
457 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
458 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
459 hdmi_default_entry
= 7;
460 } else if (IS_HASWELL(dev_priv
)) {
461 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
462 ddi_translations_dp
= hsw_ddi_translations_dp
;
463 ddi_translations_edp
= hsw_ddi_translations_dp
;
464 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
465 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
466 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
467 hdmi_default_entry
= 6;
469 WARN(1, "ddi translation table missing\n");
470 ddi_translations_edp
= bdw_ddi_translations_dp
;
471 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
472 ddi_translations_dp
= bdw_ddi_translations_dp
;
473 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
474 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
475 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
476 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
477 hdmi_default_entry
= 7;
480 switch (encoder
->type
) {
481 case INTEL_OUTPUT_EDP
:
482 ddi_translations
= ddi_translations_edp
;
483 size
= n_edp_entries
;
485 case INTEL_OUTPUT_DISPLAYPORT
:
486 case INTEL_OUTPUT_HDMI
:
487 ddi_translations
= ddi_translations_dp
;
490 case INTEL_OUTPUT_ANALOG
:
491 ddi_translations
= ddi_translations_fdi
;
498 for (i
= 0; i
< size
; i
++) {
499 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
500 ddi_translations
[i
].trans1
| iboost_bit
);
501 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
502 ddi_translations
[i
].trans2
);
505 if (encoder
->type
!= INTEL_OUTPUT_HDMI
)
508 /* Choose a good default if VBT is badly populated */
509 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
510 hdmi_level
>= n_hdmi_entries
)
511 hdmi_level
= hdmi_default_entry
;
513 /* Entry 9 is for HDMI: */
514 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
515 ddi_translations_hdmi
[hdmi_level
].trans1
| iboost_bit
);
516 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
517 ddi_translations_hdmi
[hdmi_level
].trans2
);
520 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
523 i915_reg_t reg
= DDI_BUF_CTL(port
);
526 for (i
= 0; i
< 16; i
++) {
528 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
531 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
534 /* Starting with Haswell, different DDI ports can work in FDI mode for
535 * connection to the PCH-located connectors. For this, it is necessary to train
536 * both the DDI port and PCH receiver for the desired DDI buffer settings.
538 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
539 * please note that when FDI mode is active on DDI E, it shares 2 lines with
540 * DDI A (which is used for eDP)
543 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
545 struct drm_device
*dev
= crtc
->dev
;
546 struct drm_i915_private
*dev_priv
= to_i915(dev
);
547 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
548 struct intel_encoder
*encoder
;
549 u32 temp
, i
, rx_ctl_val
;
551 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
552 WARN_ON(encoder
->type
!= INTEL_OUTPUT_ANALOG
);
553 intel_prepare_ddi_buffer(encoder
);
556 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
557 * mode set "sequence for CRT port" document:
558 * - TP1 to TP2 time with the default value
561 * WaFDIAutoLinkSetTimingOverrride:hsw
563 I915_WRITE(FDI_RX_MISC(PIPE_A
), FDI_RX_PWRDN_LANE1_VAL(2) |
564 FDI_RX_PWRDN_LANE0_VAL(2) |
565 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
567 /* Enable the PCH Receiver FDI PLL */
568 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
570 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
571 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
572 POSTING_READ(FDI_RX_CTL(PIPE_A
));
575 /* Switch from Rawclk to PCDclk */
576 rx_ctl_val
|= FDI_PCDCLK
;
577 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
579 /* Configure Port Clock Select */
580 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
581 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
583 /* Start the training iterating through available voltages and emphasis,
584 * testing each value twice. */
585 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
586 /* Configure DP_TP_CTL with auto-training */
587 I915_WRITE(DP_TP_CTL(PORT_E
),
588 DP_TP_CTL_FDI_AUTOTRAIN
|
589 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
590 DP_TP_CTL_LINK_TRAIN_PAT1
|
593 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
594 * DDI E does not support port reversal, the functionality is
595 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
596 * port reversal bit */
597 I915_WRITE(DDI_BUF_CTL(PORT_E
),
599 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
600 DDI_BUF_TRANS_SELECT(i
/ 2));
601 POSTING_READ(DDI_BUF_CTL(PORT_E
));
605 /* Program PCH FDI Receiver TU */
606 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A
), TU_SIZE(64));
608 /* Enable PCH FDI Receiver with auto-training */
609 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
610 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
611 POSTING_READ(FDI_RX_CTL(PIPE_A
));
613 /* Wait for FDI receiver lane calibration */
616 /* Unset FDI_RX_MISC pwrdn lanes */
617 temp
= I915_READ(FDI_RX_MISC(PIPE_A
));
618 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
619 I915_WRITE(FDI_RX_MISC(PIPE_A
), temp
);
620 POSTING_READ(FDI_RX_MISC(PIPE_A
));
622 /* Wait for FDI auto training time */
625 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
626 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
627 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
632 * Leave things enabled even if we failed to train FDI.
633 * Results in less fireworks from the state checker.
635 if (i
== ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2 - 1) {
636 DRM_ERROR("FDI link training failed!\n");
640 rx_ctl_val
&= ~FDI_RX_ENABLE
;
641 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
642 POSTING_READ(FDI_RX_CTL(PIPE_A
));
644 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
645 temp
&= ~DDI_BUF_CTL_ENABLE
;
646 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
647 POSTING_READ(DDI_BUF_CTL(PORT_E
));
649 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
650 temp
= I915_READ(DP_TP_CTL(PORT_E
));
651 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
652 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
653 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
654 POSTING_READ(DP_TP_CTL(PORT_E
));
656 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
658 /* Reset FDI_RX_MISC pwrdn lanes */
659 temp
= I915_READ(FDI_RX_MISC(PIPE_A
));
660 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
661 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
662 I915_WRITE(FDI_RX_MISC(PIPE_A
), temp
);
663 POSTING_READ(FDI_RX_MISC(PIPE_A
));
666 /* Enable normal pixel sending for FDI */
667 I915_WRITE(DP_TP_CTL(PORT_E
),
668 DP_TP_CTL_FDI_AUTOTRAIN
|
669 DP_TP_CTL_LINK_TRAIN_NORMAL
|
670 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
674 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
676 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
677 struct intel_digital_port
*intel_dig_port
=
678 enc_to_dig_port(&encoder
->base
);
680 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
681 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
682 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
685 static struct intel_encoder
*
686 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
688 struct drm_device
*dev
= crtc
->dev
;
689 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
690 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
691 int num_encoders
= 0;
693 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
698 if (num_encoders
!= 1)
699 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
700 pipe_name(intel_crtc
->pipe
));
706 struct intel_encoder
*
707 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
709 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
710 struct intel_encoder
*ret
= NULL
;
711 struct drm_atomic_state
*state
;
712 struct drm_connector
*connector
;
713 struct drm_connector_state
*connector_state
;
714 int num_encoders
= 0;
717 state
= crtc_state
->base
.state
;
719 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
720 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
723 ret
= to_intel_encoder(connector_state
->best_encoder
);
727 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
728 pipe_name(crtc
->pipe
));
736 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
739 int refclk
= LC_FREQ
;
743 wrpll
= I915_READ(reg
);
744 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
746 case WRPLL_PLL_NON_SSC
:
748 * We could calculate spread here, but our checking
749 * code only cares about 5% accuracy, and spread is a max of
754 case WRPLL_PLL_LCPLL
:
758 WARN(1, "bad wrpll refclk\n");
762 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
763 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
764 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
766 /* Convert to KHz, p & r have a fixed point portion */
767 return (refclk
* n
* 100) / (p
* r
);
770 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
773 i915_reg_t cfgcr1_reg
, cfgcr2_reg
;
774 uint32_t cfgcr1_val
, cfgcr2_val
;
775 uint32_t p0
, p1
, p2
, dco_freq
;
777 cfgcr1_reg
= DPLL_CFGCR1(dpll
);
778 cfgcr2_reg
= DPLL_CFGCR2(dpll
);
780 cfgcr1_val
= I915_READ(cfgcr1_reg
);
781 cfgcr2_val
= I915_READ(cfgcr2_reg
);
783 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
784 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
786 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
787 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
793 case DPLL_CFGCR2_PDIV_1
:
796 case DPLL_CFGCR2_PDIV_2
:
799 case DPLL_CFGCR2_PDIV_3
:
802 case DPLL_CFGCR2_PDIV_7
:
808 case DPLL_CFGCR2_KDIV_5
:
811 case DPLL_CFGCR2_KDIV_2
:
814 case DPLL_CFGCR2_KDIV_3
:
817 case DPLL_CFGCR2_KDIV_1
:
822 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
824 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
827 return dco_freq
/ (p0
* p1
* p2
* 5);
830 static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config
)
834 if (pipe_config
->has_pch_encoder
)
835 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
836 &pipe_config
->fdi_m_n
);
837 else if (intel_crtc_has_dp_encoder(pipe_config
))
838 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
839 &pipe_config
->dp_m_n
);
840 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
== 36)
841 dotclock
= pipe_config
->port_clock
* 2 / 3;
843 dotclock
= pipe_config
->port_clock
;
845 if (pipe_config
->pixel_multiplier
)
846 dotclock
/= pipe_config
->pixel_multiplier
;
848 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
851 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
852 struct intel_crtc_state
*pipe_config
)
854 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
856 uint32_t dpll_ctl1
, dpll
;
858 dpll
= pipe_config
->ddi_pll_sel
;
860 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
862 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
863 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
865 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(dpll
);
866 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll
);
868 switch (link_clock
) {
869 case DPLL_CTRL1_LINK_RATE_810
:
872 case DPLL_CTRL1_LINK_RATE_1080
:
875 case DPLL_CTRL1_LINK_RATE_1350
:
878 case DPLL_CTRL1_LINK_RATE_1620
:
881 case DPLL_CTRL1_LINK_RATE_2160
:
884 case DPLL_CTRL1_LINK_RATE_2700
:
888 WARN(1, "Unsupported link rate\n");
894 pipe_config
->port_clock
= link_clock
;
896 ddi_dotclock_get(pipe_config
);
899 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
900 struct intel_crtc_state
*pipe_config
)
902 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
906 val
= pipe_config
->ddi_pll_sel
;
907 switch (val
& PORT_CLK_SEL_MASK
) {
908 case PORT_CLK_SEL_LCPLL_810
:
911 case PORT_CLK_SEL_LCPLL_1350
:
914 case PORT_CLK_SEL_LCPLL_2700
:
917 case PORT_CLK_SEL_WRPLL1
:
918 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL(0));
920 case PORT_CLK_SEL_WRPLL2
:
921 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL(1));
923 case PORT_CLK_SEL_SPLL
:
924 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
925 if (pll
== SPLL_PLL_FREQ_810MHz
)
927 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
929 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
932 WARN(1, "bad spll freq\n");
937 WARN(1, "bad port clock sel\n");
941 pipe_config
->port_clock
= link_clock
* 2;
943 ddi_dotclock_get(pipe_config
);
946 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
947 enum intel_dpll_id dpll
)
949 struct intel_shared_dpll
*pll
;
950 struct intel_dpll_hw_state
*state
;
953 /* For DDI ports we always use a shared PLL. */
954 if (WARN_ON(dpll
== DPLL_ID_PRIVATE
))
957 pll
= &dev_priv
->shared_dplls
[dpll
];
958 state
= &pll
->config
.hw_state
;
961 clock
.m2
= (state
->pll0
& PORT_PLL_M2_MASK
) << 22;
962 if (state
->pll3
& PORT_PLL_M2_FRAC_ENABLE
)
963 clock
.m2
|= state
->pll2
& PORT_PLL_M2_FRAC_MASK
;
964 clock
.n
= (state
->pll1
& PORT_PLL_N_MASK
) >> PORT_PLL_N_SHIFT
;
965 clock
.p1
= (state
->ebb0
& PORT_PLL_P1_MASK
) >> PORT_PLL_P1_SHIFT
;
966 clock
.p2
= (state
->ebb0
& PORT_PLL_P2_MASK
) >> PORT_PLL_P2_SHIFT
;
968 return chv_calc_dpll_params(100000, &clock
);
971 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
972 struct intel_crtc_state
*pipe_config
)
974 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
975 enum port port
= intel_ddi_get_encoder_port(encoder
);
976 uint32_t dpll
= port
;
978 pipe_config
->port_clock
= bxt_calc_pll_link(dev_priv
, dpll
);
980 ddi_dotclock_get(pipe_config
);
983 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
984 struct intel_crtc_state
*pipe_config
)
986 struct drm_device
*dev
= encoder
->base
.dev
;
988 if (INTEL_INFO(dev
)->gen
<= 8)
989 hsw_ddi_clock_get(encoder
, pipe_config
);
990 else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
991 skl_ddi_clock_get(encoder
, pipe_config
);
992 else if (IS_BROXTON(dev
))
993 bxt_ddi_clock_get(encoder
, pipe_config
);
997 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
998 struct intel_crtc_state
*crtc_state
,
999 struct intel_encoder
*intel_encoder
)
1001 struct intel_shared_dpll
*pll
;
1003 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
,
1006 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1007 pipe_name(intel_crtc
->pipe
));
1013 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1014 struct intel_crtc_state
*crtc_state
,
1015 struct intel_encoder
*intel_encoder
)
1017 struct intel_shared_dpll
*pll
;
1019 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
, intel_encoder
);
1021 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022 pipe_name(intel_crtc
->pipe
));
1030 bxt_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1031 struct intel_crtc_state
*crtc_state
,
1032 struct intel_encoder
*intel_encoder
)
1034 return !!intel_get_shared_dpll(intel_crtc
, crtc_state
, intel_encoder
);
1038 * Tries to find a *shared* PLL for the CRTC and store it in
1039 * intel_crtc->ddi_pll_sel.
1041 * For private DPLLs, compute_config() should do the selection for us. This
1042 * function should be folded into compute_config() eventually.
1044 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1045 struct intel_crtc_state
*crtc_state
)
1047 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1048 struct intel_encoder
*intel_encoder
=
1049 intel_ddi_get_crtc_new_encoder(crtc_state
);
1051 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
1052 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1054 else if (IS_BROXTON(dev
))
1055 return bxt_ddi_pll_select(intel_crtc
, crtc_state
,
1058 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1062 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1064 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
1065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1066 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1067 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1068 int type
= intel_encoder
->type
;
1071 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1072 WARN_ON(transcoder_is_dsi(cpu_transcoder
));
1074 temp
= TRANS_MSA_SYNC_CLK
;
1075 switch (intel_crtc
->config
->pipe_bpp
) {
1077 temp
|= TRANS_MSA_6_BPC
;
1080 temp
|= TRANS_MSA_8_BPC
;
1083 temp
|= TRANS_MSA_10_BPC
;
1086 temp
|= TRANS_MSA_12_BPC
;
1091 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1095 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1097 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1098 struct drm_device
*dev
= crtc
->dev
;
1099 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1100 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1102 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1104 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1106 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1107 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1110 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1112 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1113 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1114 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1115 struct drm_device
*dev
= crtc
->dev
;
1116 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1117 enum pipe pipe
= intel_crtc
->pipe
;
1118 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1119 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1120 int type
= intel_encoder
->type
;
1123 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1124 temp
= TRANS_DDI_FUNC_ENABLE
;
1125 temp
|= TRANS_DDI_SELECT_PORT(port
);
1127 switch (intel_crtc
->config
->pipe_bpp
) {
1129 temp
|= TRANS_DDI_BPC_6
;
1132 temp
|= TRANS_DDI_BPC_8
;
1135 temp
|= TRANS_DDI_BPC_10
;
1138 temp
|= TRANS_DDI_BPC_12
;
1144 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1145 temp
|= TRANS_DDI_PVSYNC
;
1146 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1147 temp
|= TRANS_DDI_PHSYNC
;
1149 if (cpu_transcoder
== TRANSCODER_EDP
) {
1152 /* On Haswell, can only use the always-on power well for
1153 * eDP when not using the panel fitter, and when not
1154 * using motion blur mitigation (which we don't
1156 if (IS_HASWELL(dev
) &&
1157 (intel_crtc
->config
->pch_pfit
.enabled
||
1158 intel_crtc
->config
->pch_pfit
.force_thru
))
1159 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1161 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1164 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1167 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1175 if (type
== INTEL_OUTPUT_HDMI
) {
1176 if (intel_crtc
->config
->has_hdmi_sink
)
1177 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1179 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1181 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1182 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1183 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1185 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1186 type
== INTEL_OUTPUT_EDP
) {
1187 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1189 if (intel_dp
->is_mst
) {
1190 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1192 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1194 temp
|= DDI_PORT_WIDTH(intel_crtc
->config
->lane_count
);
1195 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1196 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1198 if (intel_dp
->is_mst
) {
1199 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1201 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1203 temp
|= DDI_PORT_WIDTH(intel_crtc
->config
->lane_count
);
1205 WARN(1, "Invalid encoder type %d for pipe %c\n",
1206 intel_encoder
->type
, pipe_name(pipe
));
1209 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1212 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1213 enum transcoder cpu_transcoder
)
1215 i915_reg_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1216 uint32_t val
= I915_READ(reg
);
1218 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1219 val
|= TRANS_DDI_PORT_NONE
;
1220 I915_WRITE(reg
, val
);
1223 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1225 struct drm_device
*dev
= intel_connector
->base
.dev
;
1226 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1227 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1228 int type
= intel_connector
->base
.connector_type
;
1229 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1231 enum transcoder cpu_transcoder
;
1232 enum intel_display_power_domain power_domain
;
1236 power_domain
= intel_display_port_power_domain(intel_encoder
);
1237 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
1240 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
)) {
1246 cpu_transcoder
= TRANSCODER_EDP
;
1248 cpu_transcoder
= (enum transcoder
) pipe
;
1250 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1252 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1253 case TRANS_DDI_MODE_SELECT_HDMI
:
1254 case TRANS_DDI_MODE_SELECT_DVI
:
1255 ret
= type
== DRM_MODE_CONNECTOR_HDMIA
;
1258 case TRANS_DDI_MODE_SELECT_DP_SST
:
1259 ret
= type
== DRM_MODE_CONNECTOR_eDP
||
1260 type
== DRM_MODE_CONNECTOR_DisplayPort
;
1263 case TRANS_DDI_MODE_SELECT_DP_MST
:
1264 /* if the transcoder is in MST state then
1265 * connector isn't connected */
1269 case TRANS_DDI_MODE_SELECT_FDI
:
1270 ret
= type
== DRM_MODE_CONNECTOR_VGA
;
1279 intel_display_power_put(dev_priv
, power_domain
);
1284 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1287 struct drm_device
*dev
= encoder
->base
.dev
;
1288 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1289 enum port port
= intel_ddi_get_encoder_port(encoder
);
1290 enum intel_display_power_domain power_domain
;
1295 power_domain
= intel_display_port_power_domain(encoder
);
1296 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
1301 tmp
= I915_READ(DDI_BUF_CTL(port
));
1303 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1306 if (port
== PORT_A
) {
1307 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1309 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1310 case TRANS_DDI_EDP_INPUT_A_ON
:
1311 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1314 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1317 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1327 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1328 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1330 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(port
)) {
1331 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) ==
1332 TRANS_DDI_MODE_SELECT_DP_MST
)
1342 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1345 if (ret
&& IS_BROXTON(dev_priv
)) {
1346 tmp
= I915_READ(BXT_PHY_CTL(port
));
1347 if ((tmp
& (BXT_PHY_LANE_POWERDOWN_ACK
|
1348 BXT_PHY_LANE_ENABLED
)) != BXT_PHY_LANE_ENABLED
)
1349 DRM_ERROR("Port %c enabled but PHY powered down? "
1350 "(PHY_CTL %08x)\n", port_name(port
), tmp
);
1353 intel_display_power_put(dev_priv
, power_domain
);
1358 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1360 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1361 struct drm_device
*dev
= crtc
->dev
;
1362 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1363 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1364 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1365 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1367 if (cpu_transcoder
!= TRANSCODER_EDP
)
1368 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1369 TRANS_CLK_SEL_PORT(port
));
1372 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1374 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
1375 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1377 if (cpu_transcoder
!= TRANSCODER_EDP
)
1378 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1379 TRANS_CLK_SEL_DISABLED
);
1382 static void skl_ddi_set_iboost(struct drm_i915_private
*dev_priv
,
1383 u32 level
, enum port port
, int type
)
1385 const struct ddi_buf_trans
*ddi_translations
;
1387 uint8_t dp_iboost
, hdmi_iboost
;
1391 /* VBT may override standard boost values */
1392 dp_iboost
= dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
;
1393 hdmi_iboost
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
;
1395 if (type
== INTEL_OUTPUT_DISPLAYPORT
) {
1399 ddi_translations
= skl_get_buf_trans_dp(dev_priv
, &n_entries
);
1400 iboost
= ddi_translations
[level
].i_boost
;
1402 } else if (type
== INTEL_OUTPUT_EDP
) {
1406 ddi_translations
= skl_get_buf_trans_edp(dev_priv
, &n_entries
);
1408 if (WARN_ON(port
!= PORT_A
&&
1409 port
!= PORT_E
&& n_entries
> 9))
1412 iboost
= ddi_translations
[level
].i_boost
;
1414 } else if (type
== INTEL_OUTPUT_HDMI
) {
1416 iboost
= hdmi_iboost
;
1418 ddi_translations
= skl_get_buf_trans_hdmi(dev_priv
, &n_entries
);
1419 iboost
= ddi_translations
[level
].i_boost
;
1425 /* Make sure that the requested I_boost is valid */
1426 if (iboost
&& iboost
!= 0x1 && iboost
!= 0x3 && iboost
!= 0x7) {
1427 DRM_ERROR("Invalid I_boost value %u\n", iboost
);
1431 reg
= I915_READ(DISPIO_CR_TX_BMU_CR0
);
1432 reg
&= ~BALANCE_LEG_MASK(port
);
1433 reg
&= ~(1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
));
1436 reg
|= iboost
<< BALANCE_LEG_SHIFT(port
);
1438 reg
|= 1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
);
1440 I915_WRITE(DISPIO_CR_TX_BMU_CR0
, reg
);
1443 static void bxt_ddi_vswing_sequence(struct drm_i915_private
*dev_priv
,
1444 u32 level
, enum port port
, int type
)
1446 const struct bxt_ddi_buf_trans
*ddi_translations
;
1450 if (type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp
.low_vswing
) {
1451 n_entries
= ARRAY_SIZE(bxt_ddi_translations_edp
);
1452 ddi_translations
= bxt_ddi_translations_edp
;
1453 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
1454 || type
== INTEL_OUTPUT_EDP
) {
1455 n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
1456 ddi_translations
= bxt_ddi_translations_dp
;
1457 } else if (type
== INTEL_OUTPUT_HDMI
) {
1458 n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
1459 ddi_translations
= bxt_ddi_translations_hdmi
;
1461 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1466 /* Check if default value has to be used */
1467 if (level
>= n_entries
||
1468 (type
== INTEL_OUTPUT_HDMI
&& level
== HDMI_LEVEL_SHIFT_UNKNOWN
)) {
1469 for (i
= 0; i
< n_entries
; i
++) {
1470 if (ddi_translations
[i
].default_index
) {
1478 * While we write to the group register to program all lanes at once we
1479 * can read only lane registers and we pick lanes 0/1 for that.
1481 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
1482 val
&= ~(TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
);
1483 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
1485 val
= I915_READ(BXT_PORT_TX_DW2_LN0(port
));
1486 val
&= ~(MARGIN_000
| UNIQ_TRANS_SCALE
);
1487 val
|= ddi_translations
[level
].margin
<< MARGIN_000_SHIFT
|
1488 ddi_translations
[level
].scale
<< UNIQ_TRANS_SCALE_SHIFT
;
1489 I915_WRITE(BXT_PORT_TX_DW2_GRP(port
), val
);
1491 val
= I915_READ(BXT_PORT_TX_DW3_LN0(port
));
1492 val
&= ~SCALE_DCOMP_METHOD
;
1493 if (ddi_translations
[level
].enable
)
1494 val
|= SCALE_DCOMP_METHOD
;
1496 if ((val
& UNIQUE_TRANGE_EN_METHOD
) && !(val
& SCALE_DCOMP_METHOD
))
1497 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1499 I915_WRITE(BXT_PORT_TX_DW3_GRP(port
), val
);
1501 val
= I915_READ(BXT_PORT_TX_DW4_LN0(port
));
1502 val
&= ~DE_EMPHASIS
;
1503 val
|= ddi_translations
[level
].deemphasis
<< DEEMPH_SHIFT
;
1504 I915_WRITE(BXT_PORT_TX_DW4_GRP(port
), val
);
1506 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
1507 val
|= TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
;
1508 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
1511 static uint32_t translate_signal_level(int signal_levels
)
1515 switch (signal_levels
) {
1517 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1519 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
1522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
1525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
1528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
1532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
1535 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
1538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
1542 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
1545 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
1549 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
1557 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
)
1559 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1560 struct drm_i915_private
*dev_priv
= to_i915(dport
->base
.base
.dev
);
1561 struct intel_encoder
*encoder
= &dport
->base
;
1562 uint8_t train_set
= intel_dp
->train_set
[0];
1563 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1564 DP_TRAIN_PRE_EMPHASIS_MASK
);
1565 enum port port
= dport
->port
;
1568 level
= translate_signal_level(signal_levels
);
1570 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
1571 skl_ddi_set_iboost(dev_priv
, level
, port
, encoder
->type
);
1572 else if (IS_BROXTON(dev_priv
))
1573 bxt_ddi_vswing_sequence(dev_priv
, level
, port
, encoder
->type
);
1575 return DDI_BUF_TRANS_SELECT(level
);
1578 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
1579 const struct intel_crtc_state
*pipe_config
)
1581 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1582 enum port port
= intel_ddi_get_encoder_port(encoder
);
1584 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1585 uint32_t dpll
= pipe_config
->ddi_pll_sel
;
1588 /* DDI -> PLL mapping */
1589 val
= I915_READ(DPLL_CTRL2
);
1591 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
1592 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
1593 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
1594 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
1596 I915_WRITE(DPLL_CTRL2
, val
);
1598 } else if (INTEL_INFO(dev_priv
)->gen
< 9) {
1599 WARN_ON(pipe_config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1600 I915_WRITE(PORT_CLK_SEL(port
), pipe_config
->ddi_pll_sel
);
1604 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1606 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1607 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
1608 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1609 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1610 int type
= intel_encoder
->type
;
1612 if (type
== INTEL_OUTPUT_HDMI
) {
1613 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1615 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, true);
1618 intel_prepare_ddi_buffer(intel_encoder
);
1620 if (type
== INTEL_OUTPUT_EDP
) {
1621 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1622 intel_edp_panel_on(intel_dp
);
1625 intel_ddi_clk_select(intel_encoder
, crtc
->config
);
1627 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1628 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1630 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1632 intel_ddi_init_dp_buf_reg(intel_encoder
);
1634 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1635 intel_dp_start_link_train(intel_dp
);
1636 if (port
!= PORT_A
|| INTEL_INFO(dev_priv
)->gen
>= 9)
1637 intel_dp_stop_link_train(intel_dp
);
1638 } else if (type
== INTEL_OUTPUT_HDMI
) {
1639 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1641 intel_hdmi
->set_infoframes(encoder
,
1642 crtc
->config
->has_hdmi_sink
,
1643 &crtc
->config
->base
.adjusted_mode
);
1647 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1649 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1650 struct drm_device
*dev
= encoder
->dev
;
1651 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1652 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1653 int type
= intel_encoder
->type
;
1657 val
= I915_READ(DDI_BUF_CTL(port
));
1658 if (val
& DDI_BUF_CTL_ENABLE
) {
1659 val
&= ~DDI_BUF_CTL_ENABLE
;
1660 I915_WRITE(DDI_BUF_CTL(port
), val
);
1664 val
= I915_READ(DP_TP_CTL(port
));
1665 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1666 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1667 I915_WRITE(DP_TP_CTL(port
), val
);
1670 intel_wait_ddi_buf_idle(dev_priv
, port
);
1672 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1673 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1674 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1675 intel_edp_panel_vdd_on(intel_dp
);
1676 intel_edp_panel_off(intel_dp
);
1679 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
1680 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
1681 DPLL_CTRL2_DDI_CLK_OFF(port
)));
1682 else if (INTEL_INFO(dev
)->gen
< 9)
1683 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1685 if (type
== INTEL_OUTPUT_HDMI
) {
1686 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1688 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, false);
1692 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1694 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1695 struct drm_crtc
*crtc
= encoder
->crtc
;
1696 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1697 struct drm_device
*dev
= encoder
->dev
;
1698 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1699 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1700 int type
= intel_encoder
->type
;
1702 if (type
== INTEL_OUTPUT_HDMI
) {
1703 struct intel_digital_port
*intel_dig_port
=
1704 enc_to_dig_port(encoder
);
1706 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1707 * are ignored so nothing special needs to be done besides
1708 * enabling the port.
1710 I915_WRITE(DDI_BUF_CTL(port
),
1711 intel_dig_port
->saved_port_bits
|
1712 DDI_BUF_CTL_ENABLE
);
1713 } else if (type
== INTEL_OUTPUT_EDP
) {
1714 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1716 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
1717 intel_dp_stop_link_train(intel_dp
);
1719 intel_edp_backlight_on(intel_dp
);
1720 intel_psr_enable(intel_dp
);
1721 intel_edp_drrs_enable(intel_dp
);
1724 if (intel_crtc
->config
->has_audio
) {
1725 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1726 intel_audio_codec_enable(intel_encoder
);
1730 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1732 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1733 struct drm_crtc
*crtc
= encoder
->crtc
;
1734 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1735 int type
= intel_encoder
->type
;
1736 struct drm_device
*dev
= encoder
->dev
;
1737 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1739 if (intel_crtc
->config
->has_audio
) {
1740 intel_audio_codec_disable(intel_encoder
);
1741 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1744 if (type
== INTEL_OUTPUT_EDP
) {
1745 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1747 intel_edp_drrs_disable(intel_dp
);
1748 intel_psr_disable(intel_dp
);
1749 intel_edp_backlight_off(intel_dp
);
1753 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
1758 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON
) & GT_DISPLAY_POWER_ON(phy
)))
1761 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy
)) &
1762 (PHY_POWER_GOOD
| PHY_RESERVED
)) != PHY_POWER_GOOD
) {
1763 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1769 if (phy
== DPIO_PHY1
&&
1770 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
)) {
1771 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1776 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy
)) & COMMON_RESET_DIS
)) {
1777 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1783 for_each_port_masked(port
,
1784 phy
== DPIO_PHY0
? BIT(PORT_B
) | BIT(PORT_C
) :
1786 u32 tmp
= I915_READ(BXT_PHY_CTL(port
));
1788 if (tmp
& BXT_PHY_CMNLANE_POWERDOWN_ACK
) {
1789 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1790 "for port %c powered down "
1792 phy
, port_name(port
), tmp
);
1801 static u32
bxt_get_grc(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
)
1803 u32 val
= I915_READ(BXT_PORT_REF_DW6(phy
));
1805 return (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
1808 static void bxt_phy_wait_grc_done(struct drm_i915_private
*dev_priv
,
1811 if (intel_wait_for_register(dev_priv
,
1812 BXT_PORT_REF_DW3(phy
),
1815 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy
);
1818 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
)
1822 if (bxt_ddi_phy_is_enabled(dev_priv
, phy
)) {
1823 /* Still read out the GRC value for state verification */
1824 if (phy
== DPIO_PHY0
)
1825 dev_priv
->bxt_phy_grc
= bxt_get_grc(dev_priv
, phy
);
1827 if (bxt_ddi_phy_verify_state(dev_priv
, phy
)) {
1828 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1829 "won't reprogram it\n", phy
);
1834 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1835 "force reprogramming it\n", phy
);
1838 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
1839 val
|= GT_DISPLAY_POWER_ON(phy
);
1840 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
1843 * The PHY registers start out inaccessible and respond to reads with
1844 * all 1s. Eventually they become accessible as they power up, then
1845 * the reserved bit will give the default 0. Poll on the reserved bit
1846 * becoming 0 to find when the PHY is accessible.
1847 * HW team confirmed that the time to reach phypowergood status is
1848 * anywhere between 50 us and 100us.
1850 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy
)) &
1851 (PHY_RESERVED
| PHY_POWER_GOOD
)) == PHY_POWER_GOOD
), 100)) {
1852 DRM_ERROR("timeout during PHY%d power on\n", phy
);
1855 /* Program PLL Rcomp code offset */
1856 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
1857 val
&= ~IREF0RC_OFFSET_MASK
;
1858 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
1859 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
1861 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
1862 val
&= ~IREF1RC_OFFSET_MASK
;
1863 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
1864 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
1866 /* Program power gating */
1867 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
1868 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
1870 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
1872 if (phy
== DPIO_PHY0
) {
1873 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
1874 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
1875 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
1878 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
1879 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
1881 * On PHY1 disable power on the second channel, since no port is
1882 * connected there. On PHY0 both channels have a port, so leave it
1884 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1885 * power down the second channel on PHY0 as well.
1887 * FIXME: Clarify programming of the following, the register is
1888 * read-only with bit 6 fixed at 0 at least in stepping A.
1890 if (phy
== DPIO_PHY1
)
1891 val
|= OCL2_LDOFUSE_PWR_DIS
;
1892 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
1894 if (phy
== DPIO_PHY0
) {
1897 * PHY0 isn't connected to an RCOMP resistor so copy over
1898 * the corresponding calibrated value from PHY1, and disable
1899 * the automatic calibration on PHY0.
1901 val
= dev_priv
->bxt_phy_grc
= bxt_get_grc(dev_priv
, DPIO_PHY1
);
1902 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
1903 val
<< GRC_CODE_SLOW_SHIFT
|
1905 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
1907 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
1908 val
|= GRC_DIS
| GRC_RDY_OVRD
;
1909 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
1912 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
1913 val
|= COMMON_RESET_DIS
;
1914 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
1916 if (phy
== DPIO_PHY1
)
1917 bxt_phy_wait_grc_done(dev_priv
, DPIO_PHY1
);
1920 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
)
1924 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
1925 val
&= ~COMMON_RESET_DIS
;
1926 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
1928 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
1929 val
&= ~GT_DISPLAY_POWER_ON(phy
);
1930 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
1933 static bool __printf(6, 7)
1934 __phy_reg_verify_state(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1935 i915_reg_t reg
, u32 mask
, u32 expected
,
1936 const char *reg_fmt
, ...)
1938 struct va_format vaf
;
1942 val
= I915_READ(reg
);
1943 if ((val
& mask
) == expected
)
1946 va_start(args
, reg_fmt
);
1950 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1951 "current %08x, expected %08x (mask %08x)\n",
1952 phy
, &vaf
, reg
.reg
, val
, (val
& ~mask
) | expected
,
1960 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
1966 #define _CHK(reg, mask, exp, fmt, ...) \
1967 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
1970 if (!bxt_ddi_phy_is_enabled(dev_priv
, phy
))
1975 /* PLL Rcomp code offset */
1976 ok
&= _CHK(BXT_PORT_CL1CM_DW9(phy
),
1977 IREF0RC_OFFSET_MASK
, 0xe4 << IREF0RC_OFFSET_SHIFT
,
1978 "BXT_PORT_CL1CM_DW9(%d)", phy
);
1979 ok
&= _CHK(BXT_PORT_CL1CM_DW10(phy
),
1980 IREF1RC_OFFSET_MASK
, 0xe4 << IREF1RC_OFFSET_SHIFT
,
1981 "BXT_PORT_CL1CM_DW10(%d)", phy
);
1984 mask
= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
| SUS_CLK_CONFIG
;
1985 ok
&= _CHK(BXT_PORT_CL1CM_DW28(phy
), mask
, mask
,
1986 "BXT_PORT_CL1CM_DW28(%d)", phy
);
1988 if (phy
== DPIO_PHY0
)
1989 ok
&= _CHK(BXT_PORT_CL2CM_DW6_BC
,
1990 DW6_OLDO_DYN_PWR_DOWN_EN
, DW6_OLDO_DYN_PWR_DOWN_EN
,
1991 "BXT_PORT_CL2CM_DW6_BC");
1994 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
1995 * at least on stepping A this bit is read-only and fixed at 0.
1998 if (phy
== DPIO_PHY0
) {
1999 u32 grc_code
= dev_priv
->bxt_phy_grc
;
2001 grc_code
= grc_code
<< GRC_CODE_FAST_SHIFT
|
2002 grc_code
<< GRC_CODE_SLOW_SHIFT
|
2004 mask
= GRC_CODE_FAST_MASK
| GRC_CODE_SLOW_MASK
|
2006 ok
&= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0
), mask
, grc_code
,
2007 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0
);
2009 mask
= GRC_DIS
| GRC_RDY_OVRD
;
2010 ok
&= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0
), mask
, mask
,
2011 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0
);
2019 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
2020 struct intel_crtc_state
*pipe_config
)
2022 switch (pipe_config
->lane_count
) {
2026 return BIT(2) | BIT(0);
2028 return BIT(3) | BIT(2) | BIT(0);
2030 MISSING_CASE(pipe_config
->lane_count
);
2036 static void bxt_ddi_pre_pll_enable(struct intel_encoder
*encoder
)
2038 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2039 struct drm_i915_private
*dev_priv
= to_i915(dport
->base
.base
.dev
);
2040 enum port port
= dport
->port
;
2041 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2044 for (lane
= 0; lane
< 4; lane
++) {
2045 u32 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2048 * Note that on CHV this flag is called UPAR, but has
2049 * the same function.
2051 val
&= ~LATENCY_OPTIM
;
2052 if (intel_crtc
->config
->lane_lat_optim_mask
& BIT(lane
))
2053 val
|= LATENCY_OPTIM
;
2055 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
2060 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
)
2062 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2063 struct drm_i915_private
*dev_priv
= to_i915(dport
->base
.base
.dev
);
2064 enum port port
= dport
->port
;
2069 for (lane
= 0; lane
< 4; lane
++) {
2070 u32 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2072 if (val
& LATENCY_OPTIM
)
2079 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
)
2081 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2082 struct drm_i915_private
*dev_priv
=
2083 to_i915(intel_dig_port
->base
.base
.dev
);
2084 enum port port
= intel_dig_port
->port
;
2088 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2089 val
= I915_READ(DDI_BUF_CTL(port
));
2090 if (val
& DDI_BUF_CTL_ENABLE
) {
2091 val
&= ~DDI_BUF_CTL_ENABLE
;
2092 I915_WRITE(DDI_BUF_CTL(port
), val
);
2096 val
= I915_READ(DP_TP_CTL(port
));
2097 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2098 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2099 I915_WRITE(DP_TP_CTL(port
), val
);
2100 POSTING_READ(DP_TP_CTL(port
));
2103 intel_wait_ddi_buf_idle(dev_priv
, port
);
2106 val
= DP_TP_CTL_ENABLE
|
2107 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2108 if (intel_dp
->is_mst
)
2109 val
|= DP_TP_CTL_MODE_MST
;
2111 val
|= DP_TP_CTL_MODE_SST
;
2112 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2113 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2115 I915_WRITE(DP_TP_CTL(port
), val
);
2116 POSTING_READ(DP_TP_CTL(port
));
2118 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2119 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
2120 POSTING_READ(DDI_BUF_CTL(port
));
2125 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
2127 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
2128 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2132 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2133 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2134 * step 13 is the correct place for it. Step 18 is where it was
2135 * originally before the BUN.
2137 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
2138 val
&= ~FDI_RX_ENABLE
;
2139 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
2141 intel_ddi_post_disable(intel_encoder
);
2143 val
= I915_READ(FDI_RX_MISC(PIPE_A
));
2144 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
2145 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2146 I915_WRITE(FDI_RX_MISC(PIPE_A
), val
);
2148 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
2150 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
2152 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
2153 val
&= ~FDI_RX_PLL_ENABLE
;
2154 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
2157 void intel_ddi_get_config(struct intel_encoder
*encoder
,
2158 struct intel_crtc_state
*pipe_config
)
2160 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2161 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2162 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2163 struct intel_hdmi
*intel_hdmi
;
2164 u32 temp
, flags
= 0;
2166 /* XXX: DSI transcoder paranoia */
2167 if (WARN_ON(transcoder_is_dsi(cpu_transcoder
)))
2170 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
2171 if (temp
& TRANS_DDI_PHSYNC
)
2172 flags
|= DRM_MODE_FLAG_PHSYNC
;
2174 flags
|= DRM_MODE_FLAG_NHSYNC
;
2175 if (temp
& TRANS_DDI_PVSYNC
)
2176 flags
|= DRM_MODE_FLAG_PVSYNC
;
2178 flags
|= DRM_MODE_FLAG_NVSYNC
;
2180 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2182 switch (temp
& TRANS_DDI_BPC_MASK
) {
2183 case TRANS_DDI_BPC_6
:
2184 pipe_config
->pipe_bpp
= 18;
2186 case TRANS_DDI_BPC_8
:
2187 pipe_config
->pipe_bpp
= 24;
2189 case TRANS_DDI_BPC_10
:
2190 pipe_config
->pipe_bpp
= 30;
2192 case TRANS_DDI_BPC_12
:
2193 pipe_config
->pipe_bpp
= 36;
2199 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
2200 case TRANS_DDI_MODE_SELECT_HDMI
:
2201 pipe_config
->has_hdmi_sink
= true;
2202 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2204 if (intel_hdmi
->infoframe_enabled(&encoder
->base
, pipe_config
))
2205 pipe_config
->has_infoframe
= true;
2207 case TRANS_DDI_MODE_SELECT_DVI
:
2208 pipe_config
->lane_count
= 4;
2210 case TRANS_DDI_MODE_SELECT_FDI
:
2212 case TRANS_DDI_MODE_SELECT_DP_SST
:
2213 case TRANS_DDI_MODE_SELECT_DP_MST
:
2214 pipe_config
->lane_count
=
2215 ((temp
& DDI_PORT_WIDTH_MASK
) >> DDI_PORT_WIDTH_SHIFT
) + 1;
2216 intel_dp_get_m_n(intel_crtc
, pipe_config
);
2222 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
2223 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
2224 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
2225 pipe_config
->has_audio
= true;
2228 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp
.bpp
&&
2229 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2231 * This is a big fat ugly hack.
2233 * Some machines in UEFI boot mode provide us a VBT that has 18
2234 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2235 * unknown we fail to light up. Yet the same BIOS boots up with
2236 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2237 * max, not what it tells us to use.
2239 * Note: This will still be broken if the eDP panel is not lit
2240 * up by the BIOS, and thus we can't get the mode at module
2243 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2244 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2245 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2248 intel_ddi_clock_get(encoder
, pipe_config
);
2250 if (IS_BROXTON(dev_priv
))
2251 pipe_config
->lane_lat_optim_mask
=
2252 bxt_ddi_phy_get_lane_lat_optim_mask(encoder
);
2255 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
2256 struct intel_crtc_state
*pipe_config
)
2258 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2259 int type
= encoder
->type
;
2260 int port
= intel_ddi_get_encoder_port(encoder
);
2263 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
2266 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
2268 if (type
== INTEL_OUTPUT_HDMI
)
2269 ret
= intel_hdmi_compute_config(encoder
, pipe_config
);
2271 ret
= intel_dp_compute_config(encoder
, pipe_config
);
2273 if (IS_BROXTON(dev_priv
) && ret
)
2274 pipe_config
->lane_lat_optim_mask
=
2275 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder
,
2282 static const struct drm_encoder_funcs intel_ddi_funcs
= {
2283 .reset
= intel_dp_encoder_reset
,
2284 .destroy
= intel_dp_encoder_destroy
,
2287 static struct intel_connector
*
2288 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
2290 struct intel_connector
*connector
;
2291 enum port port
= intel_dig_port
->port
;
2293 connector
= intel_connector_alloc();
2297 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
2298 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
2306 static struct intel_connector
*
2307 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
2309 struct intel_connector
*connector
;
2310 enum port port
= intel_dig_port
->port
;
2312 connector
= intel_connector_alloc();
2316 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
2317 intel_hdmi_init_connector(intel_dig_port
, connector
);
2322 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
2324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2325 struct intel_digital_port
*intel_dig_port
;
2326 struct intel_encoder
*intel_encoder
;
2327 struct drm_encoder
*encoder
;
2328 bool init_hdmi
, init_dp
;
2331 if (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
) {
2357 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
2358 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
2359 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
2360 if (!init_dp
&& !init_hdmi
) {
2361 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2366 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2367 if (!intel_dig_port
)
2370 intel_encoder
= &intel_dig_port
->base
;
2371 encoder
= &intel_encoder
->base
;
2373 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
2374 DRM_MODE_ENCODER_TMDS
, "DDI %c", port_name(port
));
2376 intel_encoder
->compute_config
= intel_ddi_compute_config
;
2377 intel_encoder
->enable
= intel_enable_ddi
;
2378 if (IS_BROXTON(dev_priv
))
2379 intel_encoder
->pre_pll_enable
= bxt_ddi_pre_pll_enable
;
2380 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2381 intel_encoder
->disable
= intel_disable_ddi
;
2382 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2383 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2384 intel_encoder
->get_config
= intel_ddi_get_config
;
2385 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
2387 intel_dig_port
->port
= port
;
2388 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
2389 (DDI_BUF_PORT_REVERSAL
|
2393 * Bspec says that DDI_A_4_LANES is the only supported configuration
2394 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2395 * wasn't lit up at boot. Force this bit on in our internal
2396 * configuration so that we use the proper lane count for our
2399 if (IS_BROXTON(dev
) && port
== PORT_A
) {
2400 if (!(intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
)) {
2401 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2402 intel_dig_port
->saved_port_bits
|= DDI_A_4_LANES
;
2407 intel_dig_port
->max_lanes
= max_lanes
;
2409 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
2410 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2411 intel_encoder
->cloneable
= 0;
2414 if (!intel_ddi_init_dp_connector(intel_dig_port
))
2417 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
2419 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2420 * interrupts to check the external panel connection.
2422 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
) && port
== PORT_B
)
2423 dev_priv
->hotplug
.irq_port
[PORT_A
] = intel_dig_port
;
2425 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
2428 /* In theory we don't need the encoder->type check, but leave it just in
2429 * case we have some really bad VBTs... */
2430 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
2431 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
2438 drm_encoder_cleanup(encoder
);
2439 kfree(intel_dig_port
);