2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 int type
= intel_encoder
->type
;
65 if (type
== INTEL_OUTPUT_HDMI
) {
66 struct intel_hdmi
*intel_hdmi
=
67 enc_to_intel_hdmi(&intel_encoder
->base
);
68 return intel_hdmi
->ddi_port
;
69 } else if (type
== INTEL_OUTPUT_ANALOG
) {
72 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
77 /* On Haswell, DDI port buffers must be programmed with correct values
78 * in advance. The buffer values are different for FDI and DP modes,
79 * but the HDMI/DVI fields are shared among those. So we program the DDI
80 * in either FDI or DP modes only, as HDMI connections will work with both
83 void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
, bool use_fdi_mode
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
88 const u32
*ddi_translations
= ((use_fdi_mode
) ?
89 hsw_ddi_translations_fdi
:
90 hsw_ddi_translations_dp
);
92 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
94 use_fdi_mode
? "FDI" : "DP");
96 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
97 "Programming port %c in FDI mode, this probably will not work.\n",
100 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
101 I915_WRITE(reg
, ddi_translations
[i
]);
106 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
107 * mode and port E for FDI.
109 void intel_prepare_ddi(struct drm_device
*dev
)
113 if (IS_HASWELL(dev
)) {
114 for (port
= PORT_A
; port
< PORT_E
; port
++)
115 intel_prepare_ddi_buffers(dev
, port
, false);
117 /* DDI E is the suggested one to work in FDI mode, so program is as such by
118 * default. It will have to be re-programmed in case a digital DP output
119 * will be detected on it
121 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
125 static const long hsw_ddi_buf_ctl_values
[] = {
126 DDI_BUF_EMP_400MV_0DB_HSW
,
127 DDI_BUF_EMP_400MV_3_5DB_HSW
,
128 DDI_BUF_EMP_400MV_6DB_HSW
,
129 DDI_BUF_EMP_400MV_9_5DB_HSW
,
130 DDI_BUF_EMP_600MV_0DB_HSW
,
131 DDI_BUF_EMP_600MV_3_5DB_HSW
,
132 DDI_BUF_EMP_600MV_6DB_HSW
,
133 DDI_BUF_EMP_800MV_0DB_HSW
,
134 DDI_BUF_EMP_800MV_3_5DB_HSW
138 /* Starting with Haswell, different DDI ports can work in FDI mode for
139 * connection to the PCH-located connectors. For this, it is necessary to train
140 * both the DDI port and PCH receiver for the desired DDI buffer settings.
142 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
143 * please note that when FDI mode is active on DDI E, it shares 2 lines with
144 * DDI A (which is used for eDP)
147 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
149 struct drm_device
*dev
= crtc
->dev
;
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
152 int pipe
= intel_crtc
->pipe
;
155 /* Start the training iterating through available voltages and emphasis */
156 for (i
=0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
); i
++) {
157 /* Configure DP_TP_CTL with auto-training */
158 I915_WRITE(DP_TP_CTL(PORT_E
),
159 DP_TP_CTL_FDI_AUTOTRAIN
|
160 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
161 DP_TP_CTL_LINK_TRAIN_PAT1
|
164 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
165 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
166 temp
= (temp
& ~DDI_BUF_EMP_MASK
);
167 I915_WRITE(DDI_BUF_CTL(PORT_E
),
171 hsw_ddi_buf_ctl_values
[i
]);
175 /* We need to program FDI_RX_MISC with the default TP1 to TP2
176 * values before enabling the receiver, and configure the delay
177 * for the FDI timing generator to 90h. Luckily, all the other
178 * bits are supposed to be zeroed, so we can write those values
181 I915_WRITE(FDI_RX_MISC(pipe
), FDI_RX_TP1_TO_TP2_48
|
182 FDI_RX_FDI_DELAY_90
);
184 /* Enable CPU FDI Receiver with auto-training */
185 reg
= FDI_RX_CTL(pipe
);
188 FDI_LINK_TRAIN_AUTO
|
190 FDI_LINK_TRAIN_PATTERN_1_CPT
|
191 FDI_RX_ENHANCE_FRAME_ENABLE
|
192 FDI_PORT_WIDTH_2X_LPT
|
197 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
198 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
199 DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i
);
201 /* Enable normal pixel sending for FDI */
202 I915_WRITE(DP_TP_CTL(PORT_E
),
203 DP_TP_CTL_FDI_AUTOTRAIN
|
204 DP_TP_CTL_LINK_TRAIN_NORMAL
|
205 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
210 DRM_ERROR("Error training BUF_CTL %d\n", i
);
212 /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
213 I915_WRITE(DP_TP_CTL(PORT_E
),
214 I915_READ(DP_TP_CTL(PORT_E
)) &
216 I915_WRITE(FDI_RX_CTL(pipe
),
217 I915_READ(FDI_RX_CTL(pipe
)) &
223 DRM_DEBUG_KMS("FDI train done.\n");
226 /* For DDI connections, it is possible to support different outputs over the
227 * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by
228 * the time the output is detected what exactly is on the other end of it. This
229 * function aims at providing support for this detection and proper output
232 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
234 /* For now, we don't do any proper output detection and assume that we
235 * handle HDMI only */
239 /* We don't handle eDP and DP yet */
240 DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
242 /* Assume that the ports B, C and D are working in HDMI mode for now */
246 intel_hdmi_init(dev
, DDI_BUF_CTL(port
), port
);
249 DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
255 /* WRPLL clock dividers */
256 struct wrpll_tmds_clock
{
258 u16 p
; /* Post divider */
259 u16 n2
; /* Feedback divider */
260 u16 r2
; /* Reference divider */
263 /* Table of matching values for WRPLL clocks programming for each frequency.
264 * The code assumes this table is sorted. */
265 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
280 {27027, 18, 100, 111},
308 {40541, 22, 147, 89},
318 {44900, 20, 108, 65},
334 {54054, 16, 173, 108},
386 {81081, 6, 100, 111},
431 {108108, 8, 173, 108},
438 {111264, 8, 150, 91},
482 {135250, 6, 167, 111},
505 {148352, 4, 100, 91},
527 {162162, 4, 131, 109},
535 {169000, 4, 104, 83},
582 {202000, 4, 112, 75},
584 {203000, 4, 146, 97},
641 void intel_ddi_mode_set(struct drm_encoder
*encoder
,
642 struct drm_display_mode
*mode
,
643 struct drm_display_mode
*adjusted_mode
)
645 struct drm_crtc
*crtc
= encoder
->crtc
;
646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
647 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
648 int port
= intel_hdmi
->ddi_port
;
649 int pipe
= intel_crtc
->pipe
;
651 /* On Haswell, we need to enable the clocks and prepare DDI function to
652 * work in HDMI mode for this pipe.
654 DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port
), pipe_name(pipe
));
656 if (intel_hdmi
->has_audio
) {
657 /* Proper support for digital audio needs a new logic and a new set
658 * of registers, so we leave it for future patch bombing.
660 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
661 pipe_name(intel_crtc
->pipe
));
664 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
665 intel_write_eld(encoder
, adjusted_mode
);
668 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
671 static struct intel_encoder
*
672 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
674 struct drm_device
*dev
= crtc
->dev
;
675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
676 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
677 int num_encoders
= 0;
679 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
684 if (num_encoders
!= 1)
685 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders
,
692 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
694 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
695 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
696 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
699 switch (intel_crtc
->ddi_pll_sel
) {
700 case PORT_CLK_SEL_SPLL
:
701 plls
->spll_refcount
--;
702 if (plls
->spll_refcount
== 0) {
703 DRM_DEBUG_KMS("Disabling SPLL\n");
704 val
= I915_READ(SPLL_CTL
);
705 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
706 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
707 POSTING_READ(SPLL_CTL
);
710 case PORT_CLK_SEL_WRPLL1
:
711 plls
->wrpll1_refcount
--;
712 if (plls
->wrpll1_refcount
== 0) {
713 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
714 val
= I915_READ(WRPLL_CTL1
);
715 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
716 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
717 POSTING_READ(WRPLL_CTL1
);
720 case PORT_CLK_SEL_WRPLL2
:
721 plls
->wrpll2_refcount
--;
722 if (plls
->wrpll2_refcount
== 0) {
723 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
724 val
= I915_READ(WRPLL_CTL2
);
725 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
726 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
727 POSTING_READ(WRPLL_CTL2
);
732 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
733 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
734 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
736 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
739 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
743 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
744 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
747 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
750 *p
= wrpll_tmds_clock_table
[i
].p
;
751 *n2
= wrpll_tmds_clock_table
[i
].n2
;
752 *r2
= wrpll_tmds_clock_table
[i
].r2
;
754 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
755 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
756 wrpll_tmds_clock_table
[i
].clock
, clock
);
758 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
759 clock
, *p
, *n2
, *r2
);
762 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
764 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
765 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
766 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
767 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
768 int type
= intel_encoder
->type
;
769 enum pipe pipe
= intel_crtc
->pipe
;
772 /* TODO: reuse PLLs when possible (compare values) */
774 intel_ddi_put_crtc_pll(crtc
);
776 if (type
== INTEL_OUTPUT_HDMI
) {
779 if (plls
->wrpll1_refcount
== 0) {
780 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
782 plls
->wrpll1_refcount
++;
784 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
785 } else if (plls
->wrpll2_refcount
== 0) {
786 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
788 plls
->wrpll2_refcount
++;
790 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
792 DRM_ERROR("No WRPLLs available!\n");
796 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
797 "WRPLL already enabled\n");
799 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
801 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
802 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
803 WRPLL_DIVIDER_POST(p
);
805 } else if (type
== INTEL_OUTPUT_ANALOG
) {
806 if (plls
->spll_refcount
== 0) {
807 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
809 plls
->spll_refcount
++;
811 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
814 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
815 "SPLL already enabled\n");
817 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SCC
;
820 WARN(1, "Invalid DDI encoder type %d\n", type
);
824 I915_WRITE(reg
, val
);
830 void intel_ddi_enable_pipe_func(struct drm_crtc
*crtc
)
832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
833 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
834 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
835 enum pipe pipe
= intel_crtc
->pipe
;
838 /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
839 temp
= PIPE_DDI_FUNC_ENABLE
;
841 switch (intel_crtc
->bpp
) {
843 temp
|= PIPE_DDI_BPC_6
;
846 temp
|= PIPE_DDI_BPC_8
;
849 temp
|= PIPE_DDI_BPC_10
;
852 temp
|= PIPE_DDI_BPC_12
;
855 WARN(1, "%d bpp unsupported by pipe DDI function\n",
859 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
860 temp
|= PIPE_DDI_PVSYNC
;
861 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
862 temp
|= PIPE_DDI_PHSYNC
;
864 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
865 struct intel_hdmi
*intel_hdmi
=
866 enc_to_intel_hdmi(&intel_encoder
->base
);
868 if (intel_hdmi
->has_hdmi_sink
)
869 temp
|= PIPE_DDI_MODE_SELECT_HDMI
;
871 temp
|= PIPE_DDI_MODE_SELECT_DVI
;
873 temp
|= PIPE_DDI_SELECT_PORT(intel_hdmi
->ddi_port
);
874 } else if (intel_encoder
->type
== INTEL_OUTPUT_ANALOG
) {
875 temp
|= PIPE_DDI_MODE_SELECT_FDI
;
876 temp
|= PIPE_DDI_SELECT_PORT(PORT_E
);
878 WARN(1, "Invalid encoder type %d for pipe %d\n",
879 intel_encoder
->type
, pipe
);
882 I915_WRITE(DDI_FUNC_CTL(pipe
), temp
);
885 void intel_ddi_disable_pipe_func(struct drm_i915_private
*dev_priv
,
888 uint32_t reg
= DDI_FUNC_CTL(pipe
);
889 uint32_t val
= I915_READ(reg
);
891 val
&= ~(PIPE_DDI_FUNC_ENABLE
| PIPE_DDI_PORT_MASK
);
892 val
|= PIPE_DDI_PORT_NONE
;
893 I915_WRITE(reg
, val
);
896 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
899 struct drm_device
*dev
= encoder
->base
.dev
;
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
905 tmp
= I915_READ(DDI_BUF_CTL(intel_hdmi
->ddi_port
));
907 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
911 tmp
= I915_READ(DDI_FUNC_CTL(i
));
913 if ((tmp
& PIPE_DDI_PORT_MASK
)
914 == PIPE_DDI_SELECT_PORT(intel_hdmi
->ddi_port
)) {
920 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", intel_hdmi
->ddi_port
);
925 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
932 temp
= I915_READ(DDI_FUNC_CTL(pipe
));
933 temp
&= PIPE_DDI_PORT_MASK
;
934 for (i
= PORT_A
; i
<= PORT_E
; i
++)
935 if (temp
== PIPE_DDI_SELECT_PORT(i
))
938 ret
= I915_READ(PORT_CLK_SEL(port
));
940 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
941 pipe_name(pipe
), port_name(port
), ret
);
946 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
950 struct intel_crtc
*intel_crtc
;
952 for_each_pipe(pipe
) {
954 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
956 if (!intel_crtc
->active
)
959 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
962 switch (intel_crtc
->ddi_pll_sel
) {
963 case PORT_CLK_SEL_SPLL
:
964 dev_priv
->ddi_plls
.spll_refcount
++;
966 case PORT_CLK_SEL_WRPLL1
:
967 dev_priv
->ddi_plls
.wrpll1_refcount
++;
969 case PORT_CLK_SEL_WRPLL2
:
970 dev_priv
->ddi_plls
.wrpll2_refcount
++;
976 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
978 struct drm_crtc
*crtc
= &intel_crtc
->base
;
979 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
980 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
981 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
983 I915_WRITE(PIPE_CLK_SEL(intel_crtc
->pipe
), PIPE_CLK_SEL_PORT(port
));
986 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
988 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
990 I915_WRITE(PIPE_CLK_SEL(intel_crtc
->pipe
), PIPE_CLK_SEL_DISABLED
);
993 void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
995 struct drm_crtc
*crtc
= intel_encoder
->base
.crtc
;
996 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
997 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
998 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1000 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1002 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1005 void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1007 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1008 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1009 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1011 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1014 void intel_enable_ddi(struct intel_encoder
*encoder
)
1016 struct drm_device
*dev
= encoder
->base
.dev
;
1017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1018 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1019 int port
= intel_hdmi
->ddi_port
;
1022 temp
= I915_READ(DDI_BUF_CTL(port
));
1023 temp
|= DDI_BUF_CTL_ENABLE
;
1025 /* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
1026 * and swing/emphasis values are ignored so nothing special needs
1027 * to be done besides enabling the port.
1029 I915_WRITE(DDI_BUF_CTL(port
), temp
);
1032 void intel_disable_ddi(struct intel_encoder
*encoder
)
1034 struct drm_device
*dev
= encoder
->base
.dev
;
1035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1036 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1037 int port
= intel_hdmi
->ddi_port
;
1040 temp
= I915_READ(DDI_BUF_CTL(port
));
1041 temp
&= ~DDI_BUF_CTL_ENABLE
;
1043 I915_WRITE(DDI_BUF_CTL(port
), temp
);
1046 static int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1048 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1050 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1057 void intel_ddi_pll_init(struct drm_device
*dev
)
1059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1060 uint32_t val
= I915_READ(LCPLL_CTL
);
1062 /* The LCPLL register should be turned on by the BIOS. For now let's
1063 * just check its state and print errors in case something is wrong.
1064 * Don't even try to turn it on.
1067 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1068 intel_ddi_get_cdclk_freq(dev_priv
));
1070 if (val
& LCPLL_CD_SOURCE_FCLK
)
1071 DRM_ERROR("CDCLK source is not LCPLL\n");
1073 if (val
& LCPLL_PLL_DISABLE
)
1074 DRM_ERROR("LCPLL is disabled\n");