2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
47 static const u32 hsw_ddi_translations_fdi
[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
59 static const u32 hsw_ddi_translations_hdmi
[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
75 static const u32 bdw_ddi_translations_edp
[] = {
76 0x00FFFFFF, 0x00000012, /* eDP parameters */
77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00AAAFFF, 0x000E000A,
80 0x00FFFFFF, 0x00020011,
81 0x00DB6FFF, 0x0005000F,
82 0x00BEEFFF, 0x000A000C,
83 0x00FFFFFF, 0x0005000F,
84 0x00DB6FFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
88 static const u32 bdw_ddi_translations_dp
[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x80B2CFFF, 0x001B0002,
93 0x00FFFFFF, 0x000E000A,
94 0x00D75FFF, 0x00180004,
95 0x80CB2FFF, 0x001B0002,
96 0x00F7DFFF, 0x00180004,
97 0x80D75FFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
101 static const u32 bdw_ddi_translations_fdi
[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
114 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
116 struct drm_encoder
*encoder
= &intel_encoder
->base
;
117 int type
= intel_encoder
->type
;
119 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
120 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
121 struct intel_digital_port
*intel_dig_port
=
122 enc_to_dig_port(encoder
);
123 return intel_dig_port
->port
;
125 } else if (type
== INTEL_OUTPUT_ANALOG
) {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
141 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
147 const u32
*ddi_translations_fdi
;
148 const u32
*ddi_translations_dp
;
149 const u32
*ddi_translations_edp
;
150 const u32
*ddi_translations
;
152 if (IS_BROADWELL(dev
)) {
153 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
154 ddi_translations_dp
= bdw_ddi_translations_dp
;
155 ddi_translations_edp
= bdw_ddi_translations_edp
;
156 } else if (IS_HASWELL(dev
)) {
157 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
158 ddi_translations_dp
= hsw_ddi_translations_dp
;
159 ddi_translations_edp
= hsw_ddi_translations_dp
;
161 WARN(1, "ddi translation table missing\n");
162 ddi_translations_edp
= bdw_ddi_translations_dp
;
163 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
164 ddi_translations_dp
= bdw_ddi_translations_dp
;
169 ddi_translations
= ddi_translations_edp
;
173 ddi_translations
= ddi_translations_dp
;
176 if (intel_dp_is_edp(dev
, PORT_D
))
177 ddi_translations
= ddi_translations_edp
;
179 ddi_translations
= ddi_translations_dp
;
182 ddi_translations
= ddi_translations_fdi
;
188 for (i
= 0, reg
= DDI_BUF_TRANS(port
);
189 i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
190 I915_WRITE(reg
, ddi_translations
[i
]);
193 /* Entry 9 is for HDMI: */
194 for (i
= 0; i
< 2; i
++) {
195 I915_WRITE(reg
, hsw_ddi_translations_hdmi
[hdmi_level
* 2 + i
]);
200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
203 void intel_prepare_ddi(struct drm_device
*dev
)
210 for (port
= PORT_A
; port
<= PORT_E
; port
++)
211 intel_prepare_ddi_buffers(dev
, port
);
214 static const long hsw_ddi_buf_ctl_values
[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW
,
216 DDI_BUF_EMP_400MV_3_5DB_HSW
,
217 DDI_BUF_EMP_400MV_6DB_HSW
,
218 DDI_BUF_EMP_400MV_9_5DB_HSW
,
219 DDI_BUF_EMP_600MV_0DB_HSW
,
220 DDI_BUF_EMP_600MV_3_5DB_HSW
,
221 DDI_BUF_EMP_600MV_6DB_HSW
,
222 DDI_BUF_EMP_800MV_0DB_HSW
,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
226 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
229 uint32_t reg
= DDI_BUF_CTL(port
);
232 for (i
= 0; i
< 8; i
++) {
234 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
240 /* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
249 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
251 struct drm_device
*dev
= crtc
->dev
;
252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
253 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
254 u32 temp
, i
, rx_ctl_val
;
256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
261 * WaFDIAutoLinkSetTimingOverrride:hsw
263 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
267 /* Enable the PCH Receiver FDI PLL */
268 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
270 FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
271 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
272 POSTING_READ(_FDI_RXA_CTL
);
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val
|= FDI_PCDCLK
;
277 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E
),
287 DP_TP_CTL_FDI_AUTOTRAIN
|
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
289 DP_TP_CTL_LINK_TRAIN_PAT1
|
292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
296 I915_WRITE(DDI_BUF_CTL(PORT_E
),
298 ((intel_crtc
->config
.fdi_lanes
- 1) << 1) |
299 hsw_ddi_buf_ctl_values
[i
/ 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E
));
304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
309 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
310 POSTING_READ(_FDI_RXA_CTL
);
312 /* Wait for FDI receiver lane calibration */
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp
= I915_READ(_FDI_RXA_MISC
);
317 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
318 I915_WRITE(_FDI_RXA_MISC
, temp
);
319 POSTING_READ(_FDI_RXA_MISC
);
321 /* Wait for FDI auto training time */
324 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
325 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E
),
330 DP_TP_CTL_FDI_AUTOTRAIN
|
331 DP_TP_CTL_LINK_TRAIN_NORMAL
|
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
338 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
339 temp
&= ~DDI_BUF_CTL_ENABLE
;
340 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
341 POSTING_READ(DDI_BUF_CTL(PORT_E
));
343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
344 temp
= I915_READ(DP_TP_CTL(PORT_E
));
345 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
346 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
347 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
348 POSTING_READ(DP_TP_CTL(PORT_E
));
350 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
352 rx_ctl_val
&= ~FDI_RX_ENABLE
;
353 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
354 POSTING_READ(_FDI_RXA_CTL
);
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp
= I915_READ(_FDI_RXA_MISC
);
358 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
359 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC
, temp
);
361 POSTING_READ(_FDI_RXA_MISC
);
364 DRM_ERROR("FDI link training failed!\n");
367 static struct intel_encoder
*
368 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
370 struct drm_device
*dev
= crtc
->dev
;
371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
372 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
373 int num_encoders
= 0;
375 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
380 if (num_encoders
!= 1)
381 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
382 pipe_name(intel_crtc
->pipe
));
388 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
390 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
391 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
395 switch (intel_crtc
->ddi_pll_sel
) {
396 case PORT_CLK_SEL_SPLL
:
397 DRM_DEBUG_KMS("Disabling SPLL\n");
398 val
= I915_READ(SPLL_CTL
);
399 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
400 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
401 POSTING_READ(SPLL_CTL
);
403 case PORT_CLK_SEL_WRPLL1
:
404 plls
->wrpll1_refcount
--;
405 if (plls
->wrpll1_refcount
== 0) {
406 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
407 val
= I915_READ(WRPLL_CTL1
);
408 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
409 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
410 POSTING_READ(WRPLL_CTL1
);
413 case PORT_CLK_SEL_WRPLL2
:
414 plls
->wrpll2_refcount
--;
415 if (plls
->wrpll2_refcount
== 0) {
416 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
417 val
= I915_READ(WRPLL_CTL2
);
418 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
419 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
420 POSTING_READ(WRPLL_CTL2
);
425 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
426 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
428 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
432 #define LC_FREQ_2K (LC_FREQ * 2000)
438 /* Constraints for PLL good behavior */
444 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
450 static unsigned wrpll_get_budget_for_freq(int clock
)
524 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
525 unsigned r2
, unsigned n2
, unsigned p
,
526 struct wrpll_rnp
*best
)
528 uint64_t a
, b
, c
, d
, diff
, diff_best
;
530 /* No best (r,n,p) yet */
539 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
543 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
546 * and we would like delta <= budget.
548 * If the discrepancy is above the PPM-based budget, always prefer to
549 * improve upon the previous solution. However, if you're within the
550 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
552 a
= freq2k
* budget
* p
* r2
;
553 b
= freq2k
* budget
* best
->p
* best
->r2
;
554 diff
= ABS_DIFF((freq2k
* p
* r2
), (LC_FREQ_2K
* n2
));
555 diff_best
= ABS_DIFF((freq2k
* best
->p
* best
->r2
),
556 (LC_FREQ_2K
* best
->n2
));
558 d
= 1000000 * diff_best
;
560 if (a
< c
&& b
< d
) {
561 /* If both are above the budget, pick the closer */
562 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
567 } else if (a
>= c
&& b
< d
) {
568 /* If A is below the threshold but B is above it? Update. */
572 } else if (a
>= c
&& b
>= d
) {
573 /* Both are below the limit, so pick the higher n2/(r2*r2) */
574 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
580 /* Otherwise a < c && b >= d, do nothing */
583 static int intel_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
586 int refclk
= LC_FREQ
;
590 wrpll
= I915_READ(reg
);
591 switch (wrpll
& SPLL_PLL_REF_MASK
) {
593 case SPLL_PLL_NON_SSC
:
595 * We could calculate spread here, but our checking
596 * code only cares about 5% accuracy, and spread is a max of
605 WARN(1, "bad wrpll refclk\n");
609 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
610 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
611 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
613 /* Convert to KHz, p & r have a fixed point portion */
614 return (refclk
* n
* 100) / (p
* r
);
617 static void intel_ddi_clock_get(struct intel_encoder
*encoder
,
618 struct intel_crtc_config
*pipe_config
)
620 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
621 enum port port
= intel_ddi_get_encoder_port(encoder
);
625 val
= I915_READ(PORT_CLK_SEL(port
));
626 switch (val
& PORT_CLK_SEL_MASK
) {
627 case PORT_CLK_SEL_LCPLL_810
:
630 case PORT_CLK_SEL_LCPLL_1350
:
633 case PORT_CLK_SEL_LCPLL_2700
:
636 case PORT_CLK_SEL_WRPLL1
:
637 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
639 case PORT_CLK_SEL_WRPLL2
:
640 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
642 case PORT_CLK_SEL_SPLL
:
643 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
644 if (pll
== SPLL_PLL_FREQ_810MHz
)
646 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
648 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
651 WARN(1, "bad spll freq\n");
656 WARN(1, "bad port clock sel\n");
660 pipe_config
->port_clock
= link_clock
* 2;
662 if (pipe_config
->has_pch_encoder
)
663 pipe_config
->adjusted_mode
.crtc_clock
=
664 intel_dotclock_calculate(pipe_config
->port_clock
,
665 &pipe_config
->fdi_m_n
);
666 else if (pipe_config
->has_dp_encoder
)
667 pipe_config
->adjusted_mode
.crtc_clock
=
668 intel_dotclock_calculate(pipe_config
->port_clock
,
669 &pipe_config
->dp_m_n
);
671 pipe_config
->adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
675 intel_ddi_calculate_wrpll(int clock
/* in Hz */,
676 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
680 struct wrpll_rnp best
= { 0, 0, 0 };
683 freq2k
= clock
/ 100;
685 budget
= wrpll_get_budget_for_freq(clock
);
687 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
688 * and directly pass the LC PLL to it. */
689 if (freq2k
== 5400000) {
697 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
700 * We want R so that REF_MIN <= Ref <= REF_MAX.
701 * Injecting R2 = 2 * R gives:
702 * REF_MAX * r2 > LC_FREQ * 2 and
703 * REF_MIN * r2 < LC_FREQ * 2
705 * Which means the desired boundaries for r2 are:
706 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
709 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
710 r2
<= LC_FREQ
* 2 / REF_MIN
;
714 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
716 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
717 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
718 * VCO_MAX * r2 > n2 * LC_FREQ and
719 * VCO_MIN * r2 < n2 * LC_FREQ)
721 * Which means the desired boundaries for n2 are:
722 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
724 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
725 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
728 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
729 wrpll_update_rnp(freq2k
, budget
,
740 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
741 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
742 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
745 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
)
747 struct drm_crtc
*crtc
= &intel_crtc
->base
;
748 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
749 struct drm_encoder
*encoder
= &intel_encoder
->base
;
750 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
751 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
752 int type
= intel_encoder
->type
;
753 enum pipe pipe
= intel_crtc
->pipe
;
754 int clock
= intel_crtc
->config
.port_clock
;
756 intel_ddi_put_crtc_pll(crtc
);
758 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
759 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
761 switch (intel_dp
->link_bw
) {
762 case DP_LINK_BW_1_62
:
763 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
766 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
769 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
772 DRM_ERROR("Link bandwidth %d unsupported\n",
777 } else if (type
== INTEL_OUTPUT_HDMI
) {
781 intel_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
783 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
784 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
785 WRPLL_DIVIDER_POST(p
);
787 if (val
== I915_READ(WRPLL_CTL1
)) {
788 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
791 } else if (val
== I915_READ(WRPLL_CTL2
)) {
792 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
795 } else if (plls
->wrpll1_refcount
== 0) {
796 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
799 } else if (plls
->wrpll2_refcount
== 0) {
800 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
804 DRM_ERROR("No WRPLLs available!\n");
808 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
811 if (reg
== WRPLL_CTL1
) {
812 plls
->wrpll1_refcount
++;
813 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
815 plls
->wrpll2_refcount
++;
816 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
819 } else if (type
== INTEL_OUTPUT_ANALOG
) {
820 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
822 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
824 WARN(1, "Invalid DDI encoder type %d\n", type
);
832 * To be called after intel_ddi_pll_select(). That one selects the PLL to be
833 * used, this one actually enables the PLL.
835 void intel_ddi_pll_enable(struct intel_crtc
*crtc
)
837 struct drm_device
*dev
= crtc
->base
.dev
;
838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
839 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
840 int clock
= crtc
->config
.port_clock
;
841 uint32_t reg
, cur_val
, new_val
;
843 const char *pll_name
;
844 uint32_t enable_bit
= (1 << 31);
845 unsigned int p
, n2
, r2
;
847 BUILD_BUG_ON(enable_bit
!= SPLL_PLL_ENABLE
);
848 BUILD_BUG_ON(enable_bit
!= WRPLL_PLL_ENABLE
);
850 switch (crtc
->ddi_pll_sel
) {
851 case PORT_CLK_SEL_LCPLL_2700
:
852 case PORT_CLK_SEL_LCPLL_1350
:
853 case PORT_CLK_SEL_LCPLL_810
:
855 * LCPLL should always be enabled at this point of the mode set
856 * sequence, so nothing to do.
860 case PORT_CLK_SEL_SPLL
:
861 new_val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
|
863 WARN(I915_READ(SPLL_CTL
) & enable_bit
, "SPLL already enabled\n");
864 I915_WRITE(SPLL_CTL
, new_val
);
865 POSTING_READ(SPLL_CTL
);
868 case PORT_CLK_SEL_WRPLL1
:
869 case PORT_CLK_SEL_WRPLL2
:
870 if (crtc
->ddi_pll_sel
== PORT_CLK_SEL_WRPLL1
) {
873 refcount
= plls
->wrpll1_refcount
;
877 refcount
= plls
->wrpll2_refcount
;
880 intel_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
882 new_val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
883 WRPLL_DIVIDER_REFERENCE(r2
) |
884 WRPLL_DIVIDER_FEEDBACK(n2
) | WRPLL_DIVIDER_POST(p
);
888 case PORT_CLK_SEL_NONE
:
889 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
892 WARN(1, "Bad selected pll: 0x%08x\n", crtc
->ddi_pll_sel
);
896 cur_val
= I915_READ(reg
);
898 WARN(refcount
< 1, "Bad %s refcount: %d\n", pll_name
, refcount
);
900 WARN(cur_val
& enable_bit
, "%s already enabled\n", pll_name
);
901 I915_WRITE(reg
, new_val
);
905 WARN((cur_val
& enable_bit
) == 0, "%s disabled\n", pll_name
);
909 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
911 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
913 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
914 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
915 int type
= intel_encoder
->type
;
918 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
920 temp
= TRANS_MSA_SYNC_CLK
;
921 switch (intel_crtc
->config
.pipe_bpp
) {
923 temp
|= TRANS_MSA_6_BPC
;
926 temp
|= TRANS_MSA_8_BPC
;
929 temp
|= TRANS_MSA_10_BPC
;
932 temp
|= TRANS_MSA_12_BPC
;
937 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
941 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
944 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
945 struct drm_encoder
*encoder
= &intel_encoder
->base
;
946 struct drm_device
*dev
= crtc
->dev
;
947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
948 enum pipe pipe
= intel_crtc
->pipe
;
949 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
950 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
951 int type
= intel_encoder
->type
;
954 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
955 temp
= TRANS_DDI_FUNC_ENABLE
;
956 temp
|= TRANS_DDI_SELECT_PORT(port
);
958 switch (intel_crtc
->config
.pipe_bpp
) {
960 temp
|= TRANS_DDI_BPC_6
;
963 temp
|= TRANS_DDI_BPC_8
;
966 temp
|= TRANS_DDI_BPC_10
;
969 temp
|= TRANS_DDI_BPC_12
;
975 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
976 temp
|= TRANS_DDI_PVSYNC
;
977 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
978 temp
|= TRANS_DDI_PHSYNC
;
980 if (cpu_transcoder
== TRANSCODER_EDP
) {
983 /* On Haswell, can only use the always-on power well for
984 * eDP when not using the panel fitter, and when not
985 * using motion blur mitigation (which we don't
987 if (IS_HASWELL(dev
) &&
988 (intel_crtc
->config
.pch_pfit
.enabled
||
989 intel_crtc
->config
.pch_pfit
.force_thru
))
990 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
992 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
995 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
998 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1006 if (type
== INTEL_OUTPUT_HDMI
) {
1007 if (intel_crtc
->config
.has_hdmi_sink
)
1008 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1010 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1012 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1013 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1014 temp
|= (intel_crtc
->config
.fdi_lanes
- 1) << 1;
1016 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1017 type
== INTEL_OUTPUT_EDP
) {
1018 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1020 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1022 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1024 WARN(1, "Invalid encoder type %d for pipe %c\n",
1025 intel_encoder
->type
, pipe_name(pipe
));
1028 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1031 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1032 enum transcoder cpu_transcoder
)
1034 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1035 uint32_t val
= I915_READ(reg
);
1037 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1038 val
|= TRANS_DDI_PORT_NONE
;
1039 I915_WRITE(reg
, val
);
1042 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1044 struct drm_device
*dev
= intel_connector
->base
.dev
;
1045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1046 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1047 int type
= intel_connector
->base
.connector_type
;
1048 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1050 enum transcoder cpu_transcoder
;
1051 enum intel_display_power_domain power_domain
;
1054 power_domain
= intel_display_port_power_domain(intel_encoder
);
1055 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1058 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1062 cpu_transcoder
= TRANSCODER_EDP
;
1064 cpu_transcoder
= (enum transcoder
) pipe
;
1066 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1068 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1069 case TRANS_DDI_MODE_SELECT_HDMI
:
1070 case TRANS_DDI_MODE_SELECT_DVI
:
1071 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1073 case TRANS_DDI_MODE_SELECT_DP_SST
:
1074 if (type
== DRM_MODE_CONNECTOR_eDP
)
1076 case TRANS_DDI_MODE_SELECT_DP_MST
:
1077 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1079 case TRANS_DDI_MODE_SELECT_FDI
:
1080 return (type
== DRM_MODE_CONNECTOR_VGA
);
1087 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1090 struct drm_device
*dev
= encoder
->base
.dev
;
1091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1092 enum port port
= intel_ddi_get_encoder_port(encoder
);
1093 enum intel_display_power_domain power_domain
;
1097 power_domain
= intel_display_port_power_domain(encoder
);
1098 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1101 tmp
= I915_READ(DDI_BUF_CTL(port
));
1103 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1106 if (port
== PORT_A
) {
1107 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1109 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1110 case TRANS_DDI_EDP_INPUT_A_ON
:
1111 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1114 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1117 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1124 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1125 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1127 if ((tmp
& TRANS_DDI_PORT_MASK
)
1128 == TRANS_DDI_SELECT_PORT(port
)) {
1135 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1140 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1144 enum port port
= I915_MAX_PORTS
;
1145 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1149 if (cpu_transcoder
== TRANSCODER_EDP
) {
1152 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1153 temp
&= TRANS_DDI_PORT_MASK
;
1155 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1156 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1160 if (port
== I915_MAX_PORTS
) {
1161 WARN(1, "Pipe %c enabled on an unknown port\n",
1163 ret
= PORT_CLK_SEL_NONE
;
1165 ret
= I915_READ(PORT_CLK_SEL(port
));
1166 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1167 "0x%08x\n", pipe_name(pipe
), port_name(port
),
1174 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1178 struct intel_crtc
*intel_crtc
;
1180 dev_priv
->ddi_plls
.wrpll1_refcount
= 0;
1181 dev_priv
->ddi_plls
.wrpll2_refcount
= 0;
1183 for_each_pipe(pipe
) {
1185 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1187 if (!intel_crtc
->active
) {
1188 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
1192 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1195 switch (intel_crtc
->ddi_pll_sel
) {
1196 case PORT_CLK_SEL_WRPLL1
:
1197 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1199 case PORT_CLK_SEL_WRPLL2
:
1200 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1206 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1208 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1209 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1210 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1211 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1212 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1214 if (cpu_transcoder
!= TRANSCODER_EDP
)
1215 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1216 TRANS_CLK_SEL_PORT(port
));
1219 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1221 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1222 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1224 if (cpu_transcoder
!= TRANSCODER_EDP
)
1225 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1226 TRANS_CLK_SEL_DISABLED
);
1229 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1231 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1232 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1233 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1234 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1235 int type
= intel_encoder
->type
;
1237 if (crtc
->config
.has_audio
) {
1238 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1239 pipe_name(crtc
->pipe
));
1242 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1243 intel_write_eld(encoder
, &crtc
->config
.adjusted_mode
);
1246 if (type
== INTEL_OUTPUT_EDP
) {
1247 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1248 intel_edp_panel_on(intel_dp
);
1251 WARN_ON(crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1252 I915_WRITE(PORT_CLK_SEL(port
), crtc
->ddi_pll_sel
);
1254 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1255 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1256 struct intel_digital_port
*intel_dig_port
=
1257 enc_to_dig_port(encoder
);
1259 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
1260 DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
1261 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1263 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1264 intel_dp_start_link_train(intel_dp
);
1265 intel_dp_complete_link_train(intel_dp
);
1267 intel_dp_stop_link_train(intel_dp
);
1268 } else if (type
== INTEL_OUTPUT_HDMI
) {
1269 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1271 intel_hdmi
->set_infoframes(encoder
,
1272 crtc
->config
.has_hdmi_sink
,
1273 &crtc
->config
.adjusted_mode
);
1277 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1279 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1280 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1281 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1282 int type
= intel_encoder
->type
;
1286 val
= I915_READ(DDI_BUF_CTL(port
));
1287 if (val
& DDI_BUF_CTL_ENABLE
) {
1288 val
&= ~DDI_BUF_CTL_ENABLE
;
1289 I915_WRITE(DDI_BUF_CTL(port
), val
);
1293 val
= I915_READ(DP_TP_CTL(port
));
1294 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1295 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1296 I915_WRITE(DP_TP_CTL(port
), val
);
1299 intel_wait_ddi_buf_idle(dev_priv
, port
);
1301 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1302 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1303 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1304 intel_edp_panel_vdd_on(intel_dp
);
1305 intel_edp_panel_off(intel_dp
);
1308 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1311 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1313 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1314 struct drm_crtc
*crtc
= encoder
->crtc
;
1315 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1316 int pipe
= intel_crtc
->pipe
;
1317 struct drm_device
*dev
= encoder
->dev
;
1318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1319 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1320 int type
= intel_encoder
->type
;
1323 if (type
== INTEL_OUTPUT_HDMI
) {
1324 struct intel_digital_port
*intel_dig_port
=
1325 enc_to_dig_port(encoder
);
1327 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1328 * are ignored so nothing special needs to be done besides
1329 * enabling the port.
1331 I915_WRITE(DDI_BUF_CTL(port
),
1332 intel_dig_port
->saved_port_bits
|
1333 DDI_BUF_CTL_ENABLE
);
1334 } else if (type
== INTEL_OUTPUT_EDP
) {
1335 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1338 intel_dp_stop_link_train(intel_dp
);
1340 intel_edp_backlight_on(intel_dp
);
1341 intel_edp_psr_enable(intel_dp
);
1344 if (intel_crtc
->config
.has_audio
) {
1345 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1346 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1347 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1348 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1352 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1354 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1355 struct drm_crtc
*crtc
= encoder
->crtc
;
1356 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1357 int pipe
= intel_crtc
->pipe
;
1358 int type
= intel_encoder
->type
;
1359 struct drm_device
*dev
= encoder
->dev
;
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1363 /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1364 * register is part of the power well on Haswell. */
1365 if (intel_crtc
->config
.has_audio
) {
1366 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1367 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) <<
1369 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1370 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1373 if (type
== INTEL_OUTPUT_EDP
) {
1374 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1376 intel_edp_psr_disable(intel_dp
);
1377 intel_edp_backlight_off(intel_dp
);
1381 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1383 struct drm_device
*dev
= dev_priv
->dev
;
1384 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1385 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1387 if (lcpll
& LCPLL_CD_SOURCE_FCLK
) {
1389 } else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
) {
1391 } else if (freq
== LCPLL_CLK_FREQ_450
) {
1393 } else if (IS_HASWELL(dev
)) {
1399 if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
1401 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
1408 void intel_ddi_pll_init(struct drm_device
*dev
)
1410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1411 uint32_t val
= I915_READ(LCPLL_CTL
);
1413 /* The LCPLL register should be turned on by the BIOS. For now let's
1414 * just check its state and print errors in case something is wrong.
1415 * Don't even try to turn it on.
1418 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1419 intel_ddi_get_cdclk_freq(dev_priv
));
1421 if (val
& LCPLL_CD_SOURCE_FCLK
)
1422 DRM_ERROR("CDCLK source is not LCPLL\n");
1424 if (val
& LCPLL_PLL_DISABLE
)
1425 DRM_ERROR("LCPLL is disabled\n");
1428 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1430 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1431 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1432 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1433 enum port port
= intel_dig_port
->port
;
1437 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1438 val
= I915_READ(DDI_BUF_CTL(port
));
1439 if (val
& DDI_BUF_CTL_ENABLE
) {
1440 val
&= ~DDI_BUF_CTL_ENABLE
;
1441 I915_WRITE(DDI_BUF_CTL(port
), val
);
1445 val
= I915_READ(DP_TP_CTL(port
));
1446 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1447 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1448 I915_WRITE(DP_TP_CTL(port
), val
);
1449 POSTING_READ(DP_TP_CTL(port
));
1452 intel_wait_ddi_buf_idle(dev_priv
, port
);
1455 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1456 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1457 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1458 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1459 I915_WRITE(DP_TP_CTL(port
), val
);
1460 POSTING_READ(DP_TP_CTL(port
));
1462 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1463 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1464 POSTING_READ(DDI_BUF_CTL(port
));
1469 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1471 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1472 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1475 intel_ddi_post_disable(intel_encoder
);
1477 val
= I915_READ(_FDI_RXA_CTL
);
1478 val
&= ~FDI_RX_ENABLE
;
1479 I915_WRITE(_FDI_RXA_CTL
, val
);
1481 val
= I915_READ(_FDI_RXA_MISC
);
1482 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1483 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1484 I915_WRITE(_FDI_RXA_MISC
, val
);
1486 val
= I915_READ(_FDI_RXA_CTL
);
1488 I915_WRITE(_FDI_RXA_CTL
, val
);
1490 val
= I915_READ(_FDI_RXA_CTL
);
1491 val
&= ~FDI_RX_PLL_ENABLE
;
1492 I915_WRITE(_FDI_RXA_CTL
, val
);
1495 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1497 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1498 int type
= intel_encoder
->type
;
1500 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1501 intel_dp_check_link_status(intel_dp
);
1504 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1505 struct intel_crtc_config
*pipe_config
)
1507 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1508 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1509 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1510 u32 temp
, flags
= 0;
1512 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1513 if (temp
& TRANS_DDI_PHSYNC
)
1514 flags
|= DRM_MODE_FLAG_PHSYNC
;
1516 flags
|= DRM_MODE_FLAG_NHSYNC
;
1517 if (temp
& TRANS_DDI_PVSYNC
)
1518 flags
|= DRM_MODE_FLAG_PVSYNC
;
1520 flags
|= DRM_MODE_FLAG_NVSYNC
;
1522 pipe_config
->adjusted_mode
.flags
|= flags
;
1524 switch (temp
& TRANS_DDI_BPC_MASK
) {
1525 case TRANS_DDI_BPC_6
:
1526 pipe_config
->pipe_bpp
= 18;
1528 case TRANS_DDI_BPC_8
:
1529 pipe_config
->pipe_bpp
= 24;
1531 case TRANS_DDI_BPC_10
:
1532 pipe_config
->pipe_bpp
= 30;
1534 case TRANS_DDI_BPC_12
:
1535 pipe_config
->pipe_bpp
= 36;
1541 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
1542 case TRANS_DDI_MODE_SELECT_HDMI
:
1543 pipe_config
->has_hdmi_sink
= true;
1544 case TRANS_DDI_MODE_SELECT_DVI
:
1545 case TRANS_DDI_MODE_SELECT_FDI
:
1547 case TRANS_DDI_MODE_SELECT_DP_SST
:
1548 case TRANS_DDI_MODE_SELECT_DP_MST
:
1549 pipe_config
->has_dp_encoder
= true;
1550 intel_dp_get_m_n(intel_crtc
, pipe_config
);
1556 if (intel_display_power_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
1557 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1558 if (temp
& (AUDIO_OUTPUT_ENABLE_A
<< (intel_crtc
->pipe
* 4)))
1559 pipe_config
->has_audio
= true;
1562 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
1563 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1565 * This is a big fat ugly hack.
1567 * Some machines in UEFI boot mode provide us a VBT that has 18
1568 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1569 * unknown we fail to light up. Yet the same BIOS boots up with
1570 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1571 * max, not what it tells us to use.
1573 * Note: This will still be broken if the eDP panel is not lit
1574 * up by the BIOS, and thus we can't get the mode at module
1577 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1578 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1579 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1582 intel_ddi_clock_get(encoder
, pipe_config
);
1585 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1587 /* HDMI has nothing special to destroy, so we can go with this. */
1588 intel_dp_encoder_destroy(encoder
);
1591 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1592 struct intel_crtc_config
*pipe_config
)
1594 int type
= encoder
->type
;
1595 int port
= intel_ddi_get_encoder_port(encoder
);
1597 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1600 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
1602 if (type
== INTEL_OUTPUT_HDMI
)
1603 return intel_hdmi_compute_config(encoder
, pipe_config
);
1605 return intel_dp_compute_config(encoder
, pipe_config
);
1608 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1609 .destroy
= intel_ddi_destroy
,
1612 static struct intel_connector
*
1613 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
1615 struct intel_connector
*connector
;
1616 enum port port
= intel_dig_port
->port
;
1618 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1622 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1623 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
1631 static struct intel_connector
*
1632 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
1634 struct intel_connector
*connector
;
1635 enum port port
= intel_dig_port
->port
;
1637 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1641 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1642 intel_hdmi_init_connector(intel_dig_port
, connector
);
1647 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1650 struct intel_digital_port
*intel_dig_port
;
1651 struct intel_encoder
*intel_encoder
;
1652 struct drm_encoder
*encoder
;
1653 struct intel_connector
*hdmi_connector
= NULL
;
1654 struct intel_connector
*dp_connector
= NULL
;
1655 bool init_hdmi
, init_dp
;
1657 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
1658 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
1659 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
1660 if (!init_dp
&& !init_hdmi
) {
1661 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1667 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1668 if (!intel_dig_port
)
1671 intel_encoder
= &intel_dig_port
->base
;
1672 encoder
= &intel_encoder
->base
;
1674 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1675 DRM_MODE_ENCODER_TMDS
);
1677 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1678 intel_encoder
->enable
= intel_enable_ddi
;
1679 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1680 intel_encoder
->disable
= intel_disable_ddi
;
1681 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1682 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1683 intel_encoder
->get_config
= intel_ddi_get_config
;
1685 intel_dig_port
->port
= port
;
1686 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
1687 (DDI_BUF_PORT_REVERSAL
|
1690 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1691 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1692 intel_encoder
->cloneable
= 0;
1693 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1695 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
1696 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
1699 dp_connector
= intel_ddi_init_dp_connector(intel_dig_port
);
1701 /* In theory we don't need the encoder->type check, but leave it just in
1702 * case we have some really bad VBTs... */
1703 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
)
1704 hdmi_connector
= intel_ddi_init_hdmi_connector(intel_dig_port
);
1706 if (!dp_connector
&& !hdmi_connector
) {
1707 drm_encoder_cleanup(encoder
);
1708 kfree(intel_dig_port
);