2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 const u32
*ddi_translations
= ((use_fdi_mode
) ?
94 hsw_ddi_translations_fdi
:
95 hsw_ddi_translations_dp
);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode
? "FDI" : "DP");
101 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
106 I915_WRITE(reg
, ddi_translations
[i
]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device
*dev
)
121 for (port
= PORT_A
; port
< PORT_E
; port
++)
122 intel_prepare_ddi_buffers(dev
, port
, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
131 static const long hsw_ddi_buf_ctl_values
[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW
,
133 DDI_BUF_EMP_400MV_3_5DB_HSW
,
134 DDI_BUF_EMP_400MV_6DB_HSW
,
135 DDI_BUF_EMP_400MV_9_5DB_HSW
,
136 DDI_BUF_EMP_600MV_0DB_HSW
,
137 DDI_BUF_EMP_600MV_3_5DB_HSW
,
138 DDI_BUF_EMP_600MV_6DB_HSW
,
139 DDI_BUF_EMP_800MV_0DB_HSW
,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
146 uint32_t reg
= DDI_BUF_CTL(port
);
149 for (i
= 0; i
< 8; i
++) {
151 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
168 struct drm_device
*dev
= crtc
->dev
;
169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
171 u32 temp
, i
, rx_ctl_val
;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
184 FDI_RX_PLL_ENABLE
| ((intel_crtc
->fdi_lanes
- 1) << 19);
185 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
186 POSTING_READ(_FDI_RXA_CTL
);
189 /* Switch from Rawclk to PCDclk */
190 rx_ctl_val
|= FDI_PCDCLK
;
191 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
193 /* Configure Port Clock Select */
194 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
196 /* Start the training iterating through available voltages and emphasis,
197 * testing each value twice. */
198 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
199 /* Configure DP_TP_CTL with auto-training */
200 I915_WRITE(DP_TP_CTL(PORT_E
),
201 DP_TP_CTL_FDI_AUTOTRAIN
|
202 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
203 DP_TP_CTL_LINK_TRAIN_PAT1
|
206 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
207 * DDI E does not support port reversal, the functionality is
208 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
209 * port reversal bit */
210 I915_WRITE(DDI_BUF_CTL(PORT_E
),
212 ((intel_crtc
->fdi_lanes
- 1) << 1) |
213 hsw_ddi_buf_ctl_values
[i
/ 2]);
214 POSTING_READ(DDI_BUF_CTL(PORT_E
));
218 /* Program PCH FDI Receiver TU */
219 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
221 /* Enable PCH FDI Receiver with auto-training */
222 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
223 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
224 POSTING_READ(_FDI_RXA_CTL
);
226 /* Wait for FDI receiver lane calibration */
229 /* Unset FDI_RX_MISC pwrdn lanes */
230 temp
= I915_READ(_FDI_RXA_MISC
);
231 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
232 I915_WRITE(_FDI_RXA_MISC
, temp
);
233 POSTING_READ(_FDI_RXA_MISC
);
235 /* Wait for FDI auto training time */
238 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
239 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
240 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
242 /* Enable normal pixel sending for FDI */
243 I915_WRITE(DP_TP_CTL(PORT_E
),
244 DP_TP_CTL_FDI_AUTOTRAIN
|
245 DP_TP_CTL_LINK_TRAIN_NORMAL
|
246 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
252 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
253 temp
&= ~DDI_BUF_CTL_ENABLE
;
254 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
255 POSTING_READ(DDI_BUF_CTL(PORT_E
));
257 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
258 temp
= I915_READ(DP_TP_CTL(PORT_E
));
259 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
260 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
261 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
262 POSTING_READ(DP_TP_CTL(PORT_E
));
264 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
266 rx_ctl_val
&= ~FDI_RX_ENABLE
;
267 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
268 POSTING_READ(_FDI_RXA_CTL
);
270 /* Reset FDI_RX_MISC pwrdn lanes */
271 temp
= I915_READ(_FDI_RXA_MISC
);
272 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
273 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
274 I915_WRITE(_FDI_RXA_MISC
, temp
);
275 POSTING_READ(_FDI_RXA_MISC
);
278 DRM_ERROR("FDI link training failed!\n");
281 /* WRPLL clock dividers */
282 struct wrpll_tmds_clock
{
284 u16 p
; /* Post divider */
285 u16 n2
; /* Feedback divider */
286 u16 r2
; /* Reference divider */
289 /* Table of matching values for WRPLL clocks programming for each frequency.
290 * The code assumes this table is sorted. */
291 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
306 {27027, 18, 100, 111},
334 {40541, 22, 147, 89},
344 {44900, 20, 108, 65},
360 {54054, 16, 173, 108},
412 {81081, 6, 100, 111},
457 {108108, 8, 173, 108},
464 {111264, 8, 150, 91},
508 {135250, 6, 167, 111},
531 {148352, 4, 100, 91},
553 {162162, 4, 131, 109},
561 {169000, 4, 104, 83},
608 {202000, 4, 112, 75},
610 {203000, 4, 146, 97},
667 static void intel_ddi_mode_set(struct drm_encoder
*encoder
,
668 struct drm_display_mode
*mode
,
669 struct drm_display_mode
*adjusted_mode
)
671 struct drm_crtc
*crtc
= encoder
->crtc
;
672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
673 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
674 int port
= intel_ddi_get_encoder_port(intel_encoder
);
675 int pipe
= intel_crtc
->pipe
;
676 int type
= intel_encoder
->type
;
678 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
679 port_name(port
), pipe_name(pipe
));
681 intel_crtc
->eld_vld
= false;
682 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
683 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
684 struct intel_digital_port
*intel_dig_port
=
685 enc_to_dig_port(encoder
);
687 intel_dp
->DP
= intel_dig_port
->port_reversal
|
688 DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
689 switch (intel_dp
->lane_count
) {
691 intel_dp
->DP
|= DDI_PORT_WIDTH_X1
;
694 intel_dp
->DP
|= DDI_PORT_WIDTH_X2
;
697 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
700 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
701 WARN(1, "Unexpected DP lane count %d\n",
702 intel_dp
->lane_count
);
706 if (intel_dp
->has_audio
) {
707 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
708 pipe_name(intel_crtc
->pipe
));
711 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
712 intel_write_eld(encoder
, adjusted_mode
);
715 intel_dp_init_link_config(intel_dp
);
717 } else if (type
== INTEL_OUTPUT_HDMI
) {
718 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
720 if (intel_hdmi
->has_audio
) {
721 /* Proper support for digital audio needs a new logic
722 * and a new set of registers, so we leave it for future
725 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
726 pipe_name(intel_crtc
->pipe
));
729 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
730 intel_write_eld(encoder
, adjusted_mode
);
733 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
737 static struct intel_encoder
*
738 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
740 struct drm_device
*dev
= crtc
->dev
;
741 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
742 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
743 int num_encoders
= 0;
745 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
750 if (num_encoders
!= 1)
751 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
752 pipe_name(intel_crtc
->pipe
));
758 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
760 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
761 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
765 switch (intel_crtc
->ddi_pll_sel
) {
766 case PORT_CLK_SEL_SPLL
:
767 plls
->spll_refcount
--;
768 if (plls
->spll_refcount
== 0) {
769 DRM_DEBUG_KMS("Disabling SPLL\n");
770 val
= I915_READ(SPLL_CTL
);
771 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
772 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
773 POSTING_READ(SPLL_CTL
);
776 case PORT_CLK_SEL_WRPLL1
:
777 plls
->wrpll1_refcount
--;
778 if (plls
->wrpll1_refcount
== 0) {
779 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
780 val
= I915_READ(WRPLL_CTL1
);
781 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
782 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
783 POSTING_READ(WRPLL_CTL1
);
786 case PORT_CLK_SEL_WRPLL2
:
787 plls
->wrpll2_refcount
--;
788 if (plls
->wrpll2_refcount
== 0) {
789 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
790 val
= I915_READ(WRPLL_CTL2
);
791 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
792 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
793 POSTING_READ(WRPLL_CTL2
);
798 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
799 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
800 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
802 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
805 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
809 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
810 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
813 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
816 *p
= wrpll_tmds_clock_table
[i
].p
;
817 *n2
= wrpll_tmds_clock_table
[i
].n2
;
818 *r2
= wrpll_tmds_clock_table
[i
].r2
;
820 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
821 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
822 wrpll_tmds_clock_table
[i
].clock
, clock
);
824 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
825 clock
, *p
, *n2
, *r2
);
828 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
831 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
832 struct drm_encoder
*encoder
= &intel_encoder
->base
;
833 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
834 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
835 int type
= intel_encoder
->type
;
836 enum pipe pipe
= intel_crtc
->pipe
;
839 /* TODO: reuse PLLs when possible (compare values) */
841 intel_ddi_put_crtc_pll(crtc
);
843 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
844 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
846 switch (intel_dp
->link_bw
) {
847 case DP_LINK_BW_1_62
:
848 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
851 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
854 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
857 DRM_ERROR("Link bandwidth %d unsupported\n",
862 /* We don't need to turn any PLL on because we'll use LCPLL. */
865 } else if (type
== INTEL_OUTPUT_HDMI
) {
868 if (plls
->wrpll1_refcount
== 0) {
869 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
871 plls
->wrpll1_refcount
++;
873 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
874 } else if (plls
->wrpll2_refcount
== 0) {
875 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
877 plls
->wrpll2_refcount
++;
879 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
881 DRM_ERROR("No WRPLLs available!\n");
885 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
886 "WRPLL already enabled\n");
888 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
890 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
891 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
892 WRPLL_DIVIDER_POST(p
);
894 } else if (type
== INTEL_OUTPUT_ANALOG
) {
895 if (plls
->spll_refcount
== 0) {
896 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
898 plls
->spll_refcount
++;
900 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
902 DRM_ERROR("SPLL already in use\n");
906 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
907 "SPLL already enabled\n");
909 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
912 WARN(1, "Invalid DDI encoder type %d\n", type
);
916 I915_WRITE(reg
, val
);
922 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
924 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
925 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
926 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
927 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
928 int type
= intel_encoder
->type
;
931 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
933 temp
= TRANS_MSA_SYNC_CLK
;
934 switch (intel_crtc
->config
.pipe_bpp
) {
936 temp
|= TRANS_MSA_6_BPC
;
939 temp
|= TRANS_MSA_8_BPC
;
942 temp
|= TRANS_MSA_10_BPC
;
945 temp
|= TRANS_MSA_12_BPC
;
950 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
954 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
956 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
957 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
958 struct drm_encoder
*encoder
= &intel_encoder
->base
;
959 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
960 enum pipe pipe
= intel_crtc
->pipe
;
961 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
962 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
963 int type
= intel_encoder
->type
;
966 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
967 temp
= TRANS_DDI_FUNC_ENABLE
;
968 temp
|= TRANS_DDI_SELECT_PORT(port
);
970 switch (intel_crtc
->config
.pipe_bpp
) {
972 temp
|= TRANS_DDI_BPC_6
;
975 temp
|= TRANS_DDI_BPC_8
;
978 temp
|= TRANS_DDI_BPC_10
;
981 temp
|= TRANS_DDI_BPC_12
;
987 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
988 temp
|= TRANS_DDI_PVSYNC
;
989 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
990 temp
|= TRANS_DDI_PHSYNC
;
992 if (cpu_transcoder
== TRANSCODER_EDP
) {
995 /* Can only use the always-on power well for eDP when
996 * not using the panel fitter, and when not using motion
997 * blur mitigation (which we don't support). */
998 if (dev_priv
->pch_pf_size
)
999 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1001 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1004 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1007 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1015 if (type
== INTEL_OUTPUT_HDMI
) {
1016 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1018 if (intel_hdmi
->has_hdmi_sink
)
1019 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1021 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1023 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1024 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1025 temp
|= (intel_crtc
->fdi_lanes
- 1) << 1;
1027 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1028 type
== INTEL_OUTPUT_EDP
) {
1029 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1031 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1033 switch (intel_dp
->lane_count
) {
1035 temp
|= TRANS_DDI_PORT_WIDTH_X1
;
1038 temp
|= TRANS_DDI_PORT_WIDTH_X2
;
1041 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1044 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1045 WARN(1, "Unsupported lane count %d\n",
1046 intel_dp
->lane_count
);
1050 WARN(1, "Invalid encoder type %d for pipe %c\n",
1051 intel_encoder
->type
, pipe_name(pipe
));
1054 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1057 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1058 enum transcoder cpu_transcoder
)
1060 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1061 uint32_t val
= I915_READ(reg
);
1063 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1064 val
|= TRANS_DDI_PORT_NONE
;
1065 I915_WRITE(reg
, val
);
1068 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1070 struct drm_device
*dev
= intel_connector
->base
.dev
;
1071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1073 int type
= intel_connector
->base
.connector_type
;
1074 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1076 enum transcoder cpu_transcoder
;
1079 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1083 cpu_transcoder
= TRANSCODER_EDP
;
1085 cpu_transcoder
= (enum transcoder
) pipe
;
1087 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1089 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1090 case TRANS_DDI_MODE_SELECT_HDMI
:
1091 case TRANS_DDI_MODE_SELECT_DVI
:
1092 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1094 case TRANS_DDI_MODE_SELECT_DP_SST
:
1095 if (type
== DRM_MODE_CONNECTOR_eDP
)
1097 case TRANS_DDI_MODE_SELECT_DP_MST
:
1098 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1100 case TRANS_DDI_MODE_SELECT_FDI
:
1101 return (type
== DRM_MODE_CONNECTOR_VGA
);
1108 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1111 struct drm_device
*dev
= encoder
->base
.dev
;
1112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1113 enum port port
= intel_ddi_get_encoder_port(encoder
);
1117 tmp
= I915_READ(DDI_BUF_CTL(port
));
1119 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1122 if (port
== PORT_A
) {
1123 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1125 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1126 case TRANS_DDI_EDP_INPUT_A_ON
:
1127 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1130 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1133 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1140 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1141 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1143 if ((tmp
& TRANS_DDI_PORT_MASK
)
1144 == TRANS_DDI_SELECT_PORT(port
)) {
1151 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1156 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1160 enum port port
= I915_MAX_PORTS
;
1161 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1165 if (cpu_transcoder
== TRANSCODER_EDP
) {
1168 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1169 temp
&= TRANS_DDI_PORT_MASK
;
1171 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1172 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1176 if (port
== I915_MAX_PORTS
) {
1177 WARN(1, "Pipe %c enabled on an unknown port\n",
1179 ret
= PORT_CLK_SEL_NONE
;
1181 ret
= I915_READ(PORT_CLK_SEL(port
));
1182 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1183 "0x%08x\n", pipe_name(pipe
), port_name(port
),
1190 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1194 struct intel_crtc
*intel_crtc
;
1196 for_each_pipe(pipe
) {
1198 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1200 if (!intel_crtc
->active
)
1203 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1206 switch (intel_crtc
->ddi_pll_sel
) {
1207 case PORT_CLK_SEL_SPLL
:
1208 dev_priv
->ddi_plls
.spll_refcount
++;
1210 case PORT_CLK_SEL_WRPLL1
:
1211 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1213 case PORT_CLK_SEL_WRPLL2
:
1214 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1220 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1222 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1223 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1224 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1225 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1226 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1228 if (cpu_transcoder
!= TRANSCODER_EDP
)
1229 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1230 TRANS_CLK_SEL_PORT(port
));
1233 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1235 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1236 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1238 if (cpu_transcoder
!= TRANSCODER_EDP
)
1239 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1240 TRANS_CLK_SEL_DISABLED
);
1243 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1245 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1246 struct drm_crtc
*crtc
= encoder
->crtc
;
1247 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1249 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1250 int type
= intel_encoder
->type
;
1252 if (type
== INTEL_OUTPUT_EDP
) {
1253 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1254 ironlake_edp_panel_vdd_on(intel_dp
);
1255 ironlake_edp_panel_on(intel_dp
);
1256 ironlake_edp_panel_vdd_off(intel_dp
, true);
1259 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1260 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1262 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1263 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1265 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1266 intel_dp_start_link_train(intel_dp
);
1267 intel_dp_complete_link_train(intel_dp
);
1271 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1273 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1274 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1275 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1276 int type
= intel_encoder
->type
;
1280 val
= I915_READ(DDI_BUF_CTL(port
));
1281 if (val
& DDI_BUF_CTL_ENABLE
) {
1282 val
&= ~DDI_BUF_CTL_ENABLE
;
1283 I915_WRITE(DDI_BUF_CTL(port
), val
);
1287 val
= I915_READ(DP_TP_CTL(port
));
1288 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1289 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1290 I915_WRITE(DP_TP_CTL(port
), val
);
1293 intel_wait_ddi_buf_idle(dev_priv
, port
);
1295 if (type
== INTEL_OUTPUT_EDP
) {
1296 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1297 ironlake_edp_panel_vdd_on(intel_dp
);
1298 ironlake_edp_panel_off(intel_dp
);
1301 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1304 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1306 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1307 struct drm_crtc
*crtc
= encoder
->crtc
;
1308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1309 int pipe
= intel_crtc
->pipe
;
1310 struct drm_device
*dev
= encoder
->dev
;
1311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1312 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1313 int type
= intel_encoder
->type
;
1316 if (type
== INTEL_OUTPUT_HDMI
) {
1317 struct intel_digital_port
*intel_dig_port
=
1318 enc_to_dig_port(encoder
);
1320 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1321 * are ignored so nothing special needs to be done besides
1322 * enabling the port.
1324 I915_WRITE(DDI_BUF_CTL(port
),
1325 intel_dig_port
->port_reversal
| DDI_BUF_CTL_ENABLE
);
1326 } else if (type
== INTEL_OUTPUT_EDP
) {
1327 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1329 ironlake_edp_backlight_on(intel_dp
);
1332 if (intel_crtc
->eld_vld
) {
1333 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1334 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1335 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1339 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1341 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1342 struct drm_crtc
*crtc
= encoder
->crtc
;
1343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1344 int pipe
= intel_crtc
->pipe
;
1345 int type
= intel_encoder
->type
;
1346 struct drm_device
*dev
= encoder
->dev
;
1347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1350 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1351 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1352 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1354 if (type
== INTEL_OUTPUT_EDP
) {
1355 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1357 ironlake_edp_backlight_off(intel_dp
);
1361 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1363 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1365 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1368 else if (IS_ULT(dev_priv
->dev
))
1374 void intel_ddi_pll_init(struct drm_device
*dev
)
1376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1377 uint32_t val
= I915_READ(LCPLL_CTL
);
1379 /* The LCPLL register should be turned on by the BIOS. For now let's
1380 * just check its state and print errors in case something is wrong.
1381 * Don't even try to turn it on.
1384 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1385 intel_ddi_get_cdclk_freq(dev_priv
));
1387 if (val
& LCPLL_CD_SOURCE_FCLK
)
1388 DRM_ERROR("CDCLK source is not LCPLL\n");
1390 if (val
& LCPLL_PLL_DISABLE
)
1391 DRM_ERROR("LCPLL is disabled\n");
1394 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1396 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1397 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1398 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1399 enum port port
= intel_dig_port
->port
;
1403 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1404 val
= I915_READ(DDI_BUF_CTL(port
));
1405 if (val
& DDI_BUF_CTL_ENABLE
) {
1406 val
&= ~DDI_BUF_CTL_ENABLE
;
1407 I915_WRITE(DDI_BUF_CTL(port
), val
);
1411 val
= I915_READ(DP_TP_CTL(port
));
1412 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1413 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1414 I915_WRITE(DP_TP_CTL(port
), val
);
1415 POSTING_READ(DP_TP_CTL(port
));
1418 intel_wait_ddi_buf_idle(dev_priv
, port
);
1421 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1422 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1423 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1424 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1425 I915_WRITE(DP_TP_CTL(port
), val
);
1426 POSTING_READ(DP_TP_CTL(port
));
1428 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1429 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1430 POSTING_READ(DDI_BUF_CTL(port
));
1435 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1437 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1438 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1441 intel_ddi_post_disable(intel_encoder
);
1443 val
= I915_READ(_FDI_RXA_CTL
);
1444 val
&= ~FDI_RX_ENABLE
;
1445 I915_WRITE(_FDI_RXA_CTL
, val
);
1447 val
= I915_READ(_FDI_RXA_MISC
);
1448 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1449 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1450 I915_WRITE(_FDI_RXA_MISC
, val
);
1452 val
= I915_READ(_FDI_RXA_CTL
);
1454 I915_WRITE(_FDI_RXA_CTL
, val
);
1456 val
= I915_READ(_FDI_RXA_CTL
);
1457 val
&= ~FDI_RX_PLL_ENABLE
;
1458 I915_WRITE(_FDI_RXA_CTL
, val
);
1461 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1463 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1464 int type
= intel_encoder
->type
;
1466 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1467 intel_dp_check_link_status(intel_dp
);
1470 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1472 /* HDMI has nothing special to destroy, so we can go with this. */
1473 intel_dp_encoder_destroy(encoder
);
1476 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1477 struct intel_crtc_config
*pipe_config
)
1479 int type
= encoder
->type
;
1481 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1483 if (type
== INTEL_OUTPUT_HDMI
)
1484 return intel_hdmi_compute_config(encoder
, pipe_config
);
1486 return intel_dp_compute_config(encoder
, pipe_config
);
1489 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1490 .destroy
= intel_ddi_destroy
,
1493 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs
= {
1494 .mode_set
= intel_ddi_mode_set
,
1497 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1500 struct intel_digital_port
*intel_dig_port
;
1501 struct intel_encoder
*intel_encoder
;
1502 struct drm_encoder
*encoder
;
1503 struct intel_connector
*hdmi_connector
= NULL
;
1504 struct intel_connector
*dp_connector
= NULL
;
1506 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1507 if (!intel_dig_port
)
1510 dp_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1511 if (!dp_connector
) {
1512 kfree(intel_dig_port
);
1516 if (port
!= PORT_A
) {
1517 hdmi_connector
= kzalloc(sizeof(struct intel_connector
),
1519 if (!hdmi_connector
) {
1520 kfree(dp_connector
);
1521 kfree(intel_dig_port
);
1526 intel_encoder
= &intel_dig_port
->base
;
1527 encoder
= &intel_encoder
->base
;
1529 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1530 DRM_MODE_ENCODER_TMDS
);
1531 drm_encoder_helper_add(encoder
, &intel_ddi_helper_funcs
);
1533 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1534 intel_encoder
->enable
= intel_enable_ddi
;
1535 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1536 intel_encoder
->disable
= intel_disable_ddi
;
1537 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1538 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1540 intel_dig_port
->port
= port
;
1541 intel_dig_port
->port_reversal
= I915_READ(DDI_BUF_CTL(port
)) &
1542 DDI_BUF_PORT_REVERSAL
;
1544 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1545 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1547 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1548 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1549 intel_encoder
->cloneable
= false;
1550 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1553 intel_hdmi_init_connector(intel_dig_port
, hdmi_connector
);
1554 intel_dp_init_connector(intel_dig_port
, dp_connector
);