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drm/i915: Rename intel_context[engine].ringbuf
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
51 };
52
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
63 };
64
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
79 };
80
81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
91 };
92
93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
103 };
104
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
115 };
116
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
129 };
130
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 },
142 };
143
144 /* Skylake U */
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x80007011, 0x000000CD, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake Y */
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x0 },
162 { 0x80009010, 0x000000C0, 0x3 },
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 },
168 };
169
170 /*
171 * Skylake H and S
172 * eDP 1.4 low vswing translation parameters
173 */
174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185 };
186
187 /*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
202 };
203
204 /*
205 * Skylake Y
206 * eDP 1.4 low vswing translation parameters
207 */
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219 };
220
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x80006012, 0x000000CD, 0x1 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
234 };
235
236 /* Skylake Y */
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x80007011, 0x000000CB, 0x3 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x80006013, 0x000000C0, 0x3 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
249 };
250
251 struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257 };
258
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
271 };
272
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285 };
286
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302 };
303
304 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
305 {
306 switch (encoder->type) {
307 case INTEL_OUTPUT_DP_MST:
308 return enc_to_mst(&encoder->base)->primary->port;
309 case INTEL_OUTPUT_DP:
310 case INTEL_OUTPUT_EDP:
311 case INTEL_OUTPUT_HDMI:
312 case INTEL_OUTPUT_UNKNOWN:
313 return enc_to_dig_port(&encoder->base)->port;
314 case INTEL_OUTPUT_ANALOG:
315 return PORT_E;
316 default:
317 MISSING_CASE(encoder->type);
318 return PORT_A;
319 }
320 }
321
322 static const struct ddi_buf_trans *
323 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
324 {
325 if (dev_priv->vbt.edp.low_vswing) {
326 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
327 return bdw_ddi_translations_edp;
328 } else {
329 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
330 return bdw_ddi_translations_dp;
331 }
332 }
333
334 static const struct ddi_buf_trans *
335 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
336 {
337 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
338 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
339 return skl_y_ddi_translations_dp;
340 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
341 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
342 return skl_u_ddi_translations_dp;
343 } else {
344 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
345 return skl_ddi_translations_dp;
346 }
347 }
348
349 static const struct ddi_buf_trans *
350 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
351 {
352 if (dev_priv->vbt.edp.low_vswing) {
353 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
354 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
355 return skl_y_ddi_translations_edp;
356 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
357 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
358 return skl_u_ddi_translations_edp;
359 } else {
360 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
361 return skl_ddi_translations_edp;
362 }
363 }
364
365 return skl_get_buf_trans_dp(dev_priv, n_entries);
366 }
367
368 static const struct ddi_buf_trans *
369 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
370 {
371 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
372 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
373 return skl_y_ddi_translations_hdmi;
374 } else {
375 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
376 return skl_ddi_translations_hdmi;
377 }
378 }
379
380 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
381 {
382 int n_hdmi_entries;
383 int hdmi_level;
384 int hdmi_default_entry;
385
386 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
387
388 if (IS_BROXTON(dev_priv))
389 return hdmi_level;
390
391 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
392 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
393 hdmi_default_entry = 8;
394 } else if (IS_BROADWELL(dev_priv)) {
395 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
396 hdmi_default_entry = 7;
397 } else if (IS_HASWELL(dev_priv)) {
398 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
399 hdmi_default_entry = 6;
400 } else {
401 WARN(1, "ddi translation table missing\n");
402 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
403 hdmi_default_entry = 7;
404 }
405
406 /* Choose a good default if VBT is badly populated */
407 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
408 hdmi_level >= n_hdmi_entries)
409 hdmi_level = hdmi_default_entry;
410
411 return hdmi_level;
412 }
413
414 /*
415 * Starting with Haswell, DDI port buffers must be programmed with correct
416 * values in advance. This function programs the correct values for
417 * DP/eDP/FDI use cases.
418 */
419 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
420 {
421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
422 u32 iboost_bit = 0;
423 int i, n_dp_entries, n_edp_entries, size;
424 enum port port = intel_ddi_get_encoder_port(encoder);
425 const struct ddi_buf_trans *ddi_translations_fdi;
426 const struct ddi_buf_trans *ddi_translations_dp;
427 const struct ddi_buf_trans *ddi_translations_edp;
428 const struct ddi_buf_trans *ddi_translations;
429
430 if (IS_BROXTON(dev_priv))
431 return;
432
433 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
434 ddi_translations_fdi = NULL;
435 ddi_translations_dp =
436 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
437 ddi_translations_edp =
438 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
439
440 /* If we're boosting the current, set bit 31 of trans1 */
441 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
442 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
443
444 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
445 port != PORT_A && port != PORT_E &&
446 n_edp_entries > 9))
447 n_edp_entries = 9;
448 } else if (IS_BROADWELL(dev_priv)) {
449 ddi_translations_fdi = bdw_ddi_translations_fdi;
450 ddi_translations_dp = bdw_ddi_translations_dp;
451 ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
452 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
453 } else if (IS_HASWELL(dev_priv)) {
454 ddi_translations_fdi = hsw_ddi_translations_fdi;
455 ddi_translations_dp = hsw_ddi_translations_dp;
456 ddi_translations_edp = hsw_ddi_translations_dp;
457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
458 } else {
459 WARN(1, "ddi translation table missing\n");
460 ddi_translations_edp = bdw_ddi_translations_dp;
461 ddi_translations_fdi = bdw_ddi_translations_fdi;
462 ddi_translations_dp = bdw_ddi_translations_dp;
463 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
464 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
465 }
466
467 switch (encoder->type) {
468 case INTEL_OUTPUT_EDP:
469 ddi_translations = ddi_translations_edp;
470 size = n_edp_entries;
471 break;
472 case INTEL_OUTPUT_DP:
473 ddi_translations = ddi_translations_dp;
474 size = n_dp_entries;
475 break;
476 case INTEL_OUTPUT_ANALOG:
477 ddi_translations = ddi_translations_fdi;
478 size = n_dp_entries;
479 break;
480 default:
481 BUG();
482 }
483
484 for (i = 0; i < size; i++) {
485 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
486 ddi_translations[i].trans1 | iboost_bit);
487 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
488 ddi_translations[i].trans2);
489 }
490 }
491
492 /*
493 * Starting with Haswell, DDI port buffers must be programmed with correct
494 * values in advance. This function programs the correct values for
495 * HDMI/DVI use cases.
496 */
497 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
498 {
499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
500 u32 iboost_bit = 0;
501 int n_hdmi_entries, hdmi_level;
502 enum port port = intel_ddi_get_encoder_port(encoder);
503 const struct ddi_buf_trans *ddi_translations_hdmi;
504
505 if (IS_BROXTON(dev_priv))
506 return;
507
508 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
509
510 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
511 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
512
513 /* If we're boosting the current, set bit 31 of trans1 */
514 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
515 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
516 } else if (IS_BROADWELL(dev_priv)) {
517 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
518 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
519 } else if (IS_HASWELL(dev_priv)) {
520 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
521 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
522 } else {
523 WARN(1, "ddi translation table missing\n");
524 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
525 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
526 }
527
528 /* Entry 9 is for HDMI: */
529 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
530 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
531 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
532 ddi_translations_hdmi[hdmi_level].trans2);
533 }
534
535 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
536 enum port port)
537 {
538 i915_reg_t reg = DDI_BUF_CTL(port);
539 int i;
540
541 for (i = 0; i < 16; i++) {
542 udelay(1);
543 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
544 return;
545 }
546 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
547 }
548
549 /* Starting with Haswell, different DDI ports can work in FDI mode for
550 * connection to the PCH-located connectors. For this, it is necessary to train
551 * both the DDI port and PCH receiver for the desired DDI buffer settings.
552 *
553 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
554 * please note that when FDI mode is active on DDI E, it shares 2 lines with
555 * DDI A (which is used for eDP)
556 */
557
558 void hsw_fdi_link_train(struct drm_crtc *crtc)
559 {
560 struct drm_device *dev = crtc->dev;
561 struct drm_i915_private *dev_priv = to_i915(dev);
562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
563 struct intel_encoder *encoder;
564 u32 temp, i, rx_ctl_val;
565
566 for_each_encoder_on_crtc(dev, crtc, encoder) {
567 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
568 intel_prepare_dp_ddi_buffers(encoder);
569 }
570
571 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
572 * mode set "sequence for CRT port" document:
573 * - TP1 to TP2 time with the default value
574 * - FDI delay to 90h
575 *
576 * WaFDIAutoLinkSetTimingOverrride:hsw
577 */
578 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
579 FDI_RX_PWRDN_LANE0_VAL(2) |
580 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
581
582 /* Enable the PCH Receiver FDI PLL */
583 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
584 FDI_RX_PLL_ENABLE |
585 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
586 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
587 POSTING_READ(FDI_RX_CTL(PIPE_A));
588 udelay(220);
589
590 /* Switch from Rawclk to PCDclk */
591 rx_ctl_val |= FDI_PCDCLK;
592 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
593
594 /* Configure Port Clock Select */
595 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
596 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
597
598 /* Start the training iterating through available voltages and emphasis,
599 * testing each value twice. */
600 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
601 /* Configure DP_TP_CTL with auto-training */
602 I915_WRITE(DP_TP_CTL(PORT_E),
603 DP_TP_CTL_FDI_AUTOTRAIN |
604 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
605 DP_TP_CTL_LINK_TRAIN_PAT1 |
606 DP_TP_CTL_ENABLE);
607
608 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
609 * DDI E does not support port reversal, the functionality is
610 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
611 * port reversal bit */
612 I915_WRITE(DDI_BUF_CTL(PORT_E),
613 DDI_BUF_CTL_ENABLE |
614 ((intel_crtc->config->fdi_lanes - 1) << 1) |
615 DDI_BUF_TRANS_SELECT(i / 2));
616 POSTING_READ(DDI_BUF_CTL(PORT_E));
617
618 udelay(600);
619
620 /* Program PCH FDI Receiver TU */
621 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
622
623 /* Enable PCH FDI Receiver with auto-training */
624 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
625 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
626 POSTING_READ(FDI_RX_CTL(PIPE_A));
627
628 /* Wait for FDI receiver lane calibration */
629 udelay(30);
630
631 /* Unset FDI_RX_MISC pwrdn lanes */
632 temp = I915_READ(FDI_RX_MISC(PIPE_A));
633 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
634 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
635 POSTING_READ(FDI_RX_MISC(PIPE_A));
636
637 /* Wait for FDI auto training time */
638 udelay(5);
639
640 temp = I915_READ(DP_TP_STATUS(PORT_E));
641 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
642 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
643 break;
644 }
645
646 /*
647 * Leave things enabled even if we failed to train FDI.
648 * Results in less fireworks from the state checker.
649 */
650 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
651 DRM_ERROR("FDI link training failed!\n");
652 break;
653 }
654
655 rx_ctl_val &= ~FDI_RX_ENABLE;
656 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
657 POSTING_READ(FDI_RX_CTL(PIPE_A));
658
659 temp = I915_READ(DDI_BUF_CTL(PORT_E));
660 temp &= ~DDI_BUF_CTL_ENABLE;
661 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
662 POSTING_READ(DDI_BUF_CTL(PORT_E));
663
664 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
665 temp = I915_READ(DP_TP_CTL(PORT_E));
666 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
667 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
668 I915_WRITE(DP_TP_CTL(PORT_E), temp);
669 POSTING_READ(DP_TP_CTL(PORT_E));
670
671 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
672
673 /* Reset FDI_RX_MISC pwrdn lanes */
674 temp = I915_READ(FDI_RX_MISC(PIPE_A));
675 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
676 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
678 POSTING_READ(FDI_RX_MISC(PIPE_A));
679 }
680
681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E),
683 DP_TP_CTL_FDI_AUTOTRAIN |
684 DP_TP_CTL_LINK_TRAIN_NORMAL |
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
686 DP_TP_CTL_ENABLE);
687 }
688
689 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
690 {
691 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
692 struct intel_digital_port *intel_dig_port =
693 enc_to_dig_port(&encoder->base);
694
695 intel_dp->DP = intel_dig_port->saved_port_bits |
696 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
697 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
698 }
699
700 static struct intel_encoder *
701 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
702 {
703 struct drm_device *dev = crtc->dev;
704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
705 struct intel_encoder *intel_encoder, *ret = NULL;
706 int num_encoders = 0;
707
708 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
709 ret = intel_encoder;
710 num_encoders++;
711 }
712
713 if (num_encoders != 1)
714 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
715 pipe_name(intel_crtc->pipe));
716
717 BUG_ON(ret == NULL);
718 return ret;
719 }
720
721 struct intel_encoder *
722 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
723 {
724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
725 struct intel_encoder *ret = NULL;
726 struct drm_atomic_state *state;
727 struct drm_connector *connector;
728 struct drm_connector_state *connector_state;
729 int num_encoders = 0;
730 int i;
731
732 state = crtc_state->base.state;
733
734 for_each_connector_in_state(state, connector, connector_state, i) {
735 if (connector_state->crtc != crtc_state->base.crtc)
736 continue;
737
738 ret = to_intel_encoder(connector_state->best_encoder);
739 num_encoders++;
740 }
741
742 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
743 pipe_name(crtc->pipe));
744
745 BUG_ON(ret == NULL);
746 return ret;
747 }
748
749 #define LC_FREQ 2700
750
751 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
752 i915_reg_t reg)
753 {
754 int refclk = LC_FREQ;
755 int n, p, r;
756 u32 wrpll;
757
758 wrpll = I915_READ(reg);
759 switch (wrpll & WRPLL_PLL_REF_MASK) {
760 case WRPLL_PLL_SSC:
761 case WRPLL_PLL_NON_SSC:
762 /*
763 * We could calculate spread here, but our checking
764 * code only cares about 5% accuracy, and spread is a max of
765 * 0.5% downspread.
766 */
767 refclk = 135;
768 break;
769 case WRPLL_PLL_LCPLL:
770 refclk = LC_FREQ;
771 break;
772 default:
773 WARN(1, "bad wrpll refclk\n");
774 return 0;
775 }
776
777 r = wrpll & WRPLL_DIVIDER_REF_MASK;
778 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
779 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
780
781 /* Convert to KHz, p & r have a fixed point portion */
782 return (refclk * n * 100) / (p * r);
783 }
784
785 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
786 uint32_t dpll)
787 {
788 i915_reg_t cfgcr1_reg, cfgcr2_reg;
789 uint32_t cfgcr1_val, cfgcr2_val;
790 uint32_t p0, p1, p2, dco_freq;
791
792 cfgcr1_reg = DPLL_CFGCR1(dpll);
793 cfgcr2_reg = DPLL_CFGCR2(dpll);
794
795 cfgcr1_val = I915_READ(cfgcr1_reg);
796 cfgcr2_val = I915_READ(cfgcr2_reg);
797
798 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
799 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
800
801 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
802 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
803 else
804 p1 = 1;
805
806
807 switch (p0) {
808 case DPLL_CFGCR2_PDIV_1:
809 p0 = 1;
810 break;
811 case DPLL_CFGCR2_PDIV_2:
812 p0 = 2;
813 break;
814 case DPLL_CFGCR2_PDIV_3:
815 p0 = 3;
816 break;
817 case DPLL_CFGCR2_PDIV_7:
818 p0 = 7;
819 break;
820 }
821
822 switch (p2) {
823 case DPLL_CFGCR2_KDIV_5:
824 p2 = 5;
825 break;
826 case DPLL_CFGCR2_KDIV_2:
827 p2 = 2;
828 break;
829 case DPLL_CFGCR2_KDIV_3:
830 p2 = 3;
831 break;
832 case DPLL_CFGCR2_KDIV_1:
833 p2 = 1;
834 break;
835 }
836
837 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
838
839 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
840 1000) / 0x8000;
841
842 return dco_freq / (p0 * p1 * p2 * 5);
843 }
844
845 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
846 {
847 int dotclock;
848
849 if (pipe_config->has_pch_encoder)
850 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
851 &pipe_config->fdi_m_n);
852 else if (intel_crtc_has_dp_encoder(pipe_config))
853 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
854 &pipe_config->dp_m_n);
855 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
856 dotclock = pipe_config->port_clock * 2 / 3;
857 else
858 dotclock = pipe_config->port_clock;
859
860 if (pipe_config->pixel_multiplier)
861 dotclock /= pipe_config->pixel_multiplier;
862
863 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
864 }
865
866 static void skl_ddi_clock_get(struct intel_encoder *encoder,
867 struct intel_crtc_state *pipe_config)
868 {
869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
870 int link_clock = 0;
871 uint32_t dpll_ctl1, dpll;
872
873 dpll = pipe_config->ddi_pll_sel;
874
875 dpll_ctl1 = I915_READ(DPLL_CTRL1);
876
877 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
878 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
879 } else {
880 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
881 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
882
883 switch (link_clock) {
884 case DPLL_CTRL1_LINK_RATE_810:
885 link_clock = 81000;
886 break;
887 case DPLL_CTRL1_LINK_RATE_1080:
888 link_clock = 108000;
889 break;
890 case DPLL_CTRL1_LINK_RATE_1350:
891 link_clock = 135000;
892 break;
893 case DPLL_CTRL1_LINK_RATE_1620:
894 link_clock = 162000;
895 break;
896 case DPLL_CTRL1_LINK_RATE_2160:
897 link_clock = 216000;
898 break;
899 case DPLL_CTRL1_LINK_RATE_2700:
900 link_clock = 270000;
901 break;
902 default:
903 WARN(1, "Unsupported link rate\n");
904 break;
905 }
906 link_clock *= 2;
907 }
908
909 pipe_config->port_clock = link_clock;
910
911 ddi_dotclock_get(pipe_config);
912 }
913
914 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
915 struct intel_crtc_state *pipe_config)
916 {
917 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
918 int link_clock = 0;
919 u32 val, pll;
920
921 val = pipe_config->ddi_pll_sel;
922 switch (val & PORT_CLK_SEL_MASK) {
923 case PORT_CLK_SEL_LCPLL_810:
924 link_clock = 81000;
925 break;
926 case PORT_CLK_SEL_LCPLL_1350:
927 link_clock = 135000;
928 break;
929 case PORT_CLK_SEL_LCPLL_2700:
930 link_clock = 270000;
931 break;
932 case PORT_CLK_SEL_WRPLL1:
933 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
934 break;
935 case PORT_CLK_SEL_WRPLL2:
936 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
937 break;
938 case PORT_CLK_SEL_SPLL:
939 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
940 if (pll == SPLL_PLL_FREQ_810MHz)
941 link_clock = 81000;
942 else if (pll == SPLL_PLL_FREQ_1350MHz)
943 link_clock = 135000;
944 else if (pll == SPLL_PLL_FREQ_2700MHz)
945 link_clock = 270000;
946 else {
947 WARN(1, "bad spll freq\n");
948 return;
949 }
950 break;
951 default:
952 WARN(1, "bad port clock sel\n");
953 return;
954 }
955
956 pipe_config->port_clock = link_clock * 2;
957
958 ddi_dotclock_get(pipe_config);
959 }
960
961 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
962 enum intel_dpll_id dpll)
963 {
964 struct intel_shared_dpll *pll;
965 struct intel_dpll_hw_state *state;
966 struct dpll clock;
967
968 /* For DDI ports we always use a shared PLL. */
969 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
970 return 0;
971
972 pll = &dev_priv->shared_dplls[dpll];
973 state = &pll->config.hw_state;
974
975 clock.m1 = 2;
976 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
977 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
978 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
979 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
980 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
981 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
982
983 return chv_calc_dpll_params(100000, &clock);
984 }
985
986 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
987 struct intel_crtc_state *pipe_config)
988 {
989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
990 enum port port = intel_ddi_get_encoder_port(encoder);
991 uint32_t dpll = port;
992
993 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
994
995 ddi_dotclock_get(pipe_config);
996 }
997
998 void intel_ddi_clock_get(struct intel_encoder *encoder,
999 struct intel_crtc_state *pipe_config)
1000 {
1001 struct drm_device *dev = encoder->base.dev;
1002
1003 if (INTEL_INFO(dev)->gen <= 8)
1004 hsw_ddi_clock_get(encoder, pipe_config);
1005 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1006 skl_ddi_clock_get(encoder, pipe_config);
1007 else if (IS_BROXTON(dev))
1008 bxt_ddi_clock_get(encoder, pipe_config);
1009 }
1010
1011 static bool
1012 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1013 struct intel_crtc_state *crtc_state,
1014 struct intel_encoder *intel_encoder)
1015 {
1016 struct intel_shared_dpll *pll;
1017
1018 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1019 intel_encoder);
1020 if (!pll)
1021 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022 pipe_name(intel_crtc->pipe));
1023
1024 return pll;
1025 }
1026
1027 static bool
1028 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1029 struct intel_crtc_state *crtc_state,
1030 struct intel_encoder *intel_encoder)
1031 {
1032 struct intel_shared_dpll *pll;
1033
1034 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1035 if (pll == NULL) {
1036 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1037 pipe_name(intel_crtc->pipe));
1038 return false;
1039 }
1040
1041 return true;
1042 }
1043
1044 static bool
1045 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1046 struct intel_crtc_state *crtc_state,
1047 struct intel_encoder *intel_encoder)
1048 {
1049 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1050 }
1051
1052 /*
1053 * Tries to find a *shared* PLL for the CRTC and store it in
1054 * intel_crtc->ddi_pll_sel.
1055 *
1056 * For private DPLLs, compute_config() should do the selection for us. This
1057 * function should be folded into compute_config() eventually.
1058 */
1059 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1060 struct intel_crtc_state *crtc_state)
1061 {
1062 struct drm_device *dev = intel_crtc->base.dev;
1063 struct intel_encoder *intel_encoder =
1064 intel_ddi_get_crtc_new_encoder(crtc_state);
1065
1066 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1067 return skl_ddi_pll_select(intel_crtc, crtc_state,
1068 intel_encoder);
1069 else if (IS_BROXTON(dev))
1070 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1071 intel_encoder);
1072 else
1073 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1074 intel_encoder);
1075 }
1076
1077 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1078 {
1079 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1081 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1082 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1083 int type = intel_encoder->type;
1084 uint32_t temp;
1085
1086 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1087 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1088
1089 temp = TRANS_MSA_SYNC_CLK;
1090 switch (intel_crtc->config->pipe_bpp) {
1091 case 18:
1092 temp |= TRANS_MSA_6_BPC;
1093 break;
1094 case 24:
1095 temp |= TRANS_MSA_8_BPC;
1096 break;
1097 case 30:
1098 temp |= TRANS_MSA_10_BPC;
1099 break;
1100 case 36:
1101 temp |= TRANS_MSA_12_BPC;
1102 break;
1103 default:
1104 BUG();
1105 }
1106 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1107 }
1108 }
1109
1110 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1111 {
1112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1113 struct drm_device *dev = crtc->dev;
1114 struct drm_i915_private *dev_priv = to_i915(dev);
1115 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1116 uint32_t temp;
1117 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1118 if (state == true)
1119 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1120 else
1121 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1122 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1123 }
1124
1125 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1126 {
1127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1128 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1129 struct drm_encoder *encoder = &intel_encoder->base;
1130 struct drm_device *dev = crtc->dev;
1131 struct drm_i915_private *dev_priv = to_i915(dev);
1132 enum pipe pipe = intel_crtc->pipe;
1133 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1134 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1135 int type = intel_encoder->type;
1136 uint32_t temp;
1137
1138 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1139 temp = TRANS_DDI_FUNC_ENABLE;
1140 temp |= TRANS_DDI_SELECT_PORT(port);
1141
1142 switch (intel_crtc->config->pipe_bpp) {
1143 case 18:
1144 temp |= TRANS_DDI_BPC_6;
1145 break;
1146 case 24:
1147 temp |= TRANS_DDI_BPC_8;
1148 break;
1149 case 30:
1150 temp |= TRANS_DDI_BPC_10;
1151 break;
1152 case 36:
1153 temp |= TRANS_DDI_BPC_12;
1154 break;
1155 default:
1156 BUG();
1157 }
1158
1159 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1160 temp |= TRANS_DDI_PVSYNC;
1161 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1162 temp |= TRANS_DDI_PHSYNC;
1163
1164 if (cpu_transcoder == TRANSCODER_EDP) {
1165 switch (pipe) {
1166 case PIPE_A:
1167 /* On Haswell, can only use the always-on power well for
1168 * eDP when not using the panel fitter, and when not
1169 * using motion blur mitigation (which we don't
1170 * support). */
1171 if (IS_HASWELL(dev) &&
1172 (intel_crtc->config->pch_pfit.enabled ||
1173 intel_crtc->config->pch_pfit.force_thru))
1174 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1175 else
1176 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1177 break;
1178 case PIPE_B:
1179 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1180 break;
1181 case PIPE_C:
1182 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1183 break;
1184 default:
1185 BUG();
1186 break;
1187 }
1188 }
1189
1190 if (type == INTEL_OUTPUT_HDMI) {
1191 if (intel_crtc->config->has_hdmi_sink)
1192 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1193 else
1194 temp |= TRANS_DDI_MODE_SELECT_DVI;
1195
1196 } else if (type == INTEL_OUTPUT_ANALOG) {
1197 temp |= TRANS_DDI_MODE_SELECT_FDI;
1198 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1199
1200 } else if (type == INTEL_OUTPUT_DP ||
1201 type == INTEL_OUTPUT_EDP) {
1202 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1203
1204 if (intel_dp->is_mst) {
1205 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1206 } else
1207 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1208
1209 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1210 } else if (type == INTEL_OUTPUT_DP_MST) {
1211 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1212
1213 if (intel_dp->is_mst) {
1214 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1215 } else
1216 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1217
1218 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1219 } else {
1220 WARN(1, "Invalid encoder type %d for pipe %c\n",
1221 intel_encoder->type, pipe_name(pipe));
1222 }
1223
1224 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1225 }
1226
1227 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1228 enum transcoder cpu_transcoder)
1229 {
1230 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1231 uint32_t val = I915_READ(reg);
1232
1233 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1234 val |= TRANS_DDI_PORT_NONE;
1235 I915_WRITE(reg, val);
1236 }
1237
1238 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1239 {
1240 struct drm_device *dev = intel_connector->base.dev;
1241 struct drm_i915_private *dev_priv = to_i915(dev);
1242 struct intel_encoder *intel_encoder = intel_connector->encoder;
1243 int type = intel_connector->base.connector_type;
1244 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1245 enum pipe pipe = 0;
1246 enum transcoder cpu_transcoder;
1247 enum intel_display_power_domain power_domain;
1248 uint32_t tmp;
1249 bool ret;
1250
1251 power_domain = intel_display_port_power_domain(intel_encoder);
1252 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1253 return false;
1254
1255 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1256 ret = false;
1257 goto out;
1258 }
1259
1260 if (port == PORT_A)
1261 cpu_transcoder = TRANSCODER_EDP;
1262 else
1263 cpu_transcoder = (enum transcoder) pipe;
1264
1265 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1266
1267 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1268 case TRANS_DDI_MODE_SELECT_HDMI:
1269 case TRANS_DDI_MODE_SELECT_DVI:
1270 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1271 break;
1272
1273 case TRANS_DDI_MODE_SELECT_DP_SST:
1274 ret = type == DRM_MODE_CONNECTOR_eDP ||
1275 type == DRM_MODE_CONNECTOR_DisplayPort;
1276 break;
1277
1278 case TRANS_DDI_MODE_SELECT_DP_MST:
1279 /* if the transcoder is in MST state then
1280 * connector isn't connected */
1281 ret = false;
1282 break;
1283
1284 case TRANS_DDI_MODE_SELECT_FDI:
1285 ret = type == DRM_MODE_CONNECTOR_VGA;
1286 break;
1287
1288 default:
1289 ret = false;
1290 break;
1291 }
1292
1293 out:
1294 intel_display_power_put(dev_priv, power_domain);
1295
1296 return ret;
1297 }
1298
1299 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1300 enum pipe *pipe)
1301 {
1302 struct drm_device *dev = encoder->base.dev;
1303 struct drm_i915_private *dev_priv = to_i915(dev);
1304 enum port port = intel_ddi_get_encoder_port(encoder);
1305 enum intel_display_power_domain power_domain;
1306 u32 tmp;
1307 int i;
1308 bool ret;
1309
1310 power_domain = intel_display_port_power_domain(encoder);
1311 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1312 return false;
1313
1314 ret = false;
1315
1316 tmp = I915_READ(DDI_BUF_CTL(port));
1317
1318 if (!(tmp & DDI_BUF_CTL_ENABLE))
1319 goto out;
1320
1321 if (port == PORT_A) {
1322 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1323
1324 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1325 case TRANS_DDI_EDP_INPUT_A_ON:
1326 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1327 *pipe = PIPE_A;
1328 break;
1329 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1330 *pipe = PIPE_B;
1331 break;
1332 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1333 *pipe = PIPE_C;
1334 break;
1335 }
1336
1337 ret = true;
1338
1339 goto out;
1340 }
1341
1342 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1343 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1344
1345 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1346 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1347 TRANS_DDI_MODE_SELECT_DP_MST)
1348 goto out;
1349
1350 *pipe = i;
1351 ret = true;
1352
1353 goto out;
1354 }
1355 }
1356
1357 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1358
1359 out:
1360 if (ret && IS_BROXTON(dev_priv)) {
1361 tmp = I915_READ(BXT_PHY_CTL(port));
1362 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1363 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1364 DRM_ERROR("Port %c enabled but PHY powered down? "
1365 "(PHY_CTL %08x)\n", port_name(port), tmp);
1366 }
1367
1368 intel_display_power_put(dev_priv, power_domain);
1369
1370 return ret;
1371 }
1372
1373 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1374 {
1375 struct drm_crtc *crtc = &intel_crtc->base;
1376 struct drm_device *dev = crtc->dev;
1377 struct drm_i915_private *dev_priv = to_i915(dev);
1378 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1379 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1380 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1381
1382 if (cpu_transcoder != TRANSCODER_EDP)
1383 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1384 TRANS_CLK_SEL_PORT(port));
1385 }
1386
1387 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1388 {
1389 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1390 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1391
1392 if (cpu_transcoder != TRANSCODER_EDP)
1393 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1394 TRANS_CLK_SEL_DISABLED);
1395 }
1396
1397 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1398 enum port port, uint8_t iboost)
1399 {
1400 u32 tmp;
1401
1402 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1403 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1404 if (iboost)
1405 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1406 else
1407 tmp |= BALANCE_LEG_DISABLE(port);
1408 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1409 }
1410
1411 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1412 {
1413 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1414 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1415 enum port port = intel_dig_port->port;
1416 int type = encoder->type;
1417 const struct ddi_buf_trans *ddi_translations;
1418 uint8_t iboost;
1419 uint8_t dp_iboost, hdmi_iboost;
1420 int n_entries;
1421
1422 /* VBT may override standard boost values */
1423 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1424 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1425
1426 if (type == INTEL_OUTPUT_DP) {
1427 if (dp_iboost) {
1428 iboost = dp_iboost;
1429 } else {
1430 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
1431 iboost = ddi_translations[level].i_boost;
1432 }
1433 } else if (type == INTEL_OUTPUT_EDP) {
1434 if (dp_iboost) {
1435 iboost = dp_iboost;
1436 } else {
1437 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1438
1439 if (WARN_ON(port != PORT_A &&
1440 port != PORT_E && n_entries > 9))
1441 n_entries = 9;
1442
1443 iboost = ddi_translations[level].i_boost;
1444 }
1445 } else if (type == INTEL_OUTPUT_HDMI) {
1446 if (hdmi_iboost) {
1447 iboost = hdmi_iboost;
1448 } else {
1449 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1450 iboost = ddi_translations[level].i_boost;
1451 }
1452 } else {
1453 return;
1454 }
1455
1456 /* Make sure that the requested I_boost is valid */
1457 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1458 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1459 return;
1460 }
1461
1462 _skl_ddi_set_iboost(dev_priv, port, iboost);
1463
1464 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1465 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1466 }
1467
1468 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1469 u32 level, enum port port, int type)
1470 {
1471 const struct bxt_ddi_buf_trans *ddi_translations;
1472 u32 n_entries, i;
1473 uint32_t val;
1474
1475 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1476 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1477 ddi_translations = bxt_ddi_translations_edp;
1478 } else if (type == INTEL_OUTPUT_DP
1479 || type == INTEL_OUTPUT_EDP) {
1480 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1481 ddi_translations = bxt_ddi_translations_dp;
1482 } else if (type == INTEL_OUTPUT_HDMI) {
1483 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1484 ddi_translations = bxt_ddi_translations_hdmi;
1485 } else {
1486 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1487 type);
1488 return;
1489 }
1490
1491 /* Check if default value has to be used */
1492 if (level >= n_entries ||
1493 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1494 for (i = 0; i < n_entries; i++) {
1495 if (ddi_translations[i].default_index) {
1496 level = i;
1497 break;
1498 }
1499 }
1500 }
1501
1502 /*
1503 * While we write to the group register to program all lanes at once we
1504 * can read only lane registers and we pick lanes 0/1 for that.
1505 */
1506 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1507 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1508 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1509
1510 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1511 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1512 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1513 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1514 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1515
1516 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1517 val &= ~SCALE_DCOMP_METHOD;
1518 if (ddi_translations[level].enable)
1519 val |= SCALE_DCOMP_METHOD;
1520
1521 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1522 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1523
1524 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1525
1526 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1527 val &= ~DE_EMPHASIS;
1528 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1529 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1530
1531 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1532 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1533 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1534 }
1535
1536 static uint32_t translate_signal_level(int signal_levels)
1537 {
1538 uint32_t level;
1539
1540 switch (signal_levels) {
1541 default:
1542 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1543 signal_levels);
1544 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1545 level = 0;
1546 break;
1547 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1548 level = 1;
1549 break;
1550 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1551 level = 2;
1552 break;
1553 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1554 level = 3;
1555 break;
1556
1557 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1558 level = 4;
1559 break;
1560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1561 level = 5;
1562 break;
1563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1564 level = 6;
1565 break;
1566
1567 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1568 level = 7;
1569 break;
1570 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1571 level = 8;
1572 break;
1573
1574 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1575 level = 9;
1576 break;
1577 }
1578
1579 return level;
1580 }
1581
1582 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1583 {
1584 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1585 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1586 struct intel_encoder *encoder = &dport->base;
1587 uint8_t train_set = intel_dp->train_set[0];
1588 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1589 DP_TRAIN_PRE_EMPHASIS_MASK);
1590 enum port port = dport->port;
1591 uint32_t level;
1592
1593 level = translate_signal_level(signal_levels);
1594
1595 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1596 skl_ddi_set_iboost(encoder, level);
1597 else if (IS_BROXTON(dev_priv))
1598 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1599
1600 return DDI_BUF_TRANS_SELECT(level);
1601 }
1602
1603 void intel_ddi_clk_select(struct intel_encoder *encoder,
1604 const struct intel_crtc_state *pipe_config)
1605 {
1606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1607 enum port port = intel_ddi_get_encoder_port(encoder);
1608
1609 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1610 uint32_t dpll = pipe_config->ddi_pll_sel;
1611 uint32_t val;
1612
1613 /* DDI -> PLL mapping */
1614 val = I915_READ(DPLL_CTRL2);
1615
1616 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1617 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1618 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1619 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1620
1621 I915_WRITE(DPLL_CTRL2, val);
1622
1623 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1624 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1625 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
1626 }
1627 }
1628
1629 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1630 {
1631 struct drm_encoder *encoder = &intel_encoder->base;
1632 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1634 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1635 int type = intel_encoder->type;
1636
1637 if (type == INTEL_OUTPUT_HDMI) {
1638 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1639
1640 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1641 }
1642
1643 if (type == INTEL_OUTPUT_EDP) {
1644 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1645 intel_edp_panel_on(intel_dp);
1646 }
1647
1648 intel_ddi_clk_select(intel_encoder, crtc->config);
1649
1650 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1651 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1652
1653 intel_prepare_dp_ddi_buffers(intel_encoder);
1654
1655 intel_dp_set_link_params(intel_dp, crtc->config);
1656
1657 intel_ddi_init_dp_buf_reg(intel_encoder);
1658
1659 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1660 intel_dp_start_link_train(intel_dp);
1661 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
1662 intel_dp_stop_link_train(intel_dp);
1663 } else if (type == INTEL_OUTPUT_HDMI) {
1664 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1665 int level = intel_ddi_hdmi_level(dev_priv, port);
1666
1667 intel_prepare_hdmi_ddi_buffers(intel_encoder);
1668
1669 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1670 skl_ddi_set_iboost(intel_encoder, level);
1671 else if (IS_BROXTON(dev_priv))
1672 bxt_ddi_vswing_sequence(dev_priv, level, port,
1673 INTEL_OUTPUT_HDMI);
1674
1675 intel_hdmi->set_infoframes(encoder,
1676 crtc->config->has_hdmi_sink,
1677 &crtc->config->base.adjusted_mode);
1678 }
1679 }
1680
1681 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1682 {
1683 struct drm_encoder *encoder = &intel_encoder->base;
1684 struct drm_device *dev = encoder->dev;
1685 struct drm_i915_private *dev_priv = to_i915(dev);
1686 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1687 int type = intel_encoder->type;
1688 uint32_t val;
1689 bool wait = false;
1690
1691 val = I915_READ(DDI_BUF_CTL(port));
1692 if (val & DDI_BUF_CTL_ENABLE) {
1693 val &= ~DDI_BUF_CTL_ENABLE;
1694 I915_WRITE(DDI_BUF_CTL(port), val);
1695 wait = true;
1696 }
1697
1698 val = I915_READ(DP_TP_CTL(port));
1699 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1700 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1701 I915_WRITE(DP_TP_CTL(port), val);
1702
1703 if (wait)
1704 intel_wait_ddi_buf_idle(dev_priv, port);
1705
1706 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1707 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1708 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1709 intel_edp_panel_vdd_on(intel_dp);
1710 intel_edp_panel_off(intel_dp);
1711 }
1712
1713 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1714 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1715 DPLL_CTRL2_DDI_CLK_OFF(port)));
1716 else if (INTEL_INFO(dev)->gen < 9)
1717 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1718
1719 if (type == INTEL_OUTPUT_HDMI) {
1720 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1721
1722 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1723 }
1724 }
1725
1726 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1727 {
1728 struct drm_encoder *encoder = &intel_encoder->base;
1729 struct drm_crtc *crtc = encoder->crtc;
1730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1731 struct drm_device *dev = encoder->dev;
1732 struct drm_i915_private *dev_priv = to_i915(dev);
1733 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1734 int type = intel_encoder->type;
1735
1736 if (type == INTEL_OUTPUT_HDMI) {
1737 struct intel_digital_port *intel_dig_port =
1738 enc_to_dig_port(encoder);
1739
1740 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1741 * are ignored so nothing special needs to be done besides
1742 * enabling the port.
1743 */
1744 I915_WRITE(DDI_BUF_CTL(port),
1745 intel_dig_port->saved_port_bits |
1746 DDI_BUF_CTL_ENABLE);
1747 } else if (type == INTEL_OUTPUT_EDP) {
1748 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1749
1750 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1751 intel_dp_stop_link_train(intel_dp);
1752
1753 intel_edp_backlight_on(intel_dp);
1754 intel_psr_enable(intel_dp);
1755 intel_edp_drrs_enable(intel_dp);
1756 }
1757
1758 if (intel_crtc->config->has_audio) {
1759 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1760 intel_audio_codec_enable(intel_encoder);
1761 }
1762 }
1763
1764 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1765 {
1766 struct drm_encoder *encoder = &intel_encoder->base;
1767 struct drm_crtc *crtc = encoder->crtc;
1768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1769 int type = intel_encoder->type;
1770 struct drm_device *dev = encoder->dev;
1771 struct drm_i915_private *dev_priv = to_i915(dev);
1772
1773 if (intel_crtc->config->has_audio) {
1774 intel_audio_codec_disable(intel_encoder);
1775 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1776 }
1777
1778 if (type == INTEL_OUTPUT_EDP) {
1779 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1780
1781 intel_edp_drrs_disable(intel_dp);
1782 intel_psr_disable(intel_dp);
1783 intel_edp_backlight_off(intel_dp);
1784 }
1785 }
1786
1787 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1788 enum dpio_phy phy)
1789 {
1790 enum port port;
1791
1792 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1793 return false;
1794
1795 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1796 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1797 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1798 phy);
1799
1800 return false;
1801 }
1802
1803 if (phy == DPIO_PHY1 &&
1804 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1805 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1806
1807 return false;
1808 }
1809
1810 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1811 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1812 phy);
1813
1814 return false;
1815 }
1816
1817 for_each_port_masked(port,
1818 phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1819 BIT(PORT_A)) {
1820 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1821
1822 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1823 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1824 "for port %c powered down "
1825 "(PHY_CTL %08x)\n",
1826 phy, port_name(port), tmp);
1827
1828 return false;
1829 }
1830 }
1831
1832 return true;
1833 }
1834
1835 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1836 {
1837 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1838
1839 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1840 }
1841
1842 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1843 enum dpio_phy phy)
1844 {
1845 if (intel_wait_for_register(dev_priv,
1846 BXT_PORT_REF_DW3(phy),
1847 GRC_DONE, GRC_DONE,
1848 10))
1849 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1850 }
1851
1852 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1853 {
1854 u32 val;
1855
1856 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
1857 /* Still read out the GRC value for state verification */
1858 if (phy == DPIO_PHY0)
1859 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
1860
1861 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
1862 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1863 "won't reprogram it\n", phy);
1864
1865 return;
1866 }
1867
1868 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1869 "force reprogramming it\n", phy);
1870 }
1871
1872 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1873 val |= GT_DISPLAY_POWER_ON(phy);
1874 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1875
1876 /*
1877 * The PHY registers start out inaccessible and respond to reads with
1878 * all 1s. Eventually they become accessible as they power up, then
1879 * the reserved bit will give the default 0. Poll on the reserved bit
1880 * becoming 0 to find when the PHY is accessible.
1881 * HW team confirmed that the time to reach phypowergood status is
1882 * anywhere between 50 us and 100us.
1883 */
1884 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1885 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
1886 DRM_ERROR("timeout during PHY%d power on\n", phy);
1887 }
1888
1889 /* Program PLL Rcomp code offset */
1890 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1891 val &= ~IREF0RC_OFFSET_MASK;
1892 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1893 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1894
1895 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1896 val &= ~IREF1RC_OFFSET_MASK;
1897 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1898 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1899
1900 /* Program power gating */
1901 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1902 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1903 SUS_CLK_CONFIG;
1904 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1905
1906 if (phy == DPIO_PHY0) {
1907 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1908 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1909 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1910 }
1911
1912 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1913 val &= ~OCL2_LDOFUSE_PWR_DIS;
1914 /*
1915 * On PHY1 disable power on the second channel, since no port is
1916 * connected there. On PHY0 both channels have a port, so leave it
1917 * enabled.
1918 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1919 * power down the second channel on PHY0 as well.
1920 *
1921 * FIXME: Clarify programming of the following, the register is
1922 * read-only with bit 6 fixed at 0 at least in stepping A.
1923 */
1924 if (phy == DPIO_PHY1)
1925 val |= OCL2_LDOFUSE_PWR_DIS;
1926 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1927
1928 if (phy == DPIO_PHY0) {
1929 uint32_t grc_code;
1930 /*
1931 * PHY0 isn't connected to an RCOMP resistor so copy over
1932 * the corresponding calibrated value from PHY1, and disable
1933 * the automatic calibration on PHY0.
1934 */
1935 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
1936 grc_code = val << GRC_CODE_FAST_SHIFT |
1937 val << GRC_CODE_SLOW_SHIFT |
1938 val;
1939 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1940
1941 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1942 val |= GRC_DIS | GRC_RDY_OVRD;
1943 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1944 }
1945
1946 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1947 val |= COMMON_RESET_DIS;
1948 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1949
1950 if (phy == DPIO_PHY1)
1951 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
1952 }
1953
1954 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1955 {
1956 uint32_t val;
1957
1958 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1959 val &= ~COMMON_RESET_DIS;
1960 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1961
1962 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1963 val &= ~GT_DISPLAY_POWER_ON(phy);
1964 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1965 }
1966
1967 static bool __printf(6, 7)
1968 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1969 i915_reg_t reg, u32 mask, u32 expected,
1970 const char *reg_fmt, ...)
1971 {
1972 struct va_format vaf;
1973 va_list args;
1974 u32 val;
1975
1976 val = I915_READ(reg);
1977 if ((val & mask) == expected)
1978 return true;
1979
1980 va_start(args, reg_fmt);
1981 vaf.fmt = reg_fmt;
1982 vaf.va = &args;
1983
1984 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1985 "current %08x, expected %08x (mask %08x)\n",
1986 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1987 mask);
1988
1989 va_end(args);
1990
1991 return false;
1992 }
1993
1994 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1995 enum dpio_phy phy)
1996 {
1997 uint32_t mask;
1998 bool ok;
1999
2000 #define _CHK(reg, mask, exp, fmt, ...) \
2001 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
2002 ## __VA_ARGS__)
2003
2004 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
2005 return false;
2006
2007 ok = true;
2008
2009 /* PLL Rcomp code offset */
2010 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
2011 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
2012 "BXT_PORT_CL1CM_DW9(%d)", phy);
2013 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
2014 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2015 "BXT_PORT_CL1CM_DW10(%d)", phy);
2016
2017 /* Power gating */
2018 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2019 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2020 "BXT_PORT_CL1CM_DW28(%d)", phy);
2021
2022 if (phy == DPIO_PHY0)
2023 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2024 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2025 "BXT_PORT_CL2CM_DW6_BC");
2026
2027 /*
2028 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2029 * at least on stepping A this bit is read-only and fixed at 0.
2030 */
2031
2032 if (phy == DPIO_PHY0) {
2033 u32 grc_code = dev_priv->bxt_phy_grc;
2034
2035 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2036 grc_code << GRC_CODE_SLOW_SHIFT |
2037 grc_code;
2038 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2039 GRC_CODE_NOM_MASK;
2040 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2041 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2042
2043 mask = GRC_DIS | GRC_RDY_OVRD;
2044 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2045 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2046 }
2047
2048 return ok;
2049 #undef _CHK
2050 }
2051
2052 static uint8_t
2053 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2054 struct intel_crtc_state *pipe_config)
2055 {
2056 switch (pipe_config->lane_count) {
2057 case 1:
2058 return 0;
2059 case 2:
2060 return BIT(2) | BIT(0);
2061 case 4:
2062 return BIT(3) | BIT(2) | BIT(0);
2063 default:
2064 MISSING_CASE(pipe_config->lane_count);
2065
2066 return 0;
2067 }
2068 }
2069
2070 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder)
2071 {
2072 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2073 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2074 enum port port = dport->port;
2075 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2076 int lane;
2077
2078 for (lane = 0; lane < 4; lane++) {
2079 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2080
2081 /*
2082 * Note that on CHV this flag is called UPAR, but has
2083 * the same function.
2084 */
2085 val &= ~LATENCY_OPTIM;
2086 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2087 val |= LATENCY_OPTIM;
2088
2089 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2090 }
2091 }
2092
2093 static uint8_t
2094 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2095 {
2096 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2097 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2098 enum port port = dport->port;
2099 int lane;
2100 uint8_t mask;
2101
2102 mask = 0;
2103 for (lane = 0; lane < 4; lane++) {
2104 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2105
2106 if (val & LATENCY_OPTIM)
2107 mask |= BIT(lane);
2108 }
2109
2110 return mask;
2111 }
2112
2113 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2114 {
2115 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2116 struct drm_i915_private *dev_priv =
2117 to_i915(intel_dig_port->base.base.dev);
2118 enum port port = intel_dig_port->port;
2119 uint32_t val;
2120 bool wait = false;
2121
2122 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2123 val = I915_READ(DDI_BUF_CTL(port));
2124 if (val & DDI_BUF_CTL_ENABLE) {
2125 val &= ~DDI_BUF_CTL_ENABLE;
2126 I915_WRITE(DDI_BUF_CTL(port), val);
2127 wait = true;
2128 }
2129
2130 val = I915_READ(DP_TP_CTL(port));
2131 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2132 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2133 I915_WRITE(DP_TP_CTL(port), val);
2134 POSTING_READ(DP_TP_CTL(port));
2135
2136 if (wait)
2137 intel_wait_ddi_buf_idle(dev_priv, port);
2138 }
2139
2140 val = DP_TP_CTL_ENABLE |
2141 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2142 if (intel_dp->is_mst)
2143 val |= DP_TP_CTL_MODE_MST;
2144 else {
2145 val |= DP_TP_CTL_MODE_SST;
2146 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2147 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2148 }
2149 I915_WRITE(DP_TP_CTL(port), val);
2150 POSTING_READ(DP_TP_CTL(port));
2151
2152 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2153 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2154 POSTING_READ(DDI_BUF_CTL(port));
2155
2156 udelay(600);
2157 }
2158
2159 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2160 {
2161 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2162 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2163 uint32_t val;
2164
2165 /*
2166 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2167 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2168 * step 13 is the correct place for it. Step 18 is where it was
2169 * originally before the BUN.
2170 */
2171 val = I915_READ(FDI_RX_CTL(PIPE_A));
2172 val &= ~FDI_RX_ENABLE;
2173 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2174
2175 intel_ddi_post_disable(intel_encoder);
2176
2177 val = I915_READ(FDI_RX_MISC(PIPE_A));
2178 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2179 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2180 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2181
2182 val = I915_READ(FDI_RX_CTL(PIPE_A));
2183 val &= ~FDI_PCDCLK;
2184 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2185
2186 val = I915_READ(FDI_RX_CTL(PIPE_A));
2187 val &= ~FDI_RX_PLL_ENABLE;
2188 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2189 }
2190
2191 void intel_ddi_get_config(struct intel_encoder *encoder,
2192 struct intel_crtc_state *pipe_config)
2193 {
2194 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2195 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2196 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2197 struct intel_hdmi *intel_hdmi;
2198 u32 temp, flags = 0;
2199
2200 /* XXX: DSI transcoder paranoia */
2201 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2202 return;
2203
2204 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2205 if (temp & TRANS_DDI_PHSYNC)
2206 flags |= DRM_MODE_FLAG_PHSYNC;
2207 else
2208 flags |= DRM_MODE_FLAG_NHSYNC;
2209 if (temp & TRANS_DDI_PVSYNC)
2210 flags |= DRM_MODE_FLAG_PVSYNC;
2211 else
2212 flags |= DRM_MODE_FLAG_NVSYNC;
2213
2214 pipe_config->base.adjusted_mode.flags |= flags;
2215
2216 switch (temp & TRANS_DDI_BPC_MASK) {
2217 case TRANS_DDI_BPC_6:
2218 pipe_config->pipe_bpp = 18;
2219 break;
2220 case TRANS_DDI_BPC_8:
2221 pipe_config->pipe_bpp = 24;
2222 break;
2223 case TRANS_DDI_BPC_10:
2224 pipe_config->pipe_bpp = 30;
2225 break;
2226 case TRANS_DDI_BPC_12:
2227 pipe_config->pipe_bpp = 36;
2228 break;
2229 default:
2230 break;
2231 }
2232
2233 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2234 case TRANS_DDI_MODE_SELECT_HDMI:
2235 pipe_config->has_hdmi_sink = true;
2236 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2237
2238 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2239 pipe_config->has_infoframe = true;
2240 /* fall through */
2241 case TRANS_DDI_MODE_SELECT_DVI:
2242 pipe_config->lane_count = 4;
2243 break;
2244 case TRANS_DDI_MODE_SELECT_FDI:
2245 break;
2246 case TRANS_DDI_MODE_SELECT_DP_SST:
2247 case TRANS_DDI_MODE_SELECT_DP_MST:
2248 pipe_config->lane_count =
2249 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2250 intel_dp_get_m_n(intel_crtc, pipe_config);
2251 break;
2252 default:
2253 break;
2254 }
2255
2256 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2257 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2258 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2259 pipe_config->has_audio = true;
2260 }
2261
2262 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2263 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2264 /*
2265 * This is a big fat ugly hack.
2266 *
2267 * Some machines in UEFI boot mode provide us a VBT that has 18
2268 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2269 * unknown we fail to light up. Yet the same BIOS boots up with
2270 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2271 * max, not what it tells us to use.
2272 *
2273 * Note: This will still be broken if the eDP panel is not lit
2274 * up by the BIOS, and thus we can't get the mode at module
2275 * load.
2276 */
2277 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2278 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2279 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2280 }
2281
2282 intel_ddi_clock_get(encoder, pipe_config);
2283
2284 if (IS_BROXTON(dev_priv))
2285 pipe_config->lane_lat_optim_mask =
2286 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2287 }
2288
2289 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2290 struct intel_crtc_state *pipe_config)
2291 {
2292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2293 int type = encoder->type;
2294 int port = intel_ddi_get_encoder_port(encoder);
2295 int ret;
2296
2297 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2298
2299 if (port == PORT_A)
2300 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2301
2302 if (type == INTEL_OUTPUT_HDMI)
2303 ret = intel_hdmi_compute_config(encoder, pipe_config);
2304 else
2305 ret = intel_dp_compute_config(encoder, pipe_config);
2306
2307 if (IS_BROXTON(dev_priv) && ret)
2308 pipe_config->lane_lat_optim_mask =
2309 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2310 pipe_config);
2311
2312 return ret;
2313
2314 }
2315
2316 static const struct drm_encoder_funcs intel_ddi_funcs = {
2317 .reset = intel_dp_encoder_reset,
2318 .destroy = intel_dp_encoder_destroy,
2319 };
2320
2321 static struct intel_connector *
2322 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2323 {
2324 struct intel_connector *connector;
2325 enum port port = intel_dig_port->port;
2326
2327 connector = intel_connector_alloc();
2328 if (!connector)
2329 return NULL;
2330
2331 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2332 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2333 kfree(connector);
2334 return NULL;
2335 }
2336
2337 return connector;
2338 }
2339
2340 static struct intel_connector *
2341 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2342 {
2343 struct intel_connector *connector;
2344 enum port port = intel_dig_port->port;
2345
2346 connector = intel_connector_alloc();
2347 if (!connector)
2348 return NULL;
2349
2350 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2351 intel_hdmi_init_connector(intel_dig_port, connector);
2352
2353 return connector;
2354 }
2355
2356 void intel_ddi_init(struct drm_device *dev, enum port port)
2357 {
2358 struct drm_i915_private *dev_priv = to_i915(dev);
2359 struct intel_digital_port *intel_dig_port;
2360 struct intel_encoder *intel_encoder;
2361 struct drm_encoder *encoder;
2362 bool init_hdmi, init_dp;
2363 int max_lanes;
2364
2365 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2366 switch (port) {
2367 case PORT_A:
2368 max_lanes = 4;
2369 break;
2370 case PORT_E:
2371 max_lanes = 0;
2372 break;
2373 default:
2374 max_lanes = 4;
2375 break;
2376 }
2377 } else {
2378 switch (port) {
2379 case PORT_A:
2380 max_lanes = 2;
2381 break;
2382 case PORT_E:
2383 max_lanes = 2;
2384 break;
2385 default:
2386 max_lanes = 4;
2387 break;
2388 }
2389 }
2390
2391 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2392 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2393 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2394 if (!init_dp && !init_hdmi) {
2395 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2396 port_name(port));
2397 return;
2398 }
2399
2400 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2401 if (!intel_dig_port)
2402 return;
2403
2404 intel_encoder = &intel_dig_port->base;
2405 encoder = &intel_encoder->base;
2406
2407 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2408 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2409
2410 intel_encoder->compute_config = intel_ddi_compute_config;
2411 intel_encoder->enable = intel_enable_ddi;
2412 if (IS_BROXTON(dev_priv))
2413 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2414 intel_encoder->pre_enable = intel_ddi_pre_enable;
2415 intel_encoder->disable = intel_disable_ddi;
2416 intel_encoder->post_disable = intel_ddi_post_disable;
2417 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2418 intel_encoder->get_config = intel_ddi_get_config;
2419 intel_encoder->suspend = intel_dp_encoder_suspend;
2420
2421 intel_dig_port->port = port;
2422 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2423 (DDI_BUF_PORT_REVERSAL |
2424 DDI_A_4_LANES);
2425
2426 /*
2427 * Bspec says that DDI_A_4_LANES is the only supported configuration
2428 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2429 * wasn't lit up at boot. Force this bit on in our internal
2430 * configuration so that we use the proper lane count for our
2431 * calculations.
2432 */
2433 if (IS_BROXTON(dev) && port == PORT_A) {
2434 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2435 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2436 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2437 max_lanes = 4;
2438 }
2439 }
2440
2441 intel_dig_port->max_lanes = max_lanes;
2442
2443 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2444 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2445 intel_encoder->cloneable = 0;
2446
2447 if (init_dp) {
2448 if (!intel_ddi_init_dp_connector(intel_dig_port))
2449 goto err;
2450
2451 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2452 /*
2453 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2454 * interrupts to check the external panel connection.
2455 */
2456 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
2457 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2458 else
2459 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2460 }
2461
2462 /* In theory we don't need the encoder->type check, but leave it just in
2463 * case we have some really bad VBTs... */
2464 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2465 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2466 goto err;
2467 }
2468
2469 return;
2470
2471 err:
2472 drm_encoder_cleanup(encoder);
2473 kfree(intel_dig_port);
2474 }
Linux kernel - Deliverables
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