2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
, bool use_fdi_mode
)
89 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
92 const u32
*ddi_translations
= ((use_fdi_mode
) ?
93 hsw_ddi_translations_fdi
:
94 hsw_ddi_translations_dp
);
96 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
98 use_fdi_mode
? "FDI" : "DP");
100 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
101 "Programming port %c in FDI mode, this probably will not work.\n",
104 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
105 I915_WRITE(reg
, ddi_translations
[i
]);
110 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
111 * mode and port E for FDI.
113 void intel_prepare_ddi(struct drm_device
*dev
)
117 if (IS_HASWELL(dev
)) {
118 for (port
= PORT_A
; port
< PORT_E
; port
++)
119 intel_prepare_ddi_buffers(dev
, port
, false);
121 /* DDI E is the suggested one to work in FDI mode, so program is as such by
122 * default. It will have to be re-programmed in case a digital DP output
123 * will be detected on it
125 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
129 static const long hsw_ddi_buf_ctl_values
[] = {
130 DDI_BUF_EMP_400MV_0DB_HSW
,
131 DDI_BUF_EMP_400MV_3_5DB_HSW
,
132 DDI_BUF_EMP_400MV_6DB_HSW
,
133 DDI_BUF_EMP_400MV_9_5DB_HSW
,
134 DDI_BUF_EMP_600MV_0DB_HSW
,
135 DDI_BUF_EMP_600MV_3_5DB_HSW
,
136 DDI_BUF_EMP_600MV_6DB_HSW
,
137 DDI_BUF_EMP_800MV_0DB_HSW
,
138 DDI_BUF_EMP_800MV_3_5DB_HSW
142 /* Starting with Haswell, different DDI ports can work in FDI mode for
143 * connection to the PCH-located connectors. For this, it is necessary to train
144 * both the DDI port and PCH receiver for the desired DDI buffer settings.
146 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
147 * please note that when FDI mode is active on DDI E, it shares 2 lines with
148 * DDI A (which is used for eDP)
151 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
153 struct drm_device
*dev
= crtc
->dev
;
154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
156 int pipe
= intel_crtc
->pipe
;
159 /* Start the training iterating through available voltages and emphasis */
160 for (i
=0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
); i
++) {
161 /* Configure DP_TP_CTL with auto-training */
162 I915_WRITE(DP_TP_CTL(PORT_E
),
163 DP_TP_CTL_FDI_AUTOTRAIN
|
164 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
165 DP_TP_CTL_LINK_TRAIN_PAT1
|
168 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
169 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
170 temp
= (temp
& ~DDI_BUF_EMP_MASK
);
171 I915_WRITE(DDI_BUF_CTL(PORT_E
),
175 hsw_ddi_buf_ctl_values
[i
]);
179 /* We need to program FDI_RX_MISC with the default TP1 to TP2
180 * values before enabling the receiver, and configure the delay
181 * for the FDI timing generator to 90h. Luckily, all the other
182 * bits are supposed to be zeroed, so we can write those values
185 I915_WRITE(FDI_RX_MISC(pipe
), FDI_RX_TP1_TO_TP2_48
|
186 FDI_RX_FDI_DELAY_90
);
188 /* Enable CPU FDI Receiver with auto-training */
189 reg
= FDI_RX_CTL(pipe
);
192 FDI_LINK_TRAIN_AUTO
|
194 FDI_LINK_TRAIN_PATTERN_1_CPT
|
195 FDI_RX_ENHANCE_FRAME_ENABLE
|
196 FDI_PORT_WIDTH_2X_LPT
|
201 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
202 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
203 DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i
);
205 /* Enable normal pixel sending for FDI */
206 I915_WRITE(DP_TP_CTL(PORT_E
),
207 DP_TP_CTL_FDI_AUTOTRAIN
|
208 DP_TP_CTL_LINK_TRAIN_NORMAL
|
209 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
214 DRM_ERROR("Error training BUF_CTL %d\n", i
);
216 /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
217 I915_WRITE(DP_TP_CTL(PORT_E
),
218 I915_READ(DP_TP_CTL(PORT_E
)) &
220 I915_WRITE(FDI_RX_CTL(pipe
),
221 I915_READ(FDI_RX_CTL(pipe
)) &
227 DRM_DEBUG_KMS("FDI train done.\n");
230 /* For DDI connections, it is possible to support different outputs over the
231 * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by
232 * the time the output is detected what exactly is on the other end of it. This
233 * function aims at providing support for this detection and proper output
236 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
238 /* For now, we don't do any proper output detection and assume that we
239 * handle HDMI only */
243 DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
244 intel_dp_init(dev
, DDI_BUF_CTL_A
, PORT_A
);
246 /* Assume that the ports B, C and D are working in HDMI mode for now */
250 intel_hdmi_init(dev
, DDI_BUF_CTL(port
), port
);
253 DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
259 /* WRPLL clock dividers */
260 struct wrpll_tmds_clock
{
262 u16 p
; /* Post divider */
263 u16 n2
; /* Feedback divider */
264 u16 r2
; /* Reference divider */
267 /* Table of matching values for WRPLL clocks programming for each frequency.
268 * The code assumes this table is sorted. */
269 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
284 {27027, 18, 100, 111},
312 {40541, 22, 147, 89},
322 {44900, 20, 108, 65},
338 {54054, 16, 173, 108},
390 {81081, 6, 100, 111},
435 {108108, 8, 173, 108},
442 {111264, 8, 150, 91},
486 {135250, 6, 167, 111},
509 {148352, 4, 100, 91},
531 {162162, 4, 131, 109},
539 {169000, 4, 104, 83},
586 {202000, 4, 112, 75},
588 {203000, 4, 146, 97},
645 void intel_ddi_mode_set(struct drm_encoder
*encoder
,
646 struct drm_display_mode
*mode
,
647 struct drm_display_mode
*adjusted_mode
)
649 struct drm_crtc
*crtc
= encoder
->crtc
;
650 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
651 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
652 int port
= intel_ddi_get_encoder_port(intel_encoder
);
653 int pipe
= intel_crtc
->pipe
;
654 int type
= intel_encoder
->type
;
656 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
657 port_name(port
), pipe_name(pipe
));
659 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
660 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
662 intel_dp
->DP
= DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
663 switch (intel_dp
->lane_count
) {
665 intel_dp
->DP
|= DDI_PORT_WIDTH_X1
;
668 intel_dp
->DP
|= DDI_PORT_WIDTH_X2
;
671 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
674 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
675 WARN(1, "Unexpected DP lane count %d\n",
676 intel_dp
->lane_count
);
680 intel_dp_init_link_config(intel_dp
);
682 } else if (type
== INTEL_OUTPUT_HDMI
) {
683 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
685 if (intel_hdmi
->has_audio
) {
686 /* Proper support for digital audio needs a new logic
687 * and a new set of registers, so we leave it for future
690 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
691 pipe_name(intel_crtc
->pipe
));
694 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
695 intel_write_eld(encoder
, adjusted_mode
);
698 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
702 static struct intel_encoder
*
703 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
705 struct drm_device
*dev
= crtc
->dev
;
706 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
707 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
708 int num_encoders
= 0;
710 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
715 if (num_encoders
!= 1)
716 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders
,
723 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
725 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
726 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
730 switch (intel_crtc
->ddi_pll_sel
) {
731 case PORT_CLK_SEL_SPLL
:
732 plls
->spll_refcount
--;
733 if (plls
->spll_refcount
== 0) {
734 DRM_DEBUG_KMS("Disabling SPLL\n");
735 val
= I915_READ(SPLL_CTL
);
736 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
737 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
738 POSTING_READ(SPLL_CTL
);
741 case PORT_CLK_SEL_WRPLL1
:
742 plls
->wrpll1_refcount
--;
743 if (plls
->wrpll1_refcount
== 0) {
744 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
745 val
= I915_READ(WRPLL_CTL1
);
746 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
747 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
748 POSTING_READ(WRPLL_CTL1
);
751 case PORT_CLK_SEL_WRPLL2
:
752 plls
->wrpll2_refcount
--;
753 if (plls
->wrpll2_refcount
== 0) {
754 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
755 val
= I915_READ(WRPLL_CTL2
);
756 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
757 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
758 POSTING_READ(WRPLL_CTL2
);
763 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
764 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
765 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
767 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
770 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
774 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
775 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
778 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
781 *p
= wrpll_tmds_clock_table
[i
].p
;
782 *n2
= wrpll_tmds_clock_table
[i
].n2
;
783 *r2
= wrpll_tmds_clock_table
[i
].r2
;
785 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
786 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
787 wrpll_tmds_clock_table
[i
].clock
, clock
);
789 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
790 clock
, *p
, *n2
, *r2
);
793 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
795 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
796 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
797 struct drm_encoder
*encoder
= &intel_encoder
->base
;
798 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
799 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
800 int type
= intel_encoder
->type
;
801 enum pipe pipe
= intel_crtc
->pipe
;
804 /* TODO: reuse PLLs when possible (compare values) */
806 intel_ddi_put_crtc_pll(crtc
);
808 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
809 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
811 switch (intel_dp
->link_bw
) {
812 case DP_LINK_BW_1_62
:
813 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
816 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
819 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
822 DRM_ERROR("Link bandwidth %d unsupported\n",
827 /* We don't need to turn any PLL on because we'll use LCPLL. */
830 } else if (type
== INTEL_OUTPUT_HDMI
) {
833 if (plls
->wrpll1_refcount
== 0) {
834 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
836 plls
->wrpll1_refcount
++;
838 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
839 } else if (plls
->wrpll2_refcount
== 0) {
840 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
842 plls
->wrpll2_refcount
++;
844 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
846 DRM_ERROR("No WRPLLs available!\n");
850 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
851 "WRPLL already enabled\n");
853 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
855 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
856 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
857 WRPLL_DIVIDER_POST(p
);
859 } else if (type
== INTEL_OUTPUT_ANALOG
) {
860 if (plls
->spll_refcount
== 0) {
861 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
863 plls
->spll_refcount
++;
865 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
868 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
869 "SPLL already enabled\n");
871 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
874 WARN(1, "Invalid DDI encoder type %d\n", type
);
878 I915_WRITE(reg
, val
);
884 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
886 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
888 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
889 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
890 int type
= intel_encoder
->type
;
893 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
895 temp
= TRANS_MSA_SYNC_CLK
;
896 switch (intel_crtc
->bpp
) {
898 temp
|= TRANS_MSA_6_BPC
;
901 temp
|= TRANS_MSA_8_BPC
;
904 temp
|= TRANS_MSA_10_BPC
;
907 temp
|= TRANS_MSA_12_BPC
;
910 temp
|= TRANS_MSA_8_BPC
;
911 WARN(1, "%d bpp unsupported by DDI function\n",
914 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
918 void intel_ddi_enable_pipe_func(struct drm_crtc
*crtc
)
920 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
921 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
922 struct drm_encoder
*encoder
= &intel_encoder
->base
;
923 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
924 enum pipe pipe
= intel_crtc
->pipe
;
925 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
926 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
927 int type
= intel_encoder
->type
;
930 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
931 temp
= TRANS_DDI_FUNC_ENABLE
;
932 temp
|= TRANS_DDI_SELECT_PORT(port
);
934 switch (intel_crtc
->bpp
) {
936 temp
|= TRANS_DDI_BPC_6
;
939 temp
|= TRANS_DDI_BPC_8
;
942 temp
|= TRANS_DDI_BPC_10
;
945 temp
|= TRANS_DDI_BPC_12
;
948 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
952 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
953 temp
|= TRANS_DDI_PVSYNC
;
954 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
955 temp
|= TRANS_DDI_PHSYNC
;
957 if (cpu_transcoder
== TRANSCODER_EDP
) {
960 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
963 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
966 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
974 if (type
== INTEL_OUTPUT_HDMI
) {
975 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
977 if (intel_hdmi
->has_hdmi_sink
)
978 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
980 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
982 } else if (type
== INTEL_OUTPUT_ANALOG
) {
983 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
985 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
986 type
== INTEL_OUTPUT_EDP
) {
987 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
989 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
991 switch (intel_dp
->lane_count
) {
993 temp
|= TRANS_DDI_PORT_WIDTH_X1
;
996 temp
|= TRANS_DDI_PORT_WIDTH_X2
;
999 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1002 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1003 WARN(1, "Unsupported lane count %d\n",
1004 intel_dp
->lane_count
);
1008 WARN(1, "Invalid encoder type %d for pipe %d\n",
1009 intel_encoder
->type
, pipe
);
1012 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1015 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1016 enum transcoder cpu_transcoder
)
1018 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1019 uint32_t val
= I915_READ(reg
);
1021 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1022 val
|= TRANS_DDI_PORT_NONE
;
1023 I915_WRITE(reg
, val
);
1026 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1029 struct drm_device
*dev
= encoder
->base
.dev
;
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 enum port port
= intel_ddi_get_encoder_port(encoder
);
1035 tmp
= I915_READ(DDI_BUF_CTL(port
));
1037 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1040 if (port
== PORT_A
) {
1041 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1043 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1044 case TRANS_DDI_EDP_INPUT_A_ON
:
1045 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1048 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1051 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1058 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1059 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1061 if ((tmp
& TRANS_DDI_PORT_MASK
)
1062 == TRANS_DDI_SELECT_PORT(port
)) {
1069 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port
);
1074 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1079 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1083 if (cpu_transcoder
== TRANSCODER_EDP
) {
1086 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1087 temp
&= TRANS_DDI_PORT_MASK
;
1089 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1090 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1094 ret
= I915_READ(PORT_CLK_SEL(port
));
1096 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1097 pipe_name(pipe
), port_name(port
), ret
);
1102 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1106 struct intel_crtc
*intel_crtc
;
1108 for_each_pipe(pipe
) {
1110 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1112 if (!intel_crtc
->active
)
1115 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1118 switch (intel_crtc
->ddi_pll_sel
) {
1119 case PORT_CLK_SEL_SPLL
:
1120 dev_priv
->ddi_plls
.spll_refcount
++;
1122 case PORT_CLK_SEL_WRPLL1
:
1123 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1125 case PORT_CLK_SEL_WRPLL2
:
1126 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1132 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1134 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1135 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1136 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1137 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1138 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1140 if (cpu_transcoder
!= TRANSCODER_EDP
)
1141 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1142 TRANS_CLK_SEL_PORT(port
));
1145 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1147 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1148 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1150 if (cpu_transcoder
!= TRANSCODER_EDP
)
1151 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1152 TRANS_CLK_SEL_DISABLED
);
1155 void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1157 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1158 struct drm_crtc
*crtc
= encoder
->crtc
;
1159 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1160 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1161 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1162 int type
= intel_encoder
->type
;
1164 if (type
== INTEL_OUTPUT_EDP
) {
1165 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1166 ironlake_edp_panel_vdd_on(intel_dp
);
1167 ironlake_edp_panel_on(intel_dp
);
1168 ironlake_edp_panel_vdd_off(intel_dp
, true);
1171 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1172 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1174 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1175 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1177 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1178 intel_dp_start_link_train(intel_dp
);
1179 intel_dp_complete_link_train(intel_dp
);
1183 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
1186 uint32_t reg
= DDI_BUF_CTL(port
);
1189 for (i
= 0; i
< 8; i
++) {
1191 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
1194 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
1197 void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1199 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1200 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1201 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1202 int type
= intel_encoder
->type
;
1206 val
= I915_READ(DDI_BUF_CTL(port
));
1207 if (val
& DDI_BUF_CTL_ENABLE
) {
1208 val
&= ~DDI_BUF_CTL_ENABLE
;
1209 I915_WRITE(DDI_BUF_CTL(port
), val
);
1213 val
= I915_READ(DP_TP_CTL(port
));
1214 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1215 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1216 I915_WRITE(DP_TP_CTL(port
), val
);
1219 intel_wait_ddi_buf_idle(dev_priv
, port
);
1221 if (type
== INTEL_OUTPUT_EDP
) {
1222 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1223 ironlake_edp_panel_vdd_on(intel_dp
);
1224 ironlake_edp_panel_off(intel_dp
);
1227 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1230 void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1232 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1233 struct drm_device
*dev
= encoder
->dev
;
1234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1235 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1236 int type
= intel_encoder
->type
;
1238 if (type
== INTEL_OUTPUT_HDMI
) {
1239 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1240 * are ignored so nothing special needs to be done besides
1241 * enabling the port.
1243 I915_WRITE(DDI_BUF_CTL(port
), DDI_BUF_CTL_ENABLE
);
1244 } else if (type
== INTEL_OUTPUT_EDP
) {
1245 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1247 ironlake_edp_backlight_on(intel_dp
);
1251 void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1253 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1254 int type
= intel_encoder
->type
;
1256 if (type
== INTEL_OUTPUT_EDP
) {
1257 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1259 ironlake_edp_backlight_off(intel_dp
);
1263 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1265 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1267 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1274 void intel_ddi_pll_init(struct drm_device
*dev
)
1276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1277 uint32_t val
= I915_READ(LCPLL_CTL
);
1279 /* The LCPLL register should be turned on by the BIOS. For now let's
1280 * just check its state and print errors in case something is wrong.
1281 * Don't even try to turn it on.
1284 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1285 intel_ddi_get_cdclk_freq(dev_priv
));
1287 if (val
& LCPLL_CD_SOURCE_FCLK
)
1288 DRM_ERROR("CDCLK source is not LCPLL\n");
1290 if (val
& LCPLL_PLL_DISABLE
)
1291 DRM_ERROR("LCPLL is disabled\n");
1294 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1296 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1297 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1298 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1299 enum port port
= intel_dig_port
->port
;
1303 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1304 val
= I915_READ(DDI_BUF_CTL(port
));
1305 if (val
& DDI_BUF_CTL_ENABLE
) {
1306 val
&= ~DDI_BUF_CTL_ENABLE
;
1307 I915_WRITE(DDI_BUF_CTL(port
), val
);
1311 val
= I915_READ(DP_TP_CTL(port
));
1312 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1313 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1314 I915_WRITE(DP_TP_CTL(port
), val
);
1315 POSTING_READ(DP_TP_CTL(port
));
1318 intel_wait_ddi_buf_idle(dev_priv
, port
);
1321 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1322 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1323 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1324 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1325 I915_WRITE(DP_TP_CTL(port
), val
);
1326 POSTING_READ(DP_TP_CTL(port
));
1328 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1329 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1330 POSTING_READ(DDI_BUF_CTL(port
));