2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 const u32
*ddi_translations
= ((use_fdi_mode
) ?
94 hsw_ddi_translations_fdi
:
95 hsw_ddi_translations_dp
);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode
? "FDI" : "DP");
101 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
106 I915_WRITE(reg
, ddi_translations
[i
]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device
*dev
)
121 for (port
= PORT_A
; port
< PORT_E
; port
++)
122 intel_prepare_ddi_buffers(dev
, port
, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
131 static const long hsw_ddi_buf_ctl_values
[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW
,
133 DDI_BUF_EMP_400MV_3_5DB_HSW
,
134 DDI_BUF_EMP_400MV_6DB_HSW
,
135 DDI_BUF_EMP_400MV_9_5DB_HSW
,
136 DDI_BUF_EMP_600MV_0DB_HSW
,
137 DDI_BUF_EMP_600MV_3_5DB_HSW
,
138 DDI_BUF_EMP_600MV_6DB_HSW
,
139 DDI_BUF_EMP_800MV_0DB_HSW
,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
146 uint32_t reg
= DDI_BUF_CTL(port
);
149 for (i
= 0; i
< 8; i
++) {
151 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
168 struct drm_device
*dev
= crtc
->dev
;
169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
171 u32 temp
, i
, rx_ctl_val
;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
184 FDI_RX_PLL_ENABLE
| ((intel_crtc
->fdi_lanes
- 1) << 19);
185 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
186 POSTING_READ(_FDI_RXA_CTL
);
189 /* Switch from Rawclk to PCDclk */
190 rx_ctl_val
|= FDI_PCDCLK
;
191 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
193 /* Configure Port Clock Select */
194 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
196 /* Start the training iterating through available voltages and emphasis,
197 * testing each value twice. */
198 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
199 /* Configure DP_TP_CTL with auto-training */
200 I915_WRITE(DP_TP_CTL(PORT_E
),
201 DP_TP_CTL_FDI_AUTOTRAIN
|
202 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
203 DP_TP_CTL_LINK_TRAIN_PAT1
|
206 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
207 I915_WRITE(DDI_BUF_CTL(PORT_E
),
209 ((intel_crtc
->fdi_lanes
- 1) << 1) |
210 hsw_ddi_buf_ctl_values
[i
/ 2]);
211 POSTING_READ(DDI_BUF_CTL(PORT_E
));
215 /* Program PCH FDI Receiver TU */
216 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
218 /* Enable PCH FDI Receiver with auto-training */
219 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
220 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
221 POSTING_READ(_FDI_RXA_CTL
);
223 /* Wait for FDI receiver lane calibration */
226 /* Unset FDI_RX_MISC pwrdn lanes */
227 temp
= I915_READ(_FDI_RXA_MISC
);
228 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
229 I915_WRITE(_FDI_RXA_MISC
, temp
);
230 POSTING_READ(_FDI_RXA_MISC
);
232 /* Wait for FDI auto training time */
235 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
236 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
237 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
239 /* Enable normal pixel sending for FDI */
240 I915_WRITE(DP_TP_CTL(PORT_E
),
241 DP_TP_CTL_FDI_AUTOTRAIN
|
242 DP_TP_CTL_LINK_TRAIN_NORMAL
|
243 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
249 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
250 temp
&= ~DDI_BUF_CTL_ENABLE
;
251 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
252 POSTING_READ(DDI_BUF_CTL(PORT_E
));
254 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
255 temp
= I915_READ(DP_TP_CTL(PORT_E
));
256 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
257 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
258 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
259 POSTING_READ(DP_TP_CTL(PORT_E
));
261 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
263 rx_ctl_val
&= ~FDI_RX_ENABLE
;
264 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
265 POSTING_READ(_FDI_RXA_CTL
);
267 /* Reset FDI_RX_MISC pwrdn lanes */
268 temp
= I915_READ(_FDI_RXA_MISC
);
269 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
270 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
271 I915_WRITE(_FDI_RXA_MISC
, temp
);
272 POSTING_READ(_FDI_RXA_MISC
);
275 DRM_ERROR("FDI link training failed!\n");
278 /* WRPLL clock dividers */
279 struct wrpll_tmds_clock
{
281 u16 p
; /* Post divider */
282 u16 n2
; /* Feedback divider */
283 u16 r2
; /* Reference divider */
286 /* Table of matching values for WRPLL clocks programming for each frequency.
287 * The code assumes this table is sorted. */
288 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
303 {27027, 18, 100, 111},
331 {40541, 22, 147, 89},
341 {44900, 20, 108, 65},
357 {54054, 16, 173, 108},
409 {81081, 6, 100, 111},
454 {108108, 8, 173, 108},
461 {111264, 8, 150, 91},
505 {135250, 6, 167, 111},
528 {148352, 4, 100, 91},
550 {162162, 4, 131, 109},
558 {169000, 4, 104, 83},
605 {202000, 4, 112, 75},
607 {203000, 4, 146, 97},
664 static void intel_ddi_mode_set(struct drm_encoder
*encoder
,
665 struct drm_display_mode
*mode
,
666 struct drm_display_mode
*adjusted_mode
)
668 struct drm_crtc
*crtc
= encoder
->crtc
;
669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
670 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
671 int port
= intel_ddi_get_encoder_port(intel_encoder
);
672 int pipe
= intel_crtc
->pipe
;
673 int type
= intel_encoder
->type
;
675 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
676 port_name(port
), pipe_name(pipe
));
678 intel_crtc
->eld_vld
= false;
679 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
680 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
682 intel_dp
->DP
= DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
683 switch (intel_dp
->lane_count
) {
685 intel_dp
->DP
|= DDI_PORT_WIDTH_X1
;
688 intel_dp
->DP
|= DDI_PORT_WIDTH_X2
;
691 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
694 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
695 WARN(1, "Unexpected DP lane count %d\n",
696 intel_dp
->lane_count
);
700 if (intel_dp
->has_audio
) {
701 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
702 pipe_name(intel_crtc
->pipe
));
705 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
706 intel_write_eld(encoder
, adjusted_mode
);
709 intel_dp_init_link_config(intel_dp
);
711 } else if (type
== INTEL_OUTPUT_HDMI
) {
712 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
714 if (intel_hdmi
->has_audio
) {
715 /* Proper support for digital audio needs a new logic
716 * and a new set of registers, so we leave it for future
719 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
720 pipe_name(intel_crtc
->pipe
));
723 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
724 intel_write_eld(encoder
, adjusted_mode
);
727 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
731 static struct intel_encoder
*
732 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
734 struct drm_device
*dev
= crtc
->dev
;
735 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
736 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
737 int num_encoders
= 0;
739 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
744 if (num_encoders
!= 1)
745 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders
,
752 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
754 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
755 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
759 switch (intel_crtc
->ddi_pll_sel
) {
760 case PORT_CLK_SEL_SPLL
:
761 plls
->spll_refcount
--;
762 if (plls
->spll_refcount
== 0) {
763 DRM_DEBUG_KMS("Disabling SPLL\n");
764 val
= I915_READ(SPLL_CTL
);
765 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
766 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
767 POSTING_READ(SPLL_CTL
);
770 case PORT_CLK_SEL_WRPLL1
:
771 plls
->wrpll1_refcount
--;
772 if (plls
->wrpll1_refcount
== 0) {
773 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
774 val
= I915_READ(WRPLL_CTL1
);
775 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
776 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
777 POSTING_READ(WRPLL_CTL1
);
780 case PORT_CLK_SEL_WRPLL2
:
781 plls
->wrpll2_refcount
--;
782 if (plls
->wrpll2_refcount
== 0) {
783 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
784 val
= I915_READ(WRPLL_CTL2
);
785 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
786 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
787 POSTING_READ(WRPLL_CTL2
);
792 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
793 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
794 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
796 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
799 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
803 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
804 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
807 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
810 *p
= wrpll_tmds_clock_table
[i
].p
;
811 *n2
= wrpll_tmds_clock_table
[i
].n2
;
812 *r2
= wrpll_tmds_clock_table
[i
].r2
;
814 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
815 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
816 wrpll_tmds_clock_table
[i
].clock
, clock
);
818 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
819 clock
, *p
, *n2
, *r2
);
822 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
824 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
825 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
826 struct drm_encoder
*encoder
= &intel_encoder
->base
;
827 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
828 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
829 int type
= intel_encoder
->type
;
830 enum pipe pipe
= intel_crtc
->pipe
;
833 /* TODO: reuse PLLs when possible (compare values) */
835 intel_ddi_put_crtc_pll(crtc
);
837 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
838 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
840 switch (intel_dp
->link_bw
) {
841 case DP_LINK_BW_1_62
:
842 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
845 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
848 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
851 DRM_ERROR("Link bandwidth %d unsupported\n",
856 /* We don't need to turn any PLL on because we'll use LCPLL. */
859 } else if (type
== INTEL_OUTPUT_HDMI
) {
862 if (plls
->wrpll1_refcount
== 0) {
863 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
865 plls
->wrpll1_refcount
++;
867 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
868 } else if (plls
->wrpll2_refcount
== 0) {
869 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
871 plls
->wrpll2_refcount
++;
873 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
875 DRM_ERROR("No WRPLLs available!\n");
879 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
880 "WRPLL already enabled\n");
882 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
884 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
885 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
886 WRPLL_DIVIDER_POST(p
);
888 } else if (type
== INTEL_OUTPUT_ANALOG
) {
889 if (plls
->spll_refcount
== 0) {
890 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
892 plls
->spll_refcount
++;
894 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
897 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
898 "SPLL already enabled\n");
900 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
903 WARN(1, "Invalid DDI encoder type %d\n", type
);
907 I915_WRITE(reg
, val
);
913 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
915 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
916 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
917 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
918 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
919 int type
= intel_encoder
->type
;
922 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
924 temp
= TRANS_MSA_SYNC_CLK
;
925 switch (intel_crtc
->bpp
) {
927 temp
|= TRANS_MSA_6_BPC
;
930 temp
|= TRANS_MSA_8_BPC
;
933 temp
|= TRANS_MSA_10_BPC
;
936 temp
|= TRANS_MSA_12_BPC
;
939 temp
|= TRANS_MSA_8_BPC
;
940 WARN(1, "%d bpp unsupported by DDI function\n",
943 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
947 void intel_ddi_enable_pipe_func(struct drm_crtc
*crtc
)
949 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
950 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
951 struct drm_encoder
*encoder
= &intel_encoder
->base
;
952 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
953 enum pipe pipe
= intel_crtc
->pipe
;
954 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
955 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
956 int type
= intel_encoder
->type
;
959 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
960 temp
= TRANS_DDI_FUNC_ENABLE
;
961 temp
|= TRANS_DDI_SELECT_PORT(port
);
963 switch (intel_crtc
->bpp
) {
965 temp
|= TRANS_DDI_BPC_6
;
968 temp
|= TRANS_DDI_BPC_8
;
971 temp
|= TRANS_DDI_BPC_10
;
974 temp
|= TRANS_DDI_BPC_12
;
977 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
981 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
982 temp
|= TRANS_DDI_PVSYNC
;
983 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
984 temp
|= TRANS_DDI_PHSYNC
;
986 if (cpu_transcoder
== TRANSCODER_EDP
) {
989 /* Can only use the always-on power well for eDP when
990 * not using the panel fitter, and when not using motion
991 * blur mitigation (which we don't support). */
992 if (dev_priv
->pch_pf_size
)
993 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
995 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
998 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1001 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1009 if (type
== INTEL_OUTPUT_HDMI
) {
1010 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1012 if (intel_hdmi
->has_hdmi_sink
)
1013 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1015 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1017 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1018 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1019 temp
|= (intel_crtc
->fdi_lanes
- 1) << 1;
1021 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1022 type
== INTEL_OUTPUT_EDP
) {
1023 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1025 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1027 switch (intel_dp
->lane_count
) {
1029 temp
|= TRANS_DDI_PORT_WIDTH_X1
;
1032 temp
|= TRANS_DDI_PORT_WIDTH_X2
;
1035 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1038 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1039 WARN(1, "Unsupported lane count %d\n",
1040 intel_dp
->lane_count
);
1044 WARN(1, "Invalid encoder type %d for pipe %d\n",
1045 intel_encoder
->type
, pipe
);
1048 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1051 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1052 enum transcoder cpu_transcoder
)
1054 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1055 uint32_t val
= I915_READ(reg
);
1057 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1058 val
|= TRANS_DDI_PORT_NONE
;
1059 I915_WRITE(reg
, val
);
1062 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1064 struct drm_device
*dev
= intel_connector
->base
.dev
;
1065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1066 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1067 int type
= intel_connector
->base
.connector_type
;
1068 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1070 enum transcoder cpu_transcoder
;
1073 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1077 cpu_transcoder
= TRANSCODER_EDP
;
1079 cpu_transcoder
= (enum transcoder
) pipe
;
1081 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1083 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1084 case TRANS_DDI_MODE_SELECT_HDMI
:
1085 case TRANS_DDI_MODE_SELECT_DVI
:
1086 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1088 case TRANS_DDI_MODE_SELECT_DP_SST
:
1089 if (type
== DRM_MODE_CONNECTOR_eDP
)
1091 case TRANS_DDI_MODE_SELECT_DP_MST
:
1092 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1094 case TRANS_DDI_MODE_SELECT_FDI
:
1095 return (type
== DRM_MODE_CONNECTOR_VGA
);
1102 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1105 struct drm_device
*dev
= encoder
->base
.dev
;
1106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1107 enum port port
= intel_ddi_get_encoder_port(encoder
);
1111 tmp
= I915_READ(DDI_BUF_CTL(port
));
1113 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1116 if (port
== PORT_A
) {
1117 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1119 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1120 case TRANS_DDI_EDP_INPUT_A_ON
:
1121 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1124 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1127 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1134 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1135 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1137 if ((tmp
& TRANS_DDI_PORT_MASK
)
1138 == TRANS_DDI_SELECT_PORT(port
)) {
1145 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port
);
1150 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1155 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1159 if (cpu_transcoder
== TRANSCODER_EDP
) {
1162 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1163 temp
&= TRANS_DDI_PORT_MASK
;
1165 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1166 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1170 ret
= I915_READ(PORT_CLK_SEL(port
));
1172 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1173 pipe_name(pipe
), port_name(port
), ret
);
1178 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1182 struct intel_crtc
*intel_crtc
;
1184 for_each_pipe(pipe
) {
1186 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1188 if (!intel_crtc
->active
)
1191 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1194 switch (intel_crtc
->ddi_pll_sel
) {
1195 case PORT_CLK_SEL_SPLL
:
1196 dev_priv
->ddi_plls
.spll_refcount
++;
1198 case PORT_CLK_SEL_WRPLL1
:
1199 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1201 case PORT_CLK_SEL_WRPLL2
:
1202 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1208 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1210 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1211 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1212 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1213 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1214 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1216 if (cpu_transcoder
!= TRANSCODER_EDP
)
1217 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1218 TRANS_CLK_SEL_PORT(port
));
1221 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1223 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1224 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1226 if (cpu_transcoder
!= TRANSCODER_EDP
)
1227 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1228 TRANS_CLK_SEL_DISABLED
);
1231 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1233 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1234 struct drm_crtc
*crtc
= encoder
->crtc
;
1235 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1237 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1238 int type
= intel_encoder
->type
;
1240 if (type
== INTEL_OUTPUT_EDP
) {
1241 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1242 ironlake_edp_panel_vdd_on(intel_dp
);
1243 ironlake_edp_panel_on(intel_dp
);
1244 ironlake_edp_panel_vdd_off(intel_dp
, true);
1247 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1248 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1250 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1251 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1253 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1254 intel_dp_start_link_train(intel_dp
);
1255 intel_dp_complete_link_train(intel_dp
);
1259 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1261 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1262 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1263 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1264 int type
= intel_encoder
->type
;
1268 val
= I915_READ(DDI_BUF_CTL(port
));
1269 if (val
& DDI_BUF_CTL_ENABLE
) {
1270 val
&= ~DDI_BUF_CTL_ENABLE
;
1271 I915_WRITE(DDI_BUF_CTL(port
), val
);
1275 val
= I915_READ(DP_TP_CTL(port
));
1276 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1277 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1278 I915_WRITE(DP_TP_CTL(port
), val
);
1281 intel_wait_ddi_buf_idle(dev_priv
, port
);
1283 if (type
== INTEL_OUTPUT_EDP
) {
1284 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1285 ironlake_edp_panel_vdd_on(intel_dp
);
1286 ironlake_edp_panel_off(intel_dp
);
1289 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1292 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1294 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1295 struct drm_crtc
*crtc
= encoder
->crtc
;
1296 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1297 int pipe
= intel_crtc
->pipe
;
1298 struct drm_device
*dev
= encoder
->dev
;
1299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1300 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1301 int type
= intel_encoder
->type
;
1304 if (type
== INTEL_OUTPUT_HDMI
) {
1305 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1306 * are ignored so nothing special needs to be done besides
1307 * enabling the port.
1309 I915_WRITE(DDI_BUF_CTL(port
), DDI_BUF_CTL_ENABLE
);
1310 } else if (type
== INTEL_OUTPUT_EDP
) {
1311 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1313 ironlake_edp_backlight_on(intel_dp
);
1316 if (intel_crtc
->eld_vld
) {
1317 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1318 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1319 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1323 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1325 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1326 struct drm_crtc
*crtc
= encoder
->crtc
;
1327 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1328 int pipe
= intel_crtc
->pipe
;
1329 int type
= intel_encoder
->type
;
1330 struct drm_device
*dev
= encoder
->dev
;
1331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1334 if (type
== INTEL_OUTPUT_EDP
) {
1335 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1337 ironlake_edp_backlight_off(intel_dp
);
1340 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1341 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1342 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1345 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1347 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1349 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1352 else if (IS_ULT(dev_priv
->dev
))
1358 void intel_ddi_pll_init(struct drm_device
*dev
)
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 uint32_t val
= I915_READ(LCPLL_CTL
);
1363 /* The LCPLL register should be turned on by the BIOS. For now let's
1364 * just check its state and print errors in case something is wrong.
1365 * Don't even try to turn it on.
1368 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1369 intel_ddi_get_cdclk_freq(dev_priv
));
1371 if (val
& LCPLL_CD_SOURCE_FCLK
)
1372 DRM_ERROR("CDCLK source is not LCPLL\n");
1374 if (val
& LCPLL_PLL_DISABLE
)
1375 DRM_ERROR("LCPLL is disabled\n");
1378 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1380 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1381 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1382 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1383 enum port port
= intel_dig_port
->port
;
1387 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1388 val
= I915_READ(DDI_BUF_CTL(port
));
1389 if (val
& DDI_BUF_CTL_ENABLE
) {
1390 val
&= ~DDI_BUF_CTL_ENABLE
;
1391 I915_WRITE(DDI_BUF_CTL(port
), val
);
1395 val
= I915_READ(DP_TP_CTL(port
));
1396 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1397 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1398 I915_WRITE(DP_TP_CTL(port
), val
);
1399 POSTING_READ(DP_TP_CTL(port
));
1402 intel_wait_ddi_buf_idle(dev_priv
, port
);
1405 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1406 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1407 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1408 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1409 I915_WRITE(DP_TP_CTL(port
), val
);
1410 POSTING_READ(DP_TP_CTL(port
));
1412 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1413 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1414 POSTING_READ(DDI_BUF_CTL(port
));
1419 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1421 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1422 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1425 intel_ddi_post_disable(intel_encoder
);
1427 val
= I915_READ(_FDI_RXA_CTL
);
1428 val
&= ~FDI_RX_ENABLE
;
1429 I915_WRITE(_FDI_RXA_CTL
, val
);
1431 val
= I915_READ(_FDI_RXA_MISC
);
1432 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1433 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1434 I915_WRITE(_FDI_RXA_MISC
, val
);
1436 val
= I915_READ(_FDI_RXA_CTL
);
1438 I915_WRITE(_FDI_RXA_CTL
, val
);
1440 val
= I915_READ(_FDI_RXA_CTL
);
1441 val
&= ~FDI_RX_PLL_ENABLE
;
1442 I915_WRITE(_FDI_RXA_CTL
, val
);
1445 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1447 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1448 int type
= intel_encoder
->type
;
1450 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1451 intel_dp_check_link_status(intel_dp
);
1454 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1456 /* HDMI has nothing special to destroy, so we can go with this. */
1457 intel_dp_encoder_destroy(encoder
);
1460 static bool intel_ddi_mode_fixup(struct drm_encoder
*encoder
,
1461 const struct drm_display_mode
*mode
,
1462 struct drm_display_mode
*adjusted_mode
)
1464 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1465 int type
= intel_encoder
->type
;
1467 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "mode_fixup() on unknown output!\n");
1469 if (type
== INTEL_OUTPUT_HDMI
)
1470 return intel_hdmi_mode_fixup(encoder
, mode
, adjusted_mode
);
1472 return intel_dp_mode_fixup(encoder
, mode
, adjusted_mode
);
1475 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1476 .destroy
= intel_ddi_destroy
,
1479 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs
= {
1480 .mode_fixup
= intel_ddi_mode_fixup
,
1481 .mode_set
= intel_ddi_mode_set
,
1482 .disable
= intel_encoder_noop
,
1485 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1487 struct intel_digital_port
*intel_dig_port
;
1488 struct intel_encoder
*intel_encoder
;
1489 struct drm_encoder
*encoder
;
1490 struct intel_connector
*hdmi_connector
= NULL
;
1491 struct intel_connector
*dp_connector
= NULL
;
1493 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1494 if (!intel_dig_port
)
1497 dp_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1498 if (!dp_connector
) {
1499 kfree(intel_dig_port
);
1503 if (port
!= PORT_A
) {
1504 hdmi_connector
= kzalloc(sizeof(struct intel_connector
),
1506 if (!hdmi_connector
) {
1507 kfree(dp_connector
);
1508 kfree(intel_dig_port
);
1513 intel_encoder
= &intel_dig_port
->base
;
1514 encoder
= &intel_encoder
->base
;
1516 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1517 DRM_MODE_ENCODER_TMDS
);
1518 drm_encoder_helper_add(encoder
, &intel_ddi_helper_funcs
);
1520 intel_encoder
->enable
= intel_enable_ddi
;
1521 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1522 intel_encoder
->disable
= intel_disable_ddi
;
1523 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1524 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1526 intel_dig_port
->port
= port
;
1528 intel_dig_port
->hdmi
.sdvox_reg
= DDI_BUF_CTL(port
);
1530 intel_dig_port
->hdmi
.sdvox_reg
= 0;
1531 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1533 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1534 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1535 intel_encoder
->cloneable
= false;
1536 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1539 intel_hdmi_init_connector(intel_dig_port
, hdmi_connector
);
1540 intel_dp_init_connector(intel_dig_port
, dp_connector
);