2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
34 u8 i_boost
; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp
[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp
[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp
[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp
[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi
[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
248 { 0x00000018, 0x000000C7, 0x0 },
251 struct bxt_ddi_buf_trans
{
252 u32 margin
; /* swing value */
253 u32 scale
; /* scale value */
254 u32 enable
; /* scale enable */
256 bool default_index
; /* true if the entry represents default value */
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp
[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
304 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
305 enum port port
, int type
);
307 static void ddi_get_encoder_port(struct intel_encoder
*intel_encoder
,
308 struct intel_digital_port
**dig_port
,
311 struct drm_encoder
*encoder
= &intel_encoder
->base
;
312 int type
= intel_encoder
->type
;
314 if (type
== INTEL_OUTPUT_DP_MST
) {
315 *dig_port
= enc_to_mst(encoder
)->primary
;
316 *port
= (*dig_port
)->port
;
317 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
318 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
319 *dig_port
= enc_to_dig_port(encoder
);
320 *port
= (*dig_port
)->port
;
321 } else if (type
== INTEL_OUTPUT_ANALOG
) {
325 WARN(1, "Invalid DDI encoder type %d\n", type
);
329 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
331 struct intel_digital_port
*dig_port
;
334 ddi_get_encoder_port(intel_encoder
, &dig_port
, &port
);
340 intel_dig_port_supports_hdmi(const struct intel_digital_port
*intel_dig_port
)
342 return intel_dig_port
->hdmi
.hdmi_reg
;
345 static const struct ddi_buf_trans
*skl_get_buf_trans_dp(struct drm_device
*dev
,
348 const struct ddi_buf_trans
*ddi_translations
;
350 if (IS_SKL_ULX(dev
)) {
351 ddi_translations
= skl_y_ddi_translations_dp
;
352 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_dp
);
353 } else if (IS_SKL_ULT(dev
)) {
354 ddi_translations
= skl_u_ddi_translations_dp
;
355 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
357 ddi_translations
= skl_ddi_translations_dp
;
358 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
361 return ddi_translations
;
364 static const struct ddi_buf_trans
*skl_get_buf_trans_edp(struct drm_device
*dev
,
367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
368 const struct ddi_buf_trans
*ddi_translations
;
370 if (IS_SKL_ULX(dev
)) {
371 if (dev_priv
->edp_low_vswing
) {
372 ddi_translations
= skl_y_ddi_translations_edp
;
373 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_edp
);
375 ddi_translations
= skl_y_ddi_translations_dp
;
376 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_dp
);
378 } else if (IS_SKL_ULT(dev
)) {
379 if (dev_priv
->edp_low_vswing
) {
380 ddi_translations
= skl_u_ddi_translations_edp
;
381 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_edp
);
383 ddi_translations
= skl_u_ddi_translations_dp
;
384 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
387 if (dev_priv
->edp_low_vswing
) {
388 ddi_translations
= skl_ddi_translations_edp
;
389 *n_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
391 ddi_translations
= skl_ddi_translations_dp
;
392 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
396 return ddi_translations
;
399 static const struct ddi_buf_trans
*
400 skl_get_buf_trans_hdmi(struct drm_device
*dev
,
403 const struct ddi_buf_trans
*ddi_translations
;
405 if (IS_SKL_ULX(dev
)) {
406 ddi_translations
= skl_y_ddi_translations_hdmi
;
407 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_hdmi
);
409 ddi_translations
= skl_ddi_translations_hdmi
;
410 *n_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
413 return ddi_translations
;
417 * Starting with Haswell, DDI port buffers must be programmed with correct
418 * values in advance. The buffer values are different for FDI and DP modes,
419 * but the HDMI/DVI fields are shared among those. So we program the DDI
420 * in either FDI or DP modes only, as HDMI connections will work with both
423 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
428 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
430 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
431 const struct ddi_buf_trans
*ddi_translations_fdi
;
432 const struct ddi_buf_trans
*ddi_translations_dp
;
433 const struct ddi_buf_trans
*ddi_translations_edp
;
434 const struct ddi_buf_trans
*ddi_translations_hdmi
;
435 const struct ddi_buf_trans
*ddi_translations
;
437 if (IS_BROXTON(dev
)) {
441 /* Vswing programming for HDMI */
442 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
445 } else if (IS_SKYLAKE(dev
)) {
446 ddi_translations_fdi
= NULL
;
447 ddi_translations_dp
=
448 skl_get_buf_trans_dp(dev
, &n_dp_entries
);
449 ddi_translations_edp
=
450 skl_get_buf_trans_edp(dev
, &n_edp_entries
);
451 ddi_translations_hdmi
=
452 skl_get_buf_trans_hdmi(dev
, &n_hdmi_entries
);
453 hdmi_default_entry
= 8;
454 /* If we're boosting the current, set bit 31 of trans1 */
455 if (dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
||
456 dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
)
458 } else if (IS_BROADWELL(dev
)) {
459 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
460 ddi_translations_dp
= bdw_ddi_translations_dp
;
461 ddi_translations_edp
= bdw_ddi_translations_edp
;
462 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
463 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
464 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
465 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
466 hdmi_default_entry
= 7;
467 } else if (IS_HASWELL(dev
)) {
468 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
469 ddi_translations_dp
= hsw_ddi_translations_dp
;
470 ddi_translations_edp
= hsw_ddi_translations_dp
;
471 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
472 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
473 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
474 hdmi_default_entry
= 6;
476 WARN(1, "ddi translation table missing\n");
477 ddi_translations_edp
= bdw_ddi_translations_dp
;
478 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
479 ddi_translations_dp
= bdw_ddi_translations_dp
;
480 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
481 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
482 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
483 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
484 hdmi_default_entry
= 7;
489 ddi_translations
= ddi_translations_edp
;
490 size
= n_edp_entries
;
494 ddi_translations
= ddi_translations_dp
;
498 if (intel_dp_is_edp(dev
, PORT_D
)) {
499 ddi_translations
= ddi_translations_edp
;
500 size
= n_edp_entries
;
502 ddi_translations
= ddi_translations_dp
;
507 if (ddi_translations_fdi
)
508 ddi_translations
= ddi_translations_fdi
;
510 ddi_translations
= ddi_translations_dp
;
517 for (i
= 0; i
< size
; i
++) {
518 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
519 ddi_translations
[i
].trans1
| iboost_bit
);
520 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
521 ddi_translations
[i
].trans2
);
527 /* Choose a good default if VBT is badly populated */
528 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
529 hdmi_level
>= n_hdmi_entries
)
530 hdmi_level
= hdmi_default_entry
;
532 /* Entry 9 is for HDMI: */
533 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
534 ddi_translations_hdmi
[hdmi_level
].trans1
| iboost_bit
);
535 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
536 ddi_translations_hdmi
[hdmi_level
].trans2
);
539 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
540 * mode and port E for FDI.
542 void intel_prepare_ddi(struct drm_device
*dev
)
544 struct intel_encoder
*intel_encoder
;
545 bool visited
[I915_MAX_PORTS
] = { 0, };
550 for_each_intel_encoder(dev
, intel_encoder
) {
551 struct intel_digital_port
*intel_dig_port
;
555 ddi_get_encoder_port(intel_encoder
, &intel_dig_port
, &port
);
560 supports_hdmi
= intel_dig_port
&&
561 intel_dig_port_supports_hdmi(intel_dig_port
);
563 intel_prepare_ddi_buffers(dev
, port
, supports_hdmi
);
564 visited
[port
] = true;
568 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
571 uint32_t reg
= DDI_BUF_CTL(port
);
574 for (i
= 0; i
< 16; i
++) {
576 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
579 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
582 /* Starting with Haswell, different DDI ports can work in FDI mode for
583 * connection to the PCH-located connectors. For this, it is necessary to train
584 * both the DDI port and PCH receiver for the desired DDI buffer settings.
586 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
587 * please note that when FDI mode is active on DDI E, it shares 2 lines with
588 * DDI A (which is used for eDP)
591 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
593 struct drm_device
*dev
= crtc
->dev
;
594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
595 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
596 u32 temp
, i
, rx_ctl_val
;
598 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
599 * mode set "sequence for CRT port" document:
600 * - TP1 to TP2 time with the default value
603 * WaFDIAutoLinkSetTimingOverrride:hsw
605 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
606 FDI_RX_PWRDN_LANE0_VAL(2) |
607 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
609 /* Enable the PCH Receiver FDI PLL */
610 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
612 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
613 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
614 POSTING_READ(_FDI_RXA_CTL
);
617 /* Switch from Rawclk to PCDclk */
618 rx_ctl_val
|= FDI_PCDCLK
;
619 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
621 /* Configure Port Clock Select */
622 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
623 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
625 /* Start the training iterating through available voltages and emphasis,
626 * testing each value twice. */
627 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
628 /* Configure DP_TP_CTL with auto-training */
629 I915_WRITE(DP_TP_CTL(PORT_E
),
630 DP_TP_CTL_FDI_AUTOTRAIN
|
631 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
632 DP_TP_CTL_LINK_TRAIN_PAT1
|
635 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
636 * DDI E does not support port reversal, the functionality is
637 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
638 * port reversal bit */
639 I915_WRITE(DDI_BUF_CTL(PORT_E
),
641 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
642 DDI_BUF_TRANS_SELECT(i
/ 2));
643 POSTING_READ(DDI_BUF_CTL(PORT_E
));
647 /* Program PCH FDI Receiver TU */
648 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
650 /* Enable PCH FDI Receiver with auto-training */
651 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
652 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
653 POSTING_READ(_FDI_RXA_CTL
);
655 /* Wait for FDI receiver lane calibration */
658 /* Unset FDI_RX_MISC pwrdn lanes */
659 temp
= I915_READ(_FDI_RXA_MISC
);
660 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
661 I915_WRITE(_FDI_RXA_MISC
, temp
);
662 POSTING_READ(_FDI_RXA_MISC
);
664 /* Wait for FDI auto training time */
667 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
668 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
669 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
671 /* Enable normal pixel sending for FDI */
672 I915_WRITE(DP_TP_CTL(PORT_E
),
673 DP_TP_CTL_FDI_AUTOTRAIN
|
674 DP_TP_CTL_LINK_TRAIN_NORMAL
|
675 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
681 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
682 temp
&= ~DDI_BUF_CTL_ENABLE
;
683 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
684 POSTING_READ(DDI_BUF_CTL(PORT_E
));
686 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
687 temp
= I915_READ(DP_TP_CTL(PORT_E
));
688 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
689 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
690 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
691 POSTING_READ(DP_TP_CTL(PORT_E
));
693 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
695 rx_ctl_val
&= ~FDI_RX_ENABLE
;
696 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
697 POSTING_READ(_FDI_RXA_CTL
);
699 /* Reset FDI_RX_MISC pwrdn lanes */
700 temp
= I915_READ(_FDI_RXA_MISC
);
701 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
702 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
703 I915_WRITE(_FDI_RXA_MISC
, temp
);
704 POSTING_READ(_FDI_RXA_MISC
);
707 DRM_ERROR("FDI link training failed!\n");
710 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
712 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
713 struct intel_digital_port
*intel_dig_port
=
714 enc_to_dig_port(&encoder
->base
);
716 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
717 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
718 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
721 static struct intel_encoder
*
722 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
724 struct drm_device
*dev
= crtc
->dev
;
725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
726 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
727 int num_encoders
= 0;
729 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
734 if (num_encoders
!= 1)
735 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
736 pipe_name(intel_crtc
->pipe
));
742 struct intel_encoder
*
743 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
745 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
746 struct intel_encoder
*ret
= NULL
;
747 struct drm_atomic_state
*state
;
748 struct drm_connector
*connector
;
749 struct drm_connector_state
*connector_state
;
750 int num_encoders
= 0;
753 state
= crtc_state
->base
.state
;
755 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
756 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
759 ret
= to_intel_encoder(connector_state
->best_encoder
);
763 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
764 pipe_name(crtc
->pipe
));
771 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
777 /* Constraints for PLL good behavior */
783 #define abs_diff(a, b) ({ \
784 typeof(a) __a = (a); \
785 typeof(b) __b = (b); \
786 (void) (&__a == &__b); \
787 __a > __b ? (__a - __b) : (__b - __a); })
789 struct hsw_wrpll_rnp
{
793 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
867 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
868 unsigned r2
, unsigned n2
, unsigned p
,
869 struct hsw_wrpll_rnp
*best
)
871 uint64_t a
, b
, c
, d
, diff
, diff_best
;
873 /* No best (r,n,p) yet */
882 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
886 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
889 * and we would like delta <= budget.
891 * If the discrepancy is above the PPM-based budget, always prefer to
892 * improve upon the previous solution. However, if you're within the
893 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
895 a
= freq2k
* budget
* p
* r2
;
896 b
= freq2k
* budget
* best
->p
* best
->r2
;
897 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
898 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
899 LC_FREQ_2K
* best
->n2
);
901 d
= 1000000 * diff_best
;
903 if (a
< c
&& b
< d
) {
904 /* If both are above the budget, pick the closer */
905 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
910 } else if (a
>= c
&& b
< d
) {
911 /* If A is below the threshold but B is above it? Update. */
915 } else if (a
>= c
&& b
>= d
) {
916 /* Both are below the limit, so pick the higher n2/(r2*r2) */
917 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
923 /* Otherwise a < c && b >= d, do nothing */
926 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
, int reg
)
928 int refclk
= LC_FREQ
;
932 wrpll
= I915_READ(reg
);
933 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
935 case WRPLL_PLL_NON_SSC
:
937 * We could calculate spread here, but our checking
938 * code only cares about 5% accuracy, and spread is a max of
943 case WRPLL_PLL_LCPLL
:
947 WARN(1, "bad wrpll refclk\n");
951 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
952 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
953 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
955 /* Convert to KHz, p & r have a fixed point portion */
956 return (refclk
* n
* 100) / (p
* r
);
959 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
962 uint32_t cfgcr1_reg
, cfgcr2_reg
;
963 uint32_t cfgcr1_val
, cfgcr2_val
;
964 uint32_t p0
, p1
, p2
, dco_freq
;
966 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
967 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
969 cfgcr1_val
= I915_READ(cfgcr1_reg
);
970 cfgcr2_val
= I915_READ(cfgcr2_reg
);
972 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
973 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
975 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
976 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
982 case DPLL_CFGCR2_PDIV_1
:
985 case DPLL_CFGCR2_PDIV_2
:
988 case DPLL_CFGCR2_PDIV_3
:
991 case DPLL_CFGCR2_PDIV_7
:
997 case DPLL_CFGCR2_KDIV_5
:
1000 case DPLL_CFGCR2_KDIV_2
:
1003 case DPLL_CFGCR2_KDIV_3
:
1006 case DPLL_CFGCR2_KDIV_1
:
1011 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
1013 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
1016 return dco_freq
/ (p0
* p1
* p2
* 5);
1019 static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config
)
1023 if (pipe_config
->has_pch_encoder
)
1024 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1025 &pipe_config
->fdi_m_n
);
1026 else if (pipe_config
->has_dp_encoder
)
1027 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1028 &pipe_config
->dp_m_n
);
1029 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
== 36)
1030 dotclock
= pipe_config
->port_clock
* 2 / 3;
1032 dotclock
= pipe_config
->port_clock
;
1034 if (pipe_config
->pixel_multiplier
)
1035 dotclock
/= pipe_config
->pixel_multiplier
;
1037 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
1040 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
1041 struct intel_crtc_state
*pipe_config
)
1043 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1045 uint32_t dpll_ctl1
, dpll
;
1047 dpll
= pipe_config
->ddi_pll_sel
;
1049 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
1051 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1052 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
1054 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(dpll
);
1055 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll
);
1057 switch (link_clock
) {
1058 case DPLL_CTRL1_LINK_RATE_810
:
1061 case DPLL_CTRL1_LINK_RATE_1080
:
1062 link_clock
= 108000;
1064 case DPLL_CTRL1_LINK_RATE_1350
:
1065 link_clock
= 135000;
1067 case DPLL_CTRL1_LINK_RATE_1620
:
1068 link_clock
= 162000;
1070 case DPLL_CTRL1_LINK_RATE_2160
:
1071 link_clock
= 216000;
1073 case DPLL_CTRL1_LINK_RATE_2700
:
1074 link_clock
= 270000;
1077 WARN(1, "Unsupported link rate\n");
1083 pipe_config
->port_clock
= link_clock
;
1085 ddi_dotclock_get(pipe_config
);
1088 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
1089 struct intel_crtc_state
*pipe_config
)
1091 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1095 val
= pipe_config
->ddi_pll_sel
;
1096 switch (val
& PORT_CLK_SEL_MASK
) {
1097 case PORT_CLK_SEL_LCPLL_810
:
1100 case PORT_CLK_SEL_LCPLL_1350
:
1101 link_clock
= 135000;
1103 case PORT_CLK_SEL_LCPLL_2700
:
1104 link_clock
= 270000;
1106 case PORT_CLK_SEL_WRPLL1
:
1107 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
1109 case PORT_CLK_SEL_WRPLL2
:
1110 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
1112 case PORT_CLK_SEL_SPLL
:
1113 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
1114 if (pll
== SPLL_PLL_FREQ_810MHz
)
1116 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
1117 link_clock
= 135000;
1118 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
1119 link_clock
= 270000;
1121 WARN(1, "bad spll freq\n");
1126 WARN(1, "bad port clock sel\n");
1130 pipe_config
->port_clock
= link_clock
* 2;
1132 ddi_dotclock_get(pipe_config
);
1135 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
1136 enum intel_dpll_id dpll
)
1138 struct intel_shared_dpll
*pll
;
1139 struct intel_dpll_hw_state
*state
;
1140 intel_clock_t clock
;
1142 /* For DDI ports we always use a shared PLL. */
1143 if (WARN_ON(dpll
== DPLL_ID_PRIVATE
))
1146 pll
= &dev_priv
->shared_dplls
[dpll
];
1147 state
= &pll
->config
.hw_state
;
1150 clock
.m2
= (state
->pll0
& PORT_PLL_M2_MASK
) << 22;
1151 if (state
->pll3
& PORT_PLL_M2_FRAC_ENABLE
)
1152 clock
.m2
|= state
->pll2
& PORT_PLL_M2_FRAC_MASK
;
1153 clock
.n
= (state
->pll1
& PORT_PLL_N_MASK
) >> PORT_PLL_N_SHIFT
;
1154 clock
.p1
= (state
->ebb0
& PORT_PLL_P1_MASK
) >> PORT_PLL_P1_SHIFT
;
1155 clock
.p2
= (state
->ebb0
& PORT_PLL_P2_MASK
) >> PORT_PLL_P2_SHIFT
;
1157 return chv_calc_dpll_params(100000, &clock
);
1160 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
1161 struct intel_crtc_state
*pipe_config
)
1163 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1164 enum port port
= intel_ddi_get_encoder_port(encoder
);
1165 uint32_t dpll
= port
;
1167 pipe_config
->port_clock
= bxt_calc_pll_link(dev_priv
, dpll
);
1169 ddi_dotclock_get(pipe_config
);
1172 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1173 struct intel_crtc_state
*pipe_config
)
1175 struct drm_device
*dev
= encoder
->base
.dev
;
1177 if (INTEL_INFO(dev
)->gen
<= 8)
1178 hsw_ddi_clock_get(encoder
, pipe_config
);
1179 else if (IS_SKYLAKE(dev
))
1180 skl_ddi_clock_get(encoder
, pipe_config
);
1181 else if (IS_BROXTON(dev
))
1182 bxt_ddi_clock_get(encoder
, pipe_config
);
1186 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
1187 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
1191 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
1194 freq2k
= clock
/ 100;
1196 budget
= hsw_wrpll_get_budget_for_freq(clock
);
1198 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1199 * and directly pass the LC PLL to it. */
1200 if (freq2k
== 5400000) {
1208 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1211 * We want R so that REF_MIN <= Ref <= REF_MAX.
1212 * Injecting R2 = 2 * R gives:
1213 * REF_MAX * r2 > LC_FREQ * 2 and
1214 * REF_MIN * r2 < LC_FREQ * 2
1216 * Which means the desired boundaries for r2 are:
1217 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1220 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
1221 r2
<= LC_FREQ
* 2 / REF_MIN
;
1225 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1227 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1228 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1229 * VCO_MAX * r2 > n2 * LC_FREQ and
1230 * VCO_MIN * r2 < n2 * LC_FREQ)
1232 * Which means the desired boundaries for n2 are:
1233 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1235 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
1236 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
1239 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
1240 hsw_wrpll_update_rnp(freq2k
, budget
,
1251 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1252 struct intel_crtc_state
*crtc_state
,
1253 struct intel_encoder
*intel_encoder
)
1255 int clock
= crtc_state
->port_clock
;
1257 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1258 struct intel_shared_dpll
*pll
;
1262 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
1264 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
1265 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
1266 WRPLL_DIVIDER_POST(p
);
1268 memset(&crtc_state
->dpll_hw_state
, 0,
1269 sizeof(crtc_state
->dpll_hw_state
));
1271 crtc_state
->dpll_hw_state
.wrpll
= val
;
1273 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1275 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1276 pipe_name(intel_crtc
->pipe
));
1280 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
1286 struct skl_wrpll_context
{
1287 uint64_t min_deviation
; /* current minimal deviation */
1288 uint64_t central_freq
; /* chosen central freq */
1289 uint64_t dco_freq
; /* chosen dco freq */
1290 unsigned int p
; /* chosen divider */
1293 static void skl_wrpll_context_init(struct skl_wrpll_context
*ctx
)
1295 memset(ctx
, 0, sizeof(*ctx
));
1297 ctx
->min_deviation
= U64_MAX
;
1300 /* DCO freq must be within +1%/-6% of the DCO central freq */
1301 #define SKL_DCO_MAX_PDEVIATION 100
1302 #define SKL_DCO_MAX_NDEVIATION 600
1304 static void skl_wrpll_try_divider(struct skl_wrpll_context
*ctx
,
1305 uint64_t central_freq
,
1307 unsigned int divider
)
1311 deviation
= div64_u64(10000 * abs_diff(dco_freq
, central_freq
),
1314 /* positive deviation */
1315 if (dco_freq
>= central_freq
) {
1316 if (deviation
< SKL_DCO_MAX_PDEVIATION
&&
1317 deviation
< ctx
->min_deviation
) {
1318 ctx
->min_deviation
= deviation
;
1319 ctx
->central_freq
= central_freq
;
1320 ctx
->dco_freq
= dco_freq
;
1323 /* negative deviation */
1324 } else if (deviation
< SKL_DCO_MAX_NDEVIATION
&&
1325 deviation
< ctx
->min_deviation
) {
1326 ctx
->min_deviation
= deviation
;
1327 ctx
->central_freq
= central_freq
;
1328 ctx
->dco_freq
= dco_freq
;
1333 static void skl_wrpll_get_multipliers(unsigned int p
,
1334 unsigned int *p0
/* out */,
1335 unsigned int *p1
/* out */,
1336 unsigned int *p2
/* out */)
1340 unsigned int half
= p
/ 2;
1342 if (half
== 1 || half
== 2 || half
== 3 || half
== 5) {
1346 } else if (half
% 2 == 0) {
1350 } else if (half
% 3 == 0) {
1354 } else if (half
% 7 == 0) {
1359 } else if (p
== 3 || p
== 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1363 } else if (p
== 5 || p
== 7) {
1367 } else if (p
== 15) {
1371 } else if (p
== 21) {
1375 } else if (p
== 35) {
1382 struct skl_wrpll_params
{
1383 uint32_t dco_fraction
;
1384 uint32_t dco_integer
;
1385 uint32_t qdiv_ratio
;
1389 uint32_t central_freq
;
1392 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1394 uint64_t central_freq
,
1395 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1399 switch (central_freq
) {
1401 params
->central_freq
= 0;
1404 params
->central_freq
= 1;
1407 params
->central_freq
= 3;
1424 WARN(1, "Incorrect PDiv\n");
1441 WARN(1, "Incorrect KDiv\n");
1444 params
->qdiv_ratio
= p1
;
1445 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1447 dco_freq
= p0
* p1
* p2
* afe_clock
;
1450 * Intermediate values are in Hz.
1451 * Divide by MHz to match bsepc
1453 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1454 params
->dco_fraction
=
1455 div_u64((div_u64(dco_freq
, 24) -
1456 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1460 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1461 struct skl_wrpll_params
*wrpll_params
)
1463 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1464 uint64_t dco_central_freq
[3] = {8400000000ULL,
1467 static const int even_dividers
[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1468 24, 28, 30, 32, 36, 40, 42, 44,
1469 48, 52, 54, 56, 60, 64, 66, 68,
1470 70, 72, 76, 78, 80, 84, 88, 90,
1472 static const int odd_dividers
[] = { 3, 5, 7, 9, 15, 21, 35 };
1473 static const struct {
1477 { even_dividers
, ARRAY_SIZE(even_dividers
) },
1478 { odd_dividers
, ARRAY_SIZE(odd_dividers
) },
1480 struct skl_wrpll_context ctx
;
1481 unsigned int dco
, d
, i
;
1482 unsigned int p0
, p1
, p2
;
1484 skl_wrpll_context_init(&ctx
);
1486 for (d
= 0; d
< ARRAY_SIZE(dividers
); d
++) {
1487 for (dco
= 0; dco
< ARRAY_SIZE(dco_central_freq
); dco
++) {
1488 for (i
= 0; i
< dividers
[d
].n_dividers
; i
++) {
1489 unsigned int p
= dividers
[d
].list
[i
];
1490 uint64_t dco_freq
= p
* afe_clock
;
1492 skl_wrpll_try_divider(&ctx
,
1493 dco_central_freq
[dco
],
1497 * Skip the remaining dividers if we're sure to
1498 * have found the definitive divider, we can't
1499 * improve a 0 deviation.
1501 if (ctx
.min_deviation
== 0)
1502 goto skip_remaining_dividers
;
1506 skip_remaining_dividers
:
1508 * If a solution is found with an even divider, prefer
1511 if (d
== 0 && ctx
.p
)
1516 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock
);
1521 * gcc incorrectly analyses that these can be used without being
1522 * initialized. To be fair, it's hard to guess.
1525 skl_wrpll_get_multipliers(ctx
.p
, &p0
, &p1
, &p2
);
1526 skl_wrpll_params_populate(wrpll_params
, afe_clock
, ctx
.central_freq
,
1533 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1534 struct intel_crtc_state
*crtc_state
,
1535 struct intel_encoder
*intel_encoder
)
1537 struct intel_shared_dpll
*pll
;
1538 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1539 int clock
= crtc_state
->port_clock
;
1542 * See comment in intel_dpll_hw_state to understand why we always use 0
1543 * as the DPLL id in this function.
1546 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1548 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1549 struct skl_wrpll_params wrpll_params
= { 0, };
1551 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1553 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1556 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1557 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1558 wrpll_params
.dco_integer
;
1560 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1561 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1562 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1563 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1564 wrpll_params
.central_freq
;
1565 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1566 switch (crtc_state
->port_clock
/ 2) {
1568 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1571 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1574 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1578 cfgcr1
= cfgcr2
= 0;
1582 memset(&crtc_state
->dpll_hw_state
, 0,
1583 sizeof(crtc_state
->dpll_hw_state
));
1585 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1586 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1587 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1589 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1591 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1592 pipe_name(intel_crtc
->pipe
));
1596 /* shared DPLL id 0 is DPLL 1 */
1597 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1602 /* bxt clock parameters */
1603 struct bxt_clk_div
{
1613 /* pre-calculated values for DP linkrates */
1614 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1615 {162000, 4, 2, 32, 1677722, 1, 1},
1616 {270000, 4, 1, 27, 0, 0, 1},
1617 {540000, 2, 1, 27, 0, 0, 1},
1618 {216000, 3, 2, 32, 1677722, 1, 1},
1619 {243000, 4, 1, 24, 1258291, 1, 1},
1620 {324000, 4, 1, 32, 1677722, 1, 1},
1621 {432000, 3, 1, 32, 1677722, 1, 1}
1625 bxt_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1626 struct intel_crtc_state
*crtc_state
,
1627 struct intel_encoder
*intel_encoder
)
1629 struct intel_shared_dpll
*pll
;
1630 struct bxt_clk_div clk_div
= {0};
1632 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1633 uint32_t lanestagger
;
1634 int clock
= crtc_state
->port_clock
;
1636 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1637 intel_clock_t best_clock
;
1639 /* Calculate HDMI div */
1641 * FIXME: tie the following calculation into
1642 * i9xx_crtc_compute_clock
1644 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1645 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1646 clock
, pipe_name(intel_crtc
->pipe
));
1650 clk_div
.p1
= best_clock
.p1
;
1651 clk_div
.p2
= best_clock
.p2
;
1652 WARN_ON(best_clock
.m1
!= 2);
1653 clk_div
.n
= best_clock
.n
;
1654 clk_div
.m2_int
= best_clock
.m2
>> 22;
1655 clk_div
.m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1656 clk_div
.m2_frac_en
= clk_div
.m2_frac
!= 0;
1658 vco
= best_clock
.vco
;
1659 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1660 intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
1663 clk_div
= bxt_dp_clk_val
[0];
1664 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1665 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1666 clk_div
= bxt_dp_clk_val
[i
];
1670 vco
= clock
* 10 / 2 * clk_div
.p1
* clk_div
.p2
;
1673 if (vco
>= 6200000 && vco
<= 6700000) {
1678 } else if ((vco
> 5400000 && vco
< 6200000) ||
1679 (vco
>= 4800000 && vco
< 5400000)) {
1684 } else if (vco
== 5400000) {
1690 DRM_ERROR("Invalid VCO\n");
1694 memset(&crtc_state
->dpll_hw_state
, 0,
1695 sizeof(crtc_state
->dpll_hw_state
));
1699 else if (clock
> 135000)
1701 else if (clock
> 67000)
1703 else if (clock
> 33000)
1708 crtc_state
->dpll_hw_state
.ebb0
=
1709 PORT_PLL_P1(clk_div
.p1
) | PORT_PLL_P2(clk_div
.p2
);
1710 crtc_state
->dpll_hw_state
.pll0
= clk_div
.m2_int
;
1711 crtc_state
->dpll_hw_state
.pll1
= PORT_PLL_N(clk_div
.n
);
1712 crtc_state
->dpll_hw_state
.pll2
= clk_div
.m2_frac
;
1714 if (clk_div
.m2_frac_en
)
1715 crtc_state
->dpll_hw_state
.pll3
=
1716 PORT_PLL_M2_FRAC_ENABLE
;
1718 crtc_state
->dpll_hw_state
.pll6
=
1719 prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1720 crtc_state
->dpll_hw_state
.pll6
|=
1721 PORT_PLL_GAIN_CTL(gain_ctl
);
1723 crtc_state
->dpll_hw_state
.pll8
= targ_cnt
;
1725 crtc_state
->dpll_hw_state
.pll9
= 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT
;
1727 crtc_state
->dpll_hw_state
.pll10
=
1728 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT
)
1729 | PORT_PLL_DCO_AMP_OVR_EN_H
;
1731 crtc_state
->dpll_hw_state
.ebb4
= PORT_PLL_10BIT_CLK_ENABLE
;
1733 crtc_state
->dpll_hw_state
.pcsdw12
=
1734 LANESTAGGER_STRAP_OVRD
| lanestagger
;
1736 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1738 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1739 pipe_name(intel_crtc
->pipe
));
1743 /* shared DPLL id 0 is DPLL A */
1744 crtc_state
->ddi_pll_sel
= pll
->id
;
1750 * Tries to find a *shared* PLL for the CRTC and store it in
1751 * intel_crtc->ddi_pll_sel.
1753 * For private DPLLs, compute_config() should do the selection for us. This
1754 * function should be folded into compute_config() eventually.
1756 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1757 struct intel_crtc_state
*crtc_state
)
1759 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1760 struct intel_encoder
*intel_encoder
=
1761 intel_ddi_get_crtc_new_encoder(crtc_state
);
1763 if (IS_SKYLAKE(dev
))
1764 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1766 else if (IS_BROXTON(dev
))
1767 return bxt_ddi_pll_select(intel_crtc
, crtc_state
,
1770 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1774 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1776 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1778 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1779 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1780 int type
= intel_encoder
->type
;
1783 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1784 temp
= TRANS_MSA_SYNC_CLK
;
1785 switch (intel_crtc
->config
->pipe_bpp
) {
1787 temp
|= TRANS_MSA_6_BPC
;
1790 temp
|= TRANS_MSA_8_BPC
;
1793 temp
|= TRANS_MSA_10_BPC
;
1796 temp
|= TRANS_MSA_12_BPC
;
1801 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1805 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1807 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1808 struct drm_device
*dev
= crtc
->dev
;
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1812 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1814 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1816 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1817 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1820 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1822 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1823 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1824 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1825 struct drm_device
*dev
= crtc
->dev
;
1826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1827 enum pipe pipe
= intel_crtc
->pipe
;
1828 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1829 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1830 int type
= intel_encoder
->type
;
1833 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1834 temp
= TRANS_DDI_FUNC_ENABLE
;
1835 temp
|= TRANS_DDI_SELECT_PORT(port
);
1837 switch (intel_crtc
->config
->pipe_bpp
) {
1839 temp
|= TRANS_DDI_BPC_6
;
1842 temp
|= TRANS_DDI_BPC_8
;
1845 temp
|= TRANS_DDI_BPC_10
;
1848 temp
|= TRANS_DDI_BPC_12
;
1854 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1855 temp
|= TRANS_DDI_PVSYNC
;
1856 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1857 temp
|= TRANS_DDI_PHSYNC
;
1859 if (cpu_transcoder
== TRANSCODER_EDP
) {
1862 /* On Haswell, can only use the always-on power well for
1863 * eDP when not using the panel fitter, and when not
1864 * using motion blur mitigation (which we don't
1866 if (IS_HASWELL(dev
) &&
1867 (intel_crtc
->config
->pch_pfit
.enabled
||
1868 intel_crtc
->config
->pch_pfit
.force_thru
))
1869 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1871 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1874 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1877 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1885 if (type
== INTEL_OUTPUT_HDMI
) {
1886 if (intel_crtc
->config
->has_hdmi_sink
)
1887 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1889 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1891 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1892 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1893 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1895 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1896 type
== INTEL_OUTPUT_EDP
) {
1897 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1899 if (intel_dp
->is_mst
) {
1900 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1902 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1904 temp
|= DDI_PORT_WIDTH(intel_crtc
->config
->lane_count
);
1905 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1906 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1908 if (intel_dp
->is_mst
) {
1909 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1911 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1913 temp
|= DDI_PORT_WIDTH(intel_crtc
->config
->lane_count
);
1915 WARN(1, "Invalid encoder type %d for pipe %c\n",
1916 intel_encoder
->type
, pipe_name(pipe
));
1919 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1922 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1923 enum transcoder cpu_transcoder
)
1925 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1926 uint32_t val
= I915_READ(reg
);
1928 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1929 val
|= TRANS_DDI_PORT_NONE
;
1930 I915_WRITE(reg
, val
);
1933 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1935 struct drm_device
*dev
= intel_connector
->base
.dev
;
1936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1937 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1938 int type
= intel_connector
->base
.connector_type
;
1939 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1941 enum transcoder cpu_transcoder
;
1942 enum intel_display_power_domain power_domain
;
1945 power_domain
= intel_display_port_power_domain(intel_encoder
);
1946 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1949 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1953 cpu_transcoder
= TRANSCODER_EDP
;
1955 cpu_transcoder
= (enum transcoder
) pipe
;
1957 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1959 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1960 case TRANS_DDI_MODE_SELECT_HDMI
:
1961 case TRANS_DDI_MODE_SELECT_DVI
:
1962 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1964 case TRANS_DDI_MODE_SELECT_DP_SST
:
1965 if (type
== DRM_MODE_CONNECTOR_eDP
)
1967 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1968 case TRANS_DDI_MODE_SELECT_DP_MST
:
1969 /* if the transcoder is in MST state then
1970 * connector isn't connected */
1973 case TRANS_DDI_MODE_SELECT_FDI
:
1974 return (type
== DRM_MODE_CONNECTOR_VGA
);
1981 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1984 struct drm_device
*dev
= encoder
->base
.dev
;
1985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 enum port port
= intel_ddi_get_encoder_port(encoder
);
1987 enum intel_display_power_domain power_domain
;
1991 power_domain
= intel_display_port_power_domain(encoder
);
1992 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1995 tmp
= I915_READ(DDI_BUF_CTL(port
));
1997 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
2000 if (port
== PORT_A
) {
2001 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
2003 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
2004 case TRANS_DDI_EDP_INPUT_A_ON
:
2005 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
2008 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
2011 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
2018 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
2019 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
2021 if ((tmp
& TRANS_DDI_PORT_MASK
)
2022 == TRANS_DDI_SELECT_PORT(port
)) {
2023 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
2032 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
2037 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
2039 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2040 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2041 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2042 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2043 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2045 if (cpu_transcoder
!= TRANSCODER_EDP
)
2046 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2047 TRANS_CLK_SEL_PORT(port
));
2050 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
2052 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
2053 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2055 if (cpu_transcoder
!= TRANSCODER_EDP
)
2056 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2057 TRANS_CLK_SEL_DISABLED
);
2060 static void skl_ddi_set_iboost(struct drm_device
*dev
, u32 level
,
2061 enum port port
, int type
)
2063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2064 const struct ddi_buf_trans
*ddi_translations
;
2066 uint8_t dp_iboost
, hdmi_iboost
;
2070 /* VBT may override standard boost values */
2071 dp_iboost
= dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
;
2072 hdmi_iboost
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
;
2074 if (type
== INTEL_OUTPUT_DISPLAYPORT
) {
2078 ddi_translations
= skl_get_buf_trans_dp(dev
, &n_entries
);
2079 iboost
= ddi_translations
[port
].i_boost
;
2081 } else if (type
== INTEL_OUTPUT_EDP
) {
2085 ddi_translations
= skl_get_buf_trans_edp(dev
, &n_entries
);
2086 iboost
= ddi_translations
[port
].i_boost
;
2088 } else if (type
== INTEL_OUTPUT_HDMI
) {
2090 iboost
= hdmi_iboost
;
2092 ddi_translations
= skl_get_buf_trans_hdmi(dev
, &n_entries
);
2093 iboost
= ddi_translations
[port
].i_boost
;
2099 /* Make sure that the requested I_boost is valid */
2100 if (iboost
&& iboost
!= 0x1 && iboost
!= 0x3 && iboost
!= 0x7) {
2101 DRM_ERROR("Invalid I_boost value %u\n", iboost
);
2105 reg
= I915_READ(DISPIO_CR_TX_BMU_CR0
);
2106 reg
&= ~BALANCE_LEG_MASK(port
);
2107 reg
&= ~(1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
));
2110 reg
|= iboost
<< BALANCE_LEG_SHIFT(port
);
2112 reg
|= 1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
);
2114 I915_WRITE(DISPIO_CR_TX_BMU_CR0
, reg
);
2117 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
2118 enum port port
, int type
)
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2121 const struct bxt_ddi_buf_trans
*ddi_translations
;
2125 if (type
== INTEL_OUTPUT_EDP
&& dev_priv
->edp_low_vswing
) {
2126 n_entries
= ARRAY_SIZE(bxt_ddi_translations_edp
);
2127 ddi_translations
= bxt_ddi_translations_edp
;
2128 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
2129 || type
== INTEL_OUTPUT_EDP
) {
2130 n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
2131 ddi_translations
= bxt_ddi_translations_dp
;
2132 } else if (type
== INTEL_OUTPUT_HDMI
) {
2133 n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
2134 ddi_translations
= bxt_ddi_translations_hdmi
;
2136 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2141 /* Check if default value has to be used */
2142 if (level
>= n_entries
||
2143 (type
== INTEL_OUTPUT_HDMI
&& level
== HDMI_LEVEL_SHIFT_UNKNOWN
)) {
2144 for (i
= 0; i
< n_entries
; i
++) {
2145 if (ddi_translations
[i
].default_index
) {
2153 * While we write to the group register to program all lanes at once we
2154 * can read only lane registers and we pick lanes 0/1 for that.
2156 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2157 val
&= ~(TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
);
2158 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2160 val
= I915_READ(BXT_PORT_TX_DW2_LN0(port
));
2161 val
&= ~(MARGIN_000
| UNIQ_TRANS_SCALE
);
2162 val
|= ddi_translations
[level
].margin
<< MARGIN_000_SHIFT
|
2163 ddi_translations
[level
].scale
<< UNIQ_TRANS_SCALE_SHIFT
;
2164 I915_WRITE(BXT_PORT_TX_DW2_GRP(port
), val
);
2166 val
= I915_READ(BXT_PORT_TX_DW3_LN0(port
));
2167 val
&= ~SCALE_DCOMP_METHOD
;
2168 if (ddi_translations
[level
].enable
)
2169 val
|= SCALE_DCOMP_METHOD
;
2171 if ((val
& UNIQUE_TRANGE_EN_METHOD
) && !(val
& SCALE_DCOMP_METHOD
))
2172 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2174 I915_WRITE(BXT_PORT_TX_DW3_GRP(port
), val
);
2176 val
= I915_READ(BXT_PORT_TX_DW4_LN0(port
));
2177 val
&= ~DE_EMPHASIS
;
2178 val
|= ddi_translations
[level
].deemphasis
<< DEEMPH_SHIFT
;
2179 I915_WRITE(BXT_PORT_TX_DW4_GRP(port
), val
);
2181 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2182 val
|= TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
;
2183 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2186 static uint32_t translate_signal_level(int signal_levels
)
2190 switch (signal_levels
) {
2192 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
2207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2232 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
)
2234 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2235 struct drm_device
*dev
= dport
->base
.base
.dev
;
2236 struct intel_encoder
*encoder
= &dport
->base
;
2237 uint8_t train_set
= intel_dp
->train_set
[0];
2238 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2239 DP_TRAIN_PRE_EMPHASIS_MASK
);
2240 enum port port
= dport
->port
;
2243 level
= translate_signal_level(signal_levels
);
2245 if (IS_SKYLAKE(dev
))
2246 skl_ddi_set_iboost(dev
, level
, port
, encoder
->type
);
2247 else if (IS_BROXTON(dev
))
2248 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
2250 return DDI_BUF_TRANS_SELECT(level
);
2253 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
2255 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2256 struct drm_device
*dev
= encoder
->dev
;
2257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2258 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
2259 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2260 int type
= intel_encoder
->type
;
2263 if (type
== INTEL_OUTPUT_EDP
) {
2264 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2265 intel_edp_panel_on(intel_dp
);
2268 if (IS_SKYLAKE(dev
)) {
2269 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
2273 * DPLL0 is used for eDP and is the only "private" DPLL (as
2274 * opposed to shared) on SKL
2276 if (type
== INTEL_OUTPUT_EDP
) {
2277 WARN_ON(dpll
!= SKL_DPLL0
);
2279 val
= I915_READ(DPLL_CTRL1
);
2281 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
2282 DPLL_CTRL1_SSC(dpll
) |
2283 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2284 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
2286 I915_WRITE(DPLL_CTRL1
, val
);
2287 POSTING_READ(DPLL_CTRL1
);
2290 /* DDI -> PLL mapping */
2291 val
= I915_READ(DPLL_CTRL2
);
2293 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
2294 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
2295 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
2296 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
2298 I915_WRITE(DPLL_CTRL2
, val
);
2300 } else if (INTEL_INFO(dev
)->gen
< 9) {
2301 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
2302 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
2305 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2306 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2308 intel_dp_set_link_params(intel_dp
, crtc
->config
);
2310 intel_ddi_init_dp_buf_reg(intel_encoder
);
2312 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2313 intel_dp_start_link_train(intel_dp
);
2314 intel_dp_complete_link_train(intel_dp
);
2315 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
2316 intel_dp_stop_link_train(intel_dp
);
2317 } else if (type
== INTEL_OUTPUT_HDMI
) {
2318 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2320 if (IS_BROXTON(dev
)) {
2321 hdmi_level
= dev_priv
->vbt
.
2322 ddi_port_info
[port
].hdmi_level_shift
;
2323 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
2326 intel_hdmi
->set_infoframes(encoder
,
2327 crtc
->config
->has_hdmi_sink
,
2328 &crtc
->config
->base
.adjusted_mode
);
2332 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
2334 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2335 struct drm_device
*dev
= encoder
->dev
;
2336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2337 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2338 int type
= intel_encoder
->type
;
2342 val
= I915_READ(DDI_BUF_CTL(port
));
2343 if (val
& DDI_BUF_CTL_ENABLE
) {
2344 val
&= ~DDI_BUF_CTL_ENABLE
;
2345 I915_WRITE(DDI_BUF_CTL(port
), val
);
2349 val
= I915_READ(DP_TP_CTL(port
));
2350 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2351 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2352 I915_WRITE(DP_TP_CTL(port
), val
);
2355 intel_wait_ddi_buf_idle(dev_priv
, port
);
2357 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2358 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2359 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2360 intel_edp_panel_vdd_on(intel_dp
);
2361 intel_edp_panel_off(intel_dp
);
2364 if (IS_SKYLAKE(dev
))
2365 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
2366 DPLL_CTRL2_DDI_CLK_OFF(port
)));
2367 else if (INTEL_INFO(dev
)->gen
< 9)
2368 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
2371 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
2373 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2374 struct drm_crtc
*crtc
= encoder
->crtc
;
2375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2376 struct drm_device
*dev
= encoder
->dev
;
2377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2378 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2379 int type
= intel_encoder
->type
;
2381 if (type
== INTEL_OUTPUT_HDMI
) {
2382 struct intel_digital_port
*intel_dig_port
=
2383 enc_to_dig_port(encoder
);
2385 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2386 * are ignored so nothing special needs to be done besides
2387 * enabling the port.
2389 I915_WRITE(DDI_BUF_CTL(port
),
2390 intel_dig_port
->saved_port_bits
|
2391 DDI_BUF_CTL_ENABLE
);
2392 } else if (type
== INTEL_OUTPUT_EDP
) {
2393 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2395 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
2396 intel_dp_stop_link_train(intel_dp
);
2398 intel_edp_backlight_on(intel_dp
);
2399 intel_psr_enable(intel_dp
);
2400 intel_edp_drrs_enable(intel_dp
);
2403 if (intel_crtc
->config
->has_audio
) {
2404 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
2405 intel_audio_codec_enable(intel_encoder
);
2409 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
2411 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2412 struct drm_crtc
*crtc
= encoder
->crtc
;
2413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2414 int type
= intel_encoder
->type
;
2415 struct drm_device
*dev
= encoder
->dev
;
2416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 if (intel_crtc
->config
->has_audio
) {
2419 intel_audio_codec_disable(intel_encoder
);
2420 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
2423 if (type
== INTEL_OUTPUT_EDP
) {
2424 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2426 intel_edp_drrs_disable(intel_dp
);
2427 intel_psr_disable(intel_dp
);
2428 intel_edp_backlight_off(intel_dp
);
2432 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2433 struct intel_shared_dpll
*pll
)
2435 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
2436 POSTING_READ(WRPLL_CTL(pll
->id
));
2440 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2441 struct intel_shared_dpll
*pll
)
2445 val
= I915_READ(WRPLL_CTL(pll
->id
));
2446 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
2447 POSTING_READ(WRPLL_CTL(pll
->id
));
2450 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2451 struct intel_shared_dpll
*pll
,
2452 struct intel_dpll_hw_state
*hw_state
)
2456 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2459 val
= I915_READ(WRPLL_CTL(pll
->id
));
2460 hw_state
->wrpll
= val
;
2462 return val
& WRPLL_PLL_ENABLE
;
2465 static const char * const hsw_ddi_pll_names
[] = {
2470 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2474 dev_priv
->num_shared_dpll
= 2;
2476 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2477 dev_priv
->shared_dplls
[i
].id
= i
;
2478 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
2479 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
2480 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
2481 dev_priv
->shared_dplls
[i
].get_hw_state
=
2482 hsw_ddi_pll_get_hw_state
;
2486 static const char * const skl_ddi_pll_names
[] = {
2492 struct skl_dpll_regs
{
2493 u32 ctl
, cfgcr1
, cfgcr2
;
2496 /* this array is indexed by the *shared* pll id */
2497 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
2501 .cfgcr1
= DPLL1_CFGCR1
,
2502 .cfgcr2
= DPLL1_CFGCR2
,
2507 .cfgcr1
= DPLL2_CFGCR1
,
2508 .cfgcr2
= DPLL2_CFGCR2
,
2513 .cfgcr1
= DPLL3_CFGCR1
,
2514 .cfgcr2
= DPLL3_CFGCR2
,
2518 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2519 struct intel_shared_dpll
*pll
)
2523 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2525 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2528 val
= I915_READ(DPLL_CTRL1
);
2530 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
2531 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2532 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
2534 I915_WRITE(DPLL_CTRL1
, val
);
2535 POSTING_READ(DPLL_CTRL1
);
2537 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
2538 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
2539 POSTING_READ(regs
[pll
->id
].cfgcr1
);
2540 POSTING_READ(regs
[pll
->id
].cfgcr2
);
2542 /* the enable bit is always bit 31 */
2543 I915_WRITE(regs
[pll
->id
].ctl
,
2544 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
2546 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
2547 DRM_ERROR("DPLL %d not locked\n", dpll
);
2550 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2551 struct intel_shared_dpll
*pll
)
2553 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2555 /* the enable bit is always bit 31 */
2556 I915_WRITE(regs
[pll
->id
].ctl
,
2557 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
2558 POSTING_READ(regs
[pll
->id
].ctl
);
2561 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2562 struct intel_shared_dpll
*pll
,
2563 struct intel_dpll_hw_state
*hw_state
)
2567 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2569 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2572 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2575 val
= I915_READ(regs
[pll
->id
].ctl
);
2576 if (!(val
& LCPLL_PLL_ENABLE
))
2579 val
= I915_READ(DPLL_CTRL1
);
2580 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
2582 /* avoid reading back stale values if HDMI mode is not enabled */
2583 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
2584 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
2585 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
2591 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2595 dev_priv
->num_shared_dpll
= 3;
2597 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2598 dev_priv
->shared_dplls
[i
].id
= i
;
2599 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
2600 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
2601 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
2602 dev_priv
->shared_dplls
[i
].get_hw_state
=
2603 skl_ddi_pll_get_hw_state
;
2607 static void broxton_phy_init(struct drm_i915_private
*dev_priv
,
2613 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
2614 val
|= GT_DISPLAY_POWER_ON(phy
);
2615 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
2617 /* Considering 10ms timeout until BSpec is updated */
2618 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy
)) & PHY_POWER_GOOD
, 10))
2619 DRM_ERROR("timeout during PHY%d power on\n", phy
);
2621 for (port
= (phy
== DPIO_PHY0
? PORT_B
: PORT_A
);
2622 port
<= (phy
== DPIO_PHY0
? PORT_C
: PORT_A
); port
++) {
2625 for (lane
= 0; lane
< 4; lane
++) {
2626 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2628 * Note that on CHV this flag is called UPAR, but has
2629 * the same function.
2631 val
&= ~LATENCY_OPTIM
;
2633 val
|= LATENCY_OPTIM
;
2635 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
2639 /* Program PLL Rcomp code offset */
2640 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
2641 val
&= ~IREF0RC_OFFSET_MASK
;
2642 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
2643 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
2645 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
2646 val
&= ~IREF1RC_OFFSET_MASK
;
2647 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
2648 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
2650 /* Program power gating */
2651 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
2652 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
2654 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
2656 if (phy
== DPIO_PHY0
) {
2657 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
2658 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
2659 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
2662 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
2663 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
2665 * On PHY1 disable power on the second channel, since no port is
2666 * connected there. On PHY0 both channels have a port, so leave it
2668 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2669 * power down the second channel on PHY0 as well.
2671 if (phy
== DPIO_PHY1
)
2672 val
|= OCL2_LDOFUSE_PWR_DIS
;
2673 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
2675 if (phy
== DPIO_PHY0
) {
2678 * PHY0 isn't connected to an RCOMP resistor so copy over
2679 * the corresponding calibrated value from PHY1, and disable
2680 * the automatic calibration on PHY0.
2682 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
,
2684 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2686 val
= I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1
));
2687 val
= (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
2688 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
2689 val
<< GRC_CODE_SLOW_SHIFT
|
2691 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
2693 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
2694 val
|= GRC_DIS
| GRC_RDY_OVRD
;
2695 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
2698 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2699 val
|= COMMON_RESET_DIS
;
2700 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2703 void broxton_ddi_phy_init(struct drm_device
*dev
)
2705 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2706 broxton_phy_init(dev
->dev_private
, DPIO_PHY1
);
2707 broxton_phy_init(dev
->dev_private
, DPIO_PHY0
);
2710 static void broxton_phy_uninit(struct drm_i915_private
*dev_priv
,
2715 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2716 val
&= ~COMMON_RESET_DIS
;
2717 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2720 void broxton_ddi_phy_uninit(struct drm_device
*dev
)
2722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2724 broxton_phy_uninit(dev_priv
, DPIO_PHY1
);
2725 broxton_phy_uninit(dev_priv
, DPIO_PHY0
);
2727 /* FIXME: do this in broxton_phy_uninit per phy */
2728 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, 0);
2731 static const char * const bxt_ddi_pll_names
[] = {
2737 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2738 struct intel_shared_dpll
*pll
)
2741 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2743 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2744 temp
&= ~PORT_PLL_REF_SEL
;
2745 /* Non-SSC reference */
2746 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2748 /* Disable 10 bit clock */
2749 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2750 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2751 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2754 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2755 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
2756 temp
|= pll
->config
.hw_state
.ebb0
;
2757 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
2759 /* Write M2 integer */
2760 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
2761 temp
&= ~PORT_PLL_M2_MASK
;
2762 temp
|= pll
->config
.hw_state
.pll0
;
2763 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
2766 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
2767 temp
&= ~PORT_PLL_N_MASK
;
2768 temp
|= pll
->config
.hw_state
.pll1
;
2769 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
2771 /* Write M2 fraction */
2772 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
2773 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
2774 temp
|= pll
->config
.hw_state
.pll2
;
2775 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
2777 /* Write M2 fraction enable */
2778 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
2779 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
2780 temp
|= pll
->config
.hw_state
.pll3
;
2781 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
2784 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
2785 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
2786 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
2787 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
2788 temp
|= pll
->config
.hw_state
.pll6
;
2789 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
2791 /* Write calibration val */
2792 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
2793 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
2794 temp
|= pll
->config
.hw_state
.pll8
;
2795 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
2797 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
2798 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
2799 temp
|= pll
->config
.hw_state
.pll9
;
2800 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
2802 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
2803 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
2804 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
2805 temp
|= pll
->config
.hw_state
.pll10
;
2806 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
2808 /* Recalibrate with new settings */
2809 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2810 temp
|= PORT_PLL_RECALIBRATE
;
2811 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2812 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2813 temp
|= pll
->config
.hw_state
.ebb4
;
2814 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2817 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2818 temp
|= PORT_PLL_ENABLE
;
2819 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2820 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2822 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
2823 PORT_PLL_LOCK
), 200))
2824 DRM_ERROR("PLL %d not locked\n", port
);
2827 * While we write to the group register to program all lanes at once we
2828 * can read only lane registers and we pick lanes 0/1 for that.
2830 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2831 temp
&= ~LANE_STAGGER_MASK
;
2832 temp
&= ~LANESTAGGER_STRAP_OVRD
;
2833 temp
|= pll
->config
.hw_state
.pcsdw12
;
2834 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
2837 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2838 struct intel_shared_dpll
*pll
)
2840 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2843 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2844 temp
&= ~PORT_PLL_ENABLE
;
2845 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2846 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2849 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2850 struct intel_shared_dpll
*pll
,
2851 struct intel_dpll_hw_state
*hw_state
)
2853 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2856 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2859 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2860 if (!(val
& PORT_PLL_ENABLE
))
2863 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2864 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
2866 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2867 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
2869 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
2870 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
2872 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
2873 hw_state
->pll1
&= PORT_PLL_N_MASK
;
2875 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
2876 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
2878 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
2879 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
2881 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
2882 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
2883 PORT_PLL_INT_COEFF_MASK
|
2884 PORT_PLL_GAIN_CTL_MASK
;
2886 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
2887 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
2889 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(port
, 9));
2890 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
2892 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
2893 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
2894 PORT_PLL_DCO_AMP_MASK
;
2897 * While we write to the group register to program all lanes at once we
2898 * can read only lane registers. We configure all lanes the same way, so
2899 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2901 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2902 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
)) != hw_state
->pcsdw12
)
2903 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2905 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
2906 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
2911 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2915 dev_priv
->num_shared_dpll
= 3;
2917 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2918 dev_priv
->shared_dplls
[i
].id
= i
;
2919 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
2920 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
2921 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
2922 dev_priv
->shared_dplls
[i
].get_hw_state
=
2923 bxt_ddi_pll_get_hw_state
;
2927 void intel_ddi_pll_init(struct drm_device
*dev
)
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 uint32_t val
= I915_READ(LCPLL_CTL
);
2932 if (IS_SKYLAKE(dev
))
2933 skl_shared_dplls_init(dev_priv
);
2934 else if (IS_BROXTON(dev
))
2935 bxt_shared_dplls_init(dev_priv
);
2937 hsw_shared_dplls_init(dev_priv
);
2939 if (IS_SKYLAKE(dev
)) {
2942 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
2943 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
2944 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
2945 DRM_ERROR("LCPLL1 is disabled\n");
2947 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
2948 } else if (IS_BROXTON(dev
)) {
2949 broxton_init_cdclk(dev
);
2950 broxton_ddi_phy_init(dev
);
2953 * The LCPLL register should be turned on by the BIOS. For now
2954 * let's just check its state and print errors in case
2955 * something is wrong. Don't even try to turn it on.
2958 if (val
& LCPLL_CD_SOURCE_FCLK
)
2959 DRM_ERROR("CDCLK source is not LCPLL\n");
2961 if (val
& LCPLL_PLL_DISABLE
)
2962 DRM_ERROR("LCPLL is disabled\n");
2966 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
2968 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2969 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2970 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
2971 enum port port
= intel_dig_port
->port
;
2975 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2976 val
= I915_READ(DDI_BUF_CTL(port
));
2977 if (val
& DDI_BUF_CTL_ENABLE
) {
2978 val
&= ~DDI_BUF_CTL_ENABLE
;
2979 I915_WRITE(DDI_BUF_CTL(port
), val
);
2983 val
= I915_READ(DP_TP_CTL(port
));
2984 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2985 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2986 I915_WRITE(DP_TP_CTL(port
), val
);
2987 POSTING_READ(DP_TP_CTL(port
));
2990 intel_wait_ddi_buf_idle(dev_priv
, port
);
2993 val
= DP_TP_CTL_ENABLE
|
2994 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2995 if (intel_dp
->is_mst
)
2996 val
|= DP_TP_CTL_MODE_MST
;
2998 val
|= DP_TP_CTL_MODE_SST
;
2999 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3000 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
3002 I915_WRITE(DP_TP_CTL(port
), val
);
3003 POSTING_READ(DP_TP_CTL(port
));
3005 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
3006 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
3007 POSTING_READ(DDI_BUF_CTL(port
));
3012 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
3014 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3015 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
3018 intel_ddi_post_disable(intel_encoder
);
3020 val
= I915_READ(_FDI_RXA_CTL
);
3021 val
&= ~FDI_RX_ENABLE
;
3022 I915_WRITE(_FDI_RXA_CTL
, val
);
3024 val
= I915_READ(_FDI_RXA_MISC
);
3025 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
3026 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3027 I915_WRITE(_FDI_RXA_MISC
, val
);
3029 val
= I915_READ(_FDI_RXA_CTL
);
3031 I915_WRITE(_FDI_RXA_CTL
, val
);
3033 val
= I915_READ(_FDI_RXA_CTL
);
3034 val
&= ~FDI_RX_PLL_ENABLE
;
3035 I915_WRITE(_FDI_RXA_CTL
, val
);
3038 void intel_ddi_get_config(struct intel_encoder
*encoder
,
3039 struct intel_crtc_state
*pipe_config
)
3041 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
3042 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
3043 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
3044 struct intel_hdmi
*intel_hdmi
;
3045 u32 temp
, flags
= 0;
3047 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3048 if (temp
& TRANS_DDI_PHSYNC
)
3049 flags
|= DRM_MODE_FLAG_PHSYNC
;
3051 flags
|= DRM_MODE_FLAG_NHSYNC
;
3052 if (temp
& TRANS_DDI_PVSYNC
)
3053 flags
|= DRM_MODE_FLAG_PVSYNC
;
3055 flags
|= DRM_MODE_FLAG_NVSYNC
;
3057 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
3059 switch (temp
& TRANS_DDI_BPC_MASK
) {
3060 case TRANS_DDI_BPC_6
:
3061 pipe_config
->pipe_bpp
= 18;
3063 case TRANS_DDI_BPC_8
:
3064 pipe_config
->pipe_bpp
= 24;
3066 case TRANS_DDI_BPC_10
:
3067 pipe_config
->pipe_bpp
= 30;
3069 case TRANS_DDI_BPC_12
:
3070 pipe_config
->pipe_bpp
= 36;
3076 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
3077 case TRANS_DDI_MODE_SELECT_HDMI
:
3078 pipe_config
->has_hdmi_sink
= true;
3079 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
3081 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
3082 pipe_config
->has_infoframe
= true;
3084 case TRANS_DDI_MODE_SELECT_DVI
:
3085 case TRANS_DDI_MODE_SELECT_FDI
:
3087 case TRANS_DDI_MODE_SELECT_DP_SST
:
3088 case TRANS_DDI_MODE_SELECT_DP_MST
:
3089 pipe_config
->has_dp_encoder
= true;
3090 pipe_config
->lane_count
=
3091 ((temp
& DDI_PORT_WIDTH_MASK
) >> DDI_PORT_WIDTH_SHIFT
) + 1;
3092 intel_dp_get_m_n(intel_crtc
, pipe_config
);
3098 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
3099 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
3100 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
3101 pipe_config
->has_audio
= true;
3104 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
3105 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
3107 * This is a big fat ugly hack.
3109 * Some machines in UEFI boot mode provide us a VBT that has 18
3110 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3111 * unknown we fail to light up. Yet the same BIOS boots up with
3112 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3113 * max, not what it tells us to use.
3115 * Note: This will still be broken if the eDP panel is not lit
3116 * up by the BIOS, and thus we can't get the mode at module
3119 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3120 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
3121 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
3124 intel_ddi_clock_get(encoder
, pipe_config
);
3127 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
3129 /* HDMI has nothing special to destroy, so we can go with this. */
3130 intel_dp_encoder_destroy(encoder
);
3133 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
3134 struct intel_crtc_state
*pipe_config
)
3136 int type
= encoder
->type
;
3137 int port
= intel_ddi_get_encoder_port(encoder
);
3139 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
3142 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
3144 if (type
== INTEL_OUTPUT_HDMI
)
3145 return intel_hdmi_compute_config(encoder
, pipe_config
);
3147 return intel_dp_compute_config(encoder
, pipe_config
);
3150 static const struct drm_encoder_funcs intel_ddi_funcs
= {
3151 .destroy
= intel_ddi_destroy
,
3154 static struct intel_connector
*
3155 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
3157 struct intel_connector
*connector
;
3158 enum port port
= intel_dig_port
->port
;
3160 connector
= intel_connector_alloc();
3164 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
3165 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
3173 static struct intel_connector
*
3174 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
3176 struct intel_connector
*connector
;
3177 enum port port
= intel_dig_port
->port
;
3179 connector
= intel_connector_alloc();
3183 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
3184 intel_hdmi_init_connector(intel_dig_port
, connector
);
3189 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
3191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3192 struct intel_digital_port
*intel_dig_port
;
3193 struct intel_encoder
*intel_encoder
;
3194 struct drm_encoder
*encoder
;
3195 bool init_hdmi
, init_dp
;
3197 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
3198 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
3199 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
3200 if (!init_dp
&& !init_hdmi
) {
3201 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3206 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3207 if (!intel_dig_port
)
3210 intel_encoder
= &intel_dig_port
->base
;
3211 encoder
= &intel_encoder
->base
;
3213 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
3214 DRM_MODE_ENCODER_TMDS
);
3216 intel_encoder
->compute_config
= intel_ddi_compute_config
;
3217 intel_encoder
->enable
= intel_enable_ddi
;
3218 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
3219 intel_encoder
->disable
= intel_disable_ddi
;
3220 intel_encoder
->post_disable
= intel_ddi_post_disable
;
3221 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
3222 intel_encoder
->get_config
= intel_ddi_get_config
;
3224 intel_dig_port
->port
= port
;
3225 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
3226 (DDI_BUF_PORT_REVERSAL
|
3229 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
3230 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3231 intel_encoder
->cloneable
= 0;
3234 if (!intel_ddi_init_dp_connector(intel_dig_port
))
3237 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
3239 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3240 * interrupts to check the external panel connection.
3242 if (IS_BROXTON(dev_priv
) && (INTEL_REVID(dev
) < BXT_REVID_B0
)
3244 dev_priv
->hotplug
.irq_port
[PORT_A
] = intel_dig_port
;
3246 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
3249 /* In theory we don't need the encoder->type check, but leave it just in
3250 * case we have some really bad VBTs... */
3251 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
3252 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
3259 drm_encoder_cleanup(encoder
);
3260 kfree(intel_dig_port
);