2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
47 static const u32 hsw_ddi_translations_fdi
[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
59 static const u32 hsw_ddi_translations_hdmi
[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
75 static const u32 bdw_ddi_translations_edp
[] = {
76 0x00FFFFFF, 0x00000012, /* eDP parameters */
77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00FFFFFF, 0x00020011,
80 0x00DB6FFF, 0x0005000F,
81 0x00BEEFFF, 0x000A000C,
82 0x00FFFFFF, 0x0005000F,
83 0x00DB6FFF, 0x000A000C,
84 0x00FFFFFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
88 static const u32 bdw_ddi_translations_dp
[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x00FFFFFF, 0x000E000A,
93 0x00D75FFF, 0x00180004,
94 0x80CB2FFF, 0x001B0002,
95 0x00F7DFFF, 0x00180004,
96 0x80D75FFF, 0x001B0002,
97 0x80FFFFFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
101 static const u32 bdw_ddi_translations_fdi
[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
114 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
116 struct drm_encoder
*encoder
= &intel_encoder
->base
;
117 int type
= intel_encoder
->type
;
119 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
120 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
121 struct intel_digital_port
*intel_dig_port
=
122 enc_to_dig_port(encoder
);
123 return intel_dig_port
->port
;
125 } else if (type
== INTEL_OUTPUT_ANALOG
) {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
141 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
147 const u32
*ddi_translations_fdi
;
148 const u32
*ddi_translations_dp
;
149 const u32
*ddi_translations_edp
;
150 const u32
*ddi_translations
;
152 if (IS_BROADWELL(dev
)) {
153 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
154 ddi_translations_dp
= bdw_ddi_translations_dp
;
155 ddi_translations_edp
= bdw_ddi_translations_edp
;
156 } else if (IS_HASWELL(dev
)) {
157 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
158 ddi_translations_dp
= hsw_ddi_translations_dp
;
159 ddi_translations_edp
= hsw_ddi_translations_dp
;
161 WARN(1, "ddi translation table missing\n");
162 ddi_translations_edp
= bdw_ddi_translations_dp
;
163 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
164 ddi_translations_dp
= bdw_ddi_translations_dp
;
169 ddi_translations
= ddi_translations_edp
;
173 ddi_translations
= ddi_translations_dp
;
176 if (intel_dp_is_edp(dev
, PORT_D
))
177 ddi_translations
= ddi_translations_edp
;
179 ddi_translations
= ddi_translations_dp
;
182 ddi_translations
= ddi_translations_fdi
;
188 for (i
= 0, reg
= DDI_BUF_TRANS(port
);
189 i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
190 I915_WRITE(reg
, ddi_translations
[i
]);
193 /* Entry 9 is for HDMI: */
194 for (i
= 0; i
< 2; i
++) {
195 I915_WRITE(reg
, hsw_ddi_translations_hdmi
[hdmi_level
* 2 + i
]);
200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
203 void intel_prepare_ddi(struct drm_device
*dev
)
210 for (port
= PORT_A
; port
<= PORT_E
; port
++)
211 intel_prepare_ddi_buffers(dev
, port
);
214 static const long hsw_ddi_buf_ctl_values
[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW
,
216 DDI_BUF_EMP_400MV_3_5DB_HSW
,
217 DDI_BUF_EMP_400MV_6DB_HSW
,
218 DDI_BUF_EMP_400MV_9_5DB_HSW
,
219 DDI_BUF_EMP_600MV_0DB_HSW
,
220 DDI_BUF_EMP_600MV_3_5DB_HSW
,
221 DDI_BUF_EMP_600MV_6DB_HSW
,
222 DDI_BUF_EMP_800MV_0DB_HSW
,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
226 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
229 uint32_t reg
= DDI_BUF_CTL(port
);
232 for (i
= 0; i
< 8; i
++) {
234 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
240 /* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
249 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
251 struct drm_device
*dev
= crtc
->dev
;
252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
253 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
254 u32 temp
, i
, rx_ctl_val
;
256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
261 * WaFDIAutoLinkSetTimingOverrride:hsw
263 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
267 /* Enable the PCH Receiver FDI PLL */
268 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
270 FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
271 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
272 POSTING_READ(_FDI_RXA_CTL
);
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val
|= FDI_PCDCLK
;
277 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E
),
287 DP_TP_CTL_FDI_AUTOTRAIN
|
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
289 DP_TP_CTL_LINK_TRAIN_PAT1
|
292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
296 I915_WRITE(DDI_BUF_CTL(PORT_E
),
298 ((intel_crtc
->config
.fdi_lanes
- 1) << 1) |
299 hsw_ddi_buf_ctl_values
[i
/ 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E
));
304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
309 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
310 POSTING_READ(_FDI_RXA_CTL
);
312 /* Wait for FDI receiver lane calibration */
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp
= I915_READ(_FDI_RXA_MISC
);
317 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
318 I915_WRITE(_FDI_RXA_MISC
, temp
);
319 POSTING_READ(_FDI_RXA_MISC
);
321 /* Wait for FDI auto training time */
324 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
325 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E
),
330 DP_TP_CTL_FDI_AUTOTRAIN
|
331 DP_TP_CTL_LINK_TRAIN_NORMAL
|
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
338 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
339 temp
&= ~DDI_BUF_CTL_ENABLE
;
340 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
341 POSTING_READ(DDI_BUF_CTL(PORT_E
));
343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
344 temp
= I915_READ(DP_TP_CTL(PORT_E
));
345 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
346 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
347 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
348 POSTING_READ(DP_TP_CTL(PORT_E
));
350 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
352 rx_ctl_val
&= ~FDI_RX_ENABLE
;
353 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
354 POSTING_READ(_FDI_RXA_CTL
);
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp
= I915_READ(_FDI_RXA_MISC
);
358 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
359 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC
, temp
);
361 POSTING_READ(_FDI_RXA_MISC
);
364 DRM_ERROR("FDI link training failed!\n");
367 static void intel_ddi_mode_set(struct intel_encoder
*encoder
)
369 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
370 int port
= intel_ddi_get_encoder_port(encoder
);
371 int pipe
= crtc
->pipe
;
372 int type
= encoder
->type
;
373 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
375 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
376 port_name(port
), pipe_name(pipe
));
378 crtc
->eld_vld
= false;
379 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
380 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
381 struct intel_digital_port
*intel_dig_port
=
382 enc_to_dig_port(&encoder
->base
);
384 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
385 DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
386 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
388 if (intel_dp
->has_audio
) {
389 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
390 pipe_name(crtc
->pipe
));
393 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
394 intel_write_eld(&encoder
->base
, adjusted_mode
);
396 } else if (type
== INTEL_OUTPUT_HDMI
) {
397 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
399 if (intel_hdmi
->has_audio
) {
400 /* Proper support for digital audio needs a new logic
401 * and a new set of registers, so we leave it for future
404 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
405 pipe_name(crtc
->pipe
));
408 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
409 intel_write_eld(&encoder
->base
, adjusted_mode
);
412 intel_hdmi
->set_infoframes(&encoder
->base
, adjusted_mode
);
416 static struct intel_encoder
*
417 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
419 struct drm_device
*dev
= crtc
->dev
;
420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
421 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
422 int num_encoders
= 0;
424 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
429 if (num_encoders
!= 1)
430 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
431 pipe_name(intel_crtc
->pipe
));
437 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
439 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
440 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
441 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
444 switch (intel_crtc
->ddi_pll_sel
) {
445 case PORT_CLK_SEL_SPLL
:
446 plls
->spll_refcount
--;
447 if (plls
->spll_refcount
== 0) {
448 DRM_DEBUG_KMS("Disabling SPLL\n");
449 val
= I915_READ(SPLL_CTL
);
450 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
451 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
452 POSTING_READ(SPLL_CTL
);
455 case PORT_CLK_SEL_WRPLL1
:
456 plls
->wrpll1_refcount
--;
457 if (plls
->wrpll1_refcount
== 0) {
458 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
459 val
= I915_READ(WRPLL_CTL1
);
460 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
461 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
462 POSTING_READ(WRPLL_CTL1
);
465 case PORT_CLK_SEL_WRPLL2
:
466 plls
->wrpll2_refcount
--;
467 if (plls
->wrpll2_refcount
== 0) {
468 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
469 val
= I915_READ(WRPLL_CTL2
);
470 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
471 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
472 POSTING_READ(WRPLL_CTL2
);
477 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
478 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
479 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
481 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
485 #define LC_FREQ_2K (LC_FREQ * 2000)
491 /* Constraints for PLL good behavior */
497 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
503 static unsigned wrpll_get_budget_for_freq(int clock
)
577 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
578 unsigned r2
, unsigned n2
, unsigned p
,
579 struct wrpll_rnp
*best
)
581 uint64_t a
, b
, c
, d
, diff
, diff_best
;
583 /* No best (r,n,p) yet */
592 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
596 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
599 * and we would like delta <= budget.
601 * If the discrepancy is above the PPM-based budget, always prefer to
602 * improve upon the previous solution. However, if you're within the
603 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
605 a
= freq2k
* budget
* p
* r2
;
606 b
= freq2k
* budget
* best
->p
* best
->r2
;
607 diff
= ABS_DIFF((freq2k
* p
* r2
), (LC_FREQ_2K
* n2
));
608 diff_best
= ABS_DIFF((freq2k
* best
->p
* best
->r2
),
609 (LC_FREQ_2K
* best
->n2
));
611 d
= 1000000 * diff_best
;
613 if (a
< c
&& b
< d
) {
614 /* If both are above the budget, pick the closer */
615 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
620 } else if (a
>= c
&& b
< d
) {
621 /* If A is below the threshold but B is above it? Update. */
625 } else if (a
>= c
&& b
>= d
) {
626 /* Both are below the limit, so pick the higher n2/(r2*r2) */
627 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
633 /* Otherwise a < c && b >= d, do nothing */
636 static int intel_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
639 int refclk
= LC_FREQ
;
643 wrpll
= I915_READ(reg
);
644 switch (wrpll
& SPLL_PLL_REF_MASK
) {
646 case SPLL_PLL_NON_SSC
:
648 * We could calculate spread here, but our checking
649 * code only cares about 5% accuracy, and spread is a max of
658 WARN(1, "bad wrpll refclk\n");
662 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
663 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
664 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
666 /* Convert to KHz, p & r have a fixed point portion */
667 return (refclk
* n
* 100) / (p
* r
);
670 static void intel_ddi_clock_get(struct intel_encoder
*encoder
,
671 struct intel_crtc_config
*pipe_config
)
673 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
674 enum port port
= intel_ddi_get_encoder_port(encoder
);
678 val
= I915_READ(PORT_CLK_SEL(port
));
679 switch (val
& PORT_CLK_SEL_MASK
) {
680 case PORT_CLK_SEL_LCPLL_810
:
683 case PORT_CLK_SEL_LCPLL_1350
:
686 case PORT_CLK_SEL_LCPLL_2700
:
689 case PORT_CLK_SEL_WRPLL1
:
690 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
692 case PORT_CLK_SEL_WRPLL2
:
693 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
695 case PORT_CLK_SEL_SPLL
:
696 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
697 if (pll
== SPLL_PLL_FREQ_810MHz
)
699 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
701 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
704 WARN(1, "bad spll freq\n");
709 WARN(1, "bad port clock sel\n");
713 pipe_config
->port_clock
= link_clock
* 2;
715 if (pipe_config
->has_pch_encoder
)
716 pipe_config
->adjusted_mode
.crtc_clock
=
717 intel_dotclock_calculate(pipe_config
->port_clock
,
718 &pipe_config
->fdi_m_n
);
719 else if (pipe_config
->has_dp_encoder
)
720 pipe_config
->adjusted_mode
.crtc_clock
=
721 intel_dotclock_calculate(pipe_config
->port_clock
,
722 &pipe_config
->dp_m_n
);
724 pipe_config
->adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
728 intel_ddi_calculate_wrpll(int clock
/* in Hz */,
729 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
733 struct wrpll_rnp best
= { 0, 0, 0 };
736 freq2k
= clock
/ 100;
738 budget
= wrpll_get_budget_for_freq(clock
);
740 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
741 * and directly pass the LC PLL to it. */
742 if (freq2k
== 5400000) {
750 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
753 * We want R so that REF_MIN <= Ref <= REF_MAX.
754 * Injecting R2 = 2 * R gives:
755 * REF_MAX * r2 > LC_FREQ * 2 and
756 * REF_MIN * r2 < LC_FREQ * 2
758 * Which means the desired boundaries for r2 are:
759 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
762 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
763 r2
<= LC_FREQ
* 2 / REF_MIN
;
767 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
769 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
770 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
771 * VCO_MAX * r2 > n2 * LC_FREQ and
772 * VCO_MIN * r2 < n2 * LC_FREQ)
774 * Which means the desired boundaries for n2 are:
775 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
777 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
778 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
781 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
782 wrpll_update_rnp(freq2k
, budget
,
793 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
794 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
795 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
798 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
)
800 struct drm_crtc
*crtc
= &intel_crtc
->base
;
801 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
802 struct drm_encoder
*encoder
= &intel_encoder
->base
;
803 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
804 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
805 int type
= intel_encoder
->type
;
806 enum pipe pipe
= intel_crtc
->pipe
;
807 int clock
= intel_crtc
->config
.port_clock
;
809 intel_ddi_put_crtc_pll(crtc
);
811 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
812 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
814 switch (intel_dp
->link_bw
) {
815 case DP_LINK_BW_1_62
:
816 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
819 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
822 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
825 DRM_ERROR("Link bandwidth %d unsupported\n",
830 } else if (type
== INTEL_OUTPUT_HDMI
) {
834 intel_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
836 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
837 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
838 WRPLL_DIVIDER_POST(p
);
840 if (val
== I915_READ(WRPLL_CTL1
)) {
841 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
844 } else if (val
== I915_READ(WRPLL_CTL2
)) {
845 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
848 } else if (plls
->wrpll1_refcount
== 0) {
849 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
852 } else if (plls
->wrpll2_refcount
== 0) {
853 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
857 DRM_ERROR("No WRPLLs available!\n");
861 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
864 if (reg
== WRPLL_CTL1
) {
865 plls
->wrpll1_refcount
++;
866 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
868 plls
->wrpll2_refcount
++;
869 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
872 } else if (type
== INTEL_OUTPUT_ANALOG
) {
873 if (plls
->spll_refcount
== 0) {
874 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
876 plls
->spll_refcount
++;
877 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
879 DRM_ERROR("SPLL already in use\n");
884 WARN(1, "Invalid DDI encoder type %d\n", type
);
892 * To be called after intel_ddi_pll_select(). That one selects the PLL to be
893 * used, this one actually enables the PLL.
895 void intel_ddi_pll_enable(struct intel_crtc
*crtc
)
897 struct drm_device
*dev
= crtc
->base
.dev
;
898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
899 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
900 int clock
= crtc
->config
.port_clock
;
901 uint32_t reg
, cur_val
, new_val
;
903 const char *pll_name
;
904 uint32_t enable_bit
= (1 << 31);
905 unsigned int p
, n2
, r2
;
907 BUILD_BUG_ON(enable_bit
!= SPLL_PLL_ENABLE
);
908 BUILD_BUG_ON(enable_bit
!= WRPLL_PLL_ENABLE
);
910 switch (crtc
->ddi_pll_sel
) {
911 case PORT_CLK_SEL_LCPLL_2700
:
912 case PORT_CLK_SEL_LCPLL_1350
:
913 case PORT_CLK_SEL_LCPLL_810
:
915 * LCPLL should always be enabled at this point of the mode set
916 * sequence, so nothing to do.
920 case PORT_CLK_SEL_SPLL
:
923 refcount
= plls
->spll_refcount
;
924 new_val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
|
928 case PORT_CLK_SEL_WRPLL1
:
929 case PORT_CLK_SEL_WRPLL2
:
930 if (crtc
->ddi_pll_sel
== PORT_CLK_SEL_WRPLL1
) {
933 refcount
= plls
->wrpll1_refcount
;
937 refcount
= plls
->wrpll2_refcount
;
940 intel_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
942 new_val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
943 WRPLL_DIVIDER_REFERENCE(r2
) |
944 WRPLL_DIVIDER_FEEDBACK(n2
) | WRPLL_DIVIDER_POST(p
);
948 case PORT_CLK_SEL_NONE
:
949 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
952 WARN(1, "Bad selected pll: 0x%08x\n", crtc
->ddi_pll_sel
);
956 cur_val
= I915_READ(reg
);
958 WARN(refcount
< 1, "Bad %s refcount: %d\n", pll_name
, refcount
);
960 WARN(cur_val
& enable_bit
, "%s already enabled\n", pll_name
);
961 I915_WRITE(reg
, new_val
);
965 WARN((cur_val
& enable_bit
) == 0, "%s disabled\n", pll_name
);
969 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
971 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
972 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
973 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
974 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
975 int type
= intel_encoder
->type
;
978 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
980 temp
= TRANS_MSA_SYNC_CLK
;
981 switch (intel_crtc
->config
.pipe_bpp
) {
983 temp
|= TRANS_MSA_6_BPC
;
986 temp
|= TRANS_MSA_8_BPC
;
989 temp
|= TRANS_MSA_10_BPC
;
992 temp
|= TRANS_MSA_12_BPC
;
997 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1001 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1004 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1005 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1006 struct drm_device
*dev
= crtc
->dev
;
1007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1008 enum pipe pipe
= intel_crtc
->pipe
;
1009 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1010 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1011 int type
= intel_encoder
->type
;
1014 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1015 temp
= TRANS_DDI_FUNC_ENABLE
;
1016 temp
|= TRANS_DDI_SELECT_PORT(port
);
1018 switch (intel_crtc
->config
.pipe_bpp
) {
1020 temp
|= TRANS_DDI_BPC_6
;
1023 temp
|= TRANS_DDI_BPC_8
;
1026 temp
|= TRANS_DDI_BPC_10
;
1029 temp
|= TRANS_DDI_BPC_12
;
1035 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1036 temp
|= TRANS_DDI_PVSYNC
;
1037 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1038 temp
|= TRANS_DDI_PHSYNC
;
1040 if (cpu_transcoder
== TRANSCODER_EDP
) {
1043 /* On Haswell, can only use the always-on power well for
1044 * eDP when not using the panel fitter, and when not
1045 * using motion blur mitigation (which we don't
1047 if (IS_HASWELL(dev
) && intel_crtc
->config
.pch_pfit
.enabled
)
1048 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1050 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1053 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1056 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1064 if (type
== INTEL_OUTPUT_HDMI
) {
1065 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1067 if (intel_hdmi
->has_hdmi_sink
)
1068 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1070 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1072 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1073 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1074 temp
|= (intel_crtc
->config
.fdi_lanes
- 1) << 1;
1076 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1077 type
== INTEL_OUTPUT_EDP
) {
1078 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1080 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1082 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1084 WARN(1, "Invalid encoder type %d for pipe %c\n",
1085 intel_encoder
->type
, pipe_name(pipe
));
1088 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1091 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1092 enum transcoder cpu_transcoder
)
1094 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1095 uint32_t val
= I915_READ(reg
);
1097 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1098 val
|= TRANS_DDI_PORT_NONE
;
1099 I915_WRITE(reg
, val
);
1102 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1104 struct drm_device
*dev
= intel_connector
->base
.dev
;
1105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1106 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1107 int type
= intel_connector
->base
.connector_type
;
1108 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1110 enum transcoder cpu_transcoder
;
1111 enum intel_display_power_domain power_domain
;
1114 power_domain
= intel_display_port_power_domain(intel_encoder
);
1115 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1118 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1122 cpu_transcoder
= TRANSCODER_EDP
;
1124 cpu_transcoder
= (enum transcoder
) pipe
;
1126 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1128 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1129 case TRANS_DDI_MODE_SELECT_HDMI
:
1130 case TRANS_DDI_MODE_SELECT_DVI
:
1131 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1133 case TRANS_DDI_MODE_SELECT_DP_SST
:
1134 if (type
== DRM_MODE_CONNECTOR_eDP
)
1136 case TRANS_DDI_MODE_SELECT_DP_MST
:
1137 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1139 case TRANS_DDI_MODE_SELECT_FDI
:
1140 return (type
== DRM_MODE_CONNECTOR_VGA
);
1147 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1150 struct drm_device
*dev
= encoder
->base
.dev
;
1151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1152 enum port port
= intel_ddi_get_encoder_port(encoder
);
1153 enum intel_display_power_domain power_domain
;
1157 power_domain
= intel_display_port_power_domain(encoder
);
1158 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1161 tmp
= I915_READ(DDI_BUF_CTL(port
));
1163 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1166 if (port
== PORT_A
) {
1167 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1169 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1170 case TRANS_DDI_EDP_INPUT_A_ON
:
1171 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1174 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1177 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1184 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1185 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1187 if ((tmp
& TRANS_DDI_PORT_MASK
)
1188 == TRANS_DDI_SELECT_PORT(port
)) {
1195 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1200 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1204 enum port port
= I915_MAX_PORTS
;
1205 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1209 if (cpu_transcoder
== TRANSCODER_EDP
) {
1212 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1213 temp
&= TRANS_DDI_PORT_MASK
;
1215 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1216 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1220 if (port
== I915_MAX_PORTS
) {
1221 WARN(1, "Pipe %c enabled on an unknown port\n",
1223 ret
= PORT_CLK_SEL_NONE
;
1225 ret
= I915_READ(PORT_CLK_SEL(port
));
1226 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1227 "0x%08x\n", pipe_name(pipe
), port_name(port
),
1234 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1238 struct intel_crtc
*intel_crtc
;
1240 dev_priv
->ddi_plls
.spll_refcount
= 0;
1241 dev_priv
->ddi_plls
.wrpll1_refcount
= 0;
1242 dev_priv
->ddi_plls
.wrpll2_refcount
= 0;
1244 for_each_pipe(pipe
) {
1246 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1248 if (!intel_crtc
->active
) {
1249 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
1253 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1256 switch (intel_crtc
->ddi_pll_sel
) {
1257 case PORT_CLK_SEL_SPLL
:
1258 dev_priv
->ddi_plls
.spll_refcount
++;
1260 case PORT_CLK_SEL_WRPLL1
:
1261 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1263 case PORT_CLK_SEL_WRPLL2
:
1264 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1270 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1272 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1273 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1274 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1275 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1276 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1278 if (cpu_transcoder
!= TRANSCODER_EDP
)
1279 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1280 TRANS_CLK_SEL_PORT(port
));
1283 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1285 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1286 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1288 if (cpu_transcoder
!= TRANSCODER_EDP
)
1289 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1290 TRANS_CLK_SEL_DISABLED
);
1293 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1295 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1296 struct drm_crtc
*crtc
= encoder
->crtc
;
1297 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1298 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1299 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1300 int type
= intel_encoder
->type
;
1302 if (type
== INTEL_OUTPUT_EDP
) {
1303 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1304 intel_edp_panel_on(intel_dp
);
1307 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1308 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1310 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1311 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1313 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1314 intel_dp_start_link_train(intel_dp
);
1315 intel_dp_complete_link_train(intel_dp
);
1317 intel_dp_stop_link_train(intel_dp
);
1321 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1323 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1324 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1325 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1326 int type
= intel_encoder
->type
;
1330 val
= I915_READ(DDI_BUF_CTL(port
));
1331 if (val
& DDI_BUF_CTL_ENABLE
) {
1332 val
&= ~DDI_BUF_CTL_ENABLE
;
1333 I915_WRITE(DDI_BUF_CTL(port
), val
);
1337 val
= I915_READ(DP_TP_CTL(port
));
1338 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1339 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1340 I915_WRITE(DP_TP_CTL(port
), val
);
1343 intel_wait_ddi_buf_idle(dev_priv
, port
);
1345 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1346 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1347 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1348 intel_edp_panel_vdd_on(intel_dp
);
1349 intel_edp_panel_off(intel_dp
);
1352 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1355 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1357 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1358 struct drm_crtc
*crtc
= encoder
->crtc
;
1359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1360 int pipe
= intel_crtc
->pipe
;
1361 struct drm_device
*dev
= encoder
->dev
;
1362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1363 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1364 int type
= intel_encoder
->type
;
1367 if (type
== INTEL_OUTPUT_HDMI
) {
1368 struct intel_digital_port
*intel_dig_port
=
1369 enc_to_dig_port(encoder
);
1371 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1372 * are ignored so nothing special needs to be done besides
1373 * enabling the port.
1375 I915_WRITE(DDI_BUF_CTL(port
),
1376 intel_dig_port
->saved_port_bits
|
1377 DDI_BUF_CTL_ENABLE
);
1378 } else if (type
== INTEL_OUTPUT_EDP
) {
1379 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1382 intel_dp_stop_link_train(intel_dp
);
1384 intel_edp_backlight_on(intel_dp
);
1385 intel_edp_psr_enable(intel_dp
);
1388 if (intel_crtc
->eld_vld
&& type
!= INTEL_OUTPUT_EDP
) {
1389 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1390 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1391 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1395 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1397 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1398 struct drm_crtc
*crtc
= encoder
->crtc
;
1399 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1400 int pipe
= intel_crtc
->pipe
;
1401 int type
= intel_encoder
->type
;
1402 struct drm_device
*dev
= encoder
->dev
;
1403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1406 if (intel_crtc
->eld_vld
&& type
!= INTEL_OUTPUT_EDP
) {
1407 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1408 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) <<
1410 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1413 if (type
== INTEL_OUTPUT_EDP
) {
1414 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1416 intel_edp_psr_disable(intel_dp
);
1417 intel_edp_backlight_off(intel_dp
);
1421 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1423 struct drm_device
*dev
= dev_priv
->dev
;
1424 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1425 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1427 if (lcpll
& LCPLL_CD_SOURCE_FCLK
) {
1429 } else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
) {
1431 } else if (freq
== LCPLL_CLK_FREQ_450
) {
1433 } else if (IS_HASWELL(dev
)) {
1439 if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
1441 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
1448 void intel_ddi_pll_init(struct drm_device
*dev
)
1450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 uint32_t val
= I915_READ(LCPLL_CTL
);
1453 /* The LCPLL register should be turned on by the BIOS. For now let's
1454 * just check its state and print errors in case something is wrong.
1455 * Don't even try to turn it on.
1458 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1459 intel_ddi_get_cdclk_freq(dev_priv
));
1461 if (val
& LCPLL_CD_SOURCE_FCLK
)
1462 DRM_ERROR("CDCLK source is not LCPLL\n");
1464 if (val
& LCPLL_PLL_DISABLE
)
1465 DRM_ERROR("LCPLL is disabled\n");
1468 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1470 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1471 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1472 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1473 enum port port
= intel_dig_port
->port
;
1477 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1478 val
= I915_READ(DDI_BUF_CTL(port
));
1479 if (val
& DDI_BUF_CTL_ENABLE
) {
1480 val
&= ~DDI_BUF_CTL_ENABLE
;
1481 I915_WRITE(DDI_BUF_CTL(port
), val
);
1485 val
= I915_READ(DP_TP_CTL(port
));
1486 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1487 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1488 I915_WRITE(DP_TP_CTL(port
), val
);
1489 POSTING_READ(DP_TP_CTL(port
));
1492 intel_wait_ddi_buf_idle(dev_priv
, port
);
1495 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1496 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1497 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1498 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1499 I915_WRITE(DP_TP_CTL(port
), val
);
1500 POSTING_READ(DP_TP_CTL(port
));
1502 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1503 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1504 POSTING_READ(DDI_BUF_CTL(port
));
1509 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1511 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1512 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1515 intel_ddi_post_disable(intel_encoder
);
1517 val
= I915_READ(_FDI_RXA_CTL
);
1518 val
&= ~FDI_RX_ENABLE
;
1519 I915_WRITE(_FDI_RXA_CTL
, val
);
1521 val
= I915_READ(_FDI_RXA_MISC
);
1522 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1523 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1524 I915_WRITE(_FDI_RXA_MISC
, val
);
1526 val
= I915_READ(_FDI_RXA_CTL
);
1528 I915_WRITE(_FDI_RXA_CTL
, val
);
1530 val
= I915_READ(_FDI_RXA_CTL
);
1531 val
&= ~FDI_RX_PLL_ENABLE
;
1532 I915_WRITE(_FDI_RXA_CTL
, val
);
1535 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1537 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1538 int type
= intel_encoder
->type
;
1540 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1541 intel_dp_check_link_status(intel_dp
);
1544 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1545 struct intel_crtc_config
*pipe_config
)
1547 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1548 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1549 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1550 u32 temp
, flags
= 0;
1552 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1553 if (temp
& TRANS_DDI_PHSYNC
)
1554 flags
|= DRM_MODE_FLAG_PHSYNC
;
1556 flags
|= DRM_MODE_FLAG_NHSYNC
;
1557 if (temp
& TRANS_DDI_PVSYNC
)
1558 flags
|= DRM_MODE_FLAG_PVSYNC
;
1560 flags
|= DRM_MODE_FLAG_NVSYNC
;
1562 pipe_config
->adjusted_mode
.flags
|= flags
;
1564 switch (temp
& TRANS_DDI_BPC_MASK
) {
1565 case TRANS_DDI_BPC_6
:
1566 pipe_config
->pipe_bpp
= 18;
1568 case TRANS_DDI_BPC_8
:
1569 pipe_config
->pipe_bpp
= 24;
1571 case TRANS_DDI_BPC_10
:
1572 pipe_config
->pipe_bpp
= 30;
1574 case TRANS_DDI_BPC_12
:
1575 pipe_config
->pipe_bpp
= 36;
1581 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
1582 case TRANS_DDI_MODE_SELECT_HDMI
:
1583 case TRANS_DDI_MODE_SELECT_DVI
:
1584 case TRANS_DDI_MODE_SELECT_FDI
:
1586 case TRANS_DDI_MODE_SELECT_DP_SST
:
1587 case TRANS_DDI_MODE_SELECT_DP_MST
:
1588 pipe_config
->has_dp_encoder
= true;
1589 intel_dp_get_m_n(intel_crtc
, pipe_config
);
1595 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
1596 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1598 * This is a big fat ugly hack.
1600 * Some machines in UEFI boot mode provide us a VBT that has 18
1601 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1602 * unknown we fail to light up. Yet the same BIOS boots up with
1603 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1604 * max, not what it tells us to use.
1606 * Note: This will still be broken if the eDP panel is not lit
1607 * up by the BIOS, and thus we can't get the mode at module
1610 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1611 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1612 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1615 intel_ddi_clock_get(encoder
, pipe_config
);
1618 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1620 /* HDMI has nothing special to destroy, so we can go with this. */
1621 intel_dp_encoder_destroy(encoder
);
1624 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1625 struct intel_crtc_config
*pipe_config
)
1627 int type
= encoder
->type
;
1628 int port
= intel_ddi_get_encoder_port(encoder
);
1630 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1633 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
1635 if (type
== INTEL_OUTPUT_HDMI
)
1636 return intel_hdmi_compute_config(encoder
, pipe_config
);
1638 return intel_dp_compute_config(encoder
, pipe_config
);
1641 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1642 .destroy
= intel_ddi_destroy
,
1645 static struct intel_connector
*
1646 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
1648 struct intel_connector
*connector
;
1649 enum port port
= intel_dig_port
->port
;
1651 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1655 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1656 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
1664 static struct intel_connector
*
1665 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
1667 struct intel_connector
*connector
;
1668 enum port port
= intel_dig_port
->port
;
1670 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1674 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1675 intel_hdmi_init_connector(intel_dig_port
, connector
);
1680 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1683 struct intel_digital_port
*intel_dig_port
;
1684 struct intel_encoder
*intel_encoder
;
1685 struct drm_encoder
*encoder
;
1686 struct intel_connector
*hdmi_connector
= NULL
;
1687 struct intel_connector
*dp_connector
= NULL
;
1688 bool init_hdmi
, init_dp
;
1690 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
1691 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
1692 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
1693 if (!init_dp
&& !init_hdmi
) {
1694 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1700 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1701 if (!intel_dig_port
)
1704 intel_encoder
= &intel_dig_port
->base
;
1705 encoder
= &intel_encoder
->base
;
1707 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1708 DRM_MODE_ENCODER_TMDS
);
1710 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1711 intel_encoder
->mode_set
= intel_ddi_mode_set
;
1712 intel_encoder
->enable
= intel_enable_ddi
;
1713 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1714 intel_encoder
->disable
= intel_disable_ddi
;
1715 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1716 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1717 intel_encoder
->get_config
= intel_ddi_get_config
;
1719 intel_dig_port
->port
= port
;
1720 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
1721 (DDI_BUF_PORT_REVERSAL
|
1724 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1725 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1726 intel_encoder
->cloneable
= 0;
1727 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1730 dp_connector
= intel_ddi_init_dp_connector(intel_dig_port
);
1732 /* In theory we don't need the encoder->type check, but leave it just in
1733 * case we have some really bad VBTs... */
1734 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
)
1735 hdmi_connector
= intel_ddi_init_hdmi_connector(intel_dig_port
);
1737 if (!dp_connector
&& !hdmi_connector
) {
1738 drm_encoder_cleanup(encoder
);
1739 kfree(intel_dig_port
);