2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
67 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
68 return intel_dp
->port
;
70 } else if (type
== INTEL_OUTPUT_HDMI
) {
71 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
72 return intel_hdmi
->ddi_port
;
74 } else if (type
== INTEL_OUTPUT_ANALOG
) {
78 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
83 /* On Haswell, DDI port buffers must be programmed with correct values
84 * in advance. The buffer values are different for FDI and DP modes,
85 * but the HDMI/DVI fields are shared among those. So we program the DDI
86 * in either FDI or DP modes only, as HDMI connections will work with both
89 void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
, bool use_fdi_mode
)
91 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
94 const u32
*ddi_translations
= ((use_fdi_mode
) ?
95 hsw_ddi_translations_fdi
:
96 hsw_ddi_translations_dp
);
98 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
100 use_fdi_mode
? "FDI" : "DP");
102 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
103 "Programming port %c in FDI mode, this probably will not work.\n",
106 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
107 I915_WRITE(reg
, ddi_translations
[i
]);
112 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
113 * mode and port E for FDI.
115 void intel_prepare_ddi(struct drm_device
*dev
)
119 if (IS_HASWELL(dev
)) {
120 for (port
= PORT_A
; port
< PORT_E
; port
++)
121 intel_prepare_ddi_buffers(dev
, port
, false);
123 /* DDI E is the suggested one to work in FDI mode, so program is as such by
124 * default. It will have to be re-programmed in case a digital DP output
125 * will be detected on it
127 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
131 static const long hsw_ddi_buf_ctl_values
[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW
,
133 DDI_BUF_EMP_400MV_3_5DB_HSW
,
134 DDI_BUF_EMP_400MV_6DB_HSW
,
135 DDI_BUF_EMP_400MV_9_5DB_HSW
,
136 DDI_BUF_EMP_600MV_0DB_HSW
,
137 DDI_BUF_EMP_600MV_3_5DB_HSW
,
138 DDI_BUF_EMP_600MV_6DB_HSW
,
139 DDI_BUF_EMP_800MV_0DB_HSW
,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
144 /* Starting with Haswell, different DDI ports can work in FDI mode for
145 * connection to the PCH-located connectors. For this, it is necessary to train
146 * both the DDI port and PCH receiver for the desired DDI buffer settings.
148 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
149 * please note that when FDI mode is active on DDI E, it shares 2 lines with
150 * DDI A (which is used for eDP)
153 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
155 struct drm_device
*dev
= crtc
->dev
;
156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
157 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
158 int pipe
= intel_crtc
->pipe
;
161 /* Start the training iterating through available voltages and emphasis */
162 for (i
=0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
); i
++) {
163 /* Configure DP_TP_CTL with auto-training */
164 I915_WRITE(DP_TP_CTL(PORT_E
),
165 DP_TP_CTL_FDI_AUTOTRAIN
|
166 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
167 DP_TP_CTL_LINK_TRAIN_PAT1
|
170 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
171 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
172 temp
= (temp
& ~DDI_BUF_EMP_MASK
);
173 I915_WRITE(DDI_BUF_CTL(PORT_E
),
177 hsw_ddi_buf_ctl_values
[i
]);
181 /* We need to program FDI_RX_MISC with the default TP1 to TP2
182 * values before enabling the receiver, and configure the delay
183 * for the FDI timing generator to 90h. Luckily, all the other
184 * bits are supposed to be zeroed, so we can write those values
187 I915_WRITE(FDI_RX_MISC(pipe
), FDI_RX_TP1_TO_TP2_48
|
188 FDI_RX_FDI_DELAY_90
);
190 /* Enable CPU FDI Receiver with auto-training */
191 reg
= FDI_RX_CTL(pipe
);
194 FDI_LINK_TRAIN_AUTO
|
196 FDI_LINK_TRAIN_PATTERN_1_CPT
|
197 FDI_RX_ENHANCE_FRAME_ENABLE
|
198 FDI_PORT_WIDTH_2X_LPT
|
203 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
204 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
205 DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i
);
207 /* Enable normal pixel sending for FDI */
208 I915_WRITE(DP_TP_CTL(PORT_E
),
209 DP_TP_CTL_FDI_AUTOTRAIN
|
210 DP_TP_CTL_LINK_TRAIN_NORMAL
|
211 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
216 DRM_ERROR("Error training BUF_CTL %d\n", i
);
218 /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
219 I915_WRITE(DP_TP_CTL(PORT_E
),
220 I915_READ(DP_TP_CTL(PORT_E
)) &
222 I915_WRITE(FDI_RX_CTL(pipe
),
223 I915_READ(FDI_RX_CTL(pipe
)) &
229 DRM_DEBUG_KMS("FDI train done.\n");
232 /* For DDI connections, it is possible to support different outputs over the
233 * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by
234 * the time the output is detected what exactly is on the other end of it. This
235 * function aims at providing support for this detection and proper output
238 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
240 /* For now, we don't do any proper output detection and assume that we
241 * handle HDMI only */
245 /* We don't handle eDP and DP yet */
246 DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
248 /* Assume that the ports B, C and D are working in HDMI mode for now */
252 intel_hdmi_init(dev
, DDI_BUF_CTL(port
), port
);
255 DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
261 /* WRPLL clock dividers */
262 struct wrpll_tmds_clock
{
264 u16 p
; /* Post divider */
265 u16 n2
; /* Feedback divider */
266 u16 r2
; /* Reference divider */
269 /* Table of matching values for WRPLL clocks programming for each frequency.
270 * The code assumes this table is sorted. */
271 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
286 {27027, 18, 100, 111},
314 {40541, 22, 147, 89},
324 {44900, 20, 108, 65},
340 {54054, 16, 173, 108},
392 {81081, 6, 100, 111},
437 {108108, 8, 173, 108},
444 {111264, 8, 150, 91},
488 {135250, 6, 167, 111},
511 {148352, 4, 100, 91},
533 {162162, 4, 131, 109},
541 {169000, 4, 104, 83},
588 {202000, 4, 112, 75},
590 {203000, 4, 146, 97},
647 void intel_ddi_mode_set(struct drm_encoder
*encoder
,
648 struct drm_display_mode
*mode
,
649 struct drm_display_mode
*adjusted_mode
)
651 struct drm_crtc
*crtc
= encoder
->crtc
;
652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
653 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
654 int port
= intel_ddi_get_encoder_port(intel_encoder
);
655 int pipe
= intel_crtc
->pipe
;
656 int type
= intel_encoder
->type
;
658 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
659 port_name(port
), pipe_name(pipe
));
661 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
662 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
664 intel_dp
->DP
= DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
665 switch (intel_dp
->lane_count
) {
667 intel_dp
->DP
|= DDI_PORT_WIDTH_X1
;
670 intel_dp
->DP
|= DDI_PORT_WIDTH_X2
;
673 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
676 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
677 WARN(1, "Unexpected DP lane count %d\n",
678 intel_dp
->lane_count
);
682 intel_dp_init_link_config(intel_dp
);
684 } else if (type
== INTEL_OUTPUT_HDMI
) {
685 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
687 if (intel_hdmi
->has_audio
) {
688 /* Proper support for digital audio needs a new logic
689 * and a new set of registers, so we leave it for future
692 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
693 pipe_name(intel_crtc
->pipe
));
696 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
697 intel_write_eld(encoder
, adjusted_mode
);
700 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
704 static struct intel_encoder
*
705 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
707 struct drm_device
*dev
= crtc
->dev
;
708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
709 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
710 int num_encoders
= 0;
712 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
717 if (num_encoders
!= 1)
718 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders
,
725 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
727 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
728 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
729 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
732 switch (intel_crtc
->ddi_pll_sel
) {
733 case PORT_CLK_SEL_SPLL
:
734 plls
->spll_refcount
--;
735 if (plls
->spll_refcount
== 0) {
736 DRM_DEBUG_KMS("Disabling SPLL\n");
737 val
= I915_READ(SPLL_CTL
);
738 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
739 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
740 POSTING_READ(SPLL_CTL
);
743 case PORT_CLK_SEL_WRPLL1
:
744 plls
->wrpll1_refcount
--;
745 if (plls
->wrpll1_refcount
== 0) {
746 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
747 val
= I915_READ(WRPLL_CTL1
);
748 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
749 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
750 POSTING_READ(WRPLL_CTL1
);
753 case PORT_CLK_SEL_WRPLL2
:
754 plls
->wrpll2_refcount
--;
755 if (plls
->wrpll2_refcount
== 0) {
756 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
757 val
= I915_READ(WRPLL_CTL2
);
758 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
759 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
760 POSTING_READ(WRPLL_CTL2
);
765 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
766 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
767 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
769 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
772 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
776 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
777 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
780 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
783 *p
= wrpll_tmds_clock_table
[i
].p
;
784 *n2
= wrpll_tmds_clock_table
[i
].n2
;
785 *r2
= wrpll_tmds_clock_table
[i
].r2
;
787 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
788 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
789 wrpll_tmds_clock_table
[i
].clock
, clock
);
791 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
792 clock
, *p
, *n2
, *r2
);
795 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
798 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
799 struct drm_encoder
*encoder
= &intel_encoder
->base
;
800 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
801 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
802 int type
= intel_encoder
->type
;
803 enum pipe pipe
= intel_crtc
->pipe
;
806 /* TODO: reuse PLLs when possible (compare values) */
808 intel_ddi_put_crtc_pll(crtc
);
810 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
811 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
813 switch (intel_dp
->link_bw
) {
814 case DP_LINK_BW_1_62
:
815 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
818 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
821 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
824 DRM_ERROR("Link bandwidth %d unsupported\n",
829 /* We don't need to turn any PLL on because we'll use LCPLL. */
832 } else if (type
== INTEL_OUTPUT_HDMI
) {
835 if (plls
->wrpll1_refcount
== 0) {
836 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
838 plls
->wrpll1_refcount
++;
840 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
841 } else if (plls
->wrpll2_refcount
== 0) {
842 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
844 plls
->wrpll2_refcount
++;
846 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
848 DRM_ERROR("No WRPLLs available!\n");
852 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
853 "WRPLL already enabled\n");
855 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
857 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
858 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
859 WRPLL_DIVIDER_POST(p
);
861 } else if (type
== INTEL_OUTPUT_ANALOG
) {
862 if (plls
->spll_refcount
== 0) {
863 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
865 plls
->spll_refcount
++;
867 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
870 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
871 "SPLL already enabled\n");
873 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
876 WARN(1, "Invalid DDI encoder type %d\n", type
);
880 I915_WRITE(reg
, val
);
886 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
888 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
889 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
890 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
891 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
892 int type
= intel_encoder
->type
;
895 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
897 temp
= TRANS_MSA_SYNC_CLK
;
898 switch (intel_crtc
->bpp
) {
900 temp
|= TRANS_MSA_6_BPC
;
903 temp
|= TRANS_MSA_8_BPC
;
906 temp
|= TRANS_MSA_10_BPC
;
909 temp
|= TRANS_MSA_12_BPC
;
912 temp
|= TRANS_MSA_8_BPC
;
913 WARN(1, "%d bpp unsupported by DDI function\n",
916 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
920 void intel_ddi_enable_pipe_func(struct drm_crtc
*crtc
)
922 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
923 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
924 struct drm_encoder
*encoder
= &intel_encoder
->base
;
925 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
926 enum pipe pipe
= intel_crtc
->pipe
;
927 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
928 int type
= intel_encoder
->type
;
931 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
932 temp
= TRANS_DDI_FUNC_ENABLE
;
934 switch (intel_crtc
->bpp
) {
936 temp
|= TRANS_DDI_BPC_6
;
939 temp
|= TRANS_DDI_BPC_8
;
942 temp
|= TRANS_DDI_BPC_10
;
945 temp
|= TRANS_DDI_BPC_12
;
948 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
952 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
953 temp
|= TRANS_DDI_PVSYNC
;
954 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
955 temp
|= TRANS_DDI_PHSYNC
;
957 if (type
== INTEL_OUTPUT_HDMI
) {
958 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
960 if (intel_hdmi
->has_hdmi_sink
)
961 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
963 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
965 temp
|= TRANS_DDI_SELECT_PORT(intel_hdmi
->ddi_port
);
967 } else if (type
== INTEL_OUTPUT_ANALOG
) {
968 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
969 temp
|= TRANS_DDI_SELECT_PORT(PORT_E
);
971 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
972 type
== INTEL_OUTPUT_EDP
) {
973 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
975 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
976 temp
|= TRANS_DDI_SELECT_PORT(intel_dp
->port
);
978 switch (intel_dp
->lane_count
) {
980 temp
|= TRANS_DDI_PORT_WIDTH_X1
;
983 temp
|= TRANS_DDI_PORT_WIDTH_X2
;
986 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
989 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
990 WARN(1, "Unsupported lane count %d\n",
991 intel_dp
->lane_count
);
995 WARN(1, "Invalid encoder type %d for pipe %d\n",
996 intel_encoder
->type
, pipe
);
999 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1002 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1003 enum transcoder cpu_transcoder
)
1005 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1006 uint32_t val
= I915_READ(reg
);
1008 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1009 val
|= TRANS_DDI_PORT_NONE
;
1010 I915_WRITE(reg
, val
);
1013 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1016 struct drm_device
*dev
= encoder
->base
.dev
;
1017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1018 enum port port
= intel_ddi_get_encoder_port(encoder
);
1022 tmp
= I915_READ(DDI_BUF_CTL(port
));
1024 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1027 if (port
== PORT_A
) {
1028 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1030 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1031 case TRANS_DDI_EDP_INPUT_A_ON
:
1032 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1035 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1038 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1045 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1046 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1048 if ((tmp
& TRANS_DDI_PORT_MASK
)
1049 == TRANS_DDI_SELECT_PORT(port
)) {
1056 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port
);
1061 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1066 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1070 if (cpu_transcoder
== TRANSCODER_EDP
) {
1073 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1074 temp
&= TRANS_DDI_PORT_MASK
;
1076 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1077 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1081 ret
= I915_READ(PORT_CLK_SEL(port
));
1083 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1084 pipe_name(pipe
), port_name(port
), ret
);
1089 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1093 struct intel_crtc
*intel_crtc
;
1095 for_each_pipe(pipe
) {
1097 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1099 if (!intel_crtc
->active
)
1102 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1105 switch (intel_crtc
->ddi_pll_sel
) {
1106 case PORT_CLK_SEL_SPLL
:
1107 dev_priv
->ddi_plls
.spll_refcount
++;
1109 case PORT_CLK_SEL_WRPLL1
:
1110 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1112 case PORT_CLK_SEL_WRPLL2
:
1113 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1119 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1121 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1122 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1123 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1124 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1125 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1127 if (cpu_transcoder
!= TRANSCODER_EDP
)
1128 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1129 TRANS_CLK_SEL_PORT(port
));
1132 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1134 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1135 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1137 if (cpu_transcoder
!= TRANSCODER_EDP
)
1138 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1139 TRANS_CLK_SEL_DISABLED
);
1142 void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1144 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1145 struct drm_crtc
*crtc
= encoder
->crtc
;
1146 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1148 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1150 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1152 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1154 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1155 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1157 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1158 intel_dp_start_link_train(intel_dp
);
1159 intel_dp_complete_link_train(intel_dp
);
1163 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
1166 uint32_t reg
= DDI_BUF_CTL(port
);
1169 for (i
= 0; i
< 8; i
++) {
1171 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
1174 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
1177 void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1179 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1180 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1181 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1185 val
= I915_READ(DDI_BUF_CTL(port
));
1186 if (val
& DDI_BUF_CTL_ENABLE
) {
1187 val
&= ~DDI_BUF_CTL_ENABLE
;
1188 I915_WRITE(DDI_BUF_CTL(port
), val
);
1192 val
= I915_READ(DP_TP_CTL(port
));
1193 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1194 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1195 I915_WRITE(DP_TP_CTL(port
), val
);
1198 intel_wait_ddi_buf_idle(dev_priv
, port
);
1200 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1203 void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1205 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1206 struct drm_device
*dev
= encoder
->dev
;
1207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1208 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1209 int type
= intel_encoder
->type
;
1211 if (type
== INTEL_OUTPUT_HDMI
) {
1212 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1213 * are ignored so nothing special needs to be done besides
1214 * enabling the port.
1216 I915_WRITE(DDI_BUF_CTL(port
), DDI_BUF_CTL_ENABLE
);
1220 void intel_disable_ddi(struct intel_encoder
*encoder
)
1222 /* This will be needed in the future, so leave it here for now */
1225 static int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1227 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1229 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1236 void intel_ddi_pll_init(struct drm_device
*dev
)
1238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1239 uint32_t val
= I915_READ(LCPLL_CTL
);
1241 /* The LCPLL register should be turned on by the BIOS. For now let's
1242 * just check its state and print errors in case something is wrong.
1243 * Don't even try to turn it on.
1246 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1247 intel_ddi_get_cdclk_freq(dev_priv
));
1249 if (val
& LCPLL_CD_SOURCE_FCLK
)
1250 DRM_ERROR("CDCLK source is not LCPLL\n");
1252 if (val
& LCPLL_PLL_DISABLE
)
1253 DRM_ERROR("LCPLL is disabled\n");
1256 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1258 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1259 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1260 enum port port
= intel_dp
->port
;
1264 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1265 val
= I915_READ(DDI_BUF_CTL(port
));
1266 if (val
& DDI_BUF_CTL_ENABLE
) {
1267 val
&= ~DDI_BUF_CTL_ENABLE
;
1268 I915_WRITE(DDI_BUF_CTL(port
), val
);
1272 val
= I915_READ(DP_TP_CTL(port
));
1273 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1274 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1275 I915_WRITE(DP_TP_CTL(port
), val
);
1276 POSTING_READ(DP_TP_CTL(port
));
1279 intel_wait_ddi_buf_idle(dev_priv
, port
);
1282 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1283 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1284 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1285 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1286 I915_WRITE(DP_TP_CTL(port
), val
);
1287 POSTING_READ(DP_TP_CTL(port
));
1289 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1290 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1291 POSTING_READ(DDI_BUF_CTL(port
));