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drm/i915/hsw: Avoid early timeout during LCPLL disable/restore
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
152 {
153 u32 val;
154 int divider;
155
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
159
160 divider = val & CCK_FREQUENCY_VALUES;
161
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
165
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
171 {
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
174
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
177 }
178
179 static int
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
181 {
182 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
183 }
184
185 static int
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
187 {
188 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
189 CCK_DISPLAY_REF_CLOCK_CONTROL);
190 }
191
192 static int
193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
194 {
195 uint32_t clkcfg;
196
197 /* hrawclock is 1/4 the FSB frequency */
198 clkcfg = I915_READ(CLKCFG);
199 switch (clkcfg & CLKCFG_FSB_MASK) {
200 case CLKCFG_FSB_400:
201 return 100000;
202 case CLKCFG_FSB_533:
203 return 133333;
204 case CLKCFG_FSB_667:
205 return 166667;
206 case CLKCFG_FSB_800:
207 return 200000;
208 case CLKCFG_FSB_1067:
209 return 266667;
210 case CLKCFG_FSB_1333:
211 return 333333;
212 /* these two are just a guess; one of them might be right */
213 case CLKCFG_FSB_1600:
214 case CLKCFG_FSB_1600_ALT:
215 return 400000;
216 default:
217 return 133333;
218 }
219 }
220
221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
222 {
223 if (HAS_PCH_SPLIT(dev_priv))
224 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
225 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
226 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
227 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
228 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
229 else
230 return; /* no rawclk on other platforms, or no need to know it */
231
232 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
233 }
234
235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
236 {
237 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
238 return;
239
240 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
241 CCK_CZ_CLOCK_CONTROL);
242
243 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
244 }
245
246 static inline u32 /* units of 100MHz */
247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
248 const struct intel_crtc_state *pipe_config)
249 {
250 if (HAS_DDI(dev_priv))
251 return pipe_config->port_clock; /* SPLL */
252 else if (IS_GEN5(dev_priv))
253 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
254 else
255 return 270000;
256 }
257
258 static const intel_limit_t intel_limits_i8xx_dac = {
259 .dot = { .min = 25000, .max = 350000 },
260 .vco = { .min = 908000, .max = 1512000 },
261 .n = { .min = 2, .max = 16 },
262 .m = { .min = 96, .max = 140 },
263 .m1 = { .min = 18, .max = 26 },
264 .m2 = { .min = 6, .max = 16 },
265 .p = { .min = 4, .max = 128 },
266 .p1 = { .min = 2, .max = 33 },
267 .p2 = { .dot_limit = 165000,
268 .p2_slow = 4, .p2_fast = 2 },
269 };
270
271 static const intel_limit_t intel_limits_i8xx_dvo = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 908000, .max = 1512000 },
274 .n = { .min = 2, .max = 16 },
275 .m = { .min = 96, .max = 140 },
276 .m1 = { .min = 18, .max = 26 },
277 .m2 = { .min = 6, .max = 16 },
278 .p = { .min = 4, .max = 128 },
279 .p1 = { .min = 2, .max = 33 },
280 .p2 = { .dot_limit = 165000,
281 .p2_slow = 4, .p2_fast = 4 },
282 };
283
284 static const intel_limit_t intel_limits_i8xx_lvds = {
285 .dot = { .min = 25000, .max = 350000 },
286 .vco = { .min = 908000, .max = 1512000 },
287 .n = { .min = 2, .max = 16 },
288 .m = { .min = 96, .max = 140 },
289 .m1 = { .min = 18, .max = 26 },
290 .m2 = { .min = 6, .max = 16 },
291 .p = { .min = 4, .max = 128 },
292 .p1 = { .min = 1, .max = 6 },
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 14, .p2_fast = 7 },
295 };
296
297 static const intel_limit_t intel_limits_i9xx_sdvo = {
298 .dot = { .min = 20000, .max = 400000 },
299 .vco = { .min = 1400000, .max = 2800000 },
300 .n = { .min = 1, .max = 6 },
301 .m = { .min = 70, .max = 120 },
302 .m1 = { .min = 8, .max = 18 },
303 .m2 = { .min = 3, .max = 7 },
304 .p = { .min = 5, .max = 80 },
305 .p1 = { .min = 1, .max = 8 },
306 .p2 = { .dot_limit = 200000,
307 .p2_slow = 10, .p2_fast = 5 },
308 };
309
310 static const intel_limit_t intel_limits_i9xx_lvds = {
311 .dot = { .min = 20000, .max = 400000 },
312 .vco = { .min = 1400000, .max = 2800000 },
313 .n = { .min = 1, .max = 6 },
314 .m = { .min = 70, .max = 120 },
315 .m1 = { .min = 8, .max = 18 },
316 .m2 = { .min = 3, .max = 7 },
317 .p = { .min = 7, .max = 98 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 112000,
320 .p2_slow = 14, .p2_fast = 7 },
321 };
322
323
324 static const intel_limit_t intel_limits_g4x_sdvo = {
325 .dot = { .min = 25000, .max = 270000 },
326 .vco = { .min = 1750000, .max = 3500000},
327 .n = { .min = 1, .max = 4 },
328 .m = { .min = 104, .max = 138 },
329 .m1 = { .min = 17, .max = 23 },
330 .m2 = { .min = 5, .max = 11 },
331 .p = { .min = 10, .max = 30 },
332 .p1 = { .min = 1, .max = 3},
333 .p2 = { .dot_limit = 270000,
334 .p2_slow = 10,
335 .p2_fast = 10
336 },
337 };
338
339 static const intel_limit_t intel_limits_g4x_hdmi = {
340 .dot = { .min = 22000, .max = 400000 },
341 .vco = { .min = 1750000, .max = 3500000},
342 .n = { .min = 1, .max = 4 },
343 .m = { .min = 104, .max = 138 },
344 .m1 = { .min = 16, .max = 23 },
345 .m2 = { .min = 5, .max = 11 },
346 .p = { .min = 5, .max = 80 },
347 .p1 = { .min = 1, .max = 8},
348 .p2 = { .dot_limit = 165000,
349 .p2_slow = 10, .p2_fast = 5 },
350 };
351
352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
353 .dot = { .min = 20000, .max = 115000 },
354 .vco = { .min = 1750000, .max = 3500000 },
355 .n = { .min = 1, .max = 3 },
356 .m = { .min = 104, .max = 138 },
357 .m1 = { .min = 17, .max = 23 },
358 .m2 = { .min = 5, .max = 11 },
359 .p = { .min = 28, .max = 112 },
360 .p1 = { .min = 2, .max = 8 },
361 .p2 = { .dot_limit = 0,
362 .p2_slow = 14, .p2_fast = 14
363 },
364 };
365
366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
367 .dot = { .min = 80000, .max = 224000 },
368 .vco = { .min = 1750000, .max = 3500000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 104, .max = 138 },
371 .m1 = { .min = 17, .max = 23 },
372 .m2 = { .min = 5, .max = 11 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 0,
376 .p2_slow = 7, .p2_fast = 7
377 },
378 };
379
380 static const intel_limit_t intel_limits_pineview_sdvo = {
381 .dot = { .min = 20000, .max = 400000},
382 .vco = { .min = 1700000, .max = 3500000 },
383 /* Pineview's Ncounter is a ring counter */
384 .n = { .min = 3, .max = 6 },
385 .m = { .min = 2, .max = 256 },
386 /* Pineview only has one combined m divider, which we treat as m2. */
387 .m1 = { .min = 0, .max = 0 },
388 .m2 = { .min = 0, .max = 254 },
389 .p = { .min = 5, .max = 80 },
390 .p1 = { .min = 1, .max = 8 },
391 .p2 = { .dot_limit = 200000,
392 .p2_slow = 10, .p2_fast = 5 },
393 };
394
395 static const intel_limit_t intel_limits_pineview_lvds = {
396 .dot = { .min = 20000, .max = 400000 },
397 .vco = { .min = 1700000, .max = 3500000 },
398 .n = { .min = 3, .max = 6 },
399 .m = { .min = 2, .max = 256 },
400 .m1 = { .min = 0, .max = 0 },
401 .m2 = { .min = 0, .max = 254 },
402 .p = { .min = 7, .max = 112 },
403 .p1 = { .min = 1, .max = 8 },
404 .p2 = { .dot_limit = 112000,
405 .p2_slow = 14, .p2_fast = 14 },
406 };
407
408 /* Ironlake / Sandybridge
409 *
410 * We calculate clock using (register_value + 2) for N/M1/M2, so here
411 * the range value for them is (actual_value - 2).
412 */
413 static const intel_limit_t intel_limits_ironlake_dac = {
414 .dot = { .min = 25000, .max = 350000 },
415 .vco = { .min = 1760000, .max = 3510000 },
416 .n = { .min = 1, .max = 5 },
417 .m = { .min = 79, .max = 127 },
418 .m1 = { .min = 12, .max = 22 },
419 .m2 = { .min = 5, .max = 9 },
420 .p = { .min = 5, .max = 80 },
421 .p1 = { .min = 1, .max = 8 },
422 .p2 = { .dot_limit = 225000,
423 .p2_slow = 10, .p2_fast = 5 },
424 };
425
426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
427 .dot = { .min = 25000, .max = 350000 },
428 .vco = { .min = 1760000, .max = 3510000 },
429 .n = { .min = 1, .max = 3 },
430 .m = { .min = 79, .max = 118 },
431 .m1 = { .min = 12, .max = 22 },
432 .m2 = { .min = 5, .max = 9 },
433 .p = { .min = 28, .max = 112 },
434 .p1 = { .min = 2, .max = 8 },
435 .p2 = { .dot_limit = 225000,
436 .p2_slow = 14, .p2_fast = 14 },
437 };
438
439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
440 .dot = { .min = 25000, .max = 350000 },
441 .vco = { .min = 1760000, .max = 3510000 },
442 .n = { .min = 1, .max = 3 },
443 .m = { .min = 79, .max = 127 },
444 .m1 = { .min = 12, .max = 22 },
445 .m2 = { .min = 5, .max = 9 },
446 .p = { .min = 14, .max = 56 },
447 .p1 = { .min = 2, .max = 8 },
448 .p2 = { .dot_limit = 225000,
449 .p2_slow = 7, .p2_fast = 7 },
450 };
451
452 /* LVDS 100mhz refclk limits. */
453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
454 .dot = { .min = 25000, .max = 350000 },
455 .vco = { .min = 1760000, .max = 3510000 },
456 .n = { .min = 1, .max = 2 },
457 .m = { .min = 79, .max = 126 },
458 .m1 = { .min = 12, .max = 22 },
459 .m2 = { .min = 5, .max = 9 },
460 .p = { .min = 28, .max = 112 },
461 .p1 = { .min = 2, .max = 8 },
462 .p2 = { .dot_limit = 225000,
463 .p2_slow = 14, .p2_fast = 14 },
464 };
465
466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
467 .dot = { .min = 25000, .max = 350000 },
468 .vco = { .min = 1760000, .max = 3510000 },
469 .n = { .min = 1, .max = 3 },
470 .m = { .min = 79, .max = 126 },
471 .m1 = { .min = 12, .max = 22 },
472 .m2 = { .min = 5, .max = 9 },
473 .p = { .min = 14, .max = 42 },
474 .p1 = { .min = 2, .max = 6 },
475 .p2 = { .dot_limit = 225000,
476 .p2_slow = 7, .p2_fast = 7 },
477 };
478
479 static const intel_limit_t intel_limits_vlv = {
480 /*
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
485 */
486 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
487 .vco = { .min = 4000000, .max = 6000000 },
488 .n = { .min = 1, .max = 7 },
489 .m1 = { .min = 2, .max = 3 },
490 .m2 = { .min = 11, .max = 156 },
491 .p1 = { .min = 2, .max = 3 },
492 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
493 };
494
495 static const intel_limit_t intel_limits_chv = {
496 /*
497 * These are the data rate limits (measured in fast clocks)
498 * since those are the strictest limits we have. The fast
499 * clock and actual rate limits are more relaxed, so checking
500 * them would make no difference.
501 */
502 .dot = { .min = 25000 * 5, .max = 540000 * 5},
503 .vco = { .min = 4800000, .max = 6480000 },
504 .n = { .min = 1, .max = 1 },
505 .m1 = { .min = 2, .max = 2 },
506 .m2 = { .min = 24 << 22, .max = 175 << 22 },
507 .p1 = { .min = 2, .max = 4 },
508 .p2 = { .p2_slow = 1, .p2_fast = 14 },
509 };
510
511 static const intel_limit_t intel_limits_bxt = {
512 /* FIXME: find real dot limits */
513 .dot = { .min = 0, .max = INT_MAX },
514 .vco = { .min = 4800000, .max = 6700000 },
515 .n = { .min = 1, .max = 1 },
516 .m1 = { .min = 2, .max = 2 },
517 /* FIXME: find real m2 limits */
518 .m2 = { .min = 2 << 22, .max = 255 << 22 },
519 .p1 = { .min = 2, .max = 4 },
520 .p2 = { .p2_slow = 1, .p2_fast = 20 },
521 };
522
523 static bool
524 needs_modeset(struct drm_crtc_state *state)
525 {
526 return drm_atomic_crtc_needs_modeset(state);
527 }
528
529 /**
530 * Returns whether any output on the specified pipe is of the specified type
531 */
532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
533 {
534 struct drm_device *dev = crtc->base.dev;
535 struct intel_encoder *encoder;
536
537 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
538 if (encoder->type == type)
539 return true;
540
541 return false;
542 }
543
544 /**
545 * Returns whether any output on the specified pipe will have the specified
546 * type after a staged modeset is complete, i.e., the same as
547 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
548 * encoder->crtc.
549 */
550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
551 int type)
552 {
553 struct drm_atomic_state *state = crtc_state->base.state;
554 struct drm_connector *connector;
555 struct drm_connector_state *connector_state;
556 struct intel_encoder *encoder;
557 int i, num_connectors = 0;
558
559 for_each_connector_in_state(state, connector, connector_state, i) {
560 if (connector_state->crtc != crtc_state->base.crtc)
561 continue;
562
563 num_connectors++;
564
565 encoder = to_intel_encoder(connector_state->best_encoder);
566 if (encoder->type == type)
567 return true;
568 }
569
570 WARN_ON(num_connectors == 0);
571
572 return false;
573 }
574
575 /*
576 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
577 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
578 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
579 * The helpers' return value is the rate of the clock that is fed to the
580 * display engine's pipe which can be the above fast dot clock rate or a
581 * divided-down version of it.
582 */
583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
585 {
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592
593 return clock->dot;
594 }
595
596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
597 {
598 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
599 }
600
601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
602 {
603 clock->m = i9xx_dpll_compute_m(clock);
604 clock->p = clock->p1 * clock->p2;
605 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
606 return 0;
607 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
608 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
609
610 return clock->dot;
611 }
612
613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
614 {
615 clock->m = clock->m1 * clock->m2;
616 clock->p = clock->p1 * clock->p2;
617 if (WARN_ON(clock->n == 0 || clock->p == 0))
618 return 0;
619 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
620 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
621
622 return clock->dot / 5;
623 }
624
625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
626 {
627 clock->m = clock->m1 * clock->m2;
628 clock->p = clock->p1 * clock->p2;
629 if (WARN_ON(clock->n == 0 || clock->p == 0))
630 return 0;
631 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
632 clock->n << 22);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
634
635 return clock->dot / 5;
636 }
637
638 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
639 /**
640 * Returns whether the given set of divisors are valid for a given refclk with
641 * the given connectors.
642 */
643
644 static bool intel_PLL_is_valid(struct drm_device *dev,
645 const intel_limit_t *limit,
646 const intel_clock_t *clock)
647 {
648 if (clock->n < limit->n.min || limit->n.max < clock->n)
649 INTELPllInvalid("n out of range\n");
650 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
651 INTELPllInvalid("p1 out of range\n");
652 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
653 INTELPllInvalid("m2 out of range\n");
654 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
655 INTELPllInvalid("m1 out of range\n");
656
657 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
658 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
659 if (clock->m1 <= clock->m2)
660 INTELPllInvalid("m1 <= m2\n");
661
662 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
663 if (clock->p < limit->p.min || limit->p.max < clock->p)
664 INTELPllInvalid("p out of range\n");
665 if (clock->m < limit->m.min || limit->m.max < clock->m)
666 INTELPllInvalid("m out of range\n");
667 }
668
669 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
670 INTELPllInvalid("vco out of range\n");
671 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
672 * connector, etc., rather than just a single range.
673 */
674 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
675 INTELPllInvalid("dot out of range\n");
676
677 return true;
678 }
679
680 static int
681 i9xx_select_p2_div(const intel_limit_t *limit,
682 const struct intel_crtc_state *crtc_state,
683 int target)
684 {
685 struct drm_device *dev = crtc_state->base.crtc->dev;
686
687 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
688 /*
689 * For LVDS just rely on its current settings for dual-channel.
690 * We haven't figured out how to reliably set up different
691 * single/dual channel state, if we even can.
692 */
693 if (intel_is_dual_link_lvds(dev))
694 return limit->p2.p2_fast;
695 else
696 return limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 return limit->p2.p2_slow;
700 else
701 return limit->p2.p2_fast;
702 }
703 }
704
705 /*
706 * Returns a set of divisors for the desired target clock with the given
707 * refclk, or FALSE. The returned values represent the clock equation:
708 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
709 *
710 * Target and reference clocks are specified in kHz.
711 *
712 * If match_clock is provided, then best_clock P divider must match the P
713 * divider from @match_clock used for LVDS downclocking.
714 */
715 static bool
716 i9xx_find_best_dpll(const intel_limit_t *limit,
717 struct intel_crtc_state *crtc_state,
718 int target, int refclk, intel_clock_t *match_clock,
719 intel_clock_t *best_clock)
720 {
721 struct drm_device *dev = crtc_state->base.crtc->dev;
722 intel_clock_t clock;
723 int err = target;
724
725 memset(best_clock, 0, sizeof(*best_clock));
726
727 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
728
729 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
730 clock.m1++) {
731 for (clock.m2 = limit->m2.min;
732 clock.m2 <= limit->m2.max; clock.m2++) {
733 if (clock.m2 >= clock.m1)
734 break;
735 for (clock.n = limit->n.min;
736 clock.n <= limit->n.max; clock.n++) {
737 for (clock.p1 = limit->p1.min;
738 clock.p1 <= limit->p1.max; clock.p1++) {
739 int this_err;
740
741 i9xx_calc_dpll_params(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
748
749 this_err = abs(clock.dot - target);
750 if (this_err < err) {
751 *best_clock = clock;
752 err = this_err;
753 }
754 }
755 }
756 }
757 }
758
759 return (err != target);
760 }
761
762 /*
763 * Returns a set of divisors for the desired target clock with the given
764 * refclk, or FALSE. The returned values represent the clock equation:
765 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
766 *
767 * Target and reference clocks are specified in kHz.
768 *
769 * If match_clock is provided, then best_clock P divider must match the P
770 * divider from @match_clock used for LVDS downclocking.
771 */
772 static bool
773 pnv_find_best_dpll(const intel_limit_t *limit,
774 struct intel_crtc_state *crtc_state,
775 int target, int refclk, intel_clock_t *match_clock,
776 intel_clock_t *best_clock)
777 {
778 struct drm_device *dev = crtc_state->base.crtc->dev;
779 intel_clock_t clock;
780 int err = target;
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
787 clock.m1++) {
788 for (clock.m2 = limit->m2.min;
789 clock.m2 <= limit->m2.max; clock.m2++) {
790 for (clock.n = limit->n.min;
791 clock.n <= limit->n.max; clock.n++) {
792 for (clock.p1 = limit->p1.min;
793 clock.p1 <= limit->p1.max; clock.p1++) {
794 int this_err;
795
796 pnv_calc_dpll_params(refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
799 continue;
800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
803
804 this_err = abs(clock.dot - target);
805 if (this_err < err) {
806 *best_clock = clock;
807 err = this_err;
808 }
809 }
810 }
811 }
812 }
813
814 return (err != target);
815 }
816
817 /*
818 * Returns a set of divisors for the desired target clock with the given
819 * refclk, or FALSE. The returned values represent the clock equation:
820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
821 *
822 * Target and reference clocks are specified in kHz.
823 *
824 * If match_clock is provided, then best_clock P divider must match the P
825 * divider from @match_clock used for LVDS downclocking.
826 */
827 static bool
828 g4x_find_best_dpll(const intel_limit_t *limit,
829 struct intel_crtc_state *crtc_state,
830 int target, int refclk, intel_clock_t *match_clock,
831 intel_clock_t *best_clock)
832 {
833 struct drm_device *dev = crtc_state->base.crtc->dev;
834 intel_clock_t clock;
835 int max_n;
836 bool found = false;
837 /* approximately equals target * 0.00585 */
838 int err_most = (target >> 8) + (target >> 9);
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
843
844 max_n = limit->n.max;
845 /* based on hardware requirement, prefer smaller n to precision */
846 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
847 /* based on hardware requirement, prefere larger m1,m2 */
848 for (clock.m1 = limit->m1.max;
849 clock.m1 >= limit->m1.min; clock.m1--) {
850 for (clock.m2 = limit->m2.max;
851 clock.m2 >= limit->m2.min; clock.m2--) {
852 for (clock.p1 = limit->p1.max;
853 clock.p1 >= limit->p1.min; clock.p1--) {
854 int this_err;
855
856 i9xx_calc_dpll_params(refclk, &clock);
857 if (!intel_PLL_is_valid(dev, limit,
858 &clock))
859 continue;
860
861 this_err = abs(clock.dot - target);
862 if (this_err < err_most) {
863 *best_clock = clock;
864 err_most = this_err;
865 max_n = clock.n;
866 found = true;
867 }
868 }
869 }
870 }
871 }
872 return found;
873 }
874
875 /*
876 * Check if the calculated PLL configuration is more optimal compared to the
877 * best configuration and error found so far. Return the calculated error.
878 */
879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
880 const intel_clock_t *calculated_clock,
881 const intel_clock_t *best_clock,
882 unsigned int best_error_ppm,
883 unsigned int *error_ppm)
884 {
885 /*
886 * For CHV ignore the error and consider only the P value.
887 * Prefer a bigger P value based on HW requirements.
888 */
889 if (IS_CHERRYVIEW(dev)) {
890 *error_ppm = 0;
891
892 return calculated_clock->p > best_clock->p;
893 }
894
895 if (WARN_ON_ONCE(!target_freq))
896 return false;
897
898 *error_ppm = div_u64(1000000ULL *
899 abs(target_freq - calculated_clock->dot),
900 target_freq);
901 /*
902 * Prefer a better P value over a better (smaller) error if the error
903 * is small. Ensure this preference for future configurations too by
904 * setting the error to 0.
905 */
906 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
907 *error_ppm = 0;
908
909 return true;
910 }
911
912 return *error_ppm + 10 < best_error_ppm;
913 }
914
915 /*
916 * Returns a set of divisors for the desired target clock with the given
917 * refclk, or FALSE. The returned values represent the clock equation:
918 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
919 */
920 static bool
921 vlv_find_best_dpll(const intel_limit_t *limit,
922 struct intel_crtc_state *crtc_state,
923 int target, int refclk, intel_clock_t *match_clock,
924 intel_clock_t *best_clock)
925 {
926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
927 struct drm_device *dev = crtc->base.dev;
928 intel_clock_t clock;
929 unsigned int bestppm = 1000000;
930 /* min update 19.2 MHz */
931 int max_n = min(limit->n.max, refclk / 19200);
932 bool found = false;
933
934 target *= 5; /* fast clock */
935
936 memset(best_clock, 0, sizeof(*best_clock));
937
938 /* based on hardware requirement, prefer smaller n to precision */
939 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
943 clock.p = clock.p1 * clock.p2;
944 /* based on hardware requirement, prefer bigger m1,m2 values */
945 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
946 unsigned int ppm;
947
948 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
949 refclk * clock.m1);
950
951 vlv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit,
954 &clock))
955 continue;
956
957 if (!vlv_PLL_is_optimal(dev, target,
958 &clock,
959 best_clock,
960 bestppm, &ppm))
961 continue;
962
963 *best_clock = clock;
964 bestppm = ppm;
965 found = true;
966 }
967 }
968 }
969 }
970
971 return found;
972 }
973
974 /*
975 * Returns a set of divisors for the desired target clock with the given
976 * refclk, or FALSE. The returned values represent the clock equation:
977 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
978 */
979 static bool
980 chv_find_best_dpll(const intel_limit_t *limit,
981 struct intel_crtc_state *crtc_state,
982 int target, int refclk, intel_clock_t *match_clock,
983 intel_clock_t *best_clock)
984 {
985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
986 struct drm_device *dev = crtc->base.dev;
987 unsigned int best_error_ppm;
988 intel_clock_t clock;
989 uint64_t m2;
990 int found = false;
991
992 memset(best_clock, 0, sizeof(*best_clock));
993 best_error_ppm = 1000000;
994
995 /*
996 * Based on hardware doc, the n always set to 1, and m1 always
997 * set to 2. If requires to support 200Mhz refclk, we need to
998 * revisit this because n may not 1 anymore.
999 */
1000 clock.n = 1, clock.m1 = 2;
1001 target *= 5; /* fast clock */
1002
1003 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004 for (clock.p2 = limit->p2.p2_fast;
1005 clock.p2 >= limit->p2.p2_slow;
1006 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007 unsigned int error_ppm;
1008
1009 clock.p = clock.p1 * clock.p2;
1010
1011 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012 clock.n) << 22, refclk * clock.m1);
1013
1014 if (m2 > INT_MAX/clock.m1)
1015 continue;
1016
1017 clock.m2 = m2;
1018
1019 chv_calc_dpll_params(refclk, &clock);
1020
1021 if (!intel_PLL_is_valid(dev, limit, &clock))
1022 continue;
1023
1024 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025 best_error_ppm, &error_ppm))
1026 continue;
1027
1028 *best_clock = clock;
1029 best_error_ppm = error_ppm;
1030 found = true;
1031 }
1032 }
1033
1034 return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038 intel_clock_t *best_clock)
1039 {
1040 int refclk = 100000;
1041 const intel_limit_t *limit = &intel_limits_bxt;
1042
1043 return chv_find_best_dpll(limit, crtc_state,
1044 target_clock, refclk, NULL, best_clock);
1045 }
1046
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050
1051 /* Be paranoid as we can arrive here with only partial
1052 * state retrieved from the hardware during setup.
1053 *
1054 * We can ditch the adjusted_mode.crtc_clock check as soon
1055 * as Haswell has gained clock readout/fastboot support.
1056 *
1057 * We can ditch the crtc->primary->fb check as soon as we can
1058 * properly reconstruct framebuffers.
1059 *
1060 * FIXME: The intel_crtc->active here should be switched to
1061 * crtc->state->active once we have proper CRTC states wired up
1062 * for atomic.
1063 */
1064 return intel_crtc->active && crtc->primary->state->fb &&
1065 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069 enum pipe pipe)
1070 {
1071 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073
1074 return intel_crtc->config->cpu_transcoder;
1075 }
1076
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 i915_reg_t reg = PIPEDSL(pipe);
1081 u32 line1, line2;
1082 u32 line_mask;
1083
1084 if (IS_GEN2(dev))
1085 line_mask = DSL_LINEMASK_GEN2;
1086 else
1087 line_mask = DSL_LINEMASK_GEN3;
1088
1089 line1 = I915_READ(reg) & line_mask;
1090 msleep(5);
1091 line2 = I915_READ(reg) & line_mask;
1092
1093 return line1 == line2;
1094 }
1095
1096 /*
1097 * intel_wait_for_pipe_off - wait for pipe to turn off
1098 * @crtc: crtc whose pipe to wait for
1099 *
1100 * After disabling a pipe, we can't wait for vblank in the usual way,
1101 * spinning on the vblank interrupt status bit, since we won't actually
1102 * see an interrupt when the pipe is disabled.
1103 *
1104 * On Gen4 and above:
1105 * wait for the pipe register state bit to turn off
1106 *
1107 * Otherwise:
1108 * wait for the display line value to settle (it usually
1109 * ends up stopping at the start of the next frame).
1110 *
1111 */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114 struct drm_device *dev = crtc->base.dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117 enum pipe pipe = crtc->pipe;
1118
1119 if (INTEL_INFO(dev)->gen >= 4) {
1120 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121
1122 /* Wait for the Pipe State to go off */
1123 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124 100))
1125 WARN(1, "pipe_off wait timed out\n");
1126 } else {
1127 /* Wait for the display line to settle */
1128 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 }
1131 }
1132
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1136 {
1137 u32 val;
1138 bool cur_state;
1139
1140 val = I915_READ(DPLL(pipe));
1141 cur_state = !!(val & DPLL_VCO_ENABLE);
1142 I915_STATE_WARN(cur_state != state,
1143 "PLL state assertion failure (expected %s, current %s)\n",
1144 onoff(state), onoff(cur_state));
1145 }
1146
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150 u32 val;
1151 bool cur_state;
1152
1153 mutex_lock(&dev_priv->sb_lock);
1154 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155 mutex_unlock(&dev_priv->sb_lock);
1156
1157 cur_state = val & DSI_PLL_VCO_EN;
1158 I915_STATE_WARN(cur_state != state,
1159 "DSI PLL state assertion failure (expected %s, current %s)\n",
1160 onoff(state), onoff(cur_state));
1161 }
1162
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1165 {
1166 bool cur_state;
1167 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168 pipe);
1169
1170 if (HAS_DDI(dev_priv)) {
1171 /* DDI does not have a specific FDI_TX register */
1172 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174 } else {
1175 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176 cur_state = !!(val & FDI_TX_ENABLE);
1177 }
1178 I915_STATE_WARN(cur_state != state,
1179 "FDI TX state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 u32 val;
1189 bool cur_state;
1190
1191 val = I915_READ(FDI_RX_CTL(pipe));
1192 cur_state = !!(val & FDI_RX_ENABLE);
1193 I915_STATE_WARN(cur_state != state,
1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202 {
1203 u32 val;
1204
1205 /* ILK FDI PLL is always enabled */
1206 if (INTEL_INFO(dev_priv)->gen == 5)
1207 return;
1208
1209 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210 if (HAS_DDI(dev_priv))
1211 return;
1212
1213 val = I915_READ(FDI_TX_CTL(pipe));
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 u32 val;
1221 bool cur_state;
1222
1223 val = I915_READ(FDI_RX_CTL(pipe));
1224 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227 onoff(state), onoff(cur_state));
1228 }
1229
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 struct drm_device *dev = dev_priv->dev;
1234 i915_reg_t pp_reg;
1235 u32 val;
1236 enum pipe panel_pipe = PIPE_A;
1237 bool locked = true;
1238
1239 if (WARN_ON(HAS_DDI(dev)))
1240 return;
1241
1242 if (HAS_PCH_SPLIT(dev)) {
1243 u32 port_sel;
1244
1245 pp_reg = PCH_PP_CONTROL;
1246 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247
1248 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250 panel_pipe = PIPE_B;
1251 /* XXX: else fix for eDP */
1252 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253 /* presumably write lock depends on pipe, not port select */
1254 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255 panel_pipe = pipe;
1256 } else {
1257 pp_reg = PP_CONTROL;
1258 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259 panel_pipe = PIPE_B;
1260 }
1261
1262 val = I915_READ(pp_reg);
1263 if (!(val & PANEL_POWER_ON) ||
1264 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265 locked = false;
1266
1267 I915_STATE_WARN(panel_pipe == pipe && locked,
1268 "panel assertion failure, pipe %c regs locked\n",
1269 pipe_name(pipe));
1270 }
1271
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273 enum pipe pipe, bool state)
1274 {
1275 struct drm_device *dev = dev_priv->dev;
1276 bool cur_state;
1277
1278 if (IS_845G(dev) || IS_I865G(dev))
1279 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280 else
1281 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282
1283 I915_STATE_WARN(cur_state != state,
1284 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285 pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291 enum pipe pipe, bool state)
1292 {
1293 bool cur_state;
1294 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295 pipe);
1296 enum intel_display_power_domain power_domain;
1297
1298 /* if we need the pipe quirk it must be always on */
1299 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301 state = true;
1302
1303 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306 cur_state = !!(val & PIPECONF_ENABLE);
1307
1308 intel_display_power_put(dev_priv, power_domain);
1309 } else {
1310 cur_state = false;
1311 }
1312
1313 I915_STATE_WARN(cur_state != state,
1314 "pipe %c assertion failure (expected %s, current %s)\n",
1315 pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319 enum plane plane, bool state)
1320 {
1321 u32 val;
1322 bool cur_state;
1323
1324 val = I915_READ(DSPCNTR(plane));
1325 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326 I915_STATE_WARN(cur_state != state,
1327 "plane %c assertion failure (expected %s, current %s)\n",
1328 plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335 enum pipe pipe)
1336 {
1337 struct drm_device *dev = dev_priv->dev;
1338 int i;
1339
1340 /* Primary planes are fixed to pipes on gen4+ */
1341 if (INTEL_INFO(dev)->gen >= 4) {
1342 u32 val = I915_READ(DSPCNTR(pipe));
1343 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344 "plane %c assertion failure, should be disabled but not\n",
1345 plane_name(pipe));
1346 return;
1347 }
1348
1349 /* Need to check both planes against the pipe */
1350 for_each_pipe(dev_priv, i) {
1351 u32 val = I915_READ(DSPCNTR(i));
1352 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353 DISPPLANE_SEL_PIPE_SHIFT;
1354 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(i), pipe_name(pipe));
1357 }
1358 }
1359
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 struct drm_device *dev = dev_priv->dev;
1364 int sprite;
1365
1366 if (INTEL_INFO(dev)->gen >= 9) {
1367 for_each_sprite(dev_priv, pipe, sprite) {
1368 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371 sprite, pipe_name(pipe));
1372 }
1373 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374 for_each_sprite(dev_priv, pipe, sprite) {
1375 u32 val = I915_READ(SPCNTR(pipe, sprite));
1376 I915_STATE_WARN(val & SP_ENABLE,
1377 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378 sprite_name(pipe, sprite), pipe_name(pipe));
1379 }
1380 } else if (INTEL_INFO(dev)->gen >= 7) {
1381 u32 val = I915_READ(SPRCTL(pipe));
1382 I915_STATE_WARN(val & SPRITE_ENABLE,
1383 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384 plane_name(pipe), pipe_name(pipe));
1385 } else if (INTEL_INFO(dev)->gen >= 5) {
1386 u32 val = I915_READ(DVSCNTR(pipe));
1387 I915_STATE_WARN(val & DVS_ENABLE,
1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(pipe), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396 drm_crtc_vblank_put(crtc);
1397 }
1398
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401 {
1402 u32 val;
1403 bool enabled;
1404
1405 val = I915_READ(PCH_TRANSCONF(pipe));
1406 enabled = !!(val & TRANS_ENABLE);
1407 I915_STATE_WARN(enabled,
1408 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409 pipe_name(pipe));
1410 }
1411
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415 if ((val & DP_PORT_EN) == 0)
1416 return false;
1417
1418 if (HAS_PCH_CPT(dev_priv)) {
1419 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421 return false;
1422 } else if (IS_CHERRYVIEW(dev_priv)) {
1423 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424 return false;
1425 } else {
1426 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe, u32 val)
1434 {
1435 if ((val & SDVO_ENABLE) == 0)
1436 return false;
1437
1438 if (HAS_PCH_CPT(dev_priv)) {
1439 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440 return false;
1441 } else if (IS_CHERRYVIEW(dev_priv)) {
1442 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443 return false;
1444 } else {
1445 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & LVDS_PORT_EN) == 0)
1455 return false;
1456
1457 if (HAS_PCH_CPT(dev_priv)) {
1458 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459 return false;
1460 } else {
1461 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462 return false;
1463 }
1464 return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe, u32 val)
1469 {
1470 if ((val & ADPA_DAC_ENABLE) == 0)
1471 return false;
1472 if (HAS_PCH_CPT(dev_priv)) {
1473 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474 return false;
1475 } else {
1476 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, i915_reg_t reg,
1484 u32 port_sel)
1485 {
1486 u32 val = I915_READ(reg);
1487 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489 i915_mmio_reg_offset(reg), pipe_name(pipe));
1490
1491 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1492 && (val & DP_PIPEB_SELECT),
1493 "IBX PCH dp port still using transcoder B\n");
1494 }
1495
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, i915_reg_t reg)
1498 {
1499 u32 val = I915_READ(reg);
1500 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502 i915_mmio_reg_offset(reg), pipe_name(pipe));
1503
1504 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1505 && (val & SDVO_PIPE_B_SELECT),
1506 "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe)
1511 {
1512 u32 val;
1513
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518 val = I915_READ(PCH_ADPA);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 val = I915_READ(PCH_LVDS);
1524 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526 pipe_name(pipe));
1527
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532
1533 static void _vlv_enable_pll(struct intel_crtc *crtc,
1534 const struct intel_crtc_state *pipe_config)
1535 {
1536 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1537 enum pipe pipe = crtc->pipe;
1538
1539 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1540 POSTING_READ(DPLL(pipe));
1541 udelay(150);
1542
1543 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1544 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1545 }
1546
1547 static void vlv_enable_pll(struct intel_crtc *crtc,
1548 const struct intel_crtc_state *pipe_config)
1549 {
1550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1551 enum pipe pipe = crtc->pipe;
1552
1553 assert_pipe_disabled(dev_priv, pipe);
1554
1555 /* PLL is protected by panel, make sure we can write it */
1556 assert_panel_unlocked(dev_priv, pipe);
1557
1558 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1559 _vlv_enable_pll(crtc, pipe_config);
1560
1561 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1562 POSTING_READ(DPLL_MD(pipe));
1563 }
1564
1565
1566 static void _chv_enable_pll(struct intel_crtc *crtc,
1567 const struct intel_crtc_state *pipe_config)
1568 {
1569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570 enum pipe pipe = crtc->pipe;
1571 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1572 u32 tmp;
1573
1574 mutex_lock(&dev_priv->sb_lock);
1575
1576 /* Enable back the 10bit clock to display controller */
1577 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1578 tmp |= DPIO_DCLKP_EN;
1579 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1580
1581 mutex_unlock(&dev_priv->sb_lock);
1582
1583 /*
1584 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1585 */
1586 udelay(1);
1587
1588 /* Enable PLL */
1589 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1590
1591 /* Check PLL is locked */
1592 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1593 DRM_ERROR("PLL %d failed to lock\n", pipe);
1594 }
1595
1596 static void chv_enable_pll(struct intel_crtc *crtc,
1597 const struct intel_crtc_state *pipe_config)
1598 {
1599 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1600 enum pipe pipe = crtc->pipe;
1601
1602 assert_pipe_disabled(dev_priv, pipe);
1603
1604 /* PLL is protected by panel, make sure we can write it */
1605 assert_panel_unlocked(dev_priv, pipe);
1606
1607 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1608 _chv_enable_pll(crtc, pipe_config);
1609
1610 if (pipe != PIPE_A) {
1611 /*
1612 * WaPixelRepeatModeFixForC0:chv
1613 *
1614 * DPLLCMD is AWOL. Use chicken bits to propagate
1615 * the value from DPLLBMD to either pipe B or C.
1616 */
1617 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1618 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1619 I915_WRITE(CBR4_VLV, 0);
1620 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1621
1622 /*
1623 * DPLLB VGA mode also seems to cause problems.
1624 * We should always have it disabled.
1625 */
1626 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1627 } else {
1628 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1629 POSTING_READ(DPLL_MD(pipe));
1630 }
1631 }
1632
1633 static int intel_num_dvo_pipes(struct drm_device *dev)
1634 {
1635 struct intel_crtc *crtc;
1636 int count = 0;
1637
1638 for_each_intel_crtc(dev, crtc)
1639 count += crtc->base.state->active &&
1640 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1641
1642 return count;
1643 }
1644
1645 static void i9xx_enable_pll(struct intel_crtc *crtc)
1646 {
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 i915_reg_t reg = DPLL(crtc->pipe);
1650 u32 dpll = crtc->config->dpll_hw_state.dpll;
1651
1652 assert_pipe_disabled(dev_priv, crtc->pipe);
1653
1654 /* PLL is protected by panel, make sure we can write it */
1655 if (IS_MOBILE(dev) && !IS_I830(dev))
1656 assert_panel_unlocked(dev_priv, crtc->pipe);
1657
1658 /* Enable DVO 2x clock on both PLLs if necessary */
1659 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1660 /*
1661 * It appears to be important that we don't enable this
1662 * for the current pipe before otherwise configuring the
1663 * PLL. No idea how this should be handled if multiple
1664 * DVO outputs are enabled simultaneosly.
1665 */
1666 dpll |= DPLL_DVO_2X_MODE;
1667 I915_WRITE(DPLL(!crtc->pipe),
1668 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1669 }
1670
1671 /*
1672 * Apparently we need to have VGA mode enabled prior to changing
1673 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1674 * dividers, even though the register value does change.
1675 */
1676 I915_WRITE(reg, 0);
1677
1678 I915_WRITE(reg, dpll);
1679
1680 /* Wait for the clocks to stabilize. */
1681 POSTING_READ(reg);
1682 udelay(150);
1683
1684 if (INTEL_INFO(dev)->gen >= 4) {
1685 I915_WRITE(DPLL_MD(crtc->pipe),
1686 crtc->config->dpll_hw_state.dpll_md);
1687 } else {
1688 /* The pixel multiplier can only be updated once the
1689 * DPLL is enabled and the clocks are stable.
1690 *
1691 * So write it again.
1692 */
1693 I915_WRITE(reg, dpll);
1694 }
1695
1696 /* We do this three times for luck */
1697 I915_WRITE(reg, dpll);
1698 POSTING_READ(reg);
1699 udelay(150); /* wait for warmup */
1700 I915_WRITE(reg, dpll);
1701 POSTING_READ(reg);
1702 udelay(150); /* wait for warmup */
1703 I915_WRITE(reg, dpll);
1704 POSTING_READ(reg);
1705 udelay(150); /* wait for warmup */
1706 }
1707
1708 /**
1709 * i9xx_disable_pll - disable a PLL
1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe PLL to disable
1712 *
1713 * Disable the PLL for @pipe, making sure the pipe is off first.
1714 *
1715 * Note! This is for pre-ILK only.
1716 */
1717 static void i9xx_disable_pll(struct intel_crtc *crtc)
1718 {
1719 struct drm_device *dev = crtc->base.dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 enum pipe pipe = crtc->pipe;
1722
1723 /* Disable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1726 !intel_num_dvo_pipes(dev)) {
1727 I915_WRITE(DPLL(PIPE_B),
1728 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1729 I915_WRITE(DPLL(PIPE_A),
1730 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1731 }
1732
1733 /* Don't disable pipe or pipe PLLs if needed */
1734 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1735 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1736 return;
1737
1738 /* Make sure the pipe isn't still relying on us */
1739 assert_pipe_disabled(dev_priv, pipe);
1740
1741 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1742 POSTING_READ(DPLL(pipe));
1743 }
1744
1745 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1746 {
1747 u32 val;
1748
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv, pipe);
1751
1752 val = DPLL_INTEGRATED_REF_CLK_VLV |
1753 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754 if (pipe != PIPE_A)
1755 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756
1757 I915_WRITE(DPLL(pipe), val);
1758 POSTING_READ(DPLL(pipe));
1759 }
1760
1761 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1762 {
1763 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1764 u32 val;
1765
1766 /* Make sure the pipe isn't still relying on us */
1767 assert_pipe_disabled(dev_priv, pipe);
1768
1769 val = DPLL_SSC_REF_CLK_CHV |
1770 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1771 if (pipe != PIPE_A)
1772 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1773
1774 I915_WRITE(DPLL(pipe), val);
1775 POSTING_READ(DPLL(pipe));
1776
1777 mutex_lock(&dev_priv->sb_lock);
1778
1779 /* Disable 10bit clock to display controller */
1780 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1781 val &= ~DPIO_DCLKP_EN;
1782 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1783
1784 mutex_unlock(&dev_priv->sb_lock);
1785 }
1786
1787 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1788 struct intel_digital_port *dport,
1789 unsigned int expected_mask)
1790 {
1791 u32 port_mask;
1792 i915_reg_t dpll_reg;
1793
1794 switch (dport->port) {
1795 case PORT_B:
1796 port_mask = DPLL_PORTB_READY_MASK;
1797 dpll_reg = DPLL(0);
1798 break;
1799 case PORT_C:
1800 port_mask = DPLL_PORTC_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 expected_mask <<= 4;
1803 break;
1804 case PORT_D:
1805 port_mask = DPLL_PORTD_READY_MASK;
1806 dpll_reg = DPIO_PHY_STATUS;
1807 break;
1808 default:
1809 BUG();
1810 }
1811
1812 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1813 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1814 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1815 }
1816
1817 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1818 enum pipe pipe)
1819 {
1820 struct drm_device *dev = dev_priv->dev;
1821 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823 i915_reg_t reg;
1824 uint32_t val, pipeconf_val;
1825
1826 /* Make sure PCH DPLL is enabled */
1827 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1828
1829 /* FDI must be feeding us bits for PCH ports */
1830 assert_fdi_tx_enabled(dev_priv, pipe);
1831 assert_fdi_rx_enabled(dev_priv, pipe);
1832
1833 if (HAS_PCH_CPT(dev)) {
1834 /* Workaround: Set the timing override bit before enabling the
1835 * pch transcoder. */
1836 reg = TRANS_CHICKEN2(pipe);
1837 val = I915_READ(reg);
1838 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1839 I915_WRITE(reg, val);
1840 }
1841
1842 reg = PCH_TRANSCONF(pipe);
1843 val = I915_READ(reg);
1844 pipeconf_val = I915_READ(PIPECONF(pipe));
1845
1846 if (HAS_PCH_IBX(dev_priv)) {
1847 /*
1848 * Make the BPC in transcoder be consistent with
1849 * that in pipeconf reg. For HDMI we must use 8bpc
1850 * here for both 8bpc and 12bpc.
1851 */
1852 val &= ~PIPECONF_BPC_MASK;
1853 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1854 val |= PIPECONF_8BPC;
1855 else
1856 val |= pipeconf_val & PIPECONF_BPC_MASK;
1857 }
1858
1859 val &= ~TRANS_INTERLACE_MASK;
1860 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1861 if (HAS_PCH_IBX(dev_priv) &&
1862 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1863 val |= TRANS_LEGACY_INTERLACED_ILK;
1864 else
1865 val |= TRANS_INTERLACED;
1866 else
1867 val |= TRANS_PROGRESSIVE;
1868
1869 I915_WRITE(reg, val | TRANS_ENABLE);
1870 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1871 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1872 }
1873
1874 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1875 enum transcoder cpu_transcoder)
1876 {
1877 u32 val, pipeconf_val;
1878
1879 /* FDI must be feeding us bits for PCH ports */
1880 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1881 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1882
1883 /* Workaround: set timing override bit. */
1884 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1885 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1886 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1887
1888 val = TRANS_ENABLE;
1889 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1890
1891 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1892 PIPECONF_INTERLACED_ILK)
1893 val |= TRANS_INTERLACED;
1894 else
1895 val |= TRANS_PROGRESSIVE;
1896
1897 I915_WRITE(LPT_TRANSCONF, val);
1898 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1899 DRM_ERROR("Failed to enable PCH transcoder\n");
1900 }
1901
1902 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1903 enum pipe pipe)
1904 {
1905 struct drm_device *dev = dev_priv->dev;
1906 i915_reg_t reg;
1907 uint32_t val;
1908
1909 /* FDI relies on the transcoder */
1910 assert_fdi_tx_disabled(dev_priv, pipe);
1911 assert_fdi_rx_disabled(dev_priv, pipe);
1912
1913 /* Ports must be off as well */
1914 assert_pch_ports_disabled(dev_priv, pipe);
1915
1916 reg = PCH_TRANSCONF(pipe);
1917 val = I915_READ(reg);
1918 val &= ~TRANS_ENABLE;
1919 I915_WRITE(reg, val);
1920 /* wait for PCH transcoder off, transcoder state */
1921 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1922 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1923
1924 if (HAS_PCH_CPT(dev)) {
1925 /* Workaround: Clear the timing override chicken bit again. */
1926 reg = TRANS_CHICKEN2(pipe);
1927 val = I915_READ(reg);
1928 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1929 I915_WRITE(reg, val);
1930 }
1931 }
1932
1933 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1934 {
1935 u32 val;
1936
1937 val = I915_READ(LPT_TRANSCONF);
1938 val &= ~TRANS_ENABLE;
1939 I915_WRITE(LPT_TRANSCONF, val);
1940 /* wait for PCH transcoder off, transcoder state */
1941 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1942 DRM_ERROR("Failed to disable PCH transcoder\n");
1943
1944 /* Workaround: clear timing override bit. */
1945 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1946 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1947 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1948 }
1949
1950 /**
1951 * intel_enable_pipe - enable a pipe, asserting requirements
1952 * @crtc: crtc responsible for the pipe
1953 *
1954 * Enable @crtc's pipe, making sure that various hardware specific requirements
1955 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1956 */
1957 static void intel_enable_pipe(struct intel_crtc *crtc)
1958 {
1959 struct drm_device *dev = crtc->base.dev;
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961 enum pipe pipe = crtc->pipe;
1962 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1963 enum pipe pch_transcoder;
1964 i915_reg_t reg;
1965 u32 val;
1966
1967 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1968
1969 assert_planes_disabled(dev_priv, pipe);
1970 assert_cursor_disabled(dev_priv, pipe);
1971 assert_sprites_disabled(dev_priv, pipe);
1972
1973 if (HAS_PCH_LPT(dev_priv))
1974 pch_transcoder = TRANSCODER_A;
1975 else
1976 pch_transcoder = pipe;
1977
1978 /*
1979 * A pipe without a PLL won't actually be able to drive bits from
1980 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1981 * need the check.
1982 */
1983 if (HAS_GMCH_DISPLAY(dev_priv))
1984 if (crtc->config->has_dsi_encoder)
1985 assert_dsi_pll_enabled(dev_priv);
1986 else
1987 assert_pll_enabled(dev_priv, pipe);
1988 else {
1989 if (crtc->config->has_pch_encoder) {
1990 /* if driving the PCH, we need FDI enabled */
1991 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1992 assert_fdi_tx_pll_enabled(dev_priv,
1993 (enum pipe) cpu_transcoder);
1994 }
1995 /* FIXME: assert CPU port conditions for SNB+ */
1996 }
1997
1998 reg = PIPECONF(cpu_transcoder);
1999 val = I915_READ(reg);
2000 if (val & PIPECONF_ENABLE) {
2001 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2002 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2003 return;
2004 }
2005
2006 I915_WRITE(reg, val | PIPECONF_ENABLE);
2007 POSTING_READ(reg);
2008
2009 /*
2010 * Until the pipe starts DSL will read as 0, which would cause
2011 * an apparent vblank timestamp jump, which messes up also the
2012 * frame count when it's derived from the timestamps. So let's
2013 * wait for the pipe to start properly before we call
2014 * drm_crtc_vblank_on()
2015 */
2016 if (dev->max_vblank_count == 0 &&
2017 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2018 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2019 }
2020
2021 /**
2022 * intel_disable_pipe - disable a pipe, asserting requirements
2023 * @crtc: crtc whose pipes is to be disabled
2024 *
2025 * Disable the pipe of @crtc, making sure that various hardware
2026 * specific requirements are met, if applicable, e.g. plane
2027 * disabled, panel fitter off, etc.
2028 *
2029 * Will wait until the pipe has shut down before returning.
2030 */
2031 static void intel_disable_pipe(struct intel_crtc *crtc)
2032 {
2033 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2034 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2035 enum pipe pipe = crtc->pipe;
2036 i915_reg_t reg;
2037 u32 val;
2038
2039 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2040
2041 /*
2042 * Make sure planes won't keep trying to pump pixels to us,
2043 * or we might hang the display.
2044 */
2045 assert_planes_disabled(dev_priv, pipe);
2046 assert_cursor_disabled(dev_priv, pipe);
2047 assert_sprites_disabled(dev_priv, pipe);
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if ((val & PIPECONF_ENABLE) == 0)
2052 return;
2053
2054 /*
2055 * Double wide has implications for planes
2056 * so best keep it disabled when not needed.
2057 */
2058 if (crtc->config->double_wide)
2059 val &= ~PIPECONF_DOUBLE_WIDE;
2060
2061 /* Don't disable pipe or pipe PLLs if needed */
2062 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2063 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2064 val &= ~PIPECONF_ENABLE;
2065
2066 I915_WRITE(reg, val);
2067 if ((val & PIPECONF_ENABLE) == 0)
2068 intel_wait_for_pipe_off(crtc);
2069 }
2070
2071 static bool need_vtd_wa(struct drm_device *dev)
2072 {
2073 #ifdef CONFIG_INTEL_IOMMU
2074 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2075 return true;
2076 #endif
2077 return false;
2078 }
2079
2080 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2081 {
2082 return IS_GEN2(dev_priv) ? 2048 : 4096;
2083 }
2084
2085 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2086 uint64_t fb_modifier, unsigned int cpp)
2087 {
2088 switch (fb_modifier) {
2089 case DRM_FORMAT_MOD_NONE:
2090 return cpp;
2091 case I915_FORMAT_MOD_X_TILED:
2092 if (IS_GEN2(dev_priv))
2093 return 128;
2094 else
2095 return 512;
2096 case I915_FORMAT_MOD_Y_TILED:
2097 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2098 return 128;
2099 else
2100 return 512;
2101 case I915_FORMAT_MOD_Yf_TILED:
2102 switch (cpp) {
2103 case 1:
2104 return 64;
2105 case 2:
2106 case 4:
2107 return 128;
2108 case 8:
2109 case 16:
2110 return 256;
2111 default:
2112 MISSING_CASE(cpp);
2113 return cpp;
2114 }
2115 break;
2116 default:
2117 MISSING_CASE(fb_modifier);
2118 return cpp;
2119 }
2120 }
2121
2122 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2123 uint64_t fb_modifier, unsigned int cpp)
2124 {
2125 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2126 return 1;
2127 else
2128 return intel_tile_size(dev_priv) /
2129 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2130 }
2131
2132 /* Return the tile dimensions in pixel units */
2133 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2134 unsigned int *tile_width,
2135 unsigned int *tile_height,
2136 uint64_t fb_modifier,
2137 unsigned int cpp)
2138 {
2139 unsigned int tile_width_bytes =
2140 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2141
2142 *tile_width = tile_width_bytes / cpp;
2143 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2144 }
2145
2146 unsigned int
2147 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2148 uint32_t pixel_format, uint64_t fb_modifier)
2149 {
2150 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2151 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2152
2153 return ALIGN(height, tile_height);
2154 }
2155
2156 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2157 {
2158 unsigned int size = 0;
2159 int i;
2160
2161 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2162 size += rot_info->plane[i].width * rot_info->plane[i].height;
2163
2164 return size;
2165 }
2166
2167 static void
2168 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2169 const struct drm_framebuffer *fb,
2170 unsigned int rotation)
2171 {
2172 if (intel_rotation_90_or_270(rotation)) {
2173 *view = i915_ggtt_view_rotated;
2174 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2175 } else {
2176 *view = i915_ggtt_view_normal;
2177 }
2178 }
2179
2180 static void
2181 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2182 struct drm_framebuffer *fb)
2183 {
2184 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2185 unsigned int tile_size, tile_width, tile_height, cpp;
2186
2187 tile_size = intel_tile_size(dev_priv);
2188
2189 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2190 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2191 fb->modifier[0], cpp);
2192
2193 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2194 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2195
2196 if (info->pixel_format == DRM_FORMAT_NV12) {
2197 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2198 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2199 fb->modifier[1], cpp);
2200
2201 info->uv_offset = fb->offsets[1];
2202 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2203 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2204 }
2205 }
2206
2207 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2208 {
2209 if (INTEL_INFO(dev_priv)->gen >= 9)
2210 return 256 * 1024;
2211 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2212 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2213 return 128 * 1024;
2214 else if (INTEL_INFO(dev_priv)->gen >= 4)
2215 return 4 * 1024;
2216 else
2217 return 0;
2218 }
2219
2220 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2221 uint64_t fb_modifier)
2222 {
2223 switch (fb_modifier) {
2224 case DRM_FORMAT_MOD_NONE:
2225 return intel_linear_alignment(dev_priv);
2226 case I915_FORMAT_MOD_X_TILED:
2227 if (INTEL_INFO(dev_priv)->gen >= 9)
2228 return 256 * 1024;
2229 return 0;
2230 case I915_FORMAT_MOD_Y_TILED:
2231 case I915_FORMAT_MOD_Yf_TILED:
2232 return 1 * 1024 * 1024;
2233 default:
2234 MISSING_CASE(fb_modifier);
2235 return 0;
2236 }
2237 }
2238
2239 int
2240 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2241 unsigned int rotation)
2242 {
2243 struct drm_device *dev = fb->dev;
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246 struct i915_ggtt_view view;
2247 u32 alignment;
2248 int ret;
2249
2250 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2251
2252 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2253
2254 intel_fill_fb_ggtt_view(&view, fb, rotation);
2255
2256 /* Note that the w/a also requires 64 PTE of padding following the
2257 * bo. We currently fill all unused PTE with the shadow page and so
2258 * we should always have valid PTE following the scanout preventing
2259 * the VT-d warning.
2260 */
2261 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2262 alignment = 256 * 1024;
2263
2264 /*
2265 * Global gtt pte registers are special registers which actually forward
2266 * writes to a chunk of system memory. Which means that there is no risk
2267 * that the register values disappear as soon as we call
2268 * intel_runtime_pm_put(), so it is correct to wrap only the
2269 * pin/unpin/fence and not more.
2270 */
2271 intel_runtime_pm_get(dev_priv);
2272
2273 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2274 &view);
2275 if (ret)
2276 goto err_pm;
2277
2278 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2279 * fence, whereas 965+ only requires a fence if using
2280 * framebuffer compression. For simplicity, we always install
2281 * a fence as the cost is not that onerous.
2282 */
2283 if (view.type == I915_GGTT_VIEW_NORMAL) {
2284 ret = i915_gem_object_get_fence(obj);
2285 if (ret == -EDEADLK) {
2286 /*
2287 * -EDEADLK means there are no free fences
2288 * no pending flips.
2289 *
2290 * This is propagated to atomic, but it uses
2291 * -EDEADLK to force a locking recovery, so
2292 * change the returned error to -EBUSY.
2293 */
2294 ret = -EBUSY;
2295 goto err_unpin;
2296 } else if (ret)
2297 goto err_unpin;
2298
2299 i915_gem_object_pin_fence(obj);
2300 }
2301
2302 intel_runtime_pm_put(dev_priv);
2303 return 0;
2304
2305 err_unpin:
2306 i915_gem_object_unpin_from_display_plane(obj, &view);
2307 err_pm:
2308 intel_runtime_pm_put(dev_priv);
2309 return ret;
2310 }
2311
2312 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2313 {
2314 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2315 struct i915_ggtt_view view;
2316
2317 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2318
2319 intel_fill_fb_ggtt_view(&view, fb, rotation);
2320
2321 if (view.type == I915_GGTT_VIEW_NORMAL)
2322 i915_gem_object_unpin_fence(obj);
2323
2324 i915_gem_object_unpin_from_display_plane(obj, &view);
2325 }
2326
2327 /*
2328 * Adjust the tile offset by moving the difference into
2329 * the x/y offsets.
2330 *
2331 * Input tile dimensions and pitch must already be
2332 * rotated to match x and y, and in pixel units.
2333 */
2334 static u32 intel_adjust_tile_offset(int *x, int *y,
2335 unsigned int tile_width,
2336 unsigned int tile_height,
2337 unsigned int tile_size,
2338 unsigned int pitch_tiles,
2339 u32 old_offset,
2340 u32 new_offset)
2341 {
2342 unsigned int tiles;
2343
2344 WARN_ON(old_offset & (tile_size - 1));
2345 WARN_ON(new_offset & (tile_size - 1));
2346 WARN_ON(new_offset > old_offset);
2347
2348 tiles = (old_offset - new_offset) / tile_size;
2349
2350 *y += tiles / pitch_tiles * tile_height;
2351 *x += tiles % pitch_tiles * tile_width;
2352
2353 return new_offset;
2354 }
2355
2356 /*
2357 * Computes the linear offset to the base tile and adjusts
2358 * x, y. bytes per pixel is assumed to be a power-of-two.
2359 *
2360 * In the 90/270 rotated case, x and y are assumed
2361 * to be already rotated to match the rotated GTT view, and
2362 * pitch is the tile_height aligned framebuffer height.
2363 */
2364 u32 intel_compute_tile_offset(int *x, int *y,
2365 const struct drm_framebuffer *fb, int plane,
2366 unsigned int pitch,
2367 unsigned int rotation)
2368 {
2369 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2370 uint64_t fb_modifier = fb->modifier[plane];
2371 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2372 u32 offset, offset_aligned, alignment;
2373
2374 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2375 if (alignment)
2376 alignment--;
2377
2378 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2379 unsigned int tile_size, tile_width, tile_height;
2380 unsigned int tile_rows, tiles, pitch_tiles;
2381
2382 tile_size = intel_tile_size(dev_priv);
2383 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2384 fb_modifier, cpp);
2385
2386 if (intel_rotation_90_or_270(rotation)) {
2387 pitch_tiles = pitch / tile_height;
2388 swap(tile_width, tile_height);
2389 } else {
2390 pitch_tiles = pitch / (tile_width * cpp);
2391 }
2392
2393 tile_rows = *y / tile_height;
2394 *y %= tile_height;
2395
2396 tiles = *x / tile_width;
2397 *x %= tile_width;
2398
2399 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2400 offset_aligned = offset & ~alignment;
2401
2402 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2403 tile_size, pitch_tiles,
2404 offset, offset_aligned);
2405 } else {
2406 offset = *y * pitch + *x * cpp;
2407 offset_aligned = offset & ~alignment;
2408
2409 *y = (offset & alignment) / pitch;
2410 *x = ((offset & alignment) - *y * pitch) / cpp;
2411 }
2412
2413 return offset_aligned;
2414 }
2415
2416 static int i9xx_format_to_fourcc(int format)
2417 {
2418 switch (format) {
2419 case DISPPLANE_8BPP:
2420 return DRM_FORMAT_C8;
2421 case DISPPLANE_BGRX555:
2422 return DRM_FORMAT_XRGB1555;
2423 case DISPPLANE_BGRX565:
2424 return DRM_FORMAT_RGB565;
2425 default:
2426 case DISPPLANE_BGRX888:
2427 return DRM_FORMAT_XRGB8888;
2428 case DISPPLANE_RGBX888:
2429 return DRM_FORMAT_XBGR8888;
2430 case DISPPLANE_BGRX101010:
2431 return DRM_FORMAT_XRGB2101010;
2432 case DISPPLANE_RGBX101010:
2433 return DRM_FORMAT_XBGR2101010;
2434 }
2435 }
2436
2437 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2438 {
2439 switch (format) {
2440 case PLANE_CTL_FORMAT_RGB_565:
2441 return DRM_FORMAT_RGB565;
2442 default:
2443 case PLANE_CTL_FORMAT_XRGB_8888:
2444 if (rgb_order) {
2445 if (alpha)
2446 return DRM_FORMAT_ABGR8888;
2447 else
2448 return DRM_FORMAT_XBGR8888;
2449 } else {
2450 if (alpha)
2451 return DRM_FORMAT_ARGB8888;
2452 else
2453 return DRM_FORMAT_XRGB8888;
2454 }
2455 case PLANE_CTL_FORMAT_XRGB_2101010:
2456 if (rgb_order)
2457 return DRM_FORMAT_XBGR2101010;
2458 else
2459 return DRM_FORMAT_XRGB2101010;
2460 }
2461 }
2462
2463 static bool
2464 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2465 struct intel_initial_plane_config *plane_config)
2466 {
2467 struct drm_device *dev = crtc->base.dev;
2468 struct drm_i915_private *dev_priv = to_i915(dev);
2469 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2470 struct drm_i915_gem_object *obj = NULL;
2471 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2472 struct drm_framebuffer *fb = &plane_config->fb->base;
2473 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2474 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2475 PAGE_SIZE);
2476
2477 size_aligned -= base_aligned;
2478
2479 if (plane_config->size == 0)
2480 return false;
2481
2482 /* If the FB is too big, just don't use it since fbdev is not very
2483 * important and we should probably use that space with FBC or other
2484 * features. */
2485 if (size_aligned * 2 > ggtt->stolen_usable_size)
2486 return false;
2487
2488 mutex_lock(&dev->struct_mutex);
2489
2490 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2491 base_aligned,
2492 base_aligned,
2493 size_aligned);
2494 if (!obj) {
2495 mutex_unlock(&dev->struct_mutex);
2496 return false;
2497 }
2498
2499 obj->tiling_mode = plane_config->tiling;
2500 if (obj->tiling_mode == I915_TILING_X)
2501 obj->stride = fb->pitches[0];
2502
2503 mode_cmd.pixel_format = fb->pixel_format;
2504 mode_cmd.width = fb->width;
2505 mode_cmd.height = fb->height;
2506 mode_cmd.pitches[0] = fb->pitches[0];
2507 mode_cmd.modifier[0] = fb->modifier[0];
2508 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2509
2510 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2511 &mode_cmd, obj)) {
2512 DRM_DEBUG_KMS("intel fb init failed\n");
2513 goto out_unref_obj;
2514 }
2515
2516 mutex_unlock(&dev->struct_mutex);
2517
2518 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2519 return true;
2520
2521 out_unref_obj:
2522 drm_gem_object_unreference(&obj->base);
2523 mutex_unlock(&dev->struct_mutex);
2524 return false;
2525 }
2526
2527 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2528 static void
2529 update_state_fb(struct drm_plane *plane)
2530 {
2531 if (plane->fb == plane->state->fb)
2532 return;
2533
2534 if (plane->state->fb)
2535 drm_framebuffer_unreference(plane->state->fb);
2536 plane->state->fb = plane->fb;
2537 if (plane->state->fb)
2538 drm_framebuffer_reference(plane->state->fb);
2539 }
2540
2541 static void
2542 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2543 struct intel_initial_plane_config *plane_config)
2544 {
2545 struct drm_device *dev = intel_crtc->base.dev;
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 struct drm_crtc *c;
2548 struct intel_crtc *i;
2549 struct drm_i915_gem_object *obj;
2550 struct drm_plane *primary = intel_crtc->base.primary;
2551 struct drm_plane_state *plane_state = primary->state;
2552 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2553 struct intel_plane *intel_plane = to_intel_plane(primary);
2554 struct intel_plane_state *intel_state =
2555 to_intel_plane_state(plane_state);
2556 struct drm_framebuffer *fb;
2557
2558 if (!plane_config->fb)
2559 return;
2560
2561 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2562 fb = &plane_config->fb->base;
2563 goto valid_fb;
2564 }
2565
2566 kfree(plane_config->fb);
2567
2568 /*
2569 * Failed to alloc the obj, check to see if we should share
2570 * an fb with another CRTC instead
2571 */
2572 for_each_crtc(dev, c) {
2573 i = to_intel_crtc(c);
2574
2575 if (c == &intel_crtc->base)
2576 continue;
2577
2578 if (!i->active)
2579 continue;
2580
2581 fb = c->primary->fb;
2582 if (!fb)
2583 continue;
2584
2585 obj = intel_fb_obj(fb);
2586 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2587 drm_framebuffer_reference(fb);
2588 goto valid_fb;
2589 }
2590 }
2591
2592 /*
2593 * We've failed to reconstruct the BIOS FB. Current display state
2594 * indicates that the primary plane is visible, but has a NULL FB,
2595 * which will lead to problems later if we don't fix it up. The
2596 * simplest solution is to just disable the primary plane now and
2597 * pretend the BIOS never had it enabled.
2598 */
2599 to_intel_plane_state(plane_state)->visible = false;
2600 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2601 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2602 intel_plane->disable_plane(primary, &intel_crtc->base);
2603
2604 return;
2605
2606 valid_fb:
2607 plane_state->src_x = 0;
2608 plane_state->src_y = 0;
2609 plane_state->src_w = fb->width << 16;
2610 plane_state->src_h = fb->height << 16;
2611
2612 plane_state->crtc_x = 0;
2613 plane_state->crtc_y = 0;
2614 plane_state->crtc_w = fb->width;
2615 plane_state->crtc_h = fb->height;
2616
2617 intel_state->src.x1 = plane_state->src_x;
2618 intel_state->src.y1 = plane_state->src_y;
2619 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2620 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2621 intel_state->dst.x1 = plane_state->crtc_x;
2622 intel_state->dst.y1 = plane_state->crtc_y;
2623 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2624 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2625
2626 obj = intel_fb_obj(fb);
2627 if (obj->tiling_mode != I915_TILING_NONE)
2628 dev_priv->preserve_bios_swizzle = true;
2629
2630 drm_framebuffer_reference(fb);
2631 primary->fb = primary->state->fb = fb;
2632 primary->crtc = primary->state->crtc = &intel_crtc->base;
2633 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2634 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2635 }
2636
2637 static void i9xx_update_primary_plane(struct drm_plane *primary,
2638 const struct intel_crtc_state *crtc_state,
2639 const struct intel_plane_state *plane_state)
2640 {
2641 struct drm_device *dev = primary->dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2644 struct drm_framebuffer *fb = plane_state->base.fb;
2645 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2646 int plane = intel_crtc->plane;
2647 u32 linear_offset;
2648 u32 dspcntr;
2649 i915_reg_t reg = DSPCNTR(plane);
2650 unsigned int rotation = plane_state->base.rotation;
2651 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2652 int x = plane_state->src.x1 >> 16;
2653 int y = plane_state->src.y1 >> 16;
2654
2655 dspcntr = DISPPLANE_GAMMA_ENABLE;
2656
2657 dspcntr |= DISPLAY_PLANE_ENABLE;
2658
2659 if (INTEL_INFO(dev)->gen < 4) {
2660 if (intel_crtc->pipe == PIPE_B)
2661 dspcntr |= DISPPLANE_SEL_PIPE_B;
2662
2663 /* pipesrc and dspsize control the size that is scaled from,
2664 * which should always be the user's requested size.
2665 */
2666 I915_WRITE(DSPSIZE(plane),
2667 ((crtc_state->pipe_src_h - 1) << 16) |
2668 (crtc_state->pipe_src_w - 1));
2669 I915_WRITE(DSPPOS(plane), 0);
2670 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2671 I915_WRITE(PRIMSIZE(plane),
2672 ((crtc_state->pipe_src_h - 1) << 16) |
2673 (crtc_state->pipe_src_w - 1));
2674 I915_WRITE(PRIMPOS(plane), 0);
2675 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2676 }
2677
2678 switch (fb->pixel_format) {
2679 case DRM_FORMAT_C8:
2680 dspcntr |= DISPPLANE_8BPP;
2681 break;
2682 case DRM_FORMAT_XRGB1555:
2683 dspcntr |= DISPPLANE_BGRX555;
2684 break;
2685 case DRM_FORMAT_RGB565:
2686 dspcntr |= DISPPLANE_BGRX565;
2687 break;
2688 case DRM_FORMAT_XRGB8888:
2689 dspcntr |= DISPPLANE_BGRX888;
2690 break;
2691 case DRM_FORMAT_XBGR8888:
2692 dspcntr |= DISPPLANE_RGBX888;
2693 break;
2694 case DRM_FORMAT_XRGB2101010:
2695 dspcntr |= DISPPLANE_BGRX101010;
2696 break;
2697 case DRM_FORMAT_XBGR2101010:
2698 dspcntr |= DISPPLANE_RGBX101010;
2699 break;
2700 default:
2701 BUG();
2702 }
2703
2704 if (INTEL_INFO(dev)->gen >= 4 &&
2705 obj->tiling_mode != I915_TILING_NONE)
2706 dspcntr |= DISPPLANE_TILED;
2707
2708 if (IS_G4X(dev))
2709 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2710
2711 linear_offset = y * fb->pitches[0] + x * cpp;
2712
2713 if (INTEL_INFO(dev)->gen >= 4) {
2714 intel_crtc->dspaddr_offset =
2715 intel_compute_tile_offset(&x, &y, fb, 0,
2716 fb->pitches[0], rotation);
2717 linear_offset -= intel_crtc->dspaddr_offset;
2718 } else {
2719 intel_crtc->dspaddr_offset = linear_offset;
2720 }
2721
2722 if (rotation == BIT(DRM_ROTATE_180)) {
2723 dspcntr |= DISPPLANE_ROTATE_180;
2724
2725 x += (crtc_state->pipe_src_w - 1);
2726 y += (crtc_state->pipe_src_h - 1);
2727
2728 /* Finding the last pixel of the last line of the display
2729 data and adding to linear_offset*/
2730 linear_offset +=
2731 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2732 (crtc_state->pipe_src_w - 1) * cpp;
2733 }
2734
2735 intel_crtc->adjusted_x = x;
2736 intel_crtc->adjusted_y = y;
2737
2738 I915_WRITE(reg, dspcntr);
2739
2740 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2741 if (INTEL_INFO(dev)->gen >= 4) {
2742 I915_WRITE(DSPSURF(plane),
2743 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2744 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2745 I915_WRITE(DSPLINOFF(plane), linear_offset);
2746 } else
2747 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2748 POSTING_READ(reg);
2749 }
2750
2751 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2752 struct drm_crtc *crtc)
2753 {
2754 struct drm_device *dev = crtc->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2757 int plane = intel_crtc->plane;
2758
2759 I915_WRITE(DSPCNTR(plane), 0);
2760 if (INTEL_INFO(dev_priv)->gen >= 4)
2761 I915_WRITE(DSPSURF(plane), 0);
2762 else
2763 I915_WRITE(DSPADDR(plane), 0);
2764 POSTING_READ(DSPCNTR(plane));
2765 }
2766
2767 static void ironlake_update_primary_plane(struct drm_plane *primary,
2768 const struct intel_crtc_state *crtc_state,
2769 const struct intel_plane_state *plane_state)
2770 {
2771 struct drm_device *dev = primary->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2774 struct drm_framebuffer *fb = plane_state->base.fb;
2775 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2776 int plane = intel_crtc->plane;
2777 u32 linear_offset;
2778 u32 dspcntr;
2779 i915_reg_t reg = DSPCNTR(plane);
2780 unsigned int rotation = plane_state->base.rotation;
2781 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2782 int x = plane_state->src.x1 >> 16;
2783 int y = plane_state->src.y1 >> 16;
2784
2785 dspcntr = DISPPLANE_GAMMA_ENABLE;
2786 dspcntr |= DISPLAY_PLANE_ENABLE;
2787
2788 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2789 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2790
2791 switch (fb->pixel_format) {
2792 case DRM_FORMAT_C8:
2793 dspcntr |= DISPPLANE_8BPP;
2794 break;
2795 case DRM_FORMAT_RGB565:
2796 dspcntr |= DISPPLANE_BGRX565;
2797 break;
2798 case DRM_FORMAT_XRGB8888:
2799 dspcntr |= DISPPLANE_BGRX888;
2800 break;
2801 case DRM_FORMAT_XBGR8888:
2802 dspcntr |= DISPPLANE_RGBX888;
2803 break;
2804 case DRM_FORMAT_XRGB2101010:
2805 dspcntr |= DISPPLANE_BGRX101010;
2806 break;
2807 case DRM_FORMAT_XBGR2101010:
2808 dspcntr |= DISPPLANE_RGBX101010;
2809 break;
2810 default:
2811 BUG();
2812 }
2813
2814 if (obj->tiling_mode != I915_TILING_NONE)
2815 dspcntr |= DISPPLANE_TILED;
2816
2817 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2818 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2819
2820 linear_offset = y * fb->pitches[0] + x * cpp;
2821 intel_crtc->dspaddr_offset =
2822 intel_compute_tile_offset(&x, &y, fb, 0,
2823 fb->pitches[0], rotation);
2824 linear_offset -= intel_crtc->dspaddr_offset;
2825 if (rotation == BIT(DRM_ROTATE_180)) {
2826 dspcntr |= DISPPLANE_ROTATE_180;
2827
2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2829 x += (crtc_state->pipe_src_w - 1);
2830 y += (crtc_state->pipe_src_h - 1);
2831
2832 /* Finding the last pixel of the last line of the display
2833 data and adding to linear_offset*/
2834 linear_offset +=
2835 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2836 (crtc_state->pipe_src_w - 1) * cpp;
2837 }
2838 }
2839
2840 intel_crtc->adjusted_x = x;
2841 intel_crtc->adjusted_y = y;
2842
2843 I915_WRITE(reg, dspcntr);
2844
2845 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2846 I915_WRITE(DSPSURF(plane),
2847 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2848 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2849 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2850 } else {
2851 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2852 I915_WRITE(DSPLINOFF(plane), linear_offset);
2853 }
2854 POSTING_READ(reg);
2855 }
2856
2857 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2858 uint64_t fb_modifier, uint32_t pixel_format)
2859 {
2860 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2861 return 64;
2862 } else {
2863 int cpp = drm_format_plane_cpp(pixel_format, 0);
2864
2865 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2866 }
2867 }
2868
2869 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2870 struct drm_i915_gem_object *obj,
2871 unsigned int plane)
2872 {
2873 struct i915_ggtt_view view;
2874 struct i915_vma *vma;
2875 u64 offset;
2876
2877 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2878 intel_plane->base.state->rotation);
2879
2880 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2881 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2882 view.type))
2883 return -1;
2884
2885 offset = vma->node.start;
2886
2887 if (plane == 1) {
2888 offset += vma->ggtt_view.params.rotated.uv_start_page *
2889 PAGE_SIZE;
2890 }
2891
2892 WARN_ON(upper_32_bits(offset));
2893
2894 return lower_32_bits(offset);
2895 }
2896
2897 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2898 {
2899 struct drm_device *dev = intel_crtc->base.dev;
2900 struct drm_i915_private *dev_priv = dev->dev_private;
2901
2902 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2903 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2904 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2905 }
2906
2907 /*
2908 * This function detaches (aka. unbinds) unused scalers in hardware
2909 */
2910 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2911 {
2912 struct intel_crtc_scaler_state *scaler_state;
2913 int i;
2914
2915 scaler_state = &intel_crtc->config->scaler_state;
2916
2917 /* loop through and disable scalers that aren't in use */
2918 for (i = 0; i < intel_crtc->num_scalers; i++) {
2919 if (!scaler_state->scalers[i].in_use)
2920 skl_detach_scaler(intel_crtc, i);
2921 }
2922 }
2923
2924 u32 skl_plane_ctl_format(uint32_t pixel_format)
2925 {
2926 switch (pixel_format) {
2927 case DRM_FORMAT_C8:
2928 return PLANE_CTL_FORMAT_INDEXED;
2929 case DRM_FORMAT_RGB565:
2930 return PLANE_CTL_FORMAT_RGB_565;
2931 case DRM_FORMAT_XBGR8888:
2932 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2933 case DRM_FORMAT_XRGB8888:
2934 return PLANE_CTL_FORMAT_XRGB_8888;
2935 /*
2936 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2937 * to be already pre-multiplied. We need to add a knob (or a different
2938 * DRM_FORMAT) for user-space to configure that.
2939 */
2940 case DRM_FORMAT_ABGR8888:
2941 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2942 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2943 case DRM_FORMAT_ARGB8888:
2944 return PLANE_CTL_FORMAT_XRGB_8888 |
2945 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946 case DRM_FORMAT_XRGB2101010:
2947 return PLANE_CTL_FORMAT_XRGB_2101010;
2948 case DRM_FORMAT_XBGR2101010:
2949 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2950 case DRM_FORMAT_YUYV:
2951 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2952 case DRM_FORMAT_YVYU:
2953 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2954 case DRM_FORMAT_UYVY:
2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2956 case DRM_FORMAT_VYUY:
2957 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2958 default:
2959 MISSING_CASE(pixel_format);
2960 }
2961
2962 return 0;
2963 }
2964
2965 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2966 {
2967 switch (fb_modifier) {
2968 case DRM_FORMAT_MOD_NONE:
2969 break;
2970 case I915_FORMAT_MOD_X_TILED:
2971 return PLANE_CTL_TILED_X;
2972 case I915_FORMAT_MOD_Y_TILED:
2973 return PLANE_CTL_TILED_Y;
2974 case I915_FORMAT_MOD_Yf_TILED:
2975 return PLANE_CTL_TILED_YF;
2976 default:
2977 MISSING_CASE(fb_modifier);
2978 }
2979
2980 return 0;
2981 }
2982
2983 u32 skl_plane_ctl_rotation(unsigned int rotation)
2984 {
2985 switch (rotation) {
2986 case BIT(DRM_ROTATE_0):
2987 break;
2988 /*
2989 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2990 * while i915 HW rotation is clockwise, thats why this swapping.
2991 */
2992 case BIT(DRM_ROTATE_90):
2993 return PLANE_CTL_ROTATE_270;
2994 case BIT(DRM_ROTATE_180):
2995 return PLANE_CTL_ROTATE_180;
2996 case BIT(DRM_ROTATE_270):
2997 return PLANE_CTL_ROTATE_90;
2998 default:
2999 MISSING_CASE(rotation);
3000 }
3001
3002 return 0;
3003 }
3004
3005 static void skylake_update_primary_plane(struct drm_plane *plane,
3006 const struct intel_crtc_state *crtc_state,
3007 const struct intel_plane_state *plane_state)
3008 {
3009 struct drm_device *dev = plane->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3012 struct drm_framebuffer *fb = plane_state->base.fb;
3013 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3014 int pipe = intel_crtc->pipe;
3015 u32 plane_ctl, stride_div, stride;
3016 u32 tile_height, plane_offset, plane_size;
3017 unsigned int rotation = plane_state->base.rotation;
3018 int x_offset, y_offset;
3019 u32 surf_addr;
3020 int scaler_id = plane_state->scaler_id;
3021 int src_x = plane_state->src.x1 >> 16;
3022 int src_y = plane_state->src.y1 >> 16;
3023 int src_w = drm_rect_width(&plane_state->src) >> 16;
3024 int src_h = drm_rect_height(&plane_state->src) >> 16;
3025 int dst_x = plane_state->dst.x1;
3026 int dst_y = plane_state->dst.y1;
3027 int dst_w = drm_rect_width(&plane_state->dst);
3028 int dst_h = drm_rect_height(&plane_state->dst);
3029
3030 plane_ctl = PLANE_CTL_ENABLE |
3031 PLANE_CTL_PIPE_GAMMA_ENABLE |
3032 PLANE_CTL_PIPE_CSC_ENABLE;
3033
3034 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3035 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3036 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3037 plane_ctl |= skl_plane_ctl_rotation(rotation);
3038
3039 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3040 fb->pixel_format);
3041 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3042
3043 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3044
3045 if (intel_rotation_90_or_270(rotation)) {
3046 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3047
3048 /* stride = Surface height in tiles */
3049 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3050 stride = DIV_ROUND_UP(fb->height, tile_height);
3051 x_offset = stride * tile_height - src_y - src_h;
3052 y_offset = src_x;
3053 plane_size = (src_w - 1) << 16 | (src_h - 1);
3054 } else {
3055 stride = fb->pitches[0] / stride_div;
3056 x_offset = src_x;
3057 y_offset = src_y;
3058 plane_size = (src_h - 1) << 16 | (src_w - 1);
3059 }
3060 plane_offset = y_offset << 16 | x_offset;
3061
3062 intel_crtc->adjusted_x = x_offset;
3063 intel_crtc->adjusted_y = y_offset;
3064
3065 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3066 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3067 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3068 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3069
3070 if (scaler_id >= 0) {
3071 uint32_t ps_ctrl = 0;
3072
3073 WARN_ON(!dst_w || !dst_h);
3074 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3075 crtc_state->scaler_state.scalers[scaler_id].mode;
3076 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3077 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3078 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3079 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3080 I915_WRITE(PLANE_POS(pipe, 0), 0);
3081 } else {
3082 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3083 }
3084
3085 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3086
3087 POSTING_READ(PLANE_SURF(pipe, 0));
3088 }
3089
3090 static void skylake_disable_primary_plane(struct drm_plane *primary,
3091 struct drm_crtc *crtc)
3092 {
3093 struct drm_device *dev = crtc->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095 int pipe = to_intel_crtc(crtc)->pipe;
3096
3097 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3098 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3099 POSTING_READ(PLANE_SURF(pipe, 0));
3100 }
3101
3102 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3103 static int
3104 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3105 int x, int y, enum mode_set_atomic state)
3106 {
3107 /* Support for kgdboc is disabled, this needs a major rework. */
3108 DRM_ERROR("legacy panic handler not supported any more.\n");
3109
3110 return -ENODEV;
3111 }
3112
3113 static void intel_complete_page_flips(struct drm_device *dev)
3114 {
3115 struct drm_crtc *crtc;
3116
3117 for_each_crtc(dev, crtc) {
3118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119 enum plane plane = intel_crtc->plane;
3120
3121 intel_prepare_page_flip(dev, plane);
3122 intel_finish_page_flip_plane(dev, plane);
3123 }
3124 }
3125
3126 static void intel_update_primary_planes(struct drm_device *dev)
3127 {
3128 struct drm_crtc *crtc;
3129
3130 for_each_crtc(dev, crtc) {
3131 struct intel_plane *plane = to_intel_plane(crtc->primary);
3132 struct intel_plane_state *plane_state;
3133
3134 drm_modeset_lock_crtc(crtc, &plane->base);
3135 plane_state = to_intel_plane_state(plane->base.state);
3136
3137 if (plane_state->visible)
3138 plane->update_plane(&plane->base,
3139 to_intel_crtc_state(crtc->state),
3140 plane_state);
3141
3142 drm_modeset_unlock_crtc(crtc);
3143 }
3144 }
3145
3146 void intel_prepare_reset(struct drm_device *dev)
3147 {
3148 /* no reset support for gen2 */
3149 if (IS_GEN2(dev))
3150 return;
3151
3152 /* reset doesn't touch the display */
3153 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3154 return;
3155
3156 drm_modeset_lock_all(dev);
3157 /*
3158 * Disabling the crtcs gracefully seems nicer. Also the
3159 * g33 docs say we should at least disable all the planes.
3160 */
3161 intel_display_suspend(dev);
3162 }
3163
3164 void intel_finish_reset(struct drm_device *dev)
3165 {
3166 struct drm_i915_private *dev_priv = to_i915(dev);
3167
3168 /*
3169 * Flips in the rings will be nuked by the reset,
3170 * so complete all pending flips so that user space
3171 * will get its events and not get stuck.
3172 */
3173 intel_complete_page_flips(dev);
3174
3175 /* no reset support for gen2 */
3176 if (IS_GEN2(dev))
3177 return;
3178
3179 /* reset doesn't touch the display */
3180 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3181 /*
3182 * Flips in the rings have been nuked by the reset,
3183 * so update the base address of all primary
3184 * planes to the the last fb to make sure we're
3185 * showing the correct fb after a reset.
3186 *
3187 * FIXME: Atomic will make this obsolete since we won't schedule
3188 * CS-based flips (which might get lost in gpu resets) any more.
3189 */
3190 intel_update_primary_planes(dev);
3191 return;
3192 }
3193
3194 /*
3195 * The display has been reset as well,
3196 * so need a full re-initialization.
3197 */
3198 intel_runtime_pm_disable_interrupts(dev_priv);
3199 intel_runtime_pm_enable_interrupts(dev_priv);
3200
3201 intel_modeset_init_hw(dev);
3202
3203 spin_lock_irq(&dev_priv->irq_lock);
3204 if (dev_priv->display.hpd_irq_setup)
3205 dev_priv->display.hpd_irq_setup(dev);
3206 spin_unlock_irq(&dev_priv->irq_lock);
3207
3208 intel_display_resume(dev);
3209
3210 intel_hpd_init(dev_priv);
3211
3212 drm_modeset_unlock_all(dev);
3213 }
3214
3215 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3216 {
3217 struct drm_device *dev = crtc->dev;
3218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3219 unsigned reset_counter;
3220 bool pending;
3221
3222 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3223 if (intel_crtc->reset_counter != reset_counter)
3224 return false;
3225
3226 spin_lock_irq(&dev->event_lock);
3227 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3228 spin_unlock_irq(&dev->event_lock);
3229
3230 return pending;
3231 }
3232
3233 static void intel_update_pipe_config(struct intel_crtc *crtc,
3234 struct intel_crtc_state *old_crtc_state)
3235 {
3236 struct drm_device *dev = crtc->base.dev;
3237 struct drm_i915_private *dev_priv = dev->dev_private;
3238 struct intel_crtc_state *pipe_config =
3239 to_intel_crtc_state(crtc->base.state);
3240
3241 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3242 crtc->base.mode = crtc->base.state->mode;
3243
3244 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3245 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3246 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3247
3248 /*
3249 * Update pipe size and adjust fitter if needed: the reason for this is
3250 * that in compute_mode_changes we check the native mode (not the pfit
3251 * mode) to see if we can flip rather than do a full mode set. In the
3252 * fastboot case, we'll flip, but if we don't update the pipesrc and
3253 * pfit state, we'll end up with a big fb scanned out into the wrong
3254 * sized surface.
3255 */
3256
3257 I915_WRITE(PIPESRC(crtc->pipe),
3258 ((pipe_config->pipe_src_w - 1) << 16) |
3259 (pipe_config->pipe_src_h - 1));
3260
3261 /* on skylake this is done by detaching scalers */
3262 if (INTEL_INFO(dev)->gen >= 9) {
3263 skl_detach_scalers(crtc);
3264
3265 if (pipe_config->pch_pfit.enabled)
3266 skylake_pfit_enable(crtc);
3267 } else if (HAS_PCH_SPLIT(dev)) {
3268 if (pipe_config->pch_pfit.enabled)
3269 ironlake_pfit_enable(crtc);
3270 else if (old_crtc_state->pch_pfit.enabled)
3271 ironlake_pfit_disable(crtc, true);
3272 }
3273 }
3274
3275 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3276 {
3277 struct drm_device *dev = crtc->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280 int pipe = intel_crtc->pipe;
3281 i915_reg_t reg;
3282 u32 temp;
3283
3284 /* enable normal train */
3285 reg = FDI_TX_CTL(pipe);
3286 temp = I915_READ(reg);
3287 if (IS_IVYBRIDGE(dev)) {
3288 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3289 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3290 } else {
3291 temp &= ~FDI_LINK_TRAIN_NONE;
3292 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3293 }
3294 I915_WRITE(reg, temp);
3295
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 if (HAS_PCH_CPT(dev)) {
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3301 } else {
3302 temp &= ~FDI_LINK_TRAIN_NONE;
3303 temp |= FDI_LINK_TRAIN_NONE;
3304 }
3305 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3306
3307 /* wait one idle pattern time */
3308 POSTING_READ(reg);
3309 udelay(1000);
3310
3311 /* IVB wants error correction enabled */
3312 if (IS_IVYBRIDGE(dev))
3313 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3314 FDI_FE_ERRC_ENABLE);
3315 }
3316
3317 /* The FDI link training functions for ILK/Ibexpeak. */
3318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3319 {
3320 struct drm_device *dev = crtc->dev;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 int pipe = intel_crtc->pipe;
3324 i915_reg_t reg;
3325 u32 temp, tries;
3326
3327 /* FDI needs bits from pipe first */
3328 assert_pipe_enabled(dev_priv, pipe);
3329
3330 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3331 for train result */
3332 reg = FDI_RX_IMR(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_RX_SYMBOL_LOCK;
3335 temp &= ~FDI_RX_BIT_LOCK;
3336 I915_WRITE(reg, temp);
3337 I915_READ(reg);
3338 udelay(150);
3339
3340 /* enable CPU FDI TX and PCH FDI RX */
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3344 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_PATTERN_1;
3347 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3348
3349 reg = FDI_RX_CTL(pipe);
3350 temp = I915_READ(reg);
3351 temp &= ~FDI_LINK_TRAIN_NONE;
3352 temp |= FDI_LINK_TRAIN_PATTERN_1;
3353 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3354
3355 POSTING_READ(reg);
3356 udelay(150);
3357
3358 /* Ironlake workaround, enable clock pointer after FDI enable*/
3359 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3360 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3361 FDI_RX_PHASE_SYNC_POINTER_EN);
3362
3363 reg = FDI_RX_IIR(pipe);
3364 for (tries = 0; tries < 5; tries++) {
3365 temp = I915_READ(reg);
3366 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3367
3368 if ((temp & FDI_RX_BIT_LOCK)) {
3369 DRM_DEBUG_KMS("FDI train 1 done.\n");
3370 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3371 break;
3372 }
3373 }
3374 if (tries == 5)
3375 DRM_ERROR("FDI train 1 fail!\n");
3376
3377 /* Train 2 */
3378 reg = FDI_TX_CTL(pipe);
3379 temp = I915_READ(reg);
3380 temp &= ~FDI_LINK_TRAIN_NONE;
3381 temp |= FDI_LINK_TRAIN_PATTERN_2;
3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 temp &= ~FDI_LINK_TRAIN_NONE;
3387 temp |= FDI_LINK_TRAIN_PATTERN_2;
3388 I915_WRITE(reg, temp);
3389
3390 POSTING_READ(reg);
3391 udelay(150);
3392
3393 reg = FDI_RX_IIR(pipe);
3394 for (tries = 0; tries < 5; tries++) {
3395 temp = I915_READ(reg);
3396 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3397
3398 if (temp & FDI_RX_SYMBOL_LOCK) {
3399 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3400 DRM_DEBUG_KMS("FDI train 2 done.\n");
3401 break;
3402 }
3403 }
3404 if (tries == 5)
3405 DRM_ERROR("FDI train 2 fail!\n");
3406
3407 DRM_DEBUG_KMS("FDI train done\n");
3408
3409 }
3410
3411 static const int snb_b_fdi_train_param[] = {
3412 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3413 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3414 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3415 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3416 };
3417
3418 /* The FDI link training functions for SNB/Cougarpoint. */
3419 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3420 {
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424 int pipe = intel_crtc->pipe;
3425 i915_reg_t reg;
3426 u32 temp, i, retry;
3427
3428 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3429 for train result */
3430 reg = FDI_RX_IMR(pipe);
3431 temp = I915_READ(reg);
3432 temp &= ~FDI_RX_SYMBOL_LOCK;
3433 temp &= ~FDI_RX_BIT_LOCK;
3434 I915_WRITE(reg, temp);
3435
3436 POSTING_READ(reg);
3437 udelay(150);
3438
3439 /* enable CPU FDI TX and PCH FDI RX */
3440 reg = FDI_TX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3443 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_1;
3446 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3447 /* SNB-B */
3448 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3449 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3450
3451 I915_WRITE(FDI_RX_MISC(pipe),
3452 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3453
3454 reg = FDI_RX_CTL(pipe);
3455 temp = I915_READ(reg);
3456 if (HAS_PCH_CPT(dev)) {
3457 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3459 } else {
3460 temp &= ~FDI_LINK_TRAIN_NONE;
3461 temp |= FDI_LINK_TRAIN_PATTERN_1;
3462 }
3463 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3464
3465 POSTING_READ(reg);
3466 udelay(150);
3467
3468 for (i = 0; i < 4; i++) {
3469 reg = FDI_TX_CTL(pipe);
3470 temp = I915_READ(reg);
3471 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3472 temp |= snb_b_fdi_train_param[i];
3473 I915_WRITE(reg, temp);
3474
3475 POSTING_READ(reg);
3476 udelay(500);
3477
3478 for (retry = 0; retry < 5; retry++) {
3479 reg = FDI_RX_IIR(pipe);
3480 temp = I915_READ(reg);
3481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3482 if (temp & FDI_RX_BIT_LOCK) {
3483 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3484 DRM_DEBUG_KMS("FDI train 1 done.\n");
3485 break;
3486 }
3487 udelay(50);
3488 }
3489 if (retry < 5)
3490 break;
3491 }
3492 if (i == 4)
3493 DRM_ERROR("FDI train 1 fail!\n");
3494
3495 /* Train 2 */
3496 reg = FDI_TX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_2;
3500 if (IS_GEN6(dev)) {
3501 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3502 /* SNB-B */
3503 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3504 }
3505 I915_WRITE(reg, temp);
3506
3507 reg = FDI_RX_CTL(pipe);
3508 temp = I915_READ(reg);
3509 if (HAS_PCH_CPT(dev)) {
3510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3511 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3512 } else {
3513 temp &= ~FDI_LINK_TRAIN_NONE;
3514 temp |= FDI_LINK_TRAIN_PATTERN_2;
3515 }
3516 I915_WRITE(reg, temp);
3517
3518 POSTING_READ(reg);
3519 udelay(150);
3520
3521 for (i = 0; i < 4; i++) {
3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3525 temp |= snb_b_fdi_train_param[i];
3526 I915_WRITE(reg, temp);
3527
3528 POSTING_READ(reg);
3529 udelay(500);
3530
3531 for (retry = 0; retry < 5; retry++) {
3532 reg = FDI_RX_IIR(pipe);
3533 temp = I915_READ(reg);
3534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3535 if (temp & FDI_RX_SYMBOL_LOCK) {
3536 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3537 DRM_DEBUG_KMS("FDI train 2 done.\n");
3538 break;
3539 }
3540 udelay(50);
3541 }
3542 if (retry < 5)
3543 break;
3544 }
3545 if (i == 4)
3546 DRM_ERROR("FDI train 2 fail!\n");
3547
3548 DRM_DEBUG_KMS("FDI train done.\n");
3549 }
3550
3551 /* Manual link training for Ivy Bridge A0 parts */
3552 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3553 {
3554 struct drm_device *dev = crtc->dev;
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557 int pipe = intel_crtc->pipe;
3558 i915_reg_t reg;
3559 u32 temp, i, j;
3560
3561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3562 for train result */
3563 reg = FDI_RX_IMR(pipe);
3564 temp = I915_READ(reg);
3565 temp &= ~FDI_RX_SYMBOL_LOCK;
3566 temp &= ~FDI_RX_BIT_LOCK;
3567 I915_WRITE(reg, temp);
3568
3569 POSTING_READ(reg);
3570 udelay(150);
3571
3572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3573 I915_READ(FDI_RX_IIR(pipe)));
3574
3575 /* Try each vswing and preemphasis setting twice before moving on */
3576 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3577 /* disable first in case we need to retry */
3578 reg = FDI_TX_CTL(pipe);
3579 temp = I915_READ(reg);
3580 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3581 temp &= ~FDI_TX_ENABLE;
3582 I915_WRITE(reg, temp);
3583
3584 reg = FDI_RX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 temp &= ~FDI_LINK_TRAIN_AUTO;
3587 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3588 temp &= ~FDI_RX_ENABLE;
3589 I915_WRITE(reg, temp);
3590
3591 /* enable CPU FDI TX and PCH FDI RX */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3595 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3596 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598 temp |= snb_b_fdi_train_param[j/2];
3599 temp |= FDI_COMPOSITE_SYNC;
3600 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3601
3602 I915_WRITE(FDI_RX_MISC(pipe),
3603 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3604
3605 reg = FDI_RX_CTL(pipe);
3606 temp = I915_READ(reg);
3607 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3608 temp |= FDI_COMPOSITE_SYNC;
3609 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3610
3611 POSTING_READ(reg);
3612 udelay(1); /* should be 0.5us */
3613
3614 for (i = 0; i < 4; i++) {
3615 reg = FDI_RX_IIR(pipe);
3616 temp = I915_READ(reg);
3617 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3618
3619 if (temp & FDI_RX_BIT_LOCK ||
3620 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3621 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3622 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3623 i);
3624 break;
3625 }
3626 udelay(1); /* should be 0.5us */
3627 }
3628 if (i == 4) {
3629 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3630 continue;
3631 }
3632
3633 /* Train 2 */
3634 reg = FDI_TX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3637 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3638 I915_WRITE(reg, temp);
3639
3640 reg = FDI_RX_CTL(pipe);
3641 temp = I915_READ(reg);
3642 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3643 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3644 I915_WRITE(reg, temp);
3645
3646 POSTING_READ(reg);
3647 udelay(2); /* should be 1.5us */
3648
3649 for (i = 0; i < 4; i++) {
3650 reg = FDI_RX_IIR(pipe);
3651 temp = I915_READ(reg);
3652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3653
3654 if (temp & FDI_RX_SYMBOL_LOCK ||
3655 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3657 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3658 i);
3659 goto train_done;
3660 }
3661 udelay(2); /* should be 1.5us */
3662 }
3663 if (i == 4)
3664 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3665 }
3666
3667 train_done:
3668 DRM_DEBUG_KMS("FDI train done.\n");
3669 }
3670
3671 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3672 {
3673 struct drm_device *dev = intel_crtc->base.dev;
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675 int pipe = intel_crtc->pipe;
3676 i915_reg_t reg;
3677 u32 temp;
3678
3679 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3680 reg = FDI_RX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3683 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3684 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3685 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3686
3687 POSTING_READ(reg);
3688 udelay(200);
3689
3690 /* Switch from Rawclk to PCDclk */
3691 temp = I915_READ(reg);
3692 I915_WRITE(reg, temp | FDI_PCDCLK);
3693
3694 POSTING_READ(reg);
3695 udelay(200);
3696
3697 /* Enable CPU FDI TX PLL, always on for Ironlake */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3701 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3702
3703 POSTING_READ(reg);
3704 udelay(100);
3705 }
3706 }
3707
3708 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3709 {
3710 struct drm_device *dev = intel_crtc->base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3712 int pipe = intel_crtc->pipe;
3713 i915_reg_t reg;
3714 u32 temp;
3715
3716 /* Switch from PCDclk to Rawclk */
3717 reg = FDI_RX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3720
3721 /* Disable CPU FDI TX PLL */
3722 reg = FDI_TX_CTL(pipe);
3723 temp = I915_READ(reg);
3724 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3725
3726 POSTING_READ(reg);
3727 udelay(100);
3728
3729 reg = FDI_RX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3732
3733 /* Wait for the clocks to turn off. */
3734 POSTING_READ(reg);
3735 udelay(100);
3736 }
3737
3738 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3739 {
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
3744 i915_reg_t reg;
3745 u32 temp;
3746
3747 /* disable CPU FDI tx and PCH FDI rx */
3748 reg = FDI_TX_CTL(pipe);
3749 temp = I915_READ(reg);
3750 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3751 POSTING_READ(reg);
3752
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 temp &= ~(0x7 << 16);
3756 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3758
3759 POSTING_READ(reg);
3760 udelay(100);
3761
3762 /* Ironlake workaround, disable clock pointer after downing FDI */
3763 if (HAS_PCH_IBX(dev))
3764 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3765
3766 /* still set train pattern 1 */
3767 reg = FDI_TX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 temp &= ~FDI_LINK_TRAIN_NONE;
3770 temp |= FDI_LINK_TRAIN_PATTERN_1;
3771 I915_WRITE(reg, temp);
3772
3773 reg = FDI_RX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 if (HAS_PCH_CPT(dev)) {
3776 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3777 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3778 } else {
3779 temp &= ~FDI_LINK_TRAIN_NONE;
3780 temp |= FDI_LINK_TRAIN_PATTERN_1;
3781 }
3782 /* BPC in FDI rx is consistent with that in PIPECONF */
3783 temp &= ~(0x07 << 16);
3784 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3785 I915_WRITE(reg, temp);
3786
3787 POSTING_READ(reg);
3788 udelay(100);
3789 }
3790
3791 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3792 {
3793 struct intel_crtc *crtc;
3794
3795 /* Note that we don't need to be called with mode_config.lock here
3796 * as our list of CRTC objects is static for the lifetime of the
3797 * device and so cannot disappear as we iterate. Similarly, we can
3798 * happily treat the predicates as racy, atomic checks as userspace
3799 * cannot claim and pin a new fb without at least acquring the
3800 * struct_mutex and so serialising with us.
3801 */
3802 for_each_intel_crtc(dev, crtc) {
3803 if (atomic_read(&crtc->unpin_work_count) == 0)
3804 continue;
3805
3806 if (crtc->unpin_work)
3807 intel_wait_for_vblank(dev, crtc->pipe);
3808
3809 return true;
3810 }
3811
3812 return false;
3813 }
3814
3815 static void page_flip_completed(struct intel_crtc *intel_crtc)
3816 {
3817 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3818 struct intel_unpin_work *work = intel_crtc->unpin_work;
3819
3820 /* ensure that the unpin work is consistent wrt ->pending. */
3821 smp_rmb();
3822 intel_crtc->unpin_work = NULL;
3823
3824 if (work->event)
3825 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3826
3827 drm_crtc_vblank_put(&intel_crtc->base);
3828
3829 wake_up_all(&dev_priv->pending_flip_queue);
3830 queue_work(dev_priv->wq, &work->work);
3831
3832 trace_i915_flip_complete(intel_crtc->plane,
3833 work->pending_flip_obj);
3834 }
3835
3836 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3837 {
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 long ret;
3841
3842 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3843
3844 ret = wait_event_interruptible_timeout(
3845 dev_priv->pending_flip_queue,
3846 !intel_crtc_has_pending_flip(crtc),
3847 60*HZ);
3848
3849 if (ret < 0)
3850 return ret;
3851
3852 if (ret == 0) {
3853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3854
3855 spin_lock_irq(&dev->event_lock);
3856 if (intel_crtc->unpin_work) {
3857 WARN_ONCE(1, "Removing stuck page flip\n");
3858 page_flip_completed(intel_crtc);
3859 }
3860 spin_unlock_irq(&dev->event_lock);
3861 }
3862
3863 return 0;
3864 }
3865
3866 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3867 {
3868 u32 temp;
3869
3870 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3871
3872 mutex_lock(&dev_priv->sb_lock);
3873
3874 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3875 temp |= SBI_SSCCTL_DISABLE;
3876 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3877
3878 mutex_unlock(&dev_priv->sb_lock);
3879 }
3880
3881 /* Program iCLKIP clock to the desired frequency */
3882 static void lpt_program_iclkip(struct drm_crtc *crtc)
3883 {
3884 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3885 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3886 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3887 u32 temp;
3888
3889 lpt_disable_iclkip(dev_priv);
3890
3891 /* The iCLK virtual clock root frequency is in MHz,
3892 * but the adjusted_mode->crtc_clock in in KHz. To get the
3893 * divisors, it is necessary to divide one by another, so we
3894 * convert the virtual clock precision to KHz here for higher
3895 * precision.
3896 */
3897 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3898 u32 iclk_virtual_root_freq = 172800 * 1000;
3899 u32 iclk_pi_range = 64;
3900 u32 desired_divisor;
3901
3902 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3903 clock << auxdiv);
3904 divsel = (desired_divisor / iclk_pi_range) - 2;
3905 phaseinc = desired_divisor % iclk_pi_range;
3906
3907 /*
3908 * Near 20MHz is a corner case which is
3909 * out of range for the 7-bit divisor
3910 */
3911 if (divsel <= 0x7f)
3912 break;
3913 }
3914
3915 /* This should not happen with any sane values */
3916 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3917 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3918 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3919 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3920
3921 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3922 clock,
3923 auxdiv,
3924 divsel,
3925 phasedir,
3926 phaseinc);
3927
3928 mutex_lock(&dev_priv->sb_lock);
3929
3930 /* Program SSCDIVINTPHASE6 */
3931 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3932 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3933 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3934 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3935 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3936 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3937 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3938 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3939
3940 /* Program SSCAUXDIV */
3941 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3942 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3943 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3944 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3945
3946 /* Enable modulator and associated divider */
3947 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3948 temp &= ~SBI_SSCCTL_DISABLE;
3949 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3950
3951 mutex_unlock(&dev_priv->sb_lock);
3952
3953 /* Wait for initialization time */
3954 udelay(24);
3955
3956 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3957 }
3958
3959 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3960 {
3961 u32 divsel, phaseinc, auxdiv;
3962 u32 iclk_virtual_root_freq = 172800 * 1000;
3963 u32 iclk_pi_range = 64;
3964 u32 desired_divisor;
3965 u32 temp;
3966
3967 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3968 return 0;
3969
3970 mutex_lock(&dev_priv->sb_lock);
3971
3972 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3973 if (temp & SBI_SSCCTL_DISABLE) {
3974 mutex_unlock(&dev_priv->sb_lock);
3975 return 0;
3976 }
3977
3978 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3979 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3980 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3981 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3982 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3983
3984 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3985 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3986 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3987
3988 mutex_unlock(&dev_priv->sb_lock);
3989
3990 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3991
3992 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3993 desired_divisor << auxdiv);
3994 }
3995
3996 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3997 enum pipe pch_transcoder)
3998 {
3999 struct drm_device *dev = crtc->base.dev;
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4002
4003 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4004 I915_READ(HTOTAL(cpu_transcoder)));
4005 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4006 I915_READ(HBLANK(cpu_transcoder)));
4007 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4008 I915_READ(HSYNC(cpu_transcoder)));
4009
4010 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4011 I915_READ(VTOTAL(cpu_transcoder)));
4012 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4013 I915_READ(VBLANK(cpu_transcoder)));
4014 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4015 I915_READ(VSYNC(cpu_transcoder)));
4016 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4017 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4018 }
4019
4020 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4021 {
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 uint32_t temp;
4024
4025 temp = I915_READ(SOUTH_CHICKEN1);
4026 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4027 return;
4028
4029 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4030 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4031
4032 temp &= ~FDI_BC_BIFURCATION_SELECT;
4033 if (enable)
4034 temp |= FDI_BC_BIFURCATION_SELECT;
4035
4036 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4037 I915_WRITE(SOUTH_CHICKEN1, temp);
4038 POSTING_READ(SOUTH_CHICKEN1);
4039 }
4040
4041 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4042 {
4043 struct drm_device *dev = intel_crtc->base.dev;
4044
4045 switch (intel_crtc->pipe) {
4046 case PIPE_A:
4047 break;
4048 case PIPE_B:
4049 if (intel_crtc->config->fdi_lanes > 2)
4050 cpt_set_fdi_bc_bifurcation(dev, false);
4051 else
4052 cpt_set_fdi_bc_bifurcation(dev, true);
4053
4054 break;
4055 case PIPE_C:
4056 cpt_set_fdi_bc_bifurcation(dev, true);
4057
4058 break;
4059 default:
4060 BUG();
4061 }
4062 }
4063
4064 /* Return which DP Port should be selected for Transcoder DP control */
4065 static enum port
4066 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4067 {
4068 struct drm_device *dev = crtc->dev;
4069 struct intel_encoder *encoder;
4070
4071 for_each_encoder_on_crtc(dev, crtc, encoder) {
4072 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4073 encoder->type == INTEL_OUTPUT_EDP)
4074 return enc_to_dig_port(&encoder->base)->port;
4075 }
4076
4077 return -1;
4078 }
4079
4080 /*
4081 * Enable PCH resources required for PCH ports:
4082 * - PCH PLLs
4083 * - FDI training & RX/TX
4084 * - update transcoder timings
4085 * - DP transcoding bits
4086 * - transcoder
4087 */
4088 static void ironlake_pch_enable(struct drm_crtc *crtc)
4089 {
4090 struct drm_device *dev = crtc->dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 int pipe = intel_crtc->pipe;
4094 u32 temp;
4095
4096 assert_pch_transcoder_disabled(dev_priv, pipe);
4097
4098 if (IS_IVYBRIDGE(dev))
4099 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4100
4101 /* Write the TU size bits before fdi link training, so that error
4102 * detection works. */
4103 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4104 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4105
4106 /* For PCH output, training FDI link */
4107 dev_priv->display.fdi_link_train(crtc);
4108
4109 /* We need to program the right clock selection before writing the pixel
4110 * mutliplier into the DPLL. */
4111 if (HAS_PCH_CPT(dev)) {
4112 u32 sel;
4113
4114 temp = I915_READ(PCH_DPLL_SEL);
4115 temp |= TRANS_DPLL_ENABLE(pipe);
4116 sel = TRANS_DPLLB_SEL(pipe);
4117 if (intel_crtc->config->shared_dpll ==
4118 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4119 temp |= sel;
4120 else
4121 temp &= ~sel;
4122 I915_WRITE(PCH_DPLL_SEL, temp);
4123 }
4124
4125 /* XXX: pch pll's can be enabled any time before we enable the PCH
4126 * transcoder, and we actually should do this to not upset any PCH
4127 * transcoder that already use the clock when we share it.
4128 *
4129 * Note that enable_shared_dpll tries to do the right thing, but
4130 * get_shared_dpll unconditionally resets the pll - we need that to have
4131 * the right LVDS enable sequence. */
4132 intel_enable_shared_dpll(intel_crtc);
4133
4134 /* set transcoder timing, panel must allow it */
4135 assert_panel_unlocked(dev_priv, pipe);
4136 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4137
4138 intel_fdi_normal_train(crtc);
4139
4140 /* For PCH DP, enable TRANS_DP_CTL */
4141 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4142 const struct drm_display_mode *adjusted_mode =
4143 &intel_crtc->config->base.adjusted_mode;
4144 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4145 i915_reg_t reg = TRANS_DP_CTL(pipe);
4146 temp = I915_READ(reg);
4147 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4148 TRANS_DP_SYNC_MASK |
4149 TRANS_DP_BPC_MASK);
4150 temp |= TRANS_DP_OUTPUT_ENABLE;
4151 temp |= bpc << 9; /* same format but at 11:9 */
4152
4153 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4154 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4155 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4156 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4157
4158 switch (intel_trans_dp_port_sel(crtc)) {
4159 case PORT_B:
4160 temp |= TRANS_DP_PORT_SEL_B;
4161 break;
4162 case PORT_C:
4163 temp |= TRANS_DP_PORT_SEL_C;
4164 break;
4165 case PORT_D:
4166 temp |= TRANS_DP_PORT_SEL_D;
4167 break;
4168 default:
4169 BUG();
4170 }
4171
4172 I915_WRITE(reg, temp);
4173 }
4174
4175 ironlake_enable_pch_transcoder(dev_priv, pipe);
4176 }
4177
4178 static void lpt_pch_enable(struct drm_crtc *crtc)
4179 {
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4184
4185 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4186
4187 lpt_program_iclkip(crtc);
4188
4189 /* Set transcoder timing. */
4190 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4191
4192 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4193 }
4194
4195 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4196 {
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 i915_reg_t dslreg = PIPEDSL(pipe);
4199 u32 temp;
4200
4201 temp = I915_READ(dslreg);
4202 udelay(500);
4203 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4204 if (wait_for(I915_READ(dslreg) != temp, 5))
4205 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4206 }
4207 }
4208
4209 static int
4210 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4211 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4212 int src_w, int src_h, int dst_w, int dst_h)
4213 {
4214 struct intel_crtc_scaler_state *scaler_state =
4215 &crtc_state->scaler_state;
4216 struct intel_crtc *intel_crtc =
4217 to_intel_crtc(crtc_state->base.crtc);
4218 int need_scaling;
4219
4220 need_scaling = intel_rotation_90_or_270(rotation) ?
4221 (src_h != dst_w || src_w != dst_h):
4222 (src_w != dst_w || src_h != dst_h);
4223
4224 /*
4225 * if plane is being disabled or scaler is no more required or force detach
4226 * - free scaler binded to this plane/crtc
4227 * - in order to do this, update crtc->scaler_usage
4228 *
4229 * Here scaler state in crtc_state is set free so that
4230 * scaler can be assigned to other user. Actual register
4231 * update to free the scaler is done in plane/panel-fit programming.
4232 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4233 */
4234 if (force_detach || !need_scaling) {
4235 if (*scaler_id >= 0) {
4236 scaler_state->scaler_users &= ~(1 << scaler_user);
4237 scaler_state->scalers[*scaler_id].in_use = 0;
4238
4239 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4240 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4241 intel_crtc->pipe, scaler_user, *scaler_id,
4242 scaler_state->scaler_users);
4243 *scaler_id = -1;
4244 }
4245 return 0;
4246 }
4247
4248 /* range checks */
4249 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4250 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4251
4252 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4253 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4254 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4255 "size is out of scaler range\n",
4256 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4257 return -EINVAL;
4258 }
4259
4260 /* mark this plane as a scaler user in crtc_state */
4261 scaler_state->scaler_users |= (1 << scaler_user);
4262 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4263 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4264 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4265 scaler_state->scaler_users);
4266
4267 return 0;
4268 }
4269
4270 /**
4271 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4272 *
4273 * @state: crtc's scaler state
4274 *
4275 * Return
4276 * 0 - scaler_usage updated successfully
4277 * error - requested scaling cannot be supported or other error condition
4278 */
4279 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4280 {
4281 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4282 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4283
4284 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4285 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4286
4287 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4288 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4289 state->pipe_src_w, state->pipe_src_h,
4290 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4291 }
4292
4293 /**
4294 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4295 *
4296 * @state: crtc's scaler state
4297 * @plane_state: atomic plane state to update
4298 *
4299 * Return
4300 * 0 - scaler_usage updated successfully
4301 * error - requested scaling cannot be supported or other error condition
4302 */
4303 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4304 struct intel_plane_state *plane_state)
4305 {
4306
4307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4308 struct intel_plane *intel_plane =
4309 to_intel_plane(plane_state->base.plane);
4310 struct drm_framebuffer *fb = plane_state->base.fb;
4311 int ret;
4312
4313 bool force_detach = !fb || !plane_state->visible;
4314
4315 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4316 intel_plane->base.base.id, intel_crtc->pipe,
4317 drm_plane_index(&intel_plane->base));
4318
4319 ret = skl_update_scaler(crtc_state, force_detach,
4320 drm_plane_index(&intel_plane->base),
4321 &plane_state->scaler_id,
4322 plane_state->base.rotation,
4323 drm_rect_width(&plane_state->src) >> 16,
4324 drm_rect_height(&plane_state->src) >> 16,
4325 drm_rect_width(&plane_state->dst),
4326 drm_rect_height(&plane_state->dst));
4327
4328 if (ret || plane_state->scaler_id < 0)
4329 return ret;
4330
4331 /* check colorkey */
4332 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4333 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4334 intel_plane->base.base.id);
4335 return -EINVAL;
4336 }
4337
4338 /* Check src format */
4339 switch (fb->pixel_format) {
4340 case DRM_FORMAT_RGB565:
4341 case DRM_FORMAT_XBGR8888:
4342 case DRM_FORMAT_XRGB8888:
4343 case DRM_FORMAT_ABGR8888:
4344 case DRM_FORMAT_ARGB8888:
4345 case DRM_FORMAT_XRGB2101010:
4346 case DRM_FORMAT_XBGR2101010:
4347 case DRM_FORMAT_YUYV:
4348 case DRM_FORMAT_YVYU:
4349 case DRM_FORMAT_UYVY:
4350 case DRM_FORMAT_VYUY:
4351 break;
4352 default:
4353 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4354 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4355 return -EINVAL;
4356 }
4357
4358 return 0;
4359 }
4360
4361 static void skylake_scaler_disable(struct intel_crtc *crtc)
4362 {
4363 int i;
4364
4365 for (i = 0; i < crtc->num_scalers; i++)
4366 skl_detach_scaler(crtc, i);
4367 }
4368
4369 static void skylake_pfit_enable(struct intel_crtc *crtc)
4370 {
4371 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int pipe = crtc->pipe;
4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc->config->scaler_state;
4376
4377 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4378
4379 if (crtc->config->pch_pfit.enabled) {
4380 int id;
4381
4382 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4383 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4384 return;
4385 }
4386
4387 id = scaler_state->scaler_id;
4388 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4389 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4390 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4391 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4392
4393 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4394 }
4395 }
4396
4397 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4398 {
4399 struct drm_device *dev = crtc->base.dev;
4400 struct drm_i915_private *dev_priv = dev->dev_private;
4401 int pipe = crtc->pipe;
4402
4403 if (crtc->config->pch_pfit.enabled) {
4404 /* Force use of hard-coded filter coefficients
4405 * as some pre-programmed values are broken,
4406 * e.g. x201.
4407 */
4408 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4409 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4410 PF_PIPE_SEL_IVB(pipe));
4411 else
4412 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4413 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4414 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4415 }
4416 }
4417
4418 void hsw_enable_ips(struct intel_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422
4423 if (!crtc->config->ips_enabled)
4424 return;
4425
4426 /*
4427 * We can only enable IPS after we enable a plane and wait for a vblank
4428 * This function is called from post_plane_update, which is run after
4429 * a vblank wait.
4430 */
4431
4432 assert_plane_enabled(dev_priv, crtc->plane);
4433 if (IS_BROADWELL(dev)) {
4434 mutex_lock(&dev_priv->rps.hw_lock);
4435 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4436 mutex_unlock(&dev_priv->rps.hw_lock);
4437 /* Quoting Art Runyan: "its not safe to expect any particular
4438 * value in IPS_CTL bit 31 after enabling IPS through the
4439 * mailbox." Moreover, the mailbox may return a bogus state,
4440 * so we need to just enable it and continue on.
4441 */
4442 } else {
4443 I915_WRITE(IPS_CTL, IPS_ENABLE);
4444 /* The bit only becomes 1 in the next vblank, so this wait here
4445 * is essentially intel_wait_for_vblank. If we don't have this
4446 * and don't wait for vblanks until the end of crtc_enable, then
4447 * the HW state readout code will complain that the expected
4448 * IPS_CTL value is not the one we read. */
4449 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4450 DRM_ERROR("Timed out waiting for IPS enable\n");
4451 }
4452 }
4453
4454 void hsw_disable_ips(struct intel_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459 if (!crtc->config->ips_enabled)
4460 return;
4461
4462 assert_plane_enabled(dev_priv, crtc->plane);
4463 if (IS_BROADWELL(dev)) {
4464 mutex_lock(&dev_priv->rps.hw_lock);
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4466 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4469 DRM_ERROR("Timed out waiting for IPS disable\n");
4470 } else {
4471 I915_WRITE(IPS_CTL, 0);
4472 POSTING_READ(IPS_CTL);
4473 }
4474
4475 /* We need to wait for a vblank before we can disable the plane. */
4476 intel_wait_for_vblank(dev, crtc->pipe);
4477 }
4478
4479 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4480 {
4481 if (intel_crtc->overlay) {
4482 struct drm_device *dev = intel_crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484
4485 mutex_lock(&dev->struct_mutex);
4486 dev_priv->mm.interruptible = false;
4487 (void) intel_overlay_switch_off(intel_crtc->overlay);
4488 dev_priv->mm.interruptible = true;
4489 mutex_unlock(&dev->struct_mutex);
4490 }
4491
4492 /* Let userspace switch the overlay on again. In most cases userspace
4493 * has to recompute where to put it anyway.
4494 */
4495 }
4496
4497 /**
4498 * intel_post_enable_primary - Perform operations after enabling primary plane
4499 * @crtc: the CRTC whose primary plane was just enabled
4500 *
4501 * Performs potentially sleeping operations that must be done after the primary
4502 * plane is enabled, such as updating FBC and IPS. Note that this may be
4503 * called due to an explicit primary plane update, or due to an implicit
4504 * re-enable that is caused when a sprite plane is updated to no longer
4505 * completely hide the primary plane.
4506 */
4507 static void
4508 intel_post_enable_primary(struct drm_crtc *crtc)
4509 {
4510 struct drm_device *dev = crtc->dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4513 int pipe = intel_crtc->pipe;
4514
4515 /*
4516 * FIXME IPS should be fine as long as one plane is
4517 * enabled, but in practice it seems to have problems
4518 * when going from primary only to sprite only and vice
4519 * versa.
4520 */
4521 hsw_enable_ips(intel_crtc);
4522
4523 /*
4524 * Gen2 reports pipe underruns whenever all planes are disabled.
4525 * So don't enable underrun reporting before at least some planes
4526 * are enabled.
4527 * FIXME: Need to fix the logic to work when we turn off all planes
4528 * but leave the pipe running.
4529 */
4530 if (IS_GEN2(dev))
4531 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4532
4533 /* Underruns don't always raise interrupts, so check manually. */
4534 intel_check_cpu_fifo_underruns(dev_priv);
4535 intel_check_pch_fifo_underruns(dev_priv);
4536 }
4537
4538 /* FIXME move all this to pre_plane_update() with proper state tracking */
4539 static void
4540 intel_pre_disable_primary(struct drm_crtc *crtc)
4541 {
4542 struct drm_device *dev = crtc->dev;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545 int pipe = intel_crtc->pipe;
4546
4547 /*
4548 * Gen2 reports pipe underruns whenever all planes are disabled.
4549 * So diasble underrun reporting before all the planes get disabled.
4550 * FIXME: Need to fix the logic to work when we turn off all planes
4551 * but leave the pipe running.
4552 */
4553 if (IS_GEN2(dev))
4554 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556 /*
4557 * FIXME IPS should be fine as long as one plane is
4558 * enabled, but in practice it seems to have problems
4559 * when going from primary only to sprite only and vice
4560 * versa.
4561 */
4562 hsw_disable_ips(intel_crtc);
4563 }
4564
4565 /* FIXME get rid of this and use pre_plane_update */
4566 static void
4567 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4568 {
4569 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 int pipe = intel_crtc->pipe;
4573
4574 intel_pre_disable_primary(crtc);
4575
4576 /*
4577 * Vblank time updates from the shadow to live plane control register
4578 * are blocked if the memory self-refresh mode is active at that
4579 * moment. So to make sure the plane gets truly disabled, disable
4580 * first the self-refresh mode. The self-refresh enable bit in turn
4581 * will be checked/applied by the HW only at the next frame start
4582 * event which is after the vblank start event, so we need to have a
4583 * wait-for-vblank between disabling the plane and the pipe.
4584 */
4585 if (HAS_GMCH_DISPLAY(dev)) {
4586 intel_set_memory_cxsr(dev_priv, false);
4587 dev_priv->wm.vlv.cxsr = false;
4588 intel_wait_for_vblank(dev, pipe);
4589 }
4590 }
4591
4592 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4593 {
4594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4595 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4596 struct intel_crtc_state *pipe_config =
4597 to_intel_crtc_state(crtc->base.state);
4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_plane *primary = crtc->base.primary;
4600 struct drm_plane_state *old_pri_state =
4601 drm_atomic_get_existing_plane_state(old_state, primary);
4602
4603 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4604
4605 crtc->wm.cxsr_allowed = true;
4606
4607 if (pipe_config->update_wm_post && pipe_config->base.active)
4608 intel_update_watermarks(&crtc->base);
4609
4610 if (old_pri_state) {
4611 struct intel_plane_state *primary_state =
4612 to_intel_plane_state(primary->state);
4613 struct intel_plane_state *old_primary_state =
4614 to_intel_plane_state(old_pri_state);
4615
4616 intel_fbc_post_update(crtc);
4617
4618 if (primary_state->visible &&
4619 (needs_modeset(&pipe_config->base) ||
4620 !old_primary_state->visible))
4621 intel_post_enable_primary(&crtc->base);
4622 }
4623 }
4624
4625 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4626 {
4627 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4628 struct drm_device *dev = crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_crtc_state *pipe_config =
4631 to_intel_crtc_state(crtc->base.state);
4632 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4633 struct drm_plane *primary = crtc->base.primary;
4634 struct drm_plane_state *old_pri_state =
4635 drm_atomic_get_existing_plane_state(old_state, primary);
4636 bool modeset = needs_modeset(&pipe_config->base);
4637
4638 if (old_pri_state) {
4639 struct intel_plane_state *primary_state =
4640 to_intel_plane_state(primary->state);
4641 struct intel_plane_state *old_primary_state =
4642 to_intel_plane_state(old_pri_state);
4643
4644 intel_fbc_pre_update(crtc);
4645
4646 if (old_primary_state->visible &&
4647 (modeset || !primary_state->visible))
4648 intel_pre_disable_primary(&crtc->base);
4649 }
4650
4651 if (pipe_config->disable_cxsr) {
4652 crtc->wm.cxsr_allowed = false;
4653
4654 /*
4655 * Vblank time updates from the shadow to live plane control register
4656 * are blocked if the memory self-refresh mode is active at that
4657 * moment. So to make sure the plane gets truly disabled, disable
4658 * first the self-refresh mode. The self-refresh enable bit in turn
4659 * will be checked/applied by the HW only at the next frame start
4660 * event which is after the vblank start event, so we need to have a
4661 * wait-for-vblank between disabling the plane and the pipe.
4662 */
4663 if (old_crtc_state->base.active) {
4664 intel_set_memory_cxsr(dev_priv, false);
4665 dev_priv->wm.vlv.cxsr = false;
4666 intel_wait_for_vblank(dev, crtc->pipe);
4667 }
4668 }
4669
4670 /*
4671 * IVB workaround: must disable low power watermarks for at least
4672 * one frame before enabling scaling. LP watermarks can be re-enabled
4673 * when scaling is disabled.
4674 *
4675 * WaCxSRDisabledForSpriteScaling:ivb
4676 */
4677 if (pipe_config->disable_lp_wm) {
4678 ilk_disable_lp_wm(dev);
4679 intel_wait_for_vblank(dev, crtc->pipe);
4680 }
4681
4682 /*
4683 * If we're doing a modeset, we're done. No need to do any pre-vblank
4684 * watermark programming here.
4685 */
4686 if (needs_modeset(&pipe_config->base))
4687 return;
4688
4689 /*
4690 * For platforms that support atomic watermarks, program the
4691 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4692 * will be the intermediate values that are safe for both pre- and
4693 * post- vblank; when vblank happens, the 'active' values will be set
4694 * to the final 'target' values and we'll do this again to get the
4695 * optimal watermarks. For gen9+ platforms, the values we program here
4696 * will be the final target values which will get automatically latched
4697 * at vblank time; no further programming will be necessary.
4698 *
4699 * If a platform hasn't been transitioned to atomic watermarks yet,
4700 * we'll continue to update watermarks the old way, if flags tell
4701 * us to.
4702 */
4703 if (dev_priv->display.initial_watermarks != NULL)
4704 dev_priv->display.initial_watermarks(pipe_config);
4705 else if (pipe_config->update_wm_pre)
4706 intel_update_watermarks(&crtc->base);
4707 }
4708
4709 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4710 {
4711 struct drm_device *dev = crtc->dev;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct drm_plane *p;
4714 int pipe = intel_crtc->pipe;
4715
4716 intel_crtc_dpms_overlay_disable(intel_crtc);
4717
4718 drm_for_each_plane_mask(p, dev, plane_mask)
4719 to_intel_plane(p)->disable_plane(p, crtc);
4720
4721 /*
4722 * FIXME: Once we grow proper nuclear flip support out of this we need
4723 * to compute the mask of flip planes precisely. For the time being
4724 * consider this a flip to a NULL plane.
4725 */
4726 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4727 }
4728
4729 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4730 {
4731 struct drm_device *dev = crtc->dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 struct intel_encoder *encoder;
4735 int pipe = intel_crtc->pipe;
4736 struct intel_crtc_state *pipe_config =
4737 to_intel_crtc_state(crtc->state);
4738
4739 if (WARN_ON(intel_crtc->active))
4740 return;
4741
4742 /*
4743 * Sometimes spurious CPU pipe underruns happen during FDI
4744 * training, at least with VGA+HDMI cloning. Suppress them.
4745 *
4746 * On ILK we get an occasional spurious CPU pipe underruns
4747 * between eDP port A enable and vdd enable. Also PCH port
4748 * enable seems to result in the occasional CPU pipe underrun.
4749 *
4750 * Spurious PCH underruns also occur during PCH enabling.
4751 */
4752 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4753 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 if (intel_crtc->config->has_pch_encoder)
4758 intel_prepare_shared_dpll(intel_crtc);
4759
4760 if (intel_crtc->config->has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763 intel_set_pipe_timings(intel_crtc);
4764 intel_set_pipe_src_size(intel_crtc);
4765
4766 if (intel_crtc->config->has_pch_encoder) {
4767 intel_cpu_transcoder_set_m_n(intel_crtc,
4768 &intel_crtc->config->fdi_m_n, NULL);
4769 }
4770
4771 ironlake_set_pipeconf(crtc);
4772
4773 intel_crtc->active = true;
4774
4775 for_each_encoder_on_crtc(dev, crtc, encoder)
4776 if (encoder->pre_enable)
4777 encoder->pre_enable(encoder);
4778
4779 if (intel_crtc->config->has_pch_encoder) {
4780 /* Note: FDI PLL enabling _must_ be done before we enable the
4781 * cpu pipes, hence this is separate from all the other fdi/pch
4782 * enabling. */
4783 ironlake_fdi_pll_enable(intel_crtc);
4784 } else {
4785 assert_fdi_tx_disabled(dev_priv, pipe);
4786 assert_fdi_rx_disabled(dev_priv, pipe);
4787 }
4788
4789 ironlake_pfit_enable(intel_crtc);
4790
4791 /*
4792 * On ILK+ LUT must be loaded before the pipe is running but with
4793 * clocks enabled
4794 */
4795 intel_color_load_luts(&pipe_config->base);
4796
4797 if (dev_priv->display.initial_watermarks != NULL)
4798 dev_priv->display.initial_watermarks(intel_crtc->config);
4799 intel_enable_pipe(intel_crtc);
4800
4801 if (intel_crtc->config->has_pch_encoder)
4802 ironlake_pch_enable(crtc);
4803
4804 assert_vblank_disabled(crtc);
4805 drm_crtc_vblank_on(crtc);
4806
4807 for_each_encoder_on_crtc(dev, crtc, encoder)
4808 encoder->enable(encoder);
4809
4810 if (HAS_PCH_CPT(dev))
4811 cpt_verify_modeset(dev, intel_crtc->pipe);
4812
4813 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4814 if (intel_crtc->config->has_pch_encoder)
4815 intel_wait_for_vblank(dev, pipe);
4816 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4817 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4818 }
4819
4820 /* IPS only exists on ULT machines and is tied to pipe A. */
4821 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4822 {
4823 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4824 }
4825
4826 static void haswell_crtc_enable(struct drm_crtc *crtc)
4827 {
4828 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 struct intel_encoder *encoder;
4832 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4833 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4834 struct intel_crtc_state *pipe_config =
4835 to_intel_crtc_state(crtc->state);
4836
4837 if (WARN_ON(intel_crtc->active))
4838 return;
4839
4840 if (intel_crtc->config->has_pch_encoder)
4841 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4842 false);
4843
4844 if (intel_crtc->config->shared_dpll)
4845 intel_enable_shared_dpll(intel_crtc);
4846
4847 if (intel_crtc->config->has_dp_encoder)
4848 intel_dp_set_m_n(intel_crtc, M1_N1);
4849
4850 if (!intel_crtc->config->has_dsi_encoder)
4851 intel_set_pipe_timings(intel_crtc);
4852
4853 intel_set_pipe_src_size(intel_crtc);
4854
4855 if (cpu_transcoder != TRANSCODER_EDP &&
4856 !transcoder_is_dsi(cpu_transcoder)) {
4857 I915_WRITE(PIPE_MULT(cpu_transcoder),
4858 intel_crtc->config->pixel_multiplier - 1);
4859 }
4860
4861 if (intel_crtc->config->has_pch_encoder) {
4862 intel_cpu_transcoder_set_m_n(intel_crtc,
4863 &intel_crtc->config->fdi_m_n, NULL);
4864 }
4865
4866 if (!intel_crtc->config->has_dsi_encoder)
4867 haswell_set_pipeconf(crtc);
4868
4869 haswell_set_pipemisc(crtc);
4870
4871 intel_color_set_csc(&pipe_config->base);
4872
4873 intel_crtc->active = true;
4874
4875 if (intel_crtc->config->has_pch_encoder)
4876 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4877 else
4878 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4879
4880 for_each_encoder_on_crtc(dev, crtc, encoder) {
4881 if (encoder->pre_enable)
4882 encoder->pre_enable(encoder);
4883 }
4884
4885 if (intel_crtc->config->has_pch_encoder)
4886 dev_priv->display.fdi_link_train(crtc);
4887
4888 if (!intel_crtc->config->has_dsi_encoder)
4889 intel_ddi_enable_pipe_clock(intel_crtc);
4890
4891 if (INTEL_INFO(dev)->gen >= 9)
4892 skylake_pfit_enable(intel_crtc);
4893 else
4894 ironlake_pfit_enable(intel_crtc);
4895
4896 /*
4897 * On ILK+ LUT must be loaded before the pipe is running but with
4898 * clocks enabled
4899 */
4900 intel_color_load_luts(&pipe_config->base);
4901
4902 intel_ddi_set_pipe_settings(crtc);
4903 if (!intel_crtc->config->has_dsi_encoder)
4904 intel_ddi_enable_transcoder_func(crtc);
4905
4906 if (dev_priv->display.initial_watermarks != NULL)
4907 dev_priv->display.initial_watermarks(pipe_config);
4908 else
4909 intel_update_watermarks(crtc);
4910
4911 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4912 if (!intel_crtc->config->has_dsi_encoder)
4913 intel_enable_pipe(intel_crtc);
4914
4915 if (intel_crtc->config->has_pch_encoder)
4916 lpt_pch_enable(crtc);
4917
4918 if (intel_crtc->config->dp_encoder_is_mst)
4919 intel_ddi_set_vc_payload_alloc(crtc, true);
4920
4921 assert_vblank_disabled(crtc);
4922 drm_crtc_vblank_on(crtc);
4923
4924 for_each_encoder_on_crtc(dev, crtc, encoder) {
4925 encoder->enable(encoder);
4926 intel_opregion_notify_encoder(encoder, true);
4927 }
4928
4929 if (intel_crtc->config->has_pch_encoder) {
4930 intel_wait_for_vblank(dev, pipe);
4931 intel_wait_for_vblank(dev, pipe);
4932 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4933 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4934 true);
4935 }
4936
4937 /* If we change the relative order between pipe/planes enabling, we need
4938 * to change the workaround. */
4939 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4940 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4941 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4942 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4943 }
4944 }
4945
4946 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4947 {
4948 struct drm_device *dev = crtc->base.dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 int pipe = crtc->pipe;
4951
4952 /* To avoid upsetting the power well on haswell only disable the pfit if
4953 * it's in use. The hw state code will make sure we get this right. */
4954 if (force || crtc->config->pch_pfit.enabled) {
4955 I915_WRITE(PF_CTL(pipe), 0);
4956 I915_WRITE(PF_WIN_POS(pipe), 0);
4957 I915_WRITE(PF_WIN_SZ(pipe), 0);
4958 }
4959 }
4960
4961 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4962 {
4963 struct drm_device *dev = crtc->dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966 struct intel_encoder *encoder;
4967 int pipe = intel_crtc->pipe;
4968
4969 /*
4970 * Sometimes spurious CPU pipe underruns happen when the
4971 * pipe is already disabled, but FDI RX/TX is still enabled.
4972 * Happens at least with VGA+HDMI cloning. Suppress them.
4973 */
4974 if (intel_crtc->config->has_pch_encoder) {
4975 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4976 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4977 }
4978
4979 for_each_encoder_on_crtc(dev, crtc, encoder)
4980 encoder->disable(encoder);
4981
4982 drm_crtc_vblank_off(crtc);
4983 assert_vblank_disabled(crtc);
4984
4985 intel_disable_pipe(intel_crtc);
4986
4987 ironlake_pfit_disable(intel_crtc, false);
4988
4989 if (intel_crtc->config->has_pch_encoder)
4990 ironlake_fdi_disable(crtc);
4991
4992 for_each_encoder_on_crtc(dev, crtc, encoder)
4993 if (encoder->post_disable)
4994 encoder->post_disable(encoder);
4995
4996 if (intel_crtc->config->has_pch_encoder) {
4997 ironlake_disable_pch_transcoder(dev_priv, pipe);
4998
4999 if (HAS_PCH_CPT(dev)) {
5000 i915_reg_t reg;
5001 u32 temp;
5002
5003 /* disable TRANS_DP_CTL */
5004 reg = TRANS_DP_CTL(pipe);
5005 temp = I915_READ(reg);
5006 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5007 TRANS_DP_PORT_SEL_MASK);
5008 temp |= TRANS_DP_PORT_SEL_NONE;
5009 I915_WRITE(reg, temp);
5010
5011 /* disable DPLL_SEL */
5012 temp = I915_READ(PCH_DPLL_SEL);
5013 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5014 I915_WRITE(PCH_DPLL_SEL, temp);
5015 }
5016
5017 ironlake_fdi_pll_disable(intel_crtc);
5018 }
5019
5020 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5021 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5022 }
5023
5024 static void haswell_crtc_disable(struct drm_crtc *crtc)
5025 {
5026 struct drm_device *dev = crtc->dev;
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5029 struct intel_encoder *encoder;
5030 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5031
5032 if (intel_crtc->config->has_pch_encoder)
5033 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034 false);
5035
5036 for_each_encoder_on_crtc(dev, crtc, encoder) {
5037 intel_opregion_notify_encoder(encoder, false);
5038 encoder->disable(encoder);
5039 }
5040
5041 drm_crtc_vblank_off(crtc);
5042 assert_vblank_disabled(crtc);
5043
5044 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5045 if (!intel_crtc->config->has_dsi_encoder)
5046 intel_disable_pipe(intel_crtc);
5047
5048 if (intel_crtc->config->dp_encoder_is_mst)
5049 intel_ddi_set_vc_payload_alloc(crtc, false);
5050
5051 if (!intel_crtc->config->has_dsi_encoder)
5052 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5053
5054 if (INTEL_INFO(dev)->gen >= 9)
5055 skylake_scaler_disable(intel_crtc);
5056 else
5057 ironlake_pfit_disable(intel_crtc, false);
5058
5059 if (!intel_crtc->config->has_dsi_encoder)
5060 intel_ddi_disable_pipe_clock(intel_crtc);
5061
5062 for_each_encoder_on_crtc(dev, crtc, encoder)
5063 if (encoder->post_disable)
5064 encoder->post_disable(encoder);
5065
5066 if (intel_crtc->config->has_pch_encoder) {
5067 lpt_disable_pch_transcoder(dev_priv);
5068 lpt_disable_iclkip(dev_priv);
5069 intel_ddi_fdi_disable(crtc);
5070
5071 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5072 true);
5073 }
5074 }
5075
5076 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5077 {
5078 struct drm_device *dev = crtc->base.dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct intel_crtc_state *pipe_config = crtc->config;
5081
5082 if (!pipe_config->gmch_pfit.control)
5083 return;
5084
5085 /*
5086 * The panel fitter should only be adjusted whilst the pipe is disabled,
5087 * according to register description and PRM.
5088 */
5089 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5090 assert_pipe_disabled(dev_priv, crtc->pipe);
5091
5092 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5093 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5094
5095 /* Border color in case we don't scale up to the full screen. Black by
5096 * default, change to something else for debugging. */
5097 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5098 }
5099
5100 static enum intel_display_power_domain port_to_power_domain(enum port port)
5101 {
5102 switch (port) {
5103 case PORT_A:
5104 return POWER_DOMAIN_PORT_DDI_A_LANES;
5105 case PORT_B:
5106 return POWER_DOMAIN_PORT_DDI_B_LANES;
5107 case PORT_C:
5108 return POWER_DOMAIN_PORT_DDI_C_LANES;
5109 case PORT_D:
5110 return POWER_DOMAIN_PORT_DDI_D_LANES;
5111 case PORT_E:
5112 return POWER_DOMAIN_PORT_DDI_E_LANES;
5113 default:
5114 MISSING_CASE(port);
5115 return POWER_DOMAIN_PORT_OTHER;
5116 }
5117 }
5118
5119 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5120 {
5121 switch (port) {
5122 case PORT_A:
5123 return POWER_DOMAIN_AUX_A;
5124 case PORT_B:
5125 return POWER_DOMAIN_AUX_B;
5126 case PORT_C:
5127 return POWER_DOMAIN_AUX_C;
5128 case PORT_D:
5129 return POWER_DOMAIN_AUX_D;
5130 case PORT_E:
5131 /* FIXME: Check VBT for actual wiring of PORT E */
5132 return POWER_DOMAIN_AUX_D;
5133 default:
5134 MISSING_CASE(port);
5135 return POWER_DOMAIN_AUX_A;
5136 }
5137 }
5138
5139 enum intel_display_power_domain
5140 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5141 {
5142 struct drm_device *dev = intel_encoder->base.dev;
5143 struct intel_digital_port *intel_dig_port;
5144
5145 switch (intel_encoder->type) {
5146 case INTEL_OUTPUT_UNKNOWN:
5147 /* Only DDI platforms should ever use this output type */
5148 WARN_ON_ONCE(!HAS_DDI(dev));
5149 case INTEL_OUTPUT_DISPLAYPORT:
5150 case INTEL_OUTPUT_HDMI:
5151 case INTEL_OUTPUT_EDP:
5152 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5153 return port_to_power_domain(intel_dig_port->port);
5154 case INTEL_OUTPUT_DP_MST:
5155 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5156 return port_to_power_domain(intel_dig_port->port);
5157 case INTEL_OUTPUT_ANALOG:
5158 return POWER_DOMAIN_PORT_CRT;
5159 case INTEL_OUTPUT_DSI:
5160 return POWER_DOMAIN_PORT_DSI;
5161 default:
5162 return POWER_DOMAIN_PORT_OTHER;
5163 }
5164 }
5165
5166 enum intel_display_power_domain
5167 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5168 {
5169 struct drm_device *dev = intel_encoder->base.dev;
5170 struct intel_digital_port *intel_dig_port;
5171
5172 switch (intel_encoder->type) {
5173 case INTEL_OUTPUT_UNKNOWN:
5174 case INTEL_OUTPUT_HDMI:
5175 /*
5176 * Only DDI platforms should ever use these output types.
5177 * We can get here after the HDMI detect code has already set
5178 * the type of the shared encoder. Since we can't be sure
5179 * what's the status of the given connectors, play safe and
5180 * run the DP detection too.
5181 */
5182 WARN_ON_ONCE(!HAS_DDI(dev));
5183 case INTEL_OUTPUT_DISPLAYPORT:
5184 case INTEL_OUTPUT_EDP:
5185 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5186 return port_to_aux_power_domain(intel_dig_port->port);
5187 case INTEL_OUTPUT_DP_MST:
5188 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5189 return port_to_aux_power_domain(intel_dig_port->port);
5190 default:
5191 MISSING_CASE(intel_encoder->type);
5192 return POWER_DOMAIN_AUX_A;
5193 }
5194 }
5195
5196 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5197 struct intel_crtc_state *crtc_state)
5198 {
5199 struct drm_device *dev = crtc->dev;
5200 struct drm_encoder *encoder;
5201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202 enum pipe pipe = intel_crtc->pipe;
5203 unsigned long mask;
5204 enum transcoder transcoder = crtc_state->cpu_transcoder;
5205
5206 if (!crtc_state->base.active)
5207 return 0;
5208
5209 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5210 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5211 if (crtc_state->pch_pfit.enabled ||
5212 crtc_state->pch_pfit.force_thru)
5213 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5214
5215 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5216 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5217
5218 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5219 }
5220
5221 if (crtc_state->shared_dpll)
5222 mask |= BIT(POWER_DOMAIN_PLLS);
5223
5224 return mask;
5225 }
5226
5227 static unsigned long
5228 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5229 struct intel_crtc_state *crtc_state)
5230 {
5231 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233 enum intel_display_power_domain domain;
5234 unsigned long domains, new_domains, old_domains;
5235
5236 old_domains = intel_crtc->enabled_power_domains;
5237 intel_crtc->enabled_power_domains = new_domains =
5238 get_crtc_power_domains(crtc, crtc_state);
5239
5240 domains = new_domains & ~old_domains;
5241
5242 for_each_power_domain(domain, domains)
5243 intel_display_power_get(dev_priv, domain);
5244
5245 return old_domains & ~new_domains;
5246 }
5247
5248 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5249 unsigned long domains)
5250 {
5251 enum intel_display_power_domain domain;
5252
5253 for_each_power_domain(domain, domains)
5254 intel_display_power_put(dev_priv, domain);
5255 }
5256
5257 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5258 {
5259 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5260
5261 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5262 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5263 return max_cdclk_freq;
5264 else if (IS_CHERRYVIEW(dev_priv))
5265 return max_cdclk_freq*95/100;
5266 else if (INTEL_INFO(dev_priv)->gen < 4)
5267 return 2*max_cdclk_freq*90/100;
5268 else
5269 return max_cdclk_freq*90/100;
5270 }
5271
5272 static void intel_update_max_cdclk(struct drm_device *dev)
5273 {
5274 struct drm_i915_private *dev_priv = dev->dev_private;
5275
5276 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5277 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5278
5279 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5280 dev_priv->max_cdclk_freq = 675000;
5281 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5282 dev_priv->max_cdclk_freq = 540000;
5283 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5284 dev_priv->max_cdclk_freq = 450000;
5285 else
5286 dev_priv->max_cdclk_freq = 337500;
5287 } else if (IS_BROXTON(dev)) {
5288 dev_priv->max_cdclk_freq = 624000;
5289 } else if (IS_BROADWELL(dev)) {
5290 /*
5291 * FIXME with extra cooling we can allow
5292 * 540 MHz for ULX and 675 Mhz for ULT.
5293 * How can we know if extra cooling is
5294 * available? PCI ID, VTB, something else?
5295 */
5296 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5297 dev_priv->max_cdclk_freq = 450000;
5298 else if (IS_BDW_ULX(dev))
5299 dev_priv->max_cdclk_freq = 450000;
5300 else if (IS_BDW_ULT(dev))
5301 dev_priv->max_cdclk_freq = 540000;
5302 else
5303 dev_priv->max_cdclk_freq = 675000;
5304 } else if (IS_CHERRYVIEW(dev)) {
5305 dev_priv->max_cdclk_freq = 320000;
5306 } else if (IS_VALLEYVIEW(dev)) {
5307 dev_priv->max_cdclk_freq = 400000;
5308 } else {
5309 /* otherwise assume cdclk is fixed */
5310 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5311 }
5312
5313 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5314
5315 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5316 dev_priv->max_cdclk_freq);
5317
5318 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5319 dev_priv->max_dotclk_freq);
5320 }
5321
5322 static void intel_update_cdclk(struct drm_device *dev)
5323 {
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325
5326 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5327 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5328 dev_priv->cdclk_freq);
5329
5330 /*
5331 * Program the gmbus_freq based on the cdclk frequency.
5332 * BSpec erroneously claims we should aim for 4MHz, but
5333 * in fact 1MHz is the correct frequency.
5334 */
5335 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5336 /*
5337 * Program the gmbus_freq based on the cdclk frequency.
5338 * BSpec erroneously claims we should aim for 4MHz, but
5339 * in fact 1MHz is the correct frequency.
5340 */
5341 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5342 }
5343
5344 if (dev_priv->max_cdclk_freq == 0)
5345 intel_update_max_cdclk(dev);
5346 }
5347
5348 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5349 {
5350 uint32_t divider;
5351 uint32_t ratio;
5352 uint32_t current_freq;
5353 int ret;
5354
5355 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5356 switch (frequency) {
5357 case 144000:
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5359 ratio = BXT_DE_PLL_RATIO(60);
5360 break;
5361 case 288000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 384000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 576000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371 ratio = BXT_DE_PLL_RATIO(60);
5372 break;
5373 case 624000:
5374 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375 ratio = BXT_DE_PLL_RATIO(65);
5376 break;
5377 case 19200:
5378 /*
5379 * Bypass frequency with DE PLL disabled. Init ratio, divider
5380 * to suppress GCC warning.
5381 */
5382 ratio = 0;
5383 divider = 0;
5384 break;
5385 default:
5386 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5387
5388 return;
5389 }
5390
5391 mutex_lock(&dev_priv->rps.hw_lock);
5392 /* Inform power controller of upcoming frequency change */
5393 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5394 0x80000000);
5395 mutex_unlock(&dev_priv->rps.hw_lock);
5396
5397 if (ret) {
5398 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5399 ret, frequency);
5400 return;
5401 }
5402
5403 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5404 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5405 current_freq = current_freq * 500 + 1000;
5406
5407 /*
5408 * DE PLL has to be disabled when
5409 * - setting to 19.2MHz (bypass, PLL isn't used)
5410 * - before setting to 624MHz (PLL needs toggling)
5411 * - before setting to any frequency from 624MHz (PLL needs toggling)
5412 */
5413 if (frequency == 19200 || frequency == 624000 ||
5414 current_freq == 624000) {
5415 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5416 /* Timeout 200us */
5417 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5418 1))
5419 DRM_ERROR("timout waiting for DE PLL unlock\n");
5420 }
5421
5422 if (frequency != 19200) {
5423 uint32_t val;
5424
5425 val = I915_READ(BXT_DE_PLL_CTL);
5426 val &= ~BXT_DE_PLL_RATIO_MASK;
5427 val |= ratio;
5428 I915_WRITE(BXT_DE_PLL_CTL, val);
5429
5430 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5431 /* Timeout 200us */
5432 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5433 DRM_ERROR("timeout waiting for DE PLL lock\n");
5434
5435 val = I915_READ(CDCLK_CTL);
5436 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5437 val |= divider;
5438 /*
5439 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5440 * enable otherwise.
5441 */
5442 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5443 if (frequency >= 500000)
5444 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445
5446 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5447 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5448 val |= (frequency - 1000) / 500;
5449 I915_WRITE(CDCLK_CTL, val);
5450 }
5451
5452 mutex_lock(&dev_priv->rps.hw_lock);
5453 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5454 DIV_ROUND_UP(frequency, 25000));
5455 mutex_unlock(&dev_priv->rps.hw_lock);
5456
5457 if (ret) {
5458 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5459 ret, frequency);
5460 return;
5461 }
5462
5463 intel_update_cdclk(dev_priv->dev);
5464 }
5465
5466 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5467 {
5468 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5469 return false;
5470
5471 /* TODO: Check for a valid CDCLK rate */
5472
5473 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5474 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5475
5476 return false;
5477 }
5478
5479 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5480 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5481
5482 return false;
5483 }
5484
5485 return true;
5486 }
5487
5488 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5489 {
5490 return broxton_cdclk_is_enabled(dev_priv);
5491 }
5492
5493 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5494 {
5495 /* check if cd clock is enabled */
5496 if (broxton_cdclk_is_enabled(dev_priv)) {
5497 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5498 return;
5499 }
5500
5501 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5502
5503 /*
5504 * FIXME:
5505 * - The initial CDCLK needs to be read from VBT.
5506 * Need to make this change after VBT has changes for BXT.
5507 * - check if setting the max (or any) cdclk freq is really necessary
5508 * here, it belongs to modeset time
5509 */
5510 broxton_set_cdclk(dev_priv, 624000);
5511
5512 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5513 POSTING_READ(DBUF_CTL);
5514
5515 udelay(10);
5516
5517 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5518 DRM_ERROR("DBuf power enable timeout!\n");
5519 }
5520
5521 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5522 {
5523 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5524 POSTING_READ(DBUF_CTL);
5525
5526 udelay(10);
5527
5528 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5529 DRM_ERROR("DBuf power disable timeout!\n");
5530
5531 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5532 broxton_set_cdclk(dev_priv, 19200);
5533 }
5534
5535 static const struct skl_cdclk_entry {
5536 unsigned int freq;
5537 unsigned int vco;
5538 } skl_cdclk_frequencies[] = {
5539 { .freq = 308570, .vco = 8640 },
5540 { .freq = 337500, .vco = 8100 },
5541 { .freq = 432000, .vco = 8640 },
5542 { .freq = 450000, .vco = 8100 },
5543 { .freq = 540000, .vco = 8100 },
5544 { .freq = 617140, .vco = 8640 },
5545 { .freq = 675000, .vco = 8100 },
5546 };
5547
5548 static unsigned int skl_cdclk_decimal(unsigned int freq)
5549 {
5550 return (freq - 1000) / 500;
5551 }
5552
5553 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5554 {
5555 unsigned int i;
5556
5557 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5558 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5559
5560 if (e->freq == freq)
5561 return e->vco;
5562 }
5563
5564 return 8100;
5565 }
5566
5567 static void
5568 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5569 {
5570 unsigned int min_freq;
5571 u32 val;
5572
5573 /* select the minimum CDCLK before enabling DPLL 0 */
5574 val = I915_READ(CDCLK_CTL);
5575 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5576 val |= CDCLK_FREQ_337_308;
5577
5578 if (required_vco == 8640)
5579 min_freq = 308570;
5580 else
5581 min_freq = 337500;
5582
5583 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5584
5585 I915_WRITE(CDCLK_CTL, val);
5586 POSTING_READ(CDCLK_CTL);
5587
5588 /*
5589 * We always enable DPLL0 with the lowest link rate possible, but still
5590 * taking into account the VCO required to operate the eDP panel at the
5591 * desired frequency. The usual DP link rates operate with a VCO of
5592 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5593 * The modeset code is responsible for the selection of the exact link
5594 * rate later on, with the constraint of choosing a frequency that
5595 * works with required_vco.
5596 */
5597 val = I915_READ(DPLL_CTRL1);
5598
5599 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5600 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5601 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5602 if (required_vco == 8640)
5603 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5604 SKL_DPLL0);
5605 else
5606 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5607 SKL_DPLL0);
5608
5609 I915_WRITE(DPLL_CTRL1, val);
5610 POSTING_READ(DPLL_CTRL1);
5611
5612 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5613
5614 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5615 DRM_ERROR("DPLL0 not locked\n");
5616 }
5617
5618 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5619 {
5620 int ret;
5621 u32 val;
5622
5623 /* inform PCU we want to change CDCLK */
5624 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5625 mutex_lock(&dev_priv->rps.hw_lock);
5626 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5627 mutex_unlock(&dev_priv->rps.hw_lock);
5628
5629 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5630 }
5631
5632 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5633 {
5634 unsigned int i;
5635
5636 for (i = 0; i < 15; i++) {
5637 if (skl_cdclk_pcu_ready(dev_priv))
5638 return true;
5639 udelay(10);
5640 }
5641
5642 return false;
5643 }
5644
5645 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5646 {
5647 struct drm_device *dev = dev_priv->dev;
5648 u32 freq_select, pcu_ack;
5649
5650 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5651
5652 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5653 DRM_ERROR("failed to inform PCU about cdclk change\n");
5654 return;
5655 }
5656
5657 /* set CDCLK_CTL */
5658 switch(freq) {
5659 case 450000:
5660 case 432000:
5661 freq_select = CDCLK_FREQ_450_432;
5662 pcu_ack = 1;
5663 break;
5664 case 540000:
5665 freq_select = CDCLK_FREQ_540;
5666 pcu_ack = 2;
5667 break;
5668 case 308570:
5669 case 337500:
5670 default:
5671 freq_select = CDCLK_FREQ_337_308;
5672 pcu_ack = 0;
5673 break;
5674 case 617140:
5675 case 675000:
5676 freq_select = CDCLK_FREQ_675_617;
5677 pcu_ack = 3;
5678 break;
5679 }
5680
5681 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5682 POSTING_READ(CDCLK_CTL);
5683
5684 /* inform PCU of the change */
5685 mutex_lock(&dev_priv->rps.hw_lock);
5686 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5687 mutex_unlock(&dev_priv->rps.hw_lock);
5688
5689 intel_update_cdclk(dev);
5690 }
5691
5692 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5693 {
5694 /* disable DBUF power */
5695 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5696 POSTING_READ(DBUF_CTL);
5697
5698 udelay(10);
5699
5700 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5701 DRM_ERROR("DBuf power disable timeout\n");
5702
5703 /* disable DPLL0 */
5704 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5705 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5706 DRM_ERROR("Couldn't disable DPLL0\n");
5707 }
5708
5709 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5710 {
5711 unsigned int required_vco;
5712
5713 /* DPLL0 not enabled (happens on early BIOS versions) */
5714 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5715 /* enable DPLL0 */
5716 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5717 skl_dpll0_enable(dev_priv, required_vco);
5718 }
5719
5720 /* set CDCLK to the frequency the BIOS chose */
5721 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5722
5723 /* enable DBUF power */
5724 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5725 POSTING_READ(DBUF_CTL);
5726
5727 udelay(10);
5728
5729 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5730 DRM_ERROR("DBuf power enable timeout\n");
5731 }
5732
5733 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5734 {
5735 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5736 uint32_t cdctl = I915_READ(CDCLK_CTL);
5737 int freq = dev_priv->skl_boot_cdclk;
5738
5739 /*
5740 * check if the pre-os intialized the display
5741 * There is SWF18 scratchpad register defined which is set by the
5742 * pre-os which can be used by the OS drivers to check the status
5743 */
5744 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5745 goto sanitize;
5746
5747 /* Is PLL enabled and locked ? */
5748 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5749 goto sanitize;
5750
5751 /* DPLL okay; verify the cdclock
5752 *
5753 * Noticed in some instances that the freq selection is correct but
5754 * decimal part is programmed wrong from BIOS where pre-os does not
5755 * enable display. Verify the same as well.
5756 */
5757 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5758 /* All well; nothing to sanitize */
5759 return false;
5760 sanitize:
5761 /*
5762 * As of now initialize with max cdclk till
5763 * we get dynamic cdclk support
5764 * */
5765 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5766 skl_init_cdclk(dev_priv);
5767
5768 /* we did have to sanitize */
5769 return true;
5770 }
5771
5772 /* Adjust CDclk dividers to allow high res or save power if possible */
5773 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5774 {
5775 struct drm_i915_private *dev_priv = dev->dev_private;
5776 u32 val, cmd;
5777
5778 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5779 != dev_priv->cdclk_freq);
5780
5781 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5782 cmd = 2;
5783 else if (cdclk == 266667)
5784 cmd = 1;
5785 else
5786 cmd = 0;
5787
5788 mutex_lock(&dev_priv->rps.hw_lock);
5789 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5790 val &= ~DSPFREQGUAR_MASK;
5791 val |= (cmd << DSPFREQGUAR_SHIFT);
5792 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5793 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5794 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5795 50)) {
5796 DRM_ERROR("timed out waiting for CDclk change\n");
5797 }
5798 mutex_unlock(&dev_priv->rps.hw_lock);
5799
5800 mutex_lock(&dev_priv->sb_lock);
5801
5802 if (cdclk == 400000) {
5803 u32 divider;
5804
5805 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5806
5807 /* adjust cdclk divider */
5808 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5809 val &= ~CCK_FREQUENCY_VALUES;
5810 val |= divider;
5811 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5812
5813 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5814 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5815 50))
5816 DRM_ERROR("timed out waiting for CDclk change\n");
5817 }
5818
5819 /* adjust self-refresh exit latency value */
5820 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5821 val &= ~0x7f;
5822
5823 /*
5824 * For high bandwidth configs, we set a higher latency in the bunit
5825 * so that the core display fetch happens in time to avoid underruns.
5826 */
5827 if (cdclk == 400000)
5828 val |= 4500 / 250; /* 4.5 usec */
5829 else
5830 val |= 3000 / 250; /* 3.0 usec */
5831 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5832
5833 mutex_unlock(&dev_priv->sb_lock);
5834
5835 intel_update_cdclk(dev);
5836 }
5837
5838 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5839 {
5840 struct drm_i915_private *dev_priv = dev->dev_private;
5841 u32 val, cmd;
5842
5843 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5844 != dev_priv->cdclk_freq);
5845
5846 switch (cdclk) {
5847 case 333333:
5848 case 320000:
5849 case 266667:
5850 case 200000:
5851 break;
5852 default:
5853 MISSING_CASE(cdclk);
5854 return;
5855 }
5856
5857 /*
5858 * Specs are full of misinformation, but testing on actual
5859 * hardware has shown that we just need to write the desired
5860 * CCK divider into the Punit register.
5861 */
5862 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5863
5864 mutex_lock(&dev_priv->rps.hw_lock);
5865 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5866 val &= ~DSPFREQGUAR_MASK_CHV;
5867 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5868 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5869 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5870 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5871 50)) {
5872 DRM_ERROR("timed out waiting for CDclk change\n");
5873 }
5874 mutex_unlock(&dev_priv->rps.hw_lock);
5875
5876 intel_update_cdclk(dev);
5877 }
5878
5879 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5880 int max_pixclk)
5881 {
5882 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5883 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5884
5885 /*
5886 * Really only a few cases to deal with, as only 4 CDclks are supported:
5887 * 200MHz
5888 * 267MHz
5889 * 320/333MHz (depends on HPLL freq)
5890 * 400MHz (VLV only)
5891 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5892 * of the lower bin and adjust if needed.
5893 *
5894 * We seem to get an unstable or solid color picture at 200MHz.
5895 * Not sure what's wrong. For now use 200MHz only when all pipes
5896 * are off.
5897 */
5898 if (!IS_CHERRYVIEW(dev_priv) &&
5899 max_pixclk > freq_320*limit/100)
5900 return 400000;
5901 else if (max_pixclk > 266667*limit/100)
5902 return freq_320;
5903 else if (max_pixclk > 0)
5904 return 266667;
5905 else
5906 return 200000;
5907 }
5908
5909 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5910 int max_pixclk)
5911 {
5912 /*
5913 * FIXME:
5914 * - remove the guardband, it's not needed on BXT
5915 * - set 19.2MHz bypass frequency if there are no active pipes
5916 */
5917 if (max_pixclk > 576000*9/10)
5918 return 624000;
5919 else if (max_pixclk > 384000*9/10)
5920 return 576000;
5921 else if (max_pixclk > 288000*9/10)
5922 return 384000;
5923 else if (max_pixclk > 144000*9/10)
5924 return 288000;
5925 else
5926 return 144000;
5927 }
5928
5929 /* Compute the max pixel clock for new configuration. */
5930 static int intel_mode_max_pixclk(struct drm_device *dev,
5931 struct drm_atomic_state *state)
5932 {
5933 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 struct drm_crtc *crtc;
5936 struct drm_crtc_state *crtc_state;
5937 unsigned max_pixclk = 0, i;
5938 enum pipe pipe;
5939
5940 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5941 sizeof(intel_state->min_pixclk));
5942
5943 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5944 int pixclk = 0;
5945
5946 if (crtc_state->enable)
5947 pixclk = crtc_state->adjusted_mode.crtc_clock;
5948
5949 intel_state->min_pixclk[i] = pixclk;
5950 }
5951
5952 for_each_pipe(dev_priv, pipe)
5953 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5954
5955 return max_pixclk;
5956 }
5957
5958 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5959 {
5960 struct drm_device *dev = state->dev;
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962 int max_pixclk = intel_mode_max_pixclk(dev, state);
5963 struct intel_atomic_state *intel_state =
5964 to_intel_atomic_state(state);
5965
5966 if (max_pixclk < 0)
5967 return max_pixclk;
5968
5969 intel_state->cdclk = intel_state->dev_cdclk =
5970 valleyview_calc_cdclk(dev_priv, max_pixclk);
5971
5972 if (!intel_state->active_crtcs)
5973 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5974
5975 return 0;
5976 }
5977
5978 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5979 {
5980 struct drm_device *dev = state->dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 int max_pixclk = intel_mode_max_pixclk(dev, state);
5983 struct intel_atomic_state *intel_state =
5984 to_intel_atomic_state(state);
5985
5986 if (max_pixclk < 0)
5987 return max_pixclk;
5988
5989 intel_state->cdclk = intel_state->dev_cdclk =
5990 broxton_calc_cdclk(dev_priv, max_pixclk);
5991
5992 if (!intel_state->active_crtcs)
5993 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5994
5995 return 0;
5996 }
5997
5998 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5999 {
6000 unsigned int credits, default_credits;
6001
6002 if (IS_CHERRYVIEW(dev_priv))
6003 default_credits = PFI_CREDIT(12);
6004 else
6005 default_credits = PFI_CREDIT(8);
6006
6007 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6008 /* CHV suggested value is 31 or 63 */
6009 if (IS_CHERRYVIEW(dev_priv))
6010 credits = PFI_CREDIT_63;
6011 else
6012 credits = PFI_CREDIT(15);
6013 } else {
6014 credits = default_credits;
6015 }
6016
6017 /*
6018 * WA - write default credits before re-programming
6019 * FIXME: should we also set the resend bit here?
6020 */
6021 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6022 default_credits);
6023
6024 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6025 credits | PFI_CREDIT_RESEND);
6026
6027 /*
6028 * FIXME is this guaranteed to clear
6029 * immediately or should we poll for it?
6030 */
6031 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6032 }
6033
6034 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6035 {
6036 struct drm_device *dev = old_state->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 struct intel_atomic_state *old_intel_state =
6039 to_intel_atomic_state(old_state);
6040 unsigned req_cdclk = old_intel_state->dev_cdclk;
6041
6042 /*
6043 * FIXME: We can end up here with all power domains off, yet
6044 * with a CDCLK frequency other than the minimum. To account
6045 * for this take the PIPE-A power domain, which covers the HW
6046 * blocks needed for the following programming. This can be
6047 * removed once it's guaranteed that we get here either with
6048 * the minimum CDCLK set, or the required power domains
6049 * enabled.
6050 */
6051 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6052
6053 if (IS_CHERRYVIEW(dev))
6054 cherryview_set_cdclk(dev, req_cdclk);
6055 else
6056 valleyview_set_cdclk(dev, req_cdclk);
6057
6058 vlv_program_pfi_credits(dev_priv);
6059
6060 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6061 }
6062
6063 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6064 {
6065 struct drm_device *dev = crtc->dev;
6066 struct drm_i915_private *dev_priv = to_i915(dev);
6067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6068 struct intel_encoder *encoder;
6069 struct intel_crtc_state *pipe_config =
6070 to_intel_crtc_state(crtc->state);
6071 int pipe = intel_crtc->pipe;
6072
6073 if (WARN_ON(intel_crtc->active))
6074 return;
6075
6076 if (intel_crtc->config->has_dp_encoder)
6077 intel_dp_set_m_n(intel_crtc, M1_N1);
6078
6079 intel_set_pipe_timings(intel_crtc);
6080 intel_set_pipe_src_size(intel_crtc);
6081
6082 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6083 struct drm_i915_private *dev_priv = dev->dev_private;
6084
6085 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6086 I915_WRITE(CHV_CANVAS(pipe), 0);
6087 }
6088
6089 i9xx_set_pipeconf(intel_crtc);
6090
6091 intel_crtc->active = true;
6092
6093 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6094
6095 for_each_encoder_on_crtc(dev, crtc, encoder)
6096 if (encoder->pre_pll_enable)
6097 encoder->pre_pll_enable(encoder);
6098
6099 if (IS_CHERRYVIEW(dev)) {
6100 chv_prepare_pll(intel_crtc, intel_crtc->config);
6101 chv_enable_pll(intel_crtc, intel_crtc->config);
6102 } else {
6103 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6104 vlv_enable_pll(intel_crtc, intel_crtc->config);
6105 }
6106
6107 for_each_encoder_on_crtc(dev, crtc, encoder)
6108 if (encoder->pre_enable)
6109 encoder->pre_enable(encoder);
6110
6111 i9xx_pfit_enable(intel_crtc);
6112
6113 intel_color_load_luts(&pipe_config->base);
6114
6115 intel_update_watermarks(crtc);
6116 intel_enable_pipe(intel_crtc);
6117
6118 assert_vblank_disabled(crtc);
6119 drm_crtc_vblank_on(crtc);
6120
6121 for_each_encoder_on_crtc(dev, crtc, encoder)
6122 encoder->enable(encoder);
6123 }
6124
6125 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6126 {
6127 struct drm_device *dev = crtc->base.dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129
6130 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6131 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6132 }
6133
6134 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6135 {
6136 struct drm_device *dev = crtc->dev;
6137 struct drm_i915_private *dev_priv = to_i915(dev);
6138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139 struct intel_encoder *encoder;
6140 struct intel_crtc_state *pipe_config =
6141 to_intel_crtc_state(crtc->state);
6142 enum pipe pipe = intel_crtc->pipe;
6143
6144 if (WARN_ON(intel_crtc->active))
6145 return;
6146
6147 i9xx_set_pll_dividers(intel_crtc);
6148
6149 if (intel_crtc->config->has_dp_encoder)
6150 intel_dp_set_m_n(intel_crtc, M1_N1);
6151
6152 intel_set_pipe_timings(intel_crtc);
6153 intel_set_pipe_src_size(intel_crtc);
6154
6155 i9xx_set_pipeconf(intel_crtc);
6156
6157 intel_crtc->active = true;
6158
6159 if (!IS_GEN2(dev))
6160 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6161
6162 for_each_encoder_on_crtc(dev, crtc, encoder)
6163 if (encoder->pre_enable)
6164 encoder->pre_enable(encoder);
6165
6166 i9xx_enable_pll(intel_crtc);
6167
6168 i9xx_pfit_enable(intel_crtc);
6169
6170 intel_color_load_luts(&pipe_config->base);
6171
6172 intel_update_watermarks(crtc);
6173 intel_enable_pipe(intel_crtc);
6174
6175 assert_vblank_disabled(crtc);
6176 drm_crtc_vblank_on(crtc);
6177
6178 for_each_encoder_on_crtc(dev, crtc, encoder)
6179 encoder->enable(encoder);
6180 }
6181
6182 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6183 {
6184 struct drm_device *dev = crtc->base.dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186
6187 if (!crtc->config->gmch_pfit.control)
6188 return;
6189
6190 assert_pipe_disabled(dev_priv, crtc->pipe);
6191
6192 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6193 I915_READ(PFIT_CONTROL));
6194 I915_WRITE(PFIT_CONTROL, 0);
6195 }
6196
6197 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6198 {
6199 struct drm_device *dev = crtc->dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6202 struct intel_encoder *encoder;
6203 int pipe = intel_crtc->pipe;
6204
6205 /*
6206 * On gen2 planes are double buffered but the pipe isn't, so we must
6207 * wait for planes to fully turn off before disabling the pipe.
6208 */
6209 if (IS_GEN2(dev))
6210 intel_wait_for_vblank(dev, pipe);
6211
6212 for_each_encoder_on_crtc(dev, crtc, encoder)
6213 encoder->disable(encoder);
6214
6215 drm_crtc_vblank_off(crtc);
6216 assert_vblank_disabled(crtc);
6217
6218 intel_disable_pipe(intel_crtc);
6219
6220 i9xx_pfit_disable(intel_crtc);
6221
6222 for_each_encoder_on_crtc(dev, crtc, encoder)
6223 if (encoder->post_disable)
6224 encoder->post_disable(encoder);
6225
6226 if (!intel_crtc->config->has_dsi_encoder) {
6227 if (IS_CHERRYVIEW(dev))
6228 chv_disable_pll(dev_priv, pipe);
6229 else if (IS_VALLEYVIEW(dev))
6230 vlv_disable_pll(dev_priv, pipe);
6231 else
6232 i9xx_disable_pll(intel_crtc);
6233 }
6234
6235 for_each_encoder_on_crtc(dev, crtc, encoder)
6236 if (encoder->post_pll_disable)
6237 encoder->post_pll_disable(encoder);
6238
6239 if (!IS_GEN2(dev))
6240 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6241 }
6242
6243 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6244 {
6245 struct intel_encoder *encoder;
6246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6247 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6248 enum intel_display_power_domain domain;
6249 unsigned long domains;
6250
6251 if (!intel_crtc->active)
6252 return;
6253
6254 if (to_intel_plane_state(crtc->primary->state)->visible) {
6255 WARN_ON(intel_crtc->unpin_work);
6256
6257 intel_pre_disable_primary_noatomic(crtc);
6258
6259 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6260 to_intel_plane_state(crtc->primary->state)->visible = false;
6261 }
6262
6263 dev_priv->display.crtc_disable(crtc);
6264
6265 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6266 crtc->base.id);
6267
6268 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6269 crtc->state->active = false;
6270 intel_crtc->active = false;
6271 crtc->enabled = false;
6272 crtc->state->connector_mask = 0;
6273 crtc->state->encoder_mask = 0;
6274
6275 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6276 encoder->base.crtc = NULL;
6277
6278 intel_fbc_disable(intel_crtc);
6279 intel_update_watermarks(crtc);
6280 intel_disable_shared_dpll(intel_crtc);
6281
6282 domains = intel_crtc->enabled_power_domains;
6283 for_each_power_domain(domain, domains)
6284 intel_display_power_put(dev_priv, domain);
6285 intel_crtc->enabled_power_domains = 0;
6286
6287 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6288 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6289 }
6290
6291 /*
6292 * turn all crtc's off, but do not adjust state
6293 * This has to be paired with a call to intel_modeset_setup_hw_state.
6294 */
6295 int intel_display_suspend(struct drm_device *dev)
6296 {
6297 struct drm_i915_private *dev_priv = to_i915(dev);
6298 struct drm_atomic_state *state;
6299 int ret;
6300
6301 state = drm_atomic_helper_suspend(dev);
6302 ret = PTR_ERR_OR_ZERO(state);
6303 if (ret)
6304 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6305 else
6306 dev_priv->modeset_restore_state = state;
6307 return ret;
6308 }
6309
6310 void intel_encoder_destroy(struct drm_encoder *encoder)
6311 {
6312 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6313
6314 drm_encoder_cleanup(encoder);
6315 kfree(intel_encoder);
6316 }
6317
6318 /* Cross check the actual hw state with our own modeset state tracking (and it's
6319 * internal consistency). */
6320 static void intel_connector_verify_state(struct intel_connector *connector)
6321 {
6322 struct drm_crtc *crtc = connector->base.state->crtc;
6323
6324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6325 connector->base.base.id,
6326 connector->base.name);
6327
6328 if (connector->get_hw_state(connector)) {
6329 struct intel_encoder *encoder = connector->encoder;
6330 struct drm_connector_state *conn_state = connector->base.state;
6331
6332 I915_STATE_WARN(!crtc,
6333 "connector enabled without attached crtc\n");
6334
6335 if (!crtc)
6336 return;
6337
6338 I915_STATE_WARN(!crtc->state->active,
6339 "connector is active, but attached crtc isn't\n");
6340
6341 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6342 return;
6343
6344 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6345 "atomic encoder doesn't match attached encoder\n");
6346
6347 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6348 "attached encoder crtc differs from connector crtc\n");
6349 } else {
6350 I915_STATE_WARN(crtc && crtc->state->active,
6351 "attached crtc is active, but connector isn't\n");
6352 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6353 "best encoder set without crtc!\n");
6354 }
6355 }
6356
6357 int intel_connector_init(struct intel_connector *connector)
6358 {
6359 drm_atomic_helper_connector_reset(&connector->base);
6360
6361 if (!connector->base.state)
6362 return -ENOMEM;
6363
6364 return 0;
6365 }
6366
6367 struct intel_connector *intel_connector_alloc(void)
6368 {
6369 struct intel_connector *connector;
6370
6371 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6372 if (!connector)
6373 return NULL;
6374
6375 if (intel_connector_init(connector) < 0) {
6376 kfree(connector);
6377 return NULL;
6378 }
6379
6380 return connector;
6381 }
6382
6383 /* Simple connector->get_hw_state implementation for encoders that support only
6384 * one connector and no cloning and hence the encoder state determines the state
6385 * of the connector. */
6386 bool intel_connector_get_hw_state(struct intel_connector *connector)
6387 {
6388 enum pipe pipe = 0;
6389 struct intel_encoder *encoder = connector->encoder;
6390
6391 return encoder->get_hw_state(encoder, &pipe);
6392 }
6393
6394 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6395 {
6396 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6397 return crtc_state->fdi_lanes;
6398
6399 return 0;
6400 }
6401
6402 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6403 struct intel_crtc_state *pipe_config)
6404 {
6405 struct drm_atomic_state *state = pipe_config->base.state;
6406 struct intel_crtc *other_crtc;
6407 struct intel_crtc_state *other_crtc_state;
6408
6409 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6410 pipe_name(pipe), pipe_config->fdi_lanes);
6411 if (pipe_config->fdi_lanes > 4) {
6412 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6413 pipe_name(pipe), pipe_config->fdi_lanes);
6414 return -EINVAL;
6415 }
6416
6417 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6418 if (pipe_config->fdi_lanes > 2) {
6419 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6420 pipe_config->fdi_lanes);
6421 return -EINVAL;
6422 } else {
6423 return 0;
6424 }
6425 }
6426
6427 if (INTEL_INFO(dev)->num_pipes == 2)
6428 return 0;
6429
6430 /* Ivybridge 3 pipe is really complicated */
6431 switch (pipe) {
6432 case PIPE_A:
6433 return 0;
6434 case PIPE_B:
6435 if (pipe_config->fdi_lanes <= 2)
6436 return 0;
6437
6438 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6439 other_crtc_state =
6440 intel_atomic_get_crtc_state(state, other_crtc);
6441 if (IS_ERR(other_crtc_state))
6442 return PTR_ERR(other_crtc_state);
6443
6444 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6445 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6446 pipe_name(pipe), pipe_config->fdi_lanes);
6447 return -EINVAL;
6448 }
6449 return 0;
6450 case PIPE_C:
6451 if (pipe_config->fdi_lanes > 2) {
6452 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6453 pipe_name(pipe), pipe_config->fdi_lanes);
6454 return -EINVAL;
6455 }
6456
6457 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6458 other_crtc_state =
6459 intel_atomic_get_crtc_state(state, other_crtc);
6460 if (IS_ERR(other_crtc_state))
6461 return PTR_ERR(other_crtc_state);
6462
6463 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6464 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6465 return -EINVAL;
6466 }
6467 return 0;
6468 default:
6469 BUG();
6470 }
6471 }
6472
6473 #define RETRY 1
6474 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6475 struct intel_crtc_state *pipe_config)
6476 {
6477 struct drm_device *dev = intel_crtc->base.dev;
6478 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6479 int lane, link_bw, fdi_dotclock, ret;
6480 bool needs_recompute = false;
6481
6482 retry:
6483 /* FDI is a binary signal running at ~2.7GHz, encoding
6484 * each output octet as 10 bits. The actual frequency
6485 * is stored as a divider into a 100MHz clock, and the
6486 * mode pixel clock is stored in units of 1KHz.
6487 * Hence the bw of each lane in terms of the mode signal
6488 * is:
6489 */
6490 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6491
6492 fdi_dotclock = adjusted_mode->crtc_clock;
6493
6494 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6495 pipe_config->pipe_bpp);
6496
6497 pipe_config->fdi_lanes = lane;
6498
6499 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6500 link_bw, &pipe_config->fdi_m_n);
6501
6502 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6503 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6504 pipe_config->pipe_bpp -= 2*3;
6505 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6506 pipe_config->pipe_bpp);
6507 needs_recompute = true;
6508 pipe_config->bw_constrained = true;
6509
6510 goto retry;
6511 }
6512
6513 if (needs_recompute)
6514 return RETRY;
6515
6516 return ret;
6517 }
6518
6519 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6520 struct intel_crtc_state *pipe_config)
6521 {
6522 if (pipe_config->pipe_bpp > 24)
6523 return false;
6524
6525 /* HSW can handle pixel rate up to cdclk? */
6526 if (IS_HASWELL(dev_priv))
6527 return true;
6528
6529 /*
6530 * We compare against max which means we must take
6531 * the increased cdclk requirement into account when
6532 * calculating the new cdclk.
6533 *
6534 * Should measure whether using a lower cdclk w/o IPS
6535 */
6536 return ilk_pipe_pixel_rate(pipe_config) <=
6537 dev_priv->max_cdclk_freq * 95 / 100;
6538 }
6539
6540 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6541 struct intel_crtc_state *pipe_config)
6542 {
6543 struct drm_device *dev = crtc->base.dev;
6544 struct drm_i915_private *dev_priv = dev->dev_private;
6545
6546 pipe_config->ips_enabled = i915.enable_ips &&
6547 hsw_crtc_supports_ips(crtc) &&
6548 pipe_config_supports_ips(dev_priv, pipe_config);
6549 }
6550
6551 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6552 {
6553 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6554
6555 /* GDG double wide on either pipe, otherwise pipe A only */
6556 return INTEL_INFO(dev_priv)->gen < 4 &&
6557 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6558 }
6559
6560 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6561 struct intel_crtc_state *pipe_config)
6562 {
6563 struct drm_device *dev = crtc->base.dev;
6564 struct drm_i915_private *dev_priv = dev->dev_private;
6565 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6566
6567 /* FIXME should check pixel clock limits on all platforms */
6568 if (INTEL_INFO(dev)->gen < 4) {
6569 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6570
6571 /*
6572 * Enable double wide mode when the dot clock
6573 * is > 90% of the (display) core speed.
6574 */
6575 if (intel_crtc_supports_double_wide(crtc) &&
6576 adjusted_mode->crtc_clock > clock_limit) {
6577 clock_limit *= 2;
6578 pipe_config->double_wide = true;
6579 }
6580
6581 if (adjusted_mode->crtc_clock > clock_limit) {
6582 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6583 adjusted_mode->crtc_clock, clock_limit,
6584 yesno(pipe_config->double_wide));
6585 return -EINVAL;
6586 }
6587 }
6588
6589 /*
6590 * Pipe horizontal size must be even in:
6591 * - DVO ganged mode
6592 * - LVDS dual channel mode
6593 * - Double wide pipe
6594 */
6595 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6596 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6597 pipe_config->pipe_src_w &= ~1;
6598
6599 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6600 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6601 */
6602 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6603 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6604 return -EINVAL;
6605
6606 if (HAS_IPS(dev))
6607 hsw_compute_ips_config(crtc, pipe_config);
6608
6609 if (pipe_config->has_pch_encoder)
6610 return ironlake_fdi_compute_config(crtc, pipe_config);
6611
6612 return 0;
6613 }
6614
6615 static int skylake_get_display_clock_speed(struct drm_device *dev)
6616 {
6617 struct drm_i915_private *dev_priv = to_i915(dev);
6618 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6619 uint32_t cdctl = I915_READ(CDCLK_CTL);
6620 uint32_t linkrate;
6621
6622 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6623 return 24000; /* 24MHz is the cd freq with NSSC ref */
6624
6625 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6626 return 540000;
6627
6628 linkrate = (I915_READ(DPLL_CTRL1) &
6629 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6630
6631 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6632 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6633 /* vco 8640 */
6634 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6635 case CDCLK_FREQ_450_432:
6636 return 432000;
6637 case CDCLK_FREQ_337_308:
6638 return 308570;
6639 case CDCLK_FREQ_675_617:
6640 return 617140;
6641 default:
6642 WARN(1, "Unknown cd freq selection\n");
6643 }
6644 } else {
6645 /* vco 8100 */
6646 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6647 case CDCLK_FREQ_450_432:
6648 return 450000;
6649 case CDCLK_FREQ_337_308:
6650 return 337500;
6651 case CDCLK_FREQ_675_617:
6652 return 675000;
6653 default:
6654 WARN(1, "Unknown cd freq selection\n");
6655 }
6656 }
6657
6658 /* error case, do as if DPLL0 isn't enabled */
6659 return 24000;
6660 }
6661
6662 static int broxton_get_display_clock_speed(struct drm_device *dev)
6663 {
6664 struct drm_i915_private *dev_priv = to_i915(dev);
6665 uint32_t cdctl = I915_READ(CDCLK_CTL);
6666 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6667 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6668 int cdclk;
6669
6670 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6671 return 19200;
6672
6673 cdclk = 19200 * pll_ratio / 2;
6674
6675 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6676 case BXT_CDCLK_CD2X_DIV_SEL_1:
6677 return cdclk; /* 576MHz or 624MHz */
6678 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6679 return cdclk * 2 / 3; /* 384MHz */
6680 case BXT_CDCLK_CD2X_DIV_SEL_2:
6681 return cdclk / 2; /* 288MHz */
6682 case BXT_CDCLK_CD2X_DIV_SEL_4:
6683 return cdclk / 4; /* 144MHz */
6684 }
6685
6686 /* error case, do as if DE PLL isn't enabled */
6687 return 19200;
6688 }
6689
6690 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6691 {
6692 struct drm_i915_private *dev_priv = dev->dev_private;
6693 uint32_t lcpll = I915_READ(LCPLL_CTL);
6694 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6695
6696 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6697 return 800000;
6698 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6699 return 450000;
6700 else if (freq == LCPLL_CLK_FREQ_450)
6701 return 450000;
6702 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6703 return 540000;
6704 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6705 return 337500;
6706 else
6707 return 675000;
6708 }
6709
6710 static int haswell_get_display_clock_speed(struct drm_device *dev)
6711 {
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713 uint32_t lcpll = I915_READ(LCPLL_CTL);
6714 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6715
6716 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6717 return 800000;
6718 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6719 return 450000;
6720 else if (freq == LCPLL_CLK_FREQ_450)
6721 return 450000;
6722 else if (IS_HSW_ULT(dev))
6723 return 337500;
6724 else
6725 return 540000;
6726 }
6727
6728 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6729 {
6730 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6731 CCK_DISPLAY_CLOCK_CONTROL);
6732 }
6733
6734 static int ilk_get_display_clock_speed(struct drm_device *dev)
6735 {
6736 return 450000;
6737 }
6738
6739 static int i945_get_display_clock_speed(struct drm_device *dev)
6740 {
6741 return 400000;
6742 }
6743
6744 static int i915_get_display_clock_speed(struct drm_device *dev)
6745 {
6746 return 333333;
6747 }
6748
6749 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6750 {
6751 return 200000;
6752 }
6753
6754 static int pnv_get_display_clock_speed(struct drm_device *dev)
6755 {
6756 u16 gcfgc = 0;
6757
6758 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6759
6760 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6761 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6762 return 266667;
6763 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6764 return 333333;
6765 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6766 return 444444;
6767 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6768 return 200000;
6769 default:
6770 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6771 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6772 return 133333;
6773 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6774 return 166667;
6775 }
6776 }
6777
6778 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6779 {
6780 u16 gcfgc = 0;
6781
6782 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6783
6784 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6785 return 133333;
6786 else {
6787 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6788 case GC_DISPLAY_CLOCK_333_MHZ:
6789 return 333333;
6790 default:
6791 case GC_DISPLAY_CLOCK_190_200_MHZ:
6792 return 190000;
6793 }
6794 }
6795 }
6796
6797 static int i865_get_display_clock_speed(struct drm_device *dev)
6798 {
6799 return 266667;
6800 }
6801
6802 static int i85x_get_display_clock_speed(struct drm_device *dev)
6803 {
6804 u16 hpllcc = 0;
6805
6806 /*
6807 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6808 * encoding is different :(
6809 * FIXME is this the right way to detect 852GM/852GMV?
6810 */
6811 if (dev->pdev->revision == 0x1)
6812 return 133333;
6813
6814 pci_bus_read_config_word(dev->pdev->bus,
6815 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6816
6817 /* Assume that the hardware is in the high speed state. This
6818 * should be the default.
6819 */
6820 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6821 case GC_CLOCK_133_200:
6822 case GC_CLOCK_133_200_2:
6823 case GC_CLOCK_100_200:
6824 return 200000;
6825 case GC_CLOCK_166_250:
6826 return 250000;
6827 case GC_CLOCK_100_133:
6828 return 133333;
6829 case GC_CLOCK_133_266:
6830 case GC_CLOCK_133_266_2:
6831 case GC_CLOCK_166_266:
6832 return 266667;
6833 }
6834
6835 /* Shouldn't happen */
6836 return 0;
6837 }
6838
6839 static int i830_get_display_clock_speed(struct drm_device *dev)
6840 {
6841 return 133333;
6842 }
6843
6844 static unsigned int intel_hpll_vco(struct drm_device *dev)
6845 {
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 static const unsigned int blb_vco[8] = {
6848 [0] = 3200000,
6849 [1] = 4000000,
6850 [2] = 5333333,
6851 [3] = 4800000,
6852 [4] = 6400000,
6853 };
6854 static const unsigned int pnv_vco[8] = {
6855 [0] = 3200000,
6856 [1] = 4000000,
6857 [2] = 5333333,
6858 [3] = 4800000,
6859 [4] = 2666667,
6860 };
6861 static const unsigned int cl_vco[8] = {
6862 [0] = 3200000,
6863 [1] = 4000000,
6864 [2] = 5333333,
6865 [3] = 6400000,
6866 [4] = 3333333,
6867 [5] = 3566667,
6868 [6] = 4266667,
6869 };
6870 static const unsigned int elk_vco[8] = {
6871 [0] = 3200000,
6872 [1] = 4000000,
6873 [2] = 5333333,
6874 [3] = 4800000,
6875 };
6876 static const unsigned int ctg_vco[8] = {
6877 [0] = 3200000,
6878 [1] = 4000000,
6879 [2] = 5333333,
6880 [3] = 6400000,
6881 [4] = 2666667,
6882 [5] = 4266667,
6883 };
6884 const unsigned int *vco_table;
6885 unsigned int vco;
6886 uint8_t tmp = 0;
6887
6888 /* FIXME other chipsets? */
6889 if (IS_GM45(dev))
6890 vco_table = ctg_vco;
6891 else if (IS_G4X(dev))
6892 vco_table = elk_vco;
6893 else if (IS_CRESTLINE(dev))
6894 vco_table = cl_vco;
6895 else if (IS_PINEVIEW(dev))
6896 vco_table = pnv_vco;
6897 else if (IS_G33(dev))
6898 vco_table = blb_vco;
6899 else
6900 return 0;
6901
6902 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6903
6904 vco = vco_table[tmp & 0x7];
6905 if (vco == 0)
6906 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6907 else
6908 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6909
6910 return vco;
6911 }
6912
6913 static int gm45_get_display_clock_speed(struct drm_device *dev)
6914 {
6915 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6916 uint16_t tmp = 0;
6917
6918 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6919
6920 cdclk_sel = (tmp >> 12) & 0x1;
6921
6922 switch (vco) {
6923 case 2666667:
6924 case 4000000:
6925 case 5333333:
6926 return cdclk_sel ? 333333 : 222222;
6927 case 3200000:
6928 return cdclk_sel ? 320000 : 228571;
6929 default:
6930 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6931 return 222222;
6932 }
6933 }
6934
6935 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6936 {
6937 static const uint8_t div_3200[] = { 16, 10, 8 };
6938 static const uint8_t div_4000[] = { 20, 12, 10 };
6939 static const uint8_t div_5333[] = { 24, 16, 14 };
6940 const uint8_t *div_table;
6941 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6942 uint16_t tmp = 0;
6943
6944 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6945
6946 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6947
6948 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6949 goto fail;
6950
6951 switch (vco) {
6952 case 3200000:
6953 div_table = div_3200;
6954 break;
6955 case 4000000:
6956 div_table = div_4000;
6957 break;
6958 case 5333333:
6959 div_table = div_5333;
6960 break;
6961 default:
6962 goto fail;
6963 }
6964
6965 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6966
6967 fail:
6968 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6969 return 200000;
6970 }
6971
6972 static int g33_get_display_clock_speed(struct drm_device *dev)
6973 {
6974 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6975 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6976 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6977 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6978 const uint8_t *div_table;
6979 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6980 uint16_t tmp = 0;
6981
6982 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6983
6984 cdclk_sel = (tmp >> 4) & 0x7;
6985
6986 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6987 goto fail;
6988
6989 switch (vco) {
6990 case 3200000:
6991 div_table = div_3200;
6992 break;
6993 case 4000000:
6994 div_table = div_4000;
6995 break;
6996 case 4800000:
6997 div_table = div_4800;
6998 break;
6999 case 5333333:
7000 div_table = div_5333;
7001 break;
7002 default:
7003 goto fail;
7004 }
7005
7006 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7007
7008 fail:
7009 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7010 return 190476;
7011 }
7012
7013 static void
7014 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7015 {
7016 while (*num > DATA_LINK_M_N_MASK ||
7017 *den > DATA_LINK_M_N_MASK) {
7018 *num >>= 1;
7019 *den >>= 1;
7020 }
7021 }
7022
7023 static void compute_m_n(unsigned int m, unsigned int n,
7024 uint32_t *ret_m, uint32_t *ret_n)
7025 {
7026 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7027 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7028 intel_reduce_m_n_ratio(ret_m, ret_n);
7029 }
7030
7031 void
7032 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7033 int pixel_clock, int link_clock,
7034 struct intel_link_m_n *m_n)
7035 {
7036 m_n->tu = 64;
7037
7038 compute_m_n(bits_per_pixel * pixel_clock,
7039 link_clock * nlanes * 8,
7040 &m_n->gmch_m, &m_n->gmch_n);
7041
7042 compute_m_n(pixel_clock, link_clock,
7043 &m_n->link_m, &m_n->link_n);
7044 }
7045
7046 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7047 {
7048 if (i915.panel_use_ssc >= 0)
7049 return i915.panel_use_ssc != 0;
7050 return dev_priv->vbt.lvds_use_ssc
7051 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7052 }
7053
7054 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7055 {
7056 return (1 << dpll->n) << 16 | dpll->m2;
7057 }
7058
7059 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7060 {
7061 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7062 }
7063
7064 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7065 struct intel_crtc_state *crtc_state,
7066 intel_clock_t *reduced_clock)
7067 {
7068 struct drm_device *dev = crtc->base.dev;
7069 u32 fp, fp2 = 0;
7070
7071 if (IS_PINEVIEW(dev)) {
7072 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7073 if (reduced_clock)
7074 fp2 = pnv_dpll_compute_fp(reduced_clock);
7075 } else {
7076 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7077 if (reduced_clock)
7078 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7079 }
7080
7081 crtc_state->dpll_hw_state.fp0 = fp;
7082
7083 crtc->lowfreq_avail = false;
7084 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7085 reduced_clock) {
7086 crtc_state->dpll_hw_state.fp1 = fp2;
7087 crtc->lowfreq_avail = true;
7088 } else {
7089 crtc_state->dpll_hw_state.fp1 = fp;
7090 }
7091 }
7092
7093 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7094 pipe)
7095 {
7096 u32 reg_val;
7097
7098 /*
7099 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7100 * and set it to a reasonable value instead.
7101 */
7102 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7103 reg_val &= 0xffffff00;
7104 reg_val |= 0x00000030;
7105 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7106
7107 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7108 reg_val &= 0x8cffffff;
7109 reg_val = 0x8c000000;
7110 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7111
7112 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7113 reg_val &= 0xffffff00;
7114 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7115
7116 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7117 reg_val &= 0x00ffffff;
7118 reg_val |= 0xb0000000;
7119 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7120 }
7121
7122 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7123 struct intel_link_m_n *m_n)
7124 {
7125 struct drm_device *dev = crtc->base.dev;
7126 struct drm_i915_private *dev_priv = dev->dev_private;
7127 int pipe = crtc->pipe;
7128
7129 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7130 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7131 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7132 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7133 }
7134
7135 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7136 struct intel_link_m_n *m_n,
7137 struct intel_link_m_n *m2_n2)
7138 {
7139 struct drm_device *dev = crtc->base.dev;
7140 struct drm_i915_private *dev_priv = dev->dev_private;
7141 int pipe = crtc->pipe;
7142 enum transcoder transcoder = crtc->config->cpu_transcoder;
7143
7144 if (INTEL_INFO(dev)->gen >= 5) {
7145 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7146 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7147 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7148 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7149 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7150 * for gen < 8) and if DRRS is supported (to make sure the
7151 * registers are not unnecessarily accessed).
7152 */
7153 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7154 crtc->config->has_drrs) {
7155 I915_WRITE(PIPE_DATA_M2(transcoder),
7156 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7157 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7158 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7159 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7160 }
7161 } else {
7162 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7163 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7164 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7165 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7166 }
7167 }
7168
7169 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7170 {
7171 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7172
7173 if (m_n == M1_N1) {
7174 dp_m_n = &crtc->config->dp_m_n;
7175 dp_m2_n2 = &crtc->config->dp_m2_n2;
7176 } else if (m_n == M2_N2) {
7177
7178 /*
7179 * M2_N2 registers are not supported. Hence m2_n2 divider value
7180 * needs to be programmed into M1_N1.
7181 */
7182 dp_m_n = &crtc->config->dp_m2_n2;
7183 } else {
7184 DRM_ERROR("Unsupported divider value\n");
7185 return;
7186 }
7187
7188 if (crtc->config->has_pch_encoder)
7189 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7190 else
7191 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7192 }
7193
7194 static void vlv_compute_dpll(struct intel_crtc *crtc,
7195 struct intel_crtc_state *pipe_config)
7196 {
7197 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7198 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7199 if (crtc->pipe != PIPE_A)
7200 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7201
7202 /* DPLL not used with DSI, but still need the rest set up */
7203 if (!pipe_config->has_dsi_encoder)
7204 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7205 DPLL_EXT_BUFFER_ENABLE_VLV;
7206
7207 pipe_config->dpll_hw_state.dpll_md =
7208 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7209 }
7210
7211 static void chv_compute_dpll(struct intel_crtc *crtc,
7212 struct intel_crtc_state *pipe_config)
7213 {
7214 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7215 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7216 if (crtc->pipe != PIPE_A)
7217 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7218
7219 /* DPLL not used with DSI, but still need the rest set up */
7220 if (!pipe_config->has_dsi_encoder)
7221 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7222
7223 pipe_config->dpll_hw_state.dpll_md =
7224 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7225 }
7226
7227 static void vlv_prepare_pll(struct intel_crtc *crtc,
7228 const struct intel_crtc_state *pipe_config)
7229 {
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 enum pipe pipe = crtc->pipe;
7233 u32 mdiv;
7234 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7235 u32 coreclk, reg_val;
7236
7237 /* Enable Refclk */
7238 I915_WRITE(DPLL(pipe),
7239 pipe_config->dpll_hw_state.dpll &
7240 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7241
7242 /* No need to actually set up the DPLL with DSI */
7243 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7244 return;
7245
7246 mutex_lock(&dev_priv->sb_lock);
7247
7248 bestn = pipe_config->dpll.n;
7249 bestm1 = pipe_config->dpll.m1;
7250 bestm2 = pipe_config->dpll.m2;
7251 bestp1 = pipe_config->dpll.p1;
7252 bestp2 = pipe_config->dpll.p2;
7253
7254 /* See eDP HDMI DPIO driver vbios notes doc */
7255
7256 /* PLL B needs special handling */
7257 if (pipe == PIPE_B)
7258 vlv_pllb_recal_opamp(dev_priv, pipe);
7259
7260 /* Set up Tx target for periodic Rcomp update */
7261 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7262
7263 /* Disable target IRef on PLL */
7264 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7265 reg_val &= 0x00ffffff;
7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7267
7268 /* Disable fast lock */
7269 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7270
7271 /* Set idtafcrecal before PLL is enabled */
7272 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7273 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7274 mdiv |= ((bestn << DPIO_N_SHIFT));
7275 mdiv |= (1 << DPIO_K_SHIFT);
7276
7277 /*
7278 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7279 * but we don't support that).
7280 * Note: don't use the DAC post divider as it seems unstable.
7281 */
7282 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7284
7285 mdiv |= DPIO_ENABLE_CALIBRATION;
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7287
7288 /* Set HBR and RBR LPF coefficients */
7289 if (pipe_config->port_clock == 162000 ||
7290 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7291 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7293 0x009f0003);
7294 else
7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7296 0x00d0000f);
7297
7298 if (pipe_config->has_dp_encoder) {
7299 /* Use SSC source */
7300 if (pipe == PIPE_A)
7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7302 0x0df40000);
7303 else
7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7305 0x0df70000);
7306 } else { /* HDMI or VGA */
7307 /* Use bend source */
7308 if (pipe == PIPE_A)
7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7310 0x0df70000);
7311 else
7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7313 0x0df40000);
7314 }
7315
7316 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7317 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7318 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7319 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7320 coreclk |= 0x01000000;
7321 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7322
7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7324 mutex_unlock(&dev_priv->sb_lock);
7325 }
7326
7327 static void chv_prepare_pll(struct intel_crtc *crtc,
7328 const struct intel_crtc_state *pipe_config)
7329 {
7330 struct drm_device *dev = crtc->base.dev;
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 enum pipe pipe = crtc->pipe;
7333 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7334 u32 loopfilter, tribuf_calcntr;
7335 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7336 u32 dpio_val;
7337 int vco;
7338
7339 /* Enable Refclk and SSC */
7340 I915_WRITE(DPLL(pipe),
7341 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7342
7343 /* No need to actually set up the DPLL with DSI */
7344 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7345 return;
7346
7347 bestn = pipe_config->dpll.n;
7348 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7349 bestm1 = pipe_config->dpll.m1;
7350 bestm2 = pipe_config->dpll.m2 >> 22;
7351 bestp1 = pipe_config->dpll.p1;
7352 bestp2 = pipe_config->dpll.p2;
7353 vco = pipe_config->dpll.vco;
7354 dpio_val = 0;
7355 loopfilter = 0;
7356
7357 mutex_lock(&dev_priv->sb_lock);
7358
7359 /* p1 and p2 divider */
7360 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7361 5 << DPIO_CHV_S1_DIV_SHIFT |
7362 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7363 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7364 1 << DPIO_CHV_K_DIV_SHIFT);
7365
7366 /* Feedback post-divider - m2 */
7367 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7368
7369 /* Feedback refclk divider - n and m1 */
7370 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7371 DPIO_CHV_M1_DIV_BY_2 |
7372 1 << DPIO_CHV_N_DIV_SHIFT);
7373
7374 /* M2 fraction division */
7375 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7376
7377 /* M2 fraction division enable */
7378 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7379 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7380 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7381 if (bestm2_frac)
7382 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7384
7385 /* Program digital lock detect threshold */
7386 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7387 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7388 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7389 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7390 if (!bestm2_frac)
7391 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7392 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7393
7394 /* Loop filter */
7395 if (vco == 5400000) {
7396 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7397 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7398 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7399 tribuf_calcntr = 0x9;
7400 } else if (vco <= 6200000) {
7401 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7402 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7403 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7404 tribuf_calcntr = 0x9;
7405 } else if (vco <= 6480000) {
7406 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7407 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7408 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7409 tribuf_calcntr = 0x8;
7410 } else {
7411 /* Not supported. Apply the same limits as in the max case */
7412 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7413 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7414 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7415 tribuf_calcntr = 0;
7416 }
7417 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7418
7419 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7420 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7421 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7422 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7423
7424 /* AFC Recal */
7425 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7426 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7427 DPIO_AFC_RECAL);
7428
7429 mutex_unlock(&dev_priv->sb_lock);
7430 }
7431
7432 /**
7433 * vlv_force_pll_on - forcibly enable just the PLL
7434 * @dev_priv: i915 private structure
7435 * @pipe: pipe PLL to enable
7436 * @dpll: PLL configuration
7437 *
7438 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7439 * in cases where we need the PLL enabled even when @pipe is not going to
7440 * be enabled.
7441 */
7442 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7443 const struct dpll *dpll)
7444 {
7445 struct intel_crtc *crtc =
7446 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7447 struct intel_crtc_state *pipe_config;
7448
7449 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7450 if (!pipe_config)
7451 return -ENOMEM;
7452
7453 pipe_config->base.crtc = &crtc->base;
7454 pipe_config->pixel_multiplier = 1;
7455 pipe_config->dpll = *dpll;
7456
7457 if (IS_CHERRYVIEW(dev)) {
7458 chv_compute_dpll(crtc, pipe_config);
7459 chv_prepare_pll(crtc, pipe_config);
7460 chv_enable_pll(crtc, pipe_config);
7461 } else {
7462 vlv_compute_dpll(crtc, pipe_config);
7463 vlv_prepare_pll(crtc, pipe_config);
7464 vlv_enable_pll(crtc, pipe_config);
7465 }
7466
7467 kfree(pipe_config);
7468
7469 return 0;
7470 }
7471
7472 /**
7473 * vlv_force_pll_off - forcibly disable just the PLL
7474 * @dev_priv: i915 private structure
7475 * @pipe: pipe PLL to disable
7476 *
7477 * Disable the PLL for @pipe. To be used in cases where we need
7478 * the PLL enabled even when @pipe is not going to be enabled.
7479 */
7480 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7481 {
7482 if (IS_CHERRYVIEW(dev))
7483 chv_disable_pll(to_i915(dev), pipe);
7484 else
7485 vlv_disable_pll(to_i915(dev), pipe);
7486 }
7487
7488 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7489 struct intel_crtc_state *crtc_state,
7490 intel_clock_t *reduced_clock)
7491 {
7492 struct drm_device *dev = crtc->base.dev;
7493 struct drm_i915_private *dev_priv = dev->dev_private;
7494 u32 dpll;
7495 bool is_sdvo;
7496 struct dpll *clock = &crtc_state->dpll;
7497
7498 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7499
7500 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7502
7503 dpll = DPLL_VGA_MODE_DIS;
7504
7505 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7506 dpll |= DPLLB_MODE_LVDS;
7507 else
7508 dpll |= DPLLB_MODE_DAC_SERIAL;
7509
7510 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7511 dpll |= (crtc_state->pixel_multiplier - 1)
7512 << SDVO_MULTIPLIER_SHIFT_HIRES;
7513 }
7514
7515 if (is_sdvo)
7516 dpll |= DPLL_SDVO_HIGH_SPEED;
7517
7518 if (crtc_state->has_dp_encoder)
7519 dpll |= DPLL_SDVO_HIGH_SPEED;
7520
7521 /* compute bitmask from p1 value */
7522 if (IS_PINEVIEW(dev))
7523 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7524 else {
7525 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7526 if (IS_G4X(dev) && reduced_clock)
7527 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7528 }
7529 switch (clock->p2) {
7530 case 5:
7531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7532 break;
7533 case 7:
7534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7535 break;
7536 case 10:
7537 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7538 break;
7539 case 14:
7540 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7541 break;
7542 }
7543 if (INTEL_INFO(dev)->gen >= 4)
7544 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7545
7546 if (crtc_state->sdvo_tv_clock)
7547 dpll |= PLL_REF_INPUT_TVCLKINBC;
7548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7549 intel_panel_use_ssc(dev_priv))
7550 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7551 else
7552 dpll |= PLL_REF_INPUT_DREFCLK;
7553
7554 dpll |= DPLL_VCO_ENABLE;
7555 crtc_state->dpll_hw_state.dpll = dpll;
7556
7557 if (INTEL_INFO(dev)->gen >= 4) {
7558 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7559 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7560 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7561 }
7562 }
7563
7564 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7565 struct intel_crtc_state *crtc_state,
7566 intel_clock_t *reduced_clock)
7567 {
7568 struct drm_device *dev = crtc->base.dev;
7569 struct drm_i915_private *dev_priv = dev->dev_private;
7570 u32 dpll;
7571 struct dpll *clock = &crtc_state->dpll;
7572
7573 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7574
7575 dpll = DPLL_VGA_MODE_DIS;
7576
7577 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7578 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579 } else {
7580 if (clock->p1 == 2)
7581 dpll |= PLL_P1_DIVIDE_BY_TWO;
7582 else
7583 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7584 if (clock->p2 == 4)
7585 dpll |= PLL_P2_DIVIDE_BY_4;
7586 }
7587
7588 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7589 dpll |= DPLL_DVO_2X_MODE;
7590
7591 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7592 intel_panel_use_ssc(dev_priv))
7593 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7594 else
7595 dpll |= PLL_REF_INPUT_DREFCLK;
7596
7597 dpll |= DPLL_VCO_ENABLE;
7598 crtc_state->dpll_hw_state.dpll = dpll;
7599 }
7600
7601 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7602 {
7603 struct drm_device *dev = intel_crtc->base.dev;
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 enum pipe pipe = intel_crtc->pipe;
7606 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7607 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7608 uint32_t crtc_vtotal, crtc_vblank_end;
7609 int vsyncshift = 0;
7610
7611 /* We need to be careful not to changed the adjusted mode, for otherwise
7612 * the hw state checker will get angry at the mismatch. */
7613 crtc_vtotal = adjusted_mode->crtc_vtotal;
7614 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7615
7616 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7617 /* the chip adds 2 halflines automatically */
7618 crtc_vtotal -= 1;
7619 crtc_vblank_end -= 1;
7620
7621 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7622 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7623 else
7624 vsyncshift = adjusted_mode->crtc_hsync_start -
7625 adjusted_mode->crtc_htotal / 2;
7626 if (vsyncshift < 0)
7627 vsyncshift += adjusted_mode->crtc_htotal;
7628 }
7629
7630 if (INTEL_INFO(dev)->gen > 3)
7631 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7632
7633 I915_WRITE(HTOTAL(cpu_transcoder),
7634 (adjusted_mode->crtc_hdisplay - 1) |
7635 ((adjusted_mode->crtc_htotal - 1) << 16));
7636 I915_WRITE(HBLANK(cpu_transcoder),
7637 (adjusted_mode->crtc_hblank_start - 1) |
7638 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7639 I915_WRITE(HSYNC(cpu_transcoder),
7640 (adjusted_mode->crtc_hsync_start - 1) |
7641 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7642
7643 I915_WRITE(VTOTAL(cpu_transcoder),
7644 (adjusted_mode->crtc_vdisplay - 1) |
7645 ((crtc_vtotal - 1) << 16));
7646 I915_WRITE(VBLANK(cpu_transcoder),
7647 (adjusted_mode->crtc_vblank_start - 1) |
7648 ((crtc_vblank_end - 1) << 16));
7649 I915_WRITE(VSYNC(cpu_transcoder),
7650 (adjusted_mode->crtc_vsync_start - 1) |
7651 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7652
7653 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7654 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7655 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7656 * bits. */
7657 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7658 (pipe == PIPE_B || pipe == PIPE_C))
7659 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7660
7661 }
7662
7663 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7664 {
7665 struct drm_device *dev = intel_crtc->base.dev;
7666 struct drm_i915_private *dev_priv = dev->dev_private;
7667 enum pipe pipe = intel_crtc->pipe;
7668
7669 /* pipesrc controls the size that is scaled from, which should
7670 * always be the user's requested size.
7671 */
7672 I915_WRITE(PIPESRC(pipe),
7673 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7674 (intel_crtc->config->pipe_src_h - 1));
7675 }
7676
7677 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7678 struct intel_crtc_state *pipe_config)
7679 {
7680 struct drm_device *dev = crtc->base.dev;
7681 struct drm_i915_private *dev_priv = dev->dev_private;
7682 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7683 uint32_t tmp;
7684
7685 tmp = I915_READ(HTOTAL(cpu_transcoder));
7686 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7688 tmp = I915_READ(HBLANK(cpu_transcoder));
7689 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7691 tmp = I915_READ(HSYNC(cpu_transcoder));
7692 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7694
7695 tmp = I915_READ(VTOTAL(cpu_transcoder));
7696 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7697 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7698 tmp = I915_READ(VBLANK(cpu_transcoder));
7699 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7700 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7701 tmp = I915_READ(VSYNC(cpu_transcoder));
7702 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7703 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7704
7705 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7706 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7707 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7708 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7709 }
7710 }
7711
7712 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7713 struct intel_crtc_state *pipe_config)
7714 {
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7717 u32 tmp;
7718
7719 tmp = I915_READ(PIPESRC(crtc->pipe));
7720 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7721 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7722
7723 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7724 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7725 }
7726
7727 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7728 struct intel_crtc_state *pipe_config)
7729 {
7730 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7731 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7732 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7733 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7734
7735 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7736 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7737 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7738 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7739
7740 mode->flags = pipe_config->base.adjusted_mode.flags;
7741 mode->type = DRM_MODE_TYPE_DRIVER;
7742
7743 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7744 mode->flags |= pipe_config->base.adjusted_mode.flags;
7745
7746 mode->hsync = drm_mode_hsync(mode);
7747 mode->vrefresh = drm_mode_vrefresh(mode);
7748 drm_mode_set_name(mode);
7749 }
7750
7751 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7752 {
7753 struct drm_device *dev = intel_crtc->base.dev;
7754 struct drm_i915_private *dev_priv = dev->dev_private;
7755 uint32_t pipeconf;
7756
7757 pipeconf = 0;
7758
7759 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7760 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7761 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7762
7763 if (intel_crtc->config->double_wide)
7764 pipeconf |= PIPECONF_DOUBLE_WIDE;
7765
7766 /* only g4x and later have fancy bpc/dither controls */
7767 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7768 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7769 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7770 pipeconf |= PIPECONF_DITHER_EN |
7771 PIPECONF_DITHER_TYPE_SP;
7772
7773 switch (intel_crtc->config->pipe_bpp) {
7774 case 18:
7775 pipeconf |= PIPECONF_6BPC;
7776 break;
7777 case 24:
7778 pipeconf |= PIPECONF_8BPC;
7779 break;
7780 case 30:
7781 pipeconf |= PIPECONF_10BPC;
7782 break;
7783 default:
7784 /* Case prevented by intel_choose_pipe_bpp_dither. */
7785 BUG();
7786 }
7787 }
7788
7789 if (HAS_PIPE_CXSR(dev)) {
7790 if (intel_crtc->lowfreq_avail) {
7791 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7792 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7793 } else {
7794 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7795 }
7796 }
7797
7798 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7799 if (INTEL_INFO(dev)->gen < 4 ||
7800 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7801 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7802 else
7803 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7804 } else
7805 pipeconf |= PIPECONF_PROGRESSIVE;
7806
7807 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7808 intel_crtc->config->limited_color_range)
7809 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7810
7811 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7812 POSTING_READ(PIPECONF(intel_crtc->pipe));
7813 }
7814
7815 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7816 struct intel_crtc_state *crtc_state)
7817 {
7818 struct drm_device *dev = crtc->base.dev;
7819 struct drm_i915_private *dev_priv = dev->dev_private;
7820 const intel_limit_t *limit;
7821 int refclk = 48000;
7822
7823 memset(&crtc_state->dpll_hw_state, 0,
7824 sizeof(crtc_state->dpll_hw_state));
7825
7826 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7827 if (intel_panel_use_ssc(dev_priv)) {
7828 refclk = dev_priv->vbt.lvds_ssc_freq;
7829 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7830 }
7831
7832 limit = &intel_limits_i8xx_lvds;
7833 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7834 limit = &intel_limits_i8xx_dvo;
7835 } else {
7836 limit = &intel_limits_i8xx_dac;
7837 }
7838
7839 if (!crtc_state->clock_set &&
7840 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7841 refclk, NULL, &crtc_state->dpll)) {
7842 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7843 return -EINVAL;
7844 }
7845
7846 i8xx_compute_dpll(crtc, crtc_state, NULL);
7847
7848 return 0;
7849 }
7850
7851 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7852 struct intel_crtc_state *crtc_state)
7853 {
7854 struct drm_device *dev = crtc->base.dev;
7855 struct drm_i915_private *dev_priv = dev->dev_private;
7856 const intel_limit_t *limit;
7857 int refclk = 96000;
7858
7859 memset(&crtc_state->dpll_hw_state, 0,
7860 sizeof(crtc_state->dpll_hw_state));
7861
7862 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7863 if (intel_panel_use_ssc(dev_priv)) {
7864 refclk = dev_priv->vbt.lvds_ssc_freq;
7865 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7866 }
7867
7868 if (intel_is_dual_link_lvds(dev))
7869 limit = &intel_limits_g4x_dual_channel_lvds;
7870 else
7871 limit = &intel_limits_g4x_single_channel_lvds;
7872 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7873 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7874 limit = &intel_limits_g4x_hdmi;
7875 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7876 limit = &intel_limits_g4x_sdvo;
7877 } else {
7878 /* The option is for other outputs */
7879 limit = &intel_limits_i9xx_sdvo;
7880 }
7881
7882 if (!crtc_state->clock_set &&
7883 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7884 refclk, NULL, &crtc_state->dpll)) {
7885 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7886 return -EINVAL;
7887 }
7888
7889 i9xx_compute_dpll(crtc, crtc_state, NULL);
7890
7891 return 0;
7892 }
7893
7894 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7895 struct intel_crtc_state *crtc_state)
7896 {
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 const intel_limit_t *limit;
7900 int refclk = 96000;
7901
7902 memset(&crtc_state->dpll_hw_state, 0,
7903 sizeof(crtc_state->dpll_hw_state));
7904
7905 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7906 if (intel_panel_use_ssc(dev_priv)) {
7907 refclk = dev_priv->vbt.lvds_ssc_freq;
7908 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7909 }
7910
7911 limit = &intel_limits_pineview_lvds;
7912 } else {
7913 limit = &intel_limits_pineview_sdvo;
7914 }
7915
7916 if (!crtc_state->clock_set &&
7917 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7918 refclk, NULL, &crtc_state->dpll)) {
7919 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7920 return -EINVAL;
7921 }
7922
7923 i9xx_compute_dpll(crtc, crtc_state, NULL);
7924
7925 return 0;
7926 }
7927
7928 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7929 struct intel_crtc_state *crtc_state)
7930 {
7931 struct drm_device *dev = crtc->base.dev;
7932 struct drm_i915_private *dev_priv = dev->dev_private;
7933 const intel_limit_t *limit;
7934 int refclk = 96000;
7935
7936 memset(&crtc_state->dpll_hw_state, 0,
7937 sizeof(crtc_state->dpll_hw_state));
7938
7939 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7940 if (intel_panel_use_ssc(dev_priv)) {
7941 refclk = dev_priv->vbt.lvds_ssc_freq;
7942 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7943 }
7944
7945 limit = &intel_limits_i9xx_lvds;
7946 } else {
7947 limit = &intel_limits_i9xx_sdvo;
7948 }
7949
7950 if (!crtc_state->clock_set &&
7951 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7952 refclk, NULL, &crtc_state->dpll)) {
7953 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7954 return -EINVAL;
7955 }
7956
7957 i9xx_compute_dpll(crtc, crtc_state, NULL);
7958
7959 return 0;
7960 }
7961
7962 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7963 struct intel_crtc_state *crtc_state)
7964 {
7965 int refclk = 100000;
7966 const intel_limit_t *limit = &intel_limits_chv;
7967
7968 memset(&crtc_state->dpll_hw_state, 0,
7969 sizeof(crtc_state->dpll_hw_state));
7970
7971 if (!crtc_state->clock_set &&
7972 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7973 refclk, NULL, &crtc_state->dpll)) {
7974 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7975 return -EINVAL;
7976 }
7977
7978 chv_compute_dpll(crtc, crtc_state);
7979
7980 return 0;
7981 }
7982
7983 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7984 struct intel_crtc_state *crtc_state)
7985 {
7986 int refclk = 100000;
7987 const intel_limit_t *limit = &intel_limits_vlv;
7988
7989 memset(&crtc_state->dpll_hw_state, 0,
7990 sizeof(crtc_state->dpll_hw_state));
7991
7992 if (!crtc_state->clock_set &&
7993 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7994 refclk, NULL, &crtc_state->dpll)) {
7995 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7996 return -EINVAL;
7997 }
7998
7999 vlv_compute_dpll(crtc, crtc_state);
8000
8001 return 0;
8002 }
8003
8004 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8005 struct intel_crtc_state *pipe_config)
8006 {
8007 struct drm_device *dev = crtc->base.dev;
8008 struct drm_i915_private *dev_priv = dev->dev_private;
8009 uint32_t tmp;
8010
8011 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8012 return;
8013
8014 tmp = I915_READ(PFIT_CONTROL);
8015 if (!(tmp & PFIT_ENABLE))
8016 return;
8017
8018 /* Check whether the pfit is attached to our pipe. */
8019 if (INTEL_INFO(dev)->gen < 4) {
8020 if (crtc->pipe != PIPE_B)
8021 return;
8022 } else {
8023 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8024 return;
8025 }
8026
8027 pipe_config->gmch_pfit.control = tmp;
8028 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8029 }
8030
8031 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8032 struct intel_crtc_state *pipe_config)
8033 {
8034 struct drm_device *dev = crtc->base.dev;
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 int pipe = pipe_config->cpu_transcoder;
8037 intel_clock_t clock;
8038 u32 mdiv;
8039 int refclk = 100000;
8040
8041 /* In case of DSI, DPLL will not be used */
8042 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8043 return;
8044
8045 mutex_lock(&dev_priv->sb_lock);
8046 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8047 mutex_unlock(&dev_priv->sb_lock);
8048
8049 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8050 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8051 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8052 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8053 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8054
8055 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8056 }
8057
8058 static void
8059 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8060 struct intel_initial_plane_config *plane_config)
8061 {
8062 struct drm_device *dev = crtc->base.dev;
8063 struct drm_i915_private *dev_priv = dev->dev_private;
8064 u32 val, base, offset;
8065 int pipe = crtc->pipe, plane = crtc->plane;
8066 int fourcc, pixel_format;
8067 unsigned int aligned_height;
8068 struct drm_framebuffer *fb;
8069 struct intel_framebuffer *intel_fb;
8070
8071 val = I915_READ(DSPCNTR(plane));
8072 if (!(val & DISPLAY_PLANE_ENABLE))
8073 return;
8074
8075 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8076 if (!intel_fb) {
8077 DRM_DEBUG_KMS("failed to alloc fb\n");
8078 return;
8079 }
8080
8081 fb = &intel_fb->base;
8082
8083 if (INTEL_INFO(dev)->gen >= 4) {
8084 if (val & DISPPLANE_TILED) {
8085 plane_config->tiling = I915_TILING_X;
8086 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8087 }
8088 }
8089
8090 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8091 fourcc = i9xx_format_to_fourcc(pixel_format);
8092 fb->pixel_format = fourcc;
8093 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8094
8095 if (INTEL_INFO(dev)->gen >= 4) {
8096 if (plane_config->tiling)
8097 offset = I915_READ(DSPTILEOFF(plane));
8098 else
8099 offset = I915_READ(DSPLINOFF(plane));
8100 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8101 } else {
8102 base = I915_READ(DSPADDR(plane));
8103 }
8104 plane_config->base = base;
8105
8106 val = I915_READ(PIPESRC(pipe));
8107 fb->width = ((val >> 16) & 0xfff) + 1;
8108 fb->height = ((val >> 0) & 0xfff) + 1;
8109
8110 val = I915_READ(DSPSTRIDE(pipe));
8111 fb->pitches[0] = val & 0xffffffc0;
8112
8113 aligned_height = intel_fb_align_height(dev, fb->height,
8114 fb->pixel_format,
8115 fb->modifier[0]);
8116
8117 plane_config->size = fb->pitches[0] * aligned_height;
8118
8119 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8120 pipe_name(pipe), plane, fb->width, fb->height,
8121 fb->bits_per_pixel, base, fb->pitches[0],
8122 plane_config->size);
8123
8124 plane_config->fb = intel_fb;
8125 }
8126
8127 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8128 struct intel_crtc_state *pipe_config)
8129 {
8130 struct drm_device *dev = crtc->base.dev;
8131 struct drm_i915_private *dev_priv = dev->dev_private;
8132 int pipe = pipe_config->cpu_transcoder;
8133 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8134 intel_clock_t clock;
8135 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8136 int refclk = 100000;
8137
8138 /* In case of DSI, DPLL will not be used */
8139 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8140 return;
8141
8142 mutex_lock(&dev_priv->sb_lock);
8143 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8144 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8145 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8146 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8147 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8148 mutex_unlock(&dev_priv->sb_lock);
8149
8150 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8151 clock.m2 = (pll_dw0 & 0xff) << 22;
8152 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8153 clock.m2 |= pll_dw2 & 0x3fffff;
8154 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8155 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8156 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8157
8158 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8159 }
8160
8161 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8162 struct intel_crtc_state *pipe_config)
8163 {
8164 struct drm_device *dev = crtc->base.dev;
8165 struct drm_i915_private *dev_priv = dev->dev_private;
8166 enum intel_display_power_domain power_domain;
8167 uint32_t tmp;
8168 bool ret;
8169
8170 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8171 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8172 return false;
8173
8174 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8175 pipe_config->shared_dpll = NULL;
8176
8177 ret = false;
8178
8179 tmp = I915_READ(PIPECONF(crtc->pipe));
8180 if (!(tmp & PIPECONF_ENABLE))
8181 goto out;
8182
8183 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8184 switch (tmp & PIPECONF_BPC_MASK) {
8185 case PIPECONF_6BPC:
8186 pipe_config->pipe_bpp = 18;
8187 break;
8188 case PIPECONF_8BPC:
8189 pipe_config->pipe_bpp = 24;
8190 break;
8191 case PIPECONF_10BPC:
8192 pipe_config->pipe_bpp = 30;
8193 break;
8194 default:
8195 break;
8196 }
8197 }
8198
8199 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8200 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8201 pipe_config->limited_color_range = true;
8202
8203 if (INTEL_INFO(dev)->gen < 4)
8204 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8205
8206 intel_get_pipe_timings(crtc, pipe_config);
8207 intel_get_pipe_src_size(crtc, pipe_config);
8208
8209 i9xx_get_pfit_config(crtc, pipe_config);
8210
8211 if (INTEL_INFO(dev)->gen >= 4) {
8212 /* No way to read it out on pipes B and C */
8213 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8214 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8215 else
8216 tmp = I915_READ(DPLL_MD(crtc->pipe));
8217 pipe_config->pixel_multiplier =
8218 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8219 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8220 pipe_config->dpll_hw_state.dpll_md = tmp;
8221 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8222 tmp = I915_READ(DPLL(crtc->pipe));
8223 pipe_config->pixel_multiplier =
8224 ((tmp & SDVO_MULTIPLIER_MASK)
8225 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8226 } else {
8227 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8228 * port and will be fixed up in the encoder->get_config
8229 * function. */
8230 pipe_config->pixel_multiplier = 1;
8231 }
8232 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8233 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8234 /*
8235 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8236 * on 830. Filter it out here so that we don't
8237 * report errors due to that.
8238 */
8239 if (IS_I830(dev))
8240 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8241
8242 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8243 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8244 } else {
8245 /* Mask out read-only status bits. */
8246 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8247 DPLL_PORTC_READY_MASK |
8248 DPLL_PORTB_READY_MASK);
8249 }
8250
8251 if (IS_CHERRYVIEW(dev))
8252 chv_crtc_clock_get(crtc, pipe_config);
8253 else if (IS_VALLEYVIEW(dev))
8254 vlv_crtc_clock_get(crtc, pipe_config);
8255 else
8256 i9xx_crtc_clock_get(crtc, pipe_config);
8257
8258 /*
8259 * Normally the dotclock is filled in by the encoder .get_config()
8260 * but in case the pipe is enabled w/o any ports we need a sane
8261 * default.
8262 */
8263 pipe_config->base.adjusted_mode.crtc_clock =
8264 pipe_config->port_clock / pipe_config->pixel_multiplier;
8265
8266 ret = true;
8267
8268 out:
8269 intel_display_power_put(dev_priv, power_domain);
8270
8271 return ret;
8272 }
8273
8274 static void ironlake_init_pch_refclk(struct drm_device *dev)
8275 {
8276 struct drm_i915_private *dev_priv = dev->dev_private;
8277 struct intel_encoder *encoder;
8278 int i;
8279 u32 val, final;
8280 bool has_lvds = false;
8281 bool has_cpu_edp = false;
8282 bool has_panel = false;
8283 bool has_ck505 = false;
8284 bool can_ssc = false;
8285 bool using_ssc_source = false;
8286
8287 /* We need to take the global config into account */
8288 for_each_intel_encoder(dev, encoder) {
8289 switch (encoder->type) {
8290 case INTEL_OUTPUT_LVDS:
8291 has_panel = true;
8292 has_lvds = true;
8293 break;
8294 case INTEL_OUTPUT_EDP:
8295 has_panel = true;
8296 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8297 has_cpu_edp = true;
8298 break;
8299 default:
8300 break;
8301 }
8302 }
8303
8304 if (HAS_PCH_IBX(dev)) {
8305 has_ck505 = dev_priv->vbt.display_clock_mode;
8306 can_ssc = has_ck505;
8307 } else {
8308 has_ck505 = false;
8309 can_ssc = true;
8310 }
8311
8312 /* Check if any DPLLs are using the SSC source */
8313 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8314 u32 temp = I915_READ(PCH_DPLL(i));
8315
8316 if (!(temp & DPLL_VCO_ENABLE))
8317 continue;
8318
8319 if ((temp & PLL_REF_INPUT_MASK) ==
8320 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8321 using_ssc_source = true;
8322 break;
8323 }
8324 }
8325
8326 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8327 has_panel, has_lvds, has_ck505, using_ssc_source);
8328
8329 /* Ironlake: try to setup display ref clock before DPLL
8330 * enabling. This is only under driver's control after
8331 * PCH B stepping, previous chipset stepping should be
8332 * ignoring this setting.
8333 */
8334 val = I915_READ(PCH_DREF_CONTROL);
8335
8336 /* As we must carefully and slowly disable/enable each source in turn,
8337 * compute the final state we want first and check if we need to
8338 * make any changes at all.
8339 */
8340 final = val;
8341 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8342 if (has_ck505)
8343 final |= DREF_NONSPREAD_CK505_ENABLE;
8344 else
8345 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8346
8347 final &= ~DREF_SSC_SOURCE_MASK;
8348 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8349 final &= ~DREF_SSC1_ENABLE;
8350
8351 if (has_panel) {
8352 final |= DREF_SSC_SOURCE_ENABLE;
8353
8354 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8355 final |= DREF_SSC1_ENABLE;
8356
8357 if (has_cpu_edp) {
8358 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8359 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8360 else
8361 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8362 } else
8363 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8364 } else if (using_ssc_source) {
8365 final |= DREF_SSC_SOURCE_ENABLE;
8366 final |= DREF_SSC1_ENABLE;
8367 }
8368
8369 if (final == val)
8370 return;
8371
8372 /* Always enable nonspread source */
8373 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8374
8375 if (has_ck505)
8376 val |= DREF_NONSPREAD_CK505_ENABLE;
8377 else
8378 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8379
8380 if (has_panel) {
8381 val &= ~DREF_SSC_SOURCE_MASK;
8382 val |= DREF_SSC_SOURCE_ENABLE;
8383
8384 /* SSC must be turned on before enabling the CPU output */
8385 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8386 DRM_DEBUG_KMS("Using SSC on panel\n");
8387 val |= DREF_SSC1_ENABLE;
8388 } else
8389 val &= ~DREF_SSC1_ENABLE;
8390
8391 /* Get SSC going before enabling the outputs */
8392 I915_WRITE(PCH_DREF_CONTROL, val);
8393 POSTING_READ(PCH_DREF_CONTROL);
8394 udelay(200);
8395
8396 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8397
8398 /* Enable CPU source on CPU attached eDP */
8399 if (has_cpu_edp) {
8400 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8401 DRM_DEBUG_KMS("Using SSC on eDP\n");
8402 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8403 } else
8404 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8405 } else
8406 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8407
8408 I915_WRITE(PCH_DREF_CONTROL, val);
8409 POSTING_READ(PCH_DREF_CONTROL);
8410 udelay(200);
8411 } else {
8412 DRM_DEBUG_KMS("Disabling CPU source output\n");
8413
8414 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8415
8416 /* Turn off CPU output */
8417 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8418
8419 I915_WRITE(PCH_DREF_CONTROL, val);
8420 POSTING_READ(PCH_DREF_CONTROL);
8421 udelay(200);
8422
8423 if (!using_ssc_source) {
8424 DRM_DEBUG_KMS("Disabling SSC source\n");
8425
8426 /* Turn off the SSC source */
8427 val &= ~DREF_SSC_SOURCE_MASK;
8428 val |= DREF_SSC_SOURCE_DISABLE;
8429
8430 /* Turn off SSC1 */
8431 val &= ~DREF_SSC1_ENABLE;
8432
8433 I915_WRITE(PCH_DREF_CONTROL, val);
8434 POSTING_READ(PCH_DREF_CONTROL);
8435 udelay(200);
8436 }
8437 }
8438
8439 BUG_ON(val != final);
8440 }
8441
8442 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8443 {
8444 uint32_t tmp;
8445
8446 tmp = I915_READ(SOUTH_CHICKEN2);
8447 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8448 I915_WRITE(SOUTH_CHICKEN2, tmp);
8449
8450 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8451 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8452 DRM_ERROR("FDI mPHY reset assert timeout\n");
8453
8454 tmp = I915_READ(SOUTH_CHICKEN2);
8455 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8456 I915_WRITE(SOUTH_CHICKEN2, tmp);
8457
8458 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8459 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8460 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8461 }
8462
8463 /* WaMPhyProgramming:hsw */
8464 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8465 {
8466 uint32_t tmp;
8467
8468 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8469 tmp &= ~(0xFF << 24);
8470 tmp |= (0x12 << 24);
8471 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8472
8473 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8474 tmp |= (1 << 11);
8475 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8476
8477 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8478 tmp |= (1 << 11);
8479 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8480
8481 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8482 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8483 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8484
8485 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8486 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8487 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8488
8489 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8490 tmp &= ~(7 << 13);
8491 tmp |= (5 << 13);
8492 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8493
8494 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8495 tmp &= ~(7 << 13);
8496 tmp |= (5 << 13);
8497 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8498
8499 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8500 tmp &= ~0xFF;
8501 tmp |= 0x1C;
8502 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8503
8504 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8505 tmp &= ~0xFF;
8506 tmp |= 0x1C;
8507 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8508
8509 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8510 tmp &= ~(0xFF << 16);
8511 tmp |= (0x1C << 16);
8512 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8513
8514 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8515 tmp &= ~(0xFF << 16);
8516 tmp |= (0x1C << 16);
8517 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8518
8519 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8520 tmp |= (1 << 27);
8521 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8522
8523 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8524 tmp |= (1 << 27);
8525 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8526
8527 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8528 tmp &= ~(0xF << 28);
8529 tmp |= (4 << 28);
8530 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8531
8532 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8533 tmp &= ~(0xF << 28);
8534 tmp |= (4 << 28);
8535 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8536 }
8537
8538 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8539 * Programming" based on the parameters passed:
8540 * - Sequence to enable CLKOUT_DP
8541 * - Sequence to enable CLKOUT_DP without spread
8542 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8543 */
8544 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8545 bool with_fdi)
8546 {
8547 struct drm_i915_private *dev_priv = dev->dev_private;
8548 uint32_t reg, tmp;
8549
8550 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8551 with_spread = true;
8552 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8553 with_fdi = false;
8554
8555 mutex_lock(&dev_priv->sb_lock);
8556
8557 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8558 tmp &= ~SBI_SSCCTL_DISABLE;
8559 tmp |= SBI_SSCCTL_PATHALT;
8560 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8561
8562 udelay(24);
8563
8564 if (with_spread) {
8565 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8566 tmp &= ~SBI_SSCCTL_PATHALT;
8567 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8568
8569 if (with_fdi) {
8570 lpt_reset_fdi_mphy(dev_priv);
8571 lpt_program_fdi_mphy(dev_priv);
8572 }
8573 }
8574
8575 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8576 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8577 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8578 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8579
8580 mutex_unlock(&dev_priv->sb_lock);
8581 }
8582
8583 /* Sequence to disable CLKOUT_DP */
8584 static void lpt_disable_clkout_dp(struct drm_device *dev)
8585 {
8586 struct drm_i915_private *dev_priv = dev->dev_private;
8587 uint32_t reg, tmp;
8588
8589 mutex_lock(&dev_priv->sb_lock);
8590
8591 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8592 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8593 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8594 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8595
8596 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8597 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8598 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8599 tmp |= SBI_SSCCTL_PATHALT;
8600 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8601 udelay(32);
8602 }
8603 tmp |= SBI_SSCCTL_DISABLE;
8604 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8605 }
8606
8607 mutex_unlock(&dev_priv->sb_lock);
8608 }
8609
8610 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8611
8612 static const uint16_t sscdivintphase[] = {
8613 [BEND_IDX( 50)] = 0x3B23,
8614 [BEND_IDX( 45)] = 0x3B23,
8615 [BEND_IDX( 40)] = 0x3C23,
8616 [BEND_IDX( 35)] = 0x3C23,
8617 [BEND_IDX( 30)] = 0x3D23,
8618 [BEND_IDX( 25)] = 0x3D23,
8619 [BEND_IDX( 20)] = 0x3E23,
8620 [BEND_IDX( 15)] = 0x3E23,
8621 [BEND_IDX( 10)] = 0x3F23,
8622 [BEND_IDX( 5)] = 0x3F23,
8623 [BEND_IDX( 0)] = 0x0025,
8624 [BEND_IDX( -5)] = 0x0025,
8625 [BEND_IDX(-10)] = 0x0125,
8626 [BEND_IDX(-15)] = 0x0125,
8627 [BEND_IDX(-20)] = 0x0225,
8628 [BEND_IDX(-25)] = 0x0225,
8629 [BEND_IDX(-30)] = 0x0325,
8630 [BEND_IDX(-35)] = 0x0325,
8631 [BEND_IDX(-40)] = 0x0425,
8632 [BEND_IDX(-45)] = 0x0425,
8633 [BEND_IDX(-50)] = 0x0525,
8634 };
8635
8636 /*
8637 * Bend CLKOUT_DP
8638 * steps -50 to 50 inclusive, in steps of 5
8639 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8640 * change in clock period = -(steps / 10) * 5.787 ps
8641 */
8642 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8643 {
8644 uint32_t tmp;
8645 int idx = BEND_IDX(steps);
8646
8647 if (WARN_ON(steps % 5 != 0))
8648 return;
8649
8650 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8651 return;
8652
8653 mutex_lock(&dev_priv->sb_lock);
8654
8655 if (steps % 10 != 0)
8656 tmp = 0xAAAAAAAB;
8657 else
8658 tmp = 0x00000000;
8659 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8660
8661 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8662 tmp &= 0xffff0000;
8663 tmp |= sscdivintphase[idx];
8664 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8665
8666 mutex_unlock(&dev_priv->sb_lock);
8667 }
8668
8669 #undef BEND_IDX
8670
8671 static void lpt_init_pch_refclk(struct drm_device *dev)
8672 {
8673 struct intel_encoder *encoder;
8674 bool has_vga = false;
8675
8676 for_each_intel_encoder(dev, encoder) {
8677 switch (encoder->type) {
8678 case INTEL_OUTPUT_ANALOG:
8679 has_vga = true;
8680 break;
8681 default:
8682 break;
8683 }
8684 }
8685
8686 if (has_vga) {
8687 lpt_bend_clkout_dp(to_i915(dev), 0);
8688 lpt_enable_clkout_dp(dev, true, true);
8689 } else {
8690 lpt_disable_clkout_dp(dev);
8691 }
8692 }
8693
8694 /*
8695 * Initialize reference clocks when the driver loads
8696 */
8697 void intel_init_pch_refclk(struct drm_device *dev)
8698 {
8699 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8700 ironlake_init_pch_refclk(dev);
8701 else if (HAS_PCH_LPT(dev))
8702 lpt_init_pch_refclk(dev);
8703 }
8704
8705 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8706 {
8707 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8709 int pipe = intel_crtc->pipe;
8710 uint32_t val;
8711
8712 val = 0;
8713
8714 switch (intel_crtc->config->pipe_bpp) {
8715 case 18:
8716 val |= PIPECONF_6BPC;
8717 break;
8718 case 24:
8719 val |= PIPECONF_8BPC;
8720 break;
8721 case 30:
8722 val |= PIPECONF_10BPC;
8723 break;
8724 case 36:
8725 val |= PIPECONF_12BPC;
8726 break;
8727 default:
8728 /* Case prevented by intel_choose_pipe_bpp_dither. */
8729 BUG();
8730 }
8731
8732 if (intel_crtc->config->dither)
8733 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8734
8735 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8736 val |= PIPECONF_INTERLACED_ILK;
8737 else
8738 val |= PIPECONF_PROGRESSIVE;
8739
8740 if (intel_crtc->config->limited_color_range)
8741 val |= PIPECONF_COLOR_RANGE_SELECT;
8742
8743 I915_WRITE(PIPECONF(pipe), val);
8744 POSTING_READ(PIPECONF(pipe));
8745 }
8746
8747 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8748 {
8749 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8751 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8752 u32 val = 0;
8753
8754 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8755 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8756
8757 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8758 val |= PIPECONF_INTERLACED_ILK;
8759 else
8760 val |= PIPECONF_PROGRESSIVE;
8761
8762 I915_WRITE(PIPECONF(cpu_transcoder), val);
8763 POSTING_READ(PIPECONF(cpu_transcoder));
8764 }
8765
8766 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8767 {
8768 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8770
8771 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8772 u32 val = 0;
8773
8774 switch (intel_crtc->config->pipe_bpp) {
8775 case 18:
8776 val |= PIPEMISC_DITHER_6_BPC;
8777 break;
8778 case 24:
8779 val |= PIPEMISC_DITHER_8_BPC;
8780 break;
8781 case 30:
8782 val |= PIPEMISC_DITHER_10_BPC;
8783 break;
8784 case 36:
8785 val |= PIPEMISC_DITHER_12_BPC;
8786 break;
8787 default:
8788 /* Case prevented by pipe_config_set_bpp. */
8789 BUG();
8790 }
8791
8792 if (intel_crtc->config->dither)
8793 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8794
8795 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8796 }
8797 }
8798
8799 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8800 {
8801 /*
8802 * Account for spread spectrum to avoid
8803 * oversubscribing the link. Max center spread
8804 * is 2.5%; use 5% for safety's sake.
8805 */
8806 u32 bps = target_clock * bpp * 21 / 20;
8807 return DIV_ROUND_UP(bps, link_bw * 8);
8808 }
8809
8810 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8811 {
8812 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8813 }
8814
8815 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8816 struct intel_crtc_state *crtc_state,
8817 intel_clock_t *reduced_clock)
8818 {
8819 struct drm_crtc *crtc = &intel_crtc->base;
8820 struct drm_device *dev = crtc->dev;
8821 struct drm_i915_private *dev_priv = dev->dev_private;
8822 struct drm_atomic_state *state = crtc_state->base.state;
8823 struct drm_connector *connector;
8824 struct drm_connector_state *connector_state;
8825 struct intel_encoder *encoder;
8826 u32 dpll, fp, fp2;
8827 int factor, i;
8828 bool is_lvds = false, is_sdvo = false;
8829
8830 for_each_connector_in_state(state, connector, connector_state, i) {
8831 if (connector_state->crtc != crtc_state->base.crtc)
8832 continue;
8833
8834 encoder = to_intel_encoder(connector_state->best_encoder);
8835
8836 switch (encoder->type) {
8837 case INTEL_OUTPUT_LVDS:
8838 is_lvds = true;
8839 break;
8840 case INTEL_OUTPUT_SDVO:
8841 case INTEL_OUTPUT_HDMI:
8842 is_sdvo = true;
8843 break;
8844 default:
8845 break;
8846 }
8847 }
8848
8849 /* Enable autotuning of the PLL clock (if permissible) */
8850 factor = 21;
8851 if (is_lvds) {
8852 if ((intel_panel_use_ssc(dev_priv) &&
8853 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8854 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8855 factor = 25;
8856 } else if (crtc_state->sdvo_tv_clock)
8857 factor = 20;
8858
8859 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8860
8861 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8862 fp |= FP_CB_TUNE;
8863
8864 if (reduced_clock) {
8865 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8866
8867 if (reduced_clock->m < factor * reduced_clock->n)
8868 fp2 |= FP_CB_TUNE;
8869 } else {
8870 fp2 = fp;
8871 }
8872
8873 dpll = 0;
8874
8875 if (is_lvds)
8876 dpll |= DPLLB_MODE_LVDS;
8877 else
8878 dpll |= DPLLB_MODE_DAC_SERIAL;
8879
8880 dpll |= (crtc_state->pixel_multiplier - 1)
8881 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8882
8883 if (is_sdvo)
8884 dpll |= DPLL_SDVO_HIGH_SPEED;
8885 if (crtc_state->has_dp_encoder)
8886 dpll |= DPLL_SDVO_HIGH_SPEED;
8887
8888 /* compute bitmask from p1 value */
8889 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8890 /* also FPA1 */
8891 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8892
8893 switch (crtc_state->dpll.p2) {
8894 case 5:
8895 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8896 break;
8897 case 7:
8898 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8899 break;
8900 case 10:
8901 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8902 break;
8903 case 14:
8904 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8905 break;
8906 }
8907
8908 if (is_lvds && intel_panel_use_ssc(dev_priv))
8909 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8910 else
8911 dpll |= PLL_REF_INPUT_DREFCLK;
8912
8913 dpll |= DPLL_VCO_ENABLE;
8914
8915 crtc_state->dpll_hw_state.dpll = dpll;
8916 crtc_state->dpll_hw_state.fp0 = fp;
8917 crtc_state->dpll_hw_state.fp1 = fp2;
8918 }
8919
8920 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8921 struct intel_crtc_state *crtc_state)
8922 {
8923 struct drm_device *dev = crtc->base.dev;
8924 struct drm_i915_private *dev_priv = dev->dev_private;
8925 intel_clock_t reduced_clock;
8926 bool has_reduced_clock = false;
8927 struct intel_shared_dpll *pll;
8928 const intel_limit_t *limit;
8929 int refclk = 120000;
8930
8931 memset(&crtc_state->dpll_hw_state, 0,
8932 sizeof(crtc_state->dpll_hw_state));
8933
8934 crtc->lowfreq_avail = false;
8935
8936 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8937 if (!crtc_state->has_pch_encoder)
8938 return 0;
8939
8940 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8941 if (intel_panel_use_ssc(dev_priv)) {
8942 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8943 dev_priv->vbt.lvds_ssc_freq);
8944 refclk = dev_priv->vbt.lvds_ssc_freq;
8945 }
8946
8947 if (intel_is_dual_link_lvds(dev)) {
8948 if (refclk == 100000)
8949 limit = &intel_limits_ironlake_dual_lvds_100m;
8950 else
8951 limit = &intel_limits_ironlake_dual_lvds;
8952 } else {
8953 if (refclk == 100000)
8954 limit = &intel_limits_ironlake_single_lvds_100m;
8955 else
8956 limit = &intel_limits_ironlake_single_lvds;
8957 }
8958 } else {
8959 limit = &intel_limits_ironlake_dac;
8960 }
8961
8962 if (!crtc_state->clock_set &&
8963 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8964 refclk, NULL, &crtc_state->dpll)) {
8965 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8966 return -EINVAL;
8967 }
8968
8969 ironlake_compute_dpll(crtc, crtc_state,
8970 has_reduced_clock ? &reduced_clock : NULL);
8971
8972 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8973 if (pll == NULL) {
8974 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8975 pipe_name(crtc->pipe));
8976 return -EINVAL;
8977 }
8978
8979 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8980 has_reduced_clock)
8981 crtc->lowfreq_avail = true;
8982
8983 return 0;
8984 }
8985
8986 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8987 struct intel_link_m_n *m_n)
8988 {
8989 struct drm_device *dev = crtc->base.dev;
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8991 enum pipe pipe = crtc->pipe;
8992
8993 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8994 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8995 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8996 & ~TU_SIZE_MASK;
8997 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8998 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8999 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9000 }
9001
9002 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9003 enum transcoder transcoder,
9004 struct intel_link_m_n *m_n,
9005 struct intel_link_m_n *m2_n2)
9006 {
9007 struct drm_device *dev = crtc->base.dev;
9008 struct drm_i915_private *dev_priv = dev->dev_private;
9009 enum pipe pipe = crtc->pipe;
9010
9011 if (INTEL_INFO(dev)->gen >= 5) {
9012 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9013 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9014 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9015 & ~TU_SIZE_MASK;
9016 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9017 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9018 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9019 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9020 * gen < 8) and if DRRS is supported (to make sure the
9021 * registers are not unnecessarily read).
9022 */
9023 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9024 crtc->config->has_drrs) {
9025 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9026 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9027 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9028 & ~TU_SIZE_MASK;
9029 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9030 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9031 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9032 }
9033 } else {
9034 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9035 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9036 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9037 & ~TU_SIZE_MASK;
9038 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9039 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9040 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9041 }
9042 }
9043
9044 void intel_dp_get_m_n(struct intel_crtc *crtc,
9045 struct intel_crtc_state *pipe_config)
9046 {
9047 if (pipe_config->has_pch_encoder)
9048 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9049 else
9050 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9051 &pipe_config->dp_m_n,
9052 &pipe_config->dp_m2_n2);
9053 }
9054
9055 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9056 struct intel_crtc_state *pipe_config)
9057 {
9058 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9059 &pipe_config->fdi_m_n, NULL);
9060 }
9061
9062 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9063 struct intel_crtc_state *pipe_config)
9064 {
9065 struct drm_device *dev = crtc->base.dev;
9066 struct drm_i915_private *dev_priv = dev->dev_private;
9067 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9068 uint32_t ps_ctrl = 0;
9069 int id = -1;
9070 int i;
9071
9072 /* find scaler attached to this pipe */
9073 for (i = 0; i < crtc->num_scalers; i++) {
9074 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9075 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9076 id = i;
9077 pipe_config->pch_pfit.enabled = true;
9078 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9079 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9080 break;
9081 }
9082 }
9083
9084 scaler_state->scaler_id = id;
9085 if (id >= 0) {
9086 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9087 } else {
9088 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9089 }
9090 }
9091
9092 static void
9093 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9094 struct intel_initial_plane_config *plane_config)
9095 {
9096 struct drm_device *dev = crtc->base.dev;
9097 struct drm_i915_private *dev_priv = dev->dev_private;
9098 u32 val, base, offset, stride_mult, tiling;
9099 int pipe = crtc->pipe;
9100 int fourcc, pixel_format;
9101 unsigned int aligned_height;
9102 struct drm_framebuffer *fb;
9103 struct intel_framebuffer *intel_fb;
9104
9105 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9106 if (!intel_fb) {
9107 DRM_DEBUG_KMS("failed to alloc fb\n");
9108 return;
9109 }
9110
9111 fb = &intel_fb->base;
9112
9113 val = I915_READ(PLANE_CTL(pipe, 0));
9114 if (!(val & PLANE_CTL_ENABLE))
9115 goto error;
9116
9117 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9118 fourcc = skl_format_to_fourcc(pixel_format,
9119 val & PLANE_CTL_ORDER_RGBX,
9120 val & PLANE_CTL_ALPHA_MASK);
9121 fb->pixel_format = fourcc;
9122 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9123
9124 tiling = val & PLANE_CTL_TILED_MASK;
9125 switch (tiling) {
9126 case PLANE_CTL_TILED_LINEAR:
9127 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9128 break;
9129 case PLANE_CTL_TILED_X:
9130 plane_config->tiling = I915_TILING_X;
9131 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9132 break;
9133 case PLANE_CTL_TILED_Y:
9134 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9135 break;
9136 case PLANE_CTL_TILED_YF:
9137 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9138 break;
9139 default:
9140 MISSING_CASE(tiling);
9141 goto error;
9142 }
9143
9144 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9145 plane_config->base = base;
9146
9147 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9148
9149 val = I915_READ(PLANE_SIZE(pipe, 0));
9150 fb->height = ((val >> 16) & 0xfff) + 1;
9151 fb->width = ((val >> 0) & 0x1fff) + 1;
9152
9153 val = I915_READ(PLANE_STRIDE(pipe, 0));
9154 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9155 fb->pixel_format);
9156 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9157
9158 aligned_height = intel_fb_align_height(dev, fb->height,
9159 fb->pixel_format,
9160 fb->modifier[0]);
9161
9162 plane_config->size = fb->pitches[0] * aligned_height;
9163
9164 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9165 pipe_name(pipe), fb->width, fb->height,
9166 fb->bits_per_pixel, base, fb->pitches[0],
9167 plane_config->size);
9168
9169 plane_config->fb = intel_fb;
9170 return;
9171
9172 error:
9173 kfree(fb);
9174 }
9175
9176 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9177 struct intel_crtc_state *pipe_config)
9178 {
9179 struct drm_device *dev = crtc->base.dev;
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 uint32_t tmp;
9182
9183 tmp = I915_READ(PF_CTL(crtc->pipe));
9184
9185 if (tmp & PF_ENABLE) {
9186 pipe_config->pch_pfit.enabled = true;
9187 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9188 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9189
9190 /* We currently do not free assignements of panel fitters on
9191 * ivb/hsw (since we don't use the higher upscaling modes which
9192 * differentiates them) so just WARN about this case for now. */
9193 if (IS_GEN7(dev)) {
9194 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9195 PF_PIPE_SEL_IVB(crtc->pipe));
9196 }
9197 }
9198 }
9199
9200 static void
9201 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9202 struct intel_initial_plane_config *plane_config)
9203 {
9204 struct drm_device *dev = crtc->base.dev;
9205 struct drm_i915_private *dev_priv = dev->dev_private;
9206 u32 val, base, offset;
9207 int pipe = crtc->pipe;
9208 int fourcc, pixel_format;
9209 unsigned int aligned_height;
9210 struct drm_framebuffer *fb;
9211 struct intel_framebuffer *intel_fb;
9212
9213 val = I915_READ(DSPCNTR(pipe));
9214 if (!(val & DISPLAY_PLANE_ENABLE))
9215 return;
9216
9217 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9218 if (!intel_fb) {
9219 DRM_DEBUG_KMS("failed to alloc fb\n");
9220 return;
9221 }
9222
9223 fb = &intel_fb->base;
9224
9225 if (INTEL_INFO(dev)->gen >= 4) {
9226 if (val & DISPPLANE_TILED) {
9227 plane_config->tiling = I915_TILING_X;
9228 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9229 }
9230 }
9231
9232 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9233 fourcc = i9xx_format_to_fourcc(pixel_format);
9234 fb->pixel_format = fourcc;
9235 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9236
9237 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9238 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9239 offset = I915_READ(DSPOFFSET(pipe));
9240 } else {
9241 if (plane_config->tiling)
9242 offset = I915_READ(DSPTILEOFF(pipe));
9243 else
9244 offset = I915_READ(DSPLINOFF(pipe));
9245 }
9246 plane_config->base = base;
9247
9248 val = I915_READ(PIPESRC(pipe));
9249 fb->width = ((val >> 16) & 0xfff) + 1;
9250 fb->height = ((val >> 0) & 0xfff) + 1;
9251
9252 val = I915_READ(DSPSTRIDE(pipe));
9253 fb->pitches[0] = val & 0xffffffc0;
9254
9255 aligned_height = intel_fb_align_height(dev, fb->height,
9256 fb->pixel_format,
9257 fb->modifier[0]);
9258
9259 plane_config->size = fb->pitches[0] * aligned_height;
9260
9261 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9262 pipe_name(pipe), fb->width, fb->height,
9263 fb->bits_per_pixel, base, fb->pitches[0],
9264 plane_config->size);
9265
9266 plane_config->fb = intel_fb;
9267 }
9268
9269 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9270 struct intel_crtc_state *pipe_config)
9271 {
9272 struct drm_device *dev = crtc->base.dev;
9273 struct drm_i915_private *dev_priv = dev->dev_private;
9274 enum intel_display_power_domain power_domain;
9275 uint32_t tmp;
9276 bool ret;
9277
9278 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9279 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9280 return false;
9281
9282 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9283 pipe_config->shared_dpll = NULL;
9284
9285 ret = false;
9286 tmp = I915_READ(PIPECONF(crtc->pipe));
9287 if (!(tmp & PIPECONF_ENABLE))
9288 goto out;
9289
9290 switch (tmp & PIPECONF_BPC_MASK) {
9291 case PIPECONF_6BPC:
9292 pipe_config->pipe_bpp = 18;
9293 break;
9294 case PIPECONF_8BPC:
9295 pipe_config->pipe_bpp = 24;
9296 break;
9297 case PIPECONF_10BPC:
9298 pipe_config->pipe_bpp = 30;
9299 break;
9300 case PIPECONF_12BPC:
9301 pipe_config->pipe_bpp = 36;
9302 break;
9303 default:
9304 break;
9305 }
9306
9307 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9308 pipe_config->limited_color_range = true;
9309
9310 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9311 struct intel_shared_dpll *pll;
9312 enum intel_dpll_id pll_id;
9313
9314 pipe_config->has_pch_encoder = true;
9315
9316 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9317 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9318 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9319
9320 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9321
9322 if (HAS_PCH_IBX(dev_priv)) {
9323 pll_id = (enum intel_dpll_id) crtc->pipe;
9324 } else {
9325 tmp = I915_READ(PCH_DPLL_SEL);
9326 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9327 pll_id = DPLL_ID_PCH_PLL_B;
9328 else
9329 pll_id= DPLL_ID_PCH_PLL_A;
9330 }
9331
9332 pipe_config->shared_dpll =
9333 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9334 pll = pipe_config->shared_dpll;
9335
9336 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9337 &pipe_config->dpll_hw_state));
9338
9339 tmp = pipe_config->dpll_hw_state.dpll;
9340 pipe_config->pixel_multiplier =
9341 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9342 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9343
9344 ironlake_pch_clock_get(crtc, pipe_config);
9345 } else {
9346 pipe_config->pixel_multiplier = 1;
9347 }
9348
9349 intel_get_pipe_timings(crtc, pipe_config);
9350 intel_get_pipe_src_size(crtc, pipe_config);
9351
9352 ironlake_get_pfit_config(crtc, pipe_config);
9353
9354 ret = true;
9355
9356 out:
9357 intel_display_power_put(dev_priv, power_domain);
9358
9359 return ret;
9360 }
9361
9362 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9363 {
9364 struct drm_device *dev = dev_priv->dev;
9365 struct intel_crtc *crtc;
9366
9367 for_each_intel_crtc(dev, crtc)
9368 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9369 pipe_name(crtc->pipe));
9370
9371 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9372 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9373 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9374 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9375 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9376 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9377 "CPU PWM1 enabled\n");
9378 if (IS_HASWELL(dev))
9379 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9380 "CPU PWM2 enabled\n");
9381 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9382 "PCH PWM1 enabled\n");
9383 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9384 "Utility pin enabled\n");
9385 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9386
9387 /*
9388 * In theory we can still leave IRQs enabled, as long as only the HPD
9389 * interrupts remain enabled. We used to check for that, but since it's
9390 * gen-specific and since we only disable LCPLL after we fully disable
9391 * the interrupts, the check below should be enough.
9392 */
9393 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9394 }
9395
9396 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9397 {
9398 struct drm_device *dev = dev_priv->dev;
9399
9400 if (IS_HASWELL(dev))
9401 return I915_READ(D_COMP_HSW);
9402 else
9403 return I915_READ(D_COMP_BDW);
9404 }
9405
9406 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9407 {
9408 struct drm_device *dev = dev_priv->dev;
9409
9410 if (IS_HASWELL(dev)) {
9411 mutex_lock(&dev_priv->rps.hw_lock);
9412 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9413 val))
9414 DRM_ERROR("Failed to write to D_COMP\n");
9415 mutex_unlock(&dev_priv->rps.hw_lock);
9416 } else {
9417 I915_WRITE(D_COMP_BDW, val);
9418 POSTING_READ(D_COMP_BDW);
9419 }
9420 }
9421
9422 /*
9423 * This function implements pieces of two sequences from BSpec:
9424 * - Sequence for display software to disable LCPLL
9425 * - Sequence for display software to allow package C8+
9426 * The steps implemented here are just the steps that actually touch the LCPLL
9427 * register. Callers should take care of disabling all the display engine
9428 * functions, doing the mode unset, fixing interrupts, etc.
9429 */
9430 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9431 bool switch_to_fclk, bool allow_power_down)
9432 {
9433 uint32_t val;
9434
9435 assert_can_disable_lcpll(dev_priv);
9436
9437 val = I915_READ(LCPLL_CTL);
9438
9439 if (switch_to_fclk) {
9440 val |= LCPLL_CD_SOURCE_FCLK;
9441 I915_WRITE(LCPLL_CTL, val);
9442
9443 if (wait_for_us(I915_READ(LCPLL_CTL) &
9444 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9445 DRM_ERROR("Switching to FCLK failed\n");
9446
9447 val = I915_READ(LCPLL_CTL);
9448 }
9449
9450 val |= LCPLL_PLL_DISABLE;
9451 I915_WRITE(LCPLL_CTL, val);
9452 POSTING_READ(LCPLL_CTL);
9453
9454 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9455 DRM_ERROR("LCPLL still locked\n");
9456
9457 val = hsw_read_dcomp(dev_priv);
9458 val |= D_COMP_COMP_DISABLE;
9459 hsw_write_dcomp(dev_priv, val);
9460 ndelay(100);
9461
9462 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9463 1))
9464 DRM_ERROR("D_COMP RCOMP still in progress\n");
9465
9466 if (allow_power_down) {
9467 val = I915_READ(LCPLL_CTL);
9468 val |= LCPLL_POWER_DOWN_ALLOW;
9469 I915_WRITE(LCPLL_CTL, val);
9470 POSTING_READ(LCPLL_CTL);
9471 }
9472 }
9473
9474 /*
9475 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9476 * source.
9477 */
9478 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9479 {
9480 uint32_t val;
9481
9482 val = I915_READ(LCPLL_CTL);
9483
9484 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9485 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9486 return;
9487
9488 /*
9489 * Make sure we're not on PC8 state before disabling PC8, otherwise
9490 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9491 */
9492 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9493
9494 if (val & LCPLL_POWER_DOWN_ALLOW) {
9495 val &= ~LCPLL_POWER_DOWN_ALLOW;
9496 I915_WRITE(LCPLL_CTL, val);
9497 POSTING_READ(LCPLL_CTL);
9498 }
9499
9500 val = hsw_read_dcomp(dev_priv);
9501 val |= D_COMP_COMP_FORCE;
9502 val &= ~D_COMP_COMP_DISABLE;
9503 hsw_write_dcomp(dev_priv, val);
9504
9505 val = I915_READ(LCPLL_CTL);
9506 val &= ~LCPLL_PLL_DISABLE;
9507 I915_WRITE(LCPLL_CTL, val);
9508
9509 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9510 DRM_ERROR("LCPLL not locked yet\n");
9511
9512 if (val & LCPLL_CD_SOURCE_FCLK) {
9513 val = I915_READ(LCPLL_CTL);
9514 val &= ~LCPLL_CD_SOURCE_FCLK;
9515 I915_WRITE(LCPLL_CTL, val);
9516
9517 if (wait_for_us((I915_READ(LCPLL_CTL) &
9518 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9519 DRM_ERROR("Switching back to LCPLL failed\n");
9520 }
9521
9522 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9523 intel_update_cdclk(dev_priv->dev);
9524 }
9525
9526 /*
9527 * Package states C8 and deeper are really deep PC states that can only be
9528 * reached when all the devices on the system allow it, so even if the graphics
9529 * device allows PC8+, it doesn't mean the system will actually get to these
9530 * states. Our driver only allows PC8+ when going into runtime PM.
9531 *
9532 * The requirements for PC8+ are that all the outputs are disabled, the power
9533 * well is disabled and most interrupts are disabled, and these are also
9534 * requirements for runtime PM. When these conditions are met, we manually do
9535 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9536 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9537 * hang the machine.
9538 *
9539 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9540 * the state of some registers, so when we come back from PC8+ we need to
9541 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9542 * need to take care of the registers kept by RC6. Notice that this happens even
9543 * if we don't put the device in PCI D3 state (which is what currently happens
9544 * because of the runtime PM support).
9545 *
9546 * For more, read "Display Sequences for Package C8" on the hardware
9547 * documentation.
9548 */
9549 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9550 {
9551 struct drm_device *dev = dev_priv->dev;
9552 uint32_t val;
9553
9554 DRM_DEBUG_KMS("Enabling package C8+\n");
9555
9556 if (HAS_PCH_LPT_LP(dev)) {
9557 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9558 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9559 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9560 }
9561
9562 lpt_disable_clkout_dp(dev);
9563 hsw_disable_lcpll(dev_priv, true, true);
9564 }
9565
9566 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9567 {
9568 struct drm_device *dev = dev_priv->dev;
9569 uint32_t val;
9570
9571 DRM_DEBUG_KMS("Disabling package C8+\n");
9572
9573 hsw_restore_lcpll(dev_priv);
9574 lpt_init_pch_refclk(dev);
9575
9576 if (HAS_PCH_LPT_LP(dev)) {
9577 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9578 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9579 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9580 }
9581 }
9582
9583 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9584 {
9585 struct drm_device *dev = old_state->dev;
9586 struct intel_atomic_state *old_intel_state =
9587 to_intel_atomic_state(old_state);
9588 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9589
9590 broxton_set_cdclk(to_i915(dev), req_cdclk);
9591 }
9592
9593 /* compute the max rate for new configuration */
9594 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9595 {
9596 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9597 struct drm_i915_private *dev_priv = state->dev->dev_private;
9598 struct drm_crtc *crtc;
9599 struct drm_crtc_state *cstate;
9600 struct intel_crtc_state *crtc_state;
9601 unsigned max_pixel_rate = 0, i;
9602 enum pipe pipe;
9603
9604 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9605 sizeof(intel_state->min_pixclk));
9606
9607 for_each_crtc_in_state(state, crtc, cstate, i) {
9608 int pixel_rate;
9609
9610 crtc_state = to_intel_crtc_state(cstate);
9611 if (!crtc_state->base.enable) {
9612 intel_state->min_pixclk[i] = 0;
9613 continue;
9614 }
9615
9616 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9617
9618 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9619 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9620 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9621
9622 intel_state->min_pixclk[i] = pixel_rate;
9623 }
9624
9625 for_each_pipe(dev_priv, pipe)
9626 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9627
9628 return max_pixel_rate;
9629 }
9630
9631 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9632 {
9633 struct drm_i915_private *dev_priv = dev->dev_private;
9634 uint32_t val, data;
9635 int ret;
9636
9637 if (WARN((I915_READ(LCPLL_CTL) &
9638 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9639 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9640 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9641 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9642 "trying to change cdclk frequency with cdclk not enabled\n"))
9643 return;
9644
9645 mutex_lock(&dev_priv->rps.hw_lock);
9646 ret = sandybridge_pcode_write(dev_priv,
9647 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9648 mutex_unlock(&dev_priv->rps.hw_lock);
9649 if (ret) {
9650 DRM_ERROR("failed to inform pcode about cdclk change\n");
9651 return;
9652 }
9653
9654 val = I915_READ(LCPLL_CTL);
9655 val |= LCPLL_CD_SOURCE_FCLK;
9656 I915_WRITE(LCPLL_CTL, val);
9657
9658 if (wait_for_us(I915_READ(LCPLL_CTL) &
9659 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9660 DRM_ERROR("Switching to FCLK failed\n");
9661
9662 val = I915_READ(LCPLL_CTL);
9663 val &= ~LCPLL_CLK_FREQ_MASK;
9664
9665 switch (cdclk) {
9666 case 450000:
9667 val |= LCPLL_CLK_FREQ_450;
9668 data = 0;
9669 break;
9670 case 540000:
9671 val |= LCPLL_CLK_FREQ_54O_BDW;
9672 data = 1;
9673 break;
9674 case 337500:
9675 val |= LCPLL_CLK_FREQ_337_5_BDW;
9676 data = 2;
9677 break;
9678 case 675000:
9679 val |= LCPLL_CLK_FREQ_675_BDW;
9680 data = 3;
9681 break;
9682 default:
9683 WARN(1, "invalid cdclk frequency\n");
9684 return;
9685 }
9686
9687 I915_WRITE(LCPLL_CTL, val);
9688
9689 val = I915_READ(LCPLL_CTL);
9690 val &= ~LCPLL_CD_SOURCE_FCLK;
9691 I915_WRITE(LCPLL_CTL, val);
9692
9693 if (wait_for_us((I915_READ(LCPLL_CTL) &
9694 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9695 DRM_ERROR("Switching back to LCPLL failed\n");
9696
9697 mutex_lock(&dev_priv->rps.hw_lock);
9698 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9699 mutex_unlock(&dev_priv->rps.hw_lock);
9700
9701 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9702
9703 intel_update_cdclk(dev);
9704
9705 WARN(cdclk != dev_priv->cdclk_freq,
9706 "cdclk requested %d kHz but got %d kHz\n",
9707 cdclk, dev_priv->cdclk_freq);
9708 }
9709
9710 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9711 {
9712 struct drm_i915_private *dev_priv = to_i915(state->dev);
9713 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9714 int max_pixclk = ilk_max_pixel_rate(state);
9715 int cdclk;
9716
9717 /*
9718 * FIXME should also account for plane ratio
9719 * once 64bpp pixel formats are supported.
9720 */
9721 if (max_pixclk > 540000)
9722 cdclk = 675000;
9723 else if (max_pixclk > 450000)
9724 cdclk = 540000;
9725 else if (max_pixclk > 337500)
9726 cdclk = 450000;
9727 else
9728 cdclk = 337500;
9729
9730 if (cdclk > dev_priv->max_cdclk_freq) {
9731 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9732 cdclk, dev_priv->max_cdclk_freq);
9733 return -EINVAL;
9734 }
9735
9736 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9737 if (!intel_state->active_crtcs)
9738 intel_state->dev_cdclk = 337500;
9739
9740 return 0;
9741 }
9742
9743 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9744 {
9745 struct drm_device *dev = old_state->dev;
9746 struct intel_atomic_state *old_intel_state =
9747 to_intel_atomic_state(old_state);
9748 unsigned req_cdclk = old_intel_state->dev_cdclk;
9749
9750 broadwell_set_cdclk(dev, req_cdclk);
9751 }
9752
9753 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9754 struct intel_crtc_state *crtc_state)
9755 {
9756 struct intel_encoder *intel_encoder =
9757 intel_ddi_get_crtc_new_encoder(crtc_state);
9758
9759 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9760 if (!intel_ddi_pll_select(crtc, crtc_state))
9761 return -EINVAL;
9762 }
9763
9764 crtc->lowfreq_avail = false;
9765
9766 return 0;
9767 }
9768
9769 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9770 enum port port,
9771 struct intel_crtc_state *pipe_config)
9772 {
9773 enum intel_dpll_id id;
9774
9775 switch (port) {
9776 case PORT_A:
9777 pipe_config->ddi_pll_sel = SKL_DPLL0;
9778 id = DPLL_ID_SKL_DPLL0;
9779 break;
9780 case PORT_B:
9781 pipe_config->ddi_pll_sel = SKL_DPLL1;
9782 id = DPLL_ID_SKL_DPLL1;
9783 break;
9784 case PORT_C:
9785 pipe_config->ddi_pll_sel = SKL_DPLL2;
9786 id = DPLL_ID_SKL_DPLL2;
9787 break;
9788 default:
9789 DRM_ERROR("Incorrect port type\n");
9790 return;
9791 }
9792
9793 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9794 }
9795
9796 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9797 enum port port,
9798 struct intel_crtc_state *pipe_config)
9799 {
9800 enum intel_dpll_id id;
9801 u32 temp;
9802
9803 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9804 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9805
9806 switch (pipe_config->ddi_pll_sel) {
9807 case SKL_DPLL0:
9808 id = DPLL_ID_SKL_DPLL0;
9809 break;
9810 case SKL_DPLL1:
9811 id = DPLL_ID_SKL_DPLL1;
9812 break;
9813 case SKL_DPLL2:
9814 id = DPLL_ID_SKL_DPLL2;
9815 break;
9816 case SKL_DPLL3:
9817 id = DPLL_ID_SKL_DPLL3;
9818 break;
9819 default:
9820 MISSING_CASE(pipe_config->ddi_pll_sel);
9821 return;
9822 }
9823
9824 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9825 }
9826
9827 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9828 enum port port,
9829 struct intel_crtc_state *pipe_config)
9830 {
9831 enum intel_dpll_id id;
9832
9833 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9834
9835 switch (pipe_config->ddi_pll_sel) {
9836 case PORT_CLK_SEL_WRPLL1:
9837 id = DPLL_ID_WRPLL1;
9838 break;
9839 case PORT_CLK_SEL_WRPLL2:
9840 id = DPLL_ID_WRPLL2;
9841 break;
9842 case PORT_CLK_SEL_SPLL:
9843 id = DPLL_ID_SPLL;
9844 break;
9845 case PORT_CLK_SEL_LCPLL_810:
9846 id = DPLL_ID_LCPLL_810;
9847 break;
9848 case PORT_CLK_SEL_LCPLL_1350:
9849 id = DPLL_ID_LCPLL_1350;
9850 break;
9851 case PORT_CLK_SEL_LCPLL_2700:
9852 id = DPLL_ID_LCPLL_2700;
9853 break;
9854 default:
9855 MISSING_CASE(pipe_config->ddi_pll_sel);
9856 /* fall through */
9857 case PORT_CLK_SEL_NONE:
9858 return;
9859 }
9860
9861 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9862 }
9863
9864 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9865 struct intel_crtc_state *pipe_config,
9866 unsigned long *power_domain_mask)
9867 {
9868 struct drm_device *dev = crtc->base.dev;
9869 struct drm_i915_private *dev_priv = dev->dev_private;
9870 enum intel_display_power_domain power_domain;
9871 u32 tmp;
9872
9873 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9874
9875 /*
9876 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9877 * consistency and less surprising code; it's in always on power).
9878 */
9879 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9880 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9881 enum pipe trans_edp_pipe;
9882 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9883 default:
9884 WARN(1, "unknown pipe linked to edp transcoder\n");
9885 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9886 case TRANS_DDI_EDP_INPUT_A_ON:
9887 trans_edp_pipe = PIPE_A;
9888 break;
9889 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9890 trans_edp_pipe = PIPE_B;
9891 break;
9892 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9893 trans_edp_pipe = PIPE_C;
9894 break;
9895 }
9896
9897 if (trans_edp_pipe == crtc->pipe)
9898 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9899 }
9900
9901 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9902 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9903 return false;
9904 *power_domain_mask |= BIT(power_domain);
9905
9906 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9907
9908 return tmp & PIPECONF_ENABLE;
9909 }
9910
9911 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9912 struct intel_crtc_state *pipe_config,
9913 unsigned long *power_domain_mask)
9914 {
9915 struct drm_device *dev = crtc->base.dev;
9916 struct drm_i915_private *dev_priv = dev->dev_private;
9917 enum intel_display_power_domain power_domain;
9918 enum port port;
9919 enum transcoder cpu_transcoder;
9920 u32 tmp;
9921
9922 pipe_config->has_dsi_encoder = false;
9923
9924 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9925 if (port == PORT_A)
9926 cpu_transcoder = TRANSCODER_DSI_A;
9927 else
9928 cpu_transcoder = TRANSCODER_DSI_C;
9929
9930 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9931 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9932 continue;
9933 *power_domain_mask |= BIT(power_domain);
9934
9935 /*
9936 * The PLL needs to be enabled with a valid divider
9937 * configuration, otherwise accessing DSI registers will hang
9938 * the machine. See BSpec North Display Engine
9939 * registers/MIPI[BXT]. We can break out here early, since we
9940 * need the same DSI PLL to be enabled for both DSI ports.
9941 */
9942 if (!intel_dsi_pll_is_enabled(dev_priv))
9943 break;
9944
9945 /* XXX: this works for video mode only */
9946 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9947 if (!(tmp & DPI_ENABLE))
9948 continue;
9949
9950 tmp = I915_READ(MIPI_CTRL(port));
9951 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9952 continue;
9953
9954 pipe_config->cpu_transcoder = cpu_transcoder;
9955 pipe_config->has_dsi_encoder = true;
9956 break;
9957 }
9958
9959 return pipe_config->has_dsi_encoder;
9960 }
9961
9962 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9963 struct intel_crtc_state *pipe_config)
9964 {
9965 struct drm_device *dev = crtc->base.dev;
9966 struct drm_i915_private *dev_priv = dev->dev_private;
9967 struct intel_shared_dpll *pll;
9968 enum port port;
9969 uint32_t tmp;
9970
9971 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9972
9973 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9974
9975 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9976 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9977 else if (IS_BROXTON(dev))
9978 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9979 else
9980 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9981
9982 pll = pipe_config->shared_dpll;
9983 if (pll) {
9984 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9985 &pipe_config->dpll_hw_state));
9986 }
9987
9988 /*
9989 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9990 * DDI E. So just check whether this pipe is wired to DDI E and whether
9991 * the PCH transcoder is on.
9992 */
9993 if (INTEL_INFO(dev)->gen < 9 &&
9994 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9995 pipe_config->has_pch_encoder = true;
9996
9997 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9998 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9999 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10000
10001 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10002 }
10003 }
10004
10005 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10006 struct intel_crtc_state *pipe_config)
10007 {
10008 struct drm_device *dev = crtc->base.dev;
10009 struct drm_i915_private *dev_priv = dev->dev_private;
10010 enum intel_display_power_domain power_domain;
10011 unsigned long power_domain_mask;
10012 bool active;
10013
10014 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10015 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10016 return false;
10017 power_domain_mask = BIT(power_domain);
10018
10019 pipe_config->shared_dpll = NULL;
10020
10021 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10022
10023 if (IS_BROXTON(dev_priv)) {
10024 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10025 &power_domain_mask);
10026 WARN_ON(active && pipe_config->has_dsi_encoder);
10027 if (pipe_config->has_dsi_encoder)
10028 active = true;
10029 }
10030
10031 if (!active)
10032 goto out;
10033
10034 if (!pipe_config->has_dsi_encoder) {
10035 haswell_get_ddi_port_state(crtc, pipe_config);
10036 intel_get_pipe_timings(crtc, pipe_config);
10037 }
10038
10039 intel_get_pipe_src_size(crtc, pipe_config);
10040
10041 pipe_config->gamma_mode =
10042 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10043
10044 if (INTEL_INFO(dev)->gen >= 9) {
10045 skl_init_scalers(dev, crtc, pipe_config);
10046 }
10047
10048 if (INTEL_INFO(dev)->gen >= 9) {
10049 pipe_config->scaler_state.scaler_id = -1;
10050 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10051 }
10052
10053 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10054 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10055 power_domain_mask |= BIT(power_domain);
10056 if (INTEL_INFO(dev)->gen >= 9)
10057 skylake_get_pfit_config(crtc, pipe_config);
10058 else
10059 ironlake_get_pfit_config(crtc, pipe_config);
10060 }
10061
10062 if (IS_HASWELL(dev))
10063 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10064 (I915_READ(IPS_CTL) & IPS_ENABLE);
10065
10066 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10067 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10068 pipe_config->pixel_multiplier =
10069 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10070 } else {
10071 pipe_config->pixel_multiplier = 1;
10072 }
10073
10074 out:
10075 for_each_power_domain(power_domain, power_domain_mask)
10076 intel_display_power_put(dev_priv, power_domain);
10077
10078 return active;
10079 }
10080
10081 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10082 const struct intel_plane_state *plane_state)
10083 {
10084 struct drm_device *dev = crtc->dev;
10085 struct drm_i915_private *dev_priv = dev->dev_private;
10086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10087 uint32_t cntl = 0, size = 0;
10088
10089 if (plane_state && plane_state->visible) {
10090 unsigned int width = plane_state->base.crtc_w;
10091 unsigned int height = plane_state->base.crtc_h;
10092 unsigned int stride = roundup_pow_of_two(width) * 4;
10093
10094 switch (stride) {
10095 default:
10096 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10097 width, stride);
10098 stride = 256;
10099 /* fallthrough */
10100 case 256:
10101 case 512:
10102 case 1024:
10103 case 2048:
10104 break;
10105 }
10106
10107 cntl |= CURSOR_ENABLE |
10108 CURSOR_GAMMA_ENABLE |
10109 CURSOR_FORMAT_ARGB |
10110 CURSOR_STRIDE(stride);
10111
10112 size = (height << 12) | width;
10113 }
10114
10115 if (intel_crtc->cursor_cntl != 0 &&
10116 (intel_crtc->cursor_base != base ||
10117 intel_crtc->cursor_size != size ||
10118 intel_crtc->cursor_cntl != cntl)) {
10119 /* On these chipsets we can only modify the base/size/stride
10120 * whilst the cursor is disabled.
10121 */
10122 I915_WRITE(CURCNTR(PIPE_A), 0);
10123 POSTING_READ(CURCNTR(PIPE_A));
10124 intel_crtc->cursor_cntl = 0;
10125 }
10126
10127 if (intel_crtc->cursor_base != base) {
10128 I915_WRITE(CURBASE(PIPE_A), base);
10129 intel_crtc->cursor_base = base;
10130 }
10131
10132 if (intel_crtc->cursor_size != size) {
10133 I915_WRITE(CURSIZE, size);
10134 intel_crtc->cursor_size = size;
10135 }
10136
10137 if (intel_crtc->cursor_cntl != cntl) {
10138 I915_WRITE(CURCNTR(PIPE_A), cntl);
10139 POSTING_READ(CURCNTR(PIPE_A));
10140 intel_crtc->cursor_cntl = cntl;
10141 }
10142 }
10143
10144 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10145 const struct intel_plane_state *plane_state)
10146 {
10147 struct drm_device *dev = crtc->dev;
10148 struct drm_i915_private *dev_priv = dev->dev_private;
10149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10150 int pipe = intel_crtc->pipe;
10151 uint32_t cntl = 0;
10152
10153 if (plane_state && plane_state->visible) {
10154 cntl = MCURSOR_GAMMA_ENABLE;
10155 switch (plane_state->base.crtc_w) {
10156 case 64:
10157 cntl |= CURSOR_MODE_64_ARGB_AX;
10158 break;
10159 case 128:
10160 cntl |= CURSOR_MODE_128_ARGB_AX;
10161 break;
10162 case 256:
10163 cntl |= CURSOR_MODE_256_ARGB_AX;
10164 break;
10165 default:
10166 MISSING_CASE(plane_state->base.crtc_w);
10167 return;
10168 }
10169 cntl |= pipe << 28; /* Connect to correct pipe */
10170
10171 if (HAS_DDI(dev))
10172 cntl |= CURSOR_PIPE_CSC_ENABLE;
10173
10174 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10175 cntl |= CURSOR_ROTATE_180;
10176 }
10177
10178 if (intel_crtc->cursor_cntl != cntl) {
10179 I915_WRITE(CURCNTR(pipe), cntl);
10180 POSTING_READ(CURCNTR(pipe));
10181 intel_crtc->cursor_cntl = cntl;
10182 }
10183
10184 /* and commit changes on next vblank */
10185 I915_WRITE(CURBASE(pipe), base);
10186 POSTING_READ(CURBASE(pipe));
10187
10188 intel_crtc->cursor_base = base;
10189 }
10190
10191 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10192 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10193 const struct intel_plane_state *plane_state)
10194 {
10195 struct drm_device *dev = crtc->dev;
10196 struct drm_i915_private *dev_priv = dev->dev_private;
10197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10198 int pipe = intel_crtc->pipe;
10199 u32 base = intel_crtc->cursor_addr;
10200 u32 pos = 0;
10201
10202 if (plane_state) {
10203 int x = plane_state->base.crtc_x;
10204 int y = plane_state->base.crtc_y;
10205
10206 if (x < 0) {
10207 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10208 x = -x;
10209 }
10210 pos |= x << CURSOR_X_SHIFT;
10211
10212 if (y < 0) {
10213 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10214 y = -y;
10215 }
10216 pos |= y << CURSOR_Y_SHIFT;
10217
10218 /* ILK+ do this automagically */
10219 if (HAS_GMCH_DISPLAY(dev) &&
10220 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10221 base += (plane_state->base.crtc_h *
10222 plane_state->base.crtc_w - 1) * 4;
10223 }
10224 }
10225
10226 I915_WRITE(CURPOS(pipe), pos);
10227
10228 if (IS_845G(dev) || IS_I865G(dev))
10229 i845_update_cursor(crtc, base, plane_state);
10230 else
10231 i9xx_update_cursor(crtc, base, plane_state);
10232 }
10233
10234 static bool cursor_size_ok(struct drm_device *dev,
10235 uint32_t width, uint32_t height)
10236 {
10237 if (width == 0 || height == 0)
10238 return false;
10239
10240 /*
10241 * 845g/865g are special in that they are only limited by
10242 * the width of their cursors, the height is arbitrary up to
10243 * the precision of the register. Everything else requires
10244 * square cursors, limited to a few power-of-two sizes.
10245 */
10246 if (IS_845G(dev) || IS_I865G(dev)) {
10247 if ((width & 63) != 0)
10248 return false;
10249
10250 if (width > (IS_845G(dev) ? 64 : 512))
10251 return false;
10252
10253 if (height > 1023)
10254 return false;
10255 } else {
10256 switch (width | height) {
10257 case 256:
10258 case 128:
10259 if (IS_GEN2(dev))
10260 return false;
10261 case 64:
10262 break;
10263 default:
10264 return false;
10265 }
10266 }
10267
10268 return true;
10269 }
10270
10271 /* VESA 640x480x72Hz mode to set on the pipe */
10272 static struct drm_display_mode load_detect_mode = {
10273 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10274 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10275 };
10276
10277 struct drm_framebuffer *
10278 __intel_framebuffer_create(struct drm_device *dev,
10279 struct drm_mode_fb_cmd2 *mode_cmd,
10280 struct drm_i915_gem_object *obj)
10281 {
10282 struct intel_framebuffer *intel_fb;
10283 int ret;
10284
10285 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10286 if (!intel_fb)
10287 return ERR_PTR(-ENOMEM);
10288
10289 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10290 if (ret)
10291 goto err;
10292
10293 return &intel_fb->base;
10294
10295 err:
10296 kfree(intel_fb);
10297 return ERR_PTR(ret);
10298 }
10299
10300 static struct drm_framebuffer *
10301 intel_framebuffer_create(struct drm_device *dev,
10302 struct drm_mode_fb_cmd2 *mode_cmd,
10303 struct drm_i915_gem_object *obj)
10304 {
10305 struct drm_framebuffer *fb;
10306 int ret;
10307
10308 ret = i915_mutex_lock_interruptible(dev);
10309 if (ret)
10310 return ERR_PTR(ret);
10311 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10312 mutex_unlock(&dev->struct_mutex);
10313
10314 return fb;
10315 }
10316
10317 static u32
10318 intel_framebuffer_pitch_for_width(int width, int bpp)
10319 {
10320 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10321 return ALIGN(pitch, 64);
10322 }
10323
10324 static u32
10325 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10326 {
10327 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10328 return PAGE_ALIGN(pitch * mode->vdisplay);
10329 }
10330
10331 static struct drm_framebuffer *
10332 intel_framebuffer_create_for_mode(struct drm_device *dev,
10333 struct drm_display_mode *mode,
10334 int depth, int bpp)
10335 {
10336 struct drm_framebuffer *fb;
10337 struct drm_i915_gem_object *obj;
10338 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10339
10340 obj = i915_gem_alloc_object(dev,
10341 intel_framebuffer_size_for_mode(mode, bpp));
10342 if (obj == NULL)
10343 return ERR_PTR(-ENOMEM);
10344
10345 mode_cmd.width = mode->hdisplay;
10346 mode_cmd.height = mode->vdisplay;
10347 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10348 bpp);
10349 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10350
10351 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10352 if (IS_ERR(fb))
10353 drm_gem_object_unreference_unlocked(&obj->base);
10354
10355 return fb;
10356 }
10357
10358 static struct drm_framebuffer *
10359 mode_fits_in_fbdev(struct drm_device *dev,
10360 struct drm_display_mode *mode)
10361 {
10362 #ifdef CONFIG_DRM_FBDEV_EMULATION
10363 struct drm_i915_private *dev_priv = dev->dev_private;
10364 struct drm_i915_gem_object *obj;
10365 struct drm_framebuffer *fb;
10366
10367 if (!dev_priv->fbdev)
10368 return NULL;
10369
10370 if (!dev_priv->fbdev->fb)
10371 return NULL;
10372
10373 obj = dev_priv->fbdev->fb->obj;
10374 BUG_ON(!obj);
10375
10376 fb = &dev_priv->fbdev->fb->base;
10377 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10378 fb->bits_per_pixel))
10379 return NULL;
10380
10381 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10382 return NULL;
10383
10384 drm_framebuffer_reference(fb);
10385 return fb;
10386 #else
10387 return NULL;
10388 #endif
10389 }
10390
10391 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10392 struct drm_crtc *crtc,
10393 struct drm_display_mode *mode,
10394 struct drm_framebuffer *fb,
10395 int x, int y)
10396 {
10397 struct drm_plane_state *plane_state;
10398 int hdisplay, vdisplay;
10399 int ret;
10400
10401 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10402 if (IS_ERR(plane_state))
10403 return PTR_ERR(plane_state);
10404
10405 if (mode)
10406 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10407 else
10408 hdisplay = vdisplay = 0;
10409
10410 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10411 if (ret)
10412 return ret;
10413 drm_atomic_set_fb_for_plane(plane_state, fb);
10414 plane_state->crtc_x = 0;
10415 plane_state->crtc_y = 0;
10416 plane_state->crtc_w = hdisplay;
10417 plane_state->crtc_h = vdisplay;
10418 plane_state->src_x = x << 16;
10419 plane_state->src_y = y << 16;
10420 plane_state->src_w = hdisplay << 16;
10421 plane_state->src_h = vdisplay << 16;
10422
10423 return 0;
10424 }
10425
10426 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10427 struct drm_display_mode *mode,
10428 struct intel_load_detect_pipe *old,
10429 struct drm_modeset_acquire_ctx *ctx)
10430 {
10431 struct intel_crtc *intel_crtc;
10432 struct intel_encoder *intel_encoder =
10433 intel_attached_encoder(connector);
10434 struct drm_crtc *possible_crtc;
10435 struct drm_encoder *encoder = &intel_encoder->base;
10436 struct drm_crtc *crtc = NULL;
10437 struct drm_device *dev = encoder->dev;
10438 struct drm_framebuffer *fb;
10439 struct drm_mode_config *config = &dev->mode_config;
10440 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10441 struct drm_connector_state *connector_state;
10442 struct intel_crtc_state *crtc_state;
10443 int ret, i = -1;
10444
10445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10446 connector->base.id, connector->name,
10447 encoder->base.id, encoder->name);
10448
10449 old->restore_state = NULL;
10450
10451 retry:
10452 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10453 if (ret)
10454 goto fail;
10455
10456 /*
10457 * Algorithm gets a little messy:
10458 *
10459 * - if the connector already has an assigned crtc, use it (but make
10460 * sure it's on first)
10461 *
10462 * - try to find the first unused crtc that can drive this connector,
10463 * and use that if we find one
10464 */
10465
10466 /* See if we already have a CRTC for this connector */
10467 if (connector->state->crtc) {
10468 crtc = connector->state->crtc;
10469
10470 ret = drm_modeset_lock(&crtc->mutex, ctx);
10471 if (ret)
10472 goto fail;
10473
10474 /* Make sure the crtc and connector are running */
10475 goto found;
10476 }
10477
10478 /* Find an unused one (if possible) */
10479 for_each_crtc(dev, possible_crtc) {
10480 i++;
10481 if (!(encoder->possible_crtcs & (1 << i)))
10482 continue;
10483
10484 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10485 if (ret)
10486 goto fail;
10487
10488 if (possible_crtc->state->enable) {
10489 drm_modeset_unlock(&possible_crtc->mutex);
10490 continue;
10491 }
10492
10493 crtc = possible_crtc;
10494 break;
10495 }
10496
10497 /*
10498 * If we didn't find an unused CRTC, don't use any.
10499 */
10500 if (!crtc) {
10501 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10502 goto fail;
10503 }
10504
10505 found:
10506 intel_crtc = to_intel_crtc(crtc);
10507
10508 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10509 if (ret)
10510 goto fail;
10511
10512 state = drm_atomic_state_alloc(dev);
10513 restore_state = drm_atomic_state_alloc(dev);
10514 if (!state || !restore_state) {
10515 ret = -ENOMEM;
10516 goto fail;
10517 }
10518
10519 state->acquire_ctx = ctx;
10520 restore_state->acquire_ctx = ctx;
10521
10522 connector_state = drm_atomic_get_connector_state(state, connector);
10523 if (IS_ERR(connector_state)) {
10524 ret = PTR_ERR(connector_state);
10525 goto fail;
10526 }
10527
10528 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10529 if (ret)
10530 goto fail;
10531
10532 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10533 if (IS_ERR(crtc_state)) {
10534 ret = PTR_ERR(crtc_state);
10535 goto fail;
10536 }
10537
10538 crtc_state->base.active = crtc_state->base.enable = true;
10539
10540 if (!mode)
10541 mode = &load_detect_mode;
10542
10543 /* We need a framebuffer large enough to accommodate all accesses
10544 * that the plane may generate whilst we perform load detection.
10545 * We can not rely on the fbcon either being present (we get called
10546 * during its initialisation to detect all boot displays, or it may
10547 * not even exist) or that it is large enough to satisfy the
10548 * requested mode.
10549 */
10550 fb = mode_fits_in_fbdev(dev, mode);
10551 if (fb == NULL) {
10552 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10553 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10554 } else
10555 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10556 if (IS_ERR(fb)) {
10557 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10558 goto fail;
10559 }
10560
10561 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10562 if (ret)
10563 goto fail;
10564
10565 drm_framebuffer_unreference(fb);
10566
10567 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10568 if (ret)
10569 goto fail;
10570
10571 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10572 if (!ret)
10573 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10574 if (!ret)
10575 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10576 if (ret) {
10577 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10578 goto fail;
10579 }
10580
10581 ret = drm_atomic_commit(state);
10582 if (ret) {
10583 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10584 goto fail;
10585 }
10586
10587 old->restore_state = restore_state;
10588
10589 /* let the connector get through one full cycle before testing */
10590 intel_wait_for_vblank(dev, intel_crtc->pipe);
10591 return true;
10592
10593 fail:
10594 drm_atomic_state_free(state);
10595 drm_atomic_state_free(restore_state);
10596 restore_state = state = NULL;
10597
10598 if (ret == -EDEADLK) {
10599 drm_modeset_backoff(ctx);
10600 goto retry;
10601 }
10602
10603 return false;
10604 }
10605
10606 void intel_release_load_detect_pipe(struct drm_connector *connector,
10607 struct intel_load_detect_pipe *old,
10608 struct drm_modeset_acquire_ctx *ctx)
10609 {
10610 struct intel_encoder *intel_encoder =
10611 intel_attached_encoder(connector);
10612 struct drm_encoder *encoder = &intel_encoder->base;
10613 struct drm_atomic_state *state = old->restore_state;
10614 int ret;
10615
10616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10617 connector->base.id, connector->name,
10618 encoder->base.id, encoder->name);
10619
10620 if (!state)
10621 return;
10622
10623 ret = drm_atomic_commit(state);
10624 if (ret) {
10625 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10626 drm_atomic_state_free(state);
10627 }
10628 }
10629
10630 static int i9xx_pll_refclk(struct drm_device *dev,
10631 const struct intel_crtc_state *pipe_config)
10632 {
10633 struct drm_i915_private *dev_priv = dev->dev_private;
10634 u32 dpll = pipe_config->dpll_hw_state.dpll;
10635
10636 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10637 return dev_priv->vbt.lvds_ssc_freq;
10638 else if (HAS_PCH_SPLIT(dev))
10639 return 120000;
10640 else if (!IS_GEN2(dev))
10641 return 96000;
10642 else
10643 return 48000;
10644 }
10645
10646 /* Returns the clock of the currently programmed mode of the given pipe. */
10647 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10648 struct intel_crtc_state *pipe_config)
10649 {
10650 struct drm_device *dev = crtc->base.dev;
10651 struct drm_i915_private *dev_priv = dev->dev_private;
10652 int pipe = pipe_config->cpu_transcoder;
10653 u32 dpll = pipe_config->dpll_hw_state.dpll;
10654 u32 fp;
10655 intel_clock_t clock;
10656 int port_clock;
10657 int refclk = i9xx_pll_refclk(dev, pipe_config);
10658
10659 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10660 fp = pipe_config->dpll_hw_state.fp0;
10661 else
10662 fp = pipe_config->dpll_hw_state.fp1;
10663
10664 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10665 if (IS_PINEVIEW(dev)) {
10666 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10667 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10668 } else {
10669 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10670 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10671 }
10672
10673 if (!IS_GEN2(dev)) {
10674 if (IS_PINEVIEW(dev))
10675 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10676 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10677 else
10678 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10679 DPLL_FPA01_P1_POST_DIV_SHIFT);
10680
10681 switch (dpll & DPLL_MODE_MASK) {
10682 case DPLLB_MODE_DAC_SERIAL:
10683 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10684 5 : 10;
10685 break;
10686 case DPLLB_MODE_LVDS:
10687 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10688 7 : 14;
10689 break;
10690 default:
10691 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10692 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10693 return;
10694 }
10695
10696 if (IS_PINEVIEW(dev))
10697 port_clock = pnv_calc_dpll_params(refclk, &clock);
10698 else
10699 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10700 } else {
10701 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10702 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10703
10704 if (is_lvds) {
10705 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10706 DPLL_FPA01_P1_POST_DIV_SHIFT);
10707
10708 if (lvds & LVDS_CLKB_POWER_UP)
10709 clock.p2 = 7;
10710 else
10711 clock.p2 = 14;
10712 } else {
10713 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10714 clock.p1 = 2;
10715 else {
10716 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10717 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10718 }
10719 if (dpll & PLL_P2_DIVIDE_BY_4)
10720 clock.p2 = 4;
10721 else
10722 clock.p2 = 2;
10723 }
10724
10725 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10726 }
10727
10728 /*
10729 * This value includes pixel_multiplier. We will use
10730 * port_clock to compute adjusted_mode.crtc_clock in the
10731 * encoder's get_config() function.
10732 */
10733 pipe_config->port_clock = port_clock;
10734 }
10735
10736 int intel_dotclock_calculate(int link_freq,
10737 const struct intel_link_m_n *m_n)
10738 {
10739 /*
10740 * The calculation for the data clock is:
10741 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10742 * But we want to avoid losing precison if possible, so:
10743 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10744 *
10745 * and the link clock is simpler:
10746 * link_clock = (m * link_clock) / n
10747 */
10748
10749 if (!m_n->link_n)
10750 return 0;
10751
10752 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10753 }
10754
10755 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10756 struct intel_crtc_state *pipe_config)
10757 {
10758 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10759
10760 /* read out port_clock from the DPLL */
10761 i9xx_crtc_clock_get(crtc, pipe_config);
10762
10763 /*
10764 * In case there is an active pipe without active ports,
10765 * we may need some idea for the dotclock anyway.
10766 * Calculate one based on the FDI configuration.
10767 */
10768 pipe_config->base.adjusted_mode.crtc_clock =
10769 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10770 &pipe_config->fdi_m_n);
10771 }
10772
10773 /** Returns the currently programmed mode of the given pipe. */
10774 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10775 struct drm_crtc *crtc)
10776 {
10777 struct drm_i915_private *dev_priv = dev->dev_private;
10778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10780 struct drm_display_mode *mode;
10781 struct intel_crtc_state *pipe_config;
10782 int htot = I915_READ(HTOTAL(cpu_transcoder));
10783 int hsync = I915_READ(HSYNC(cpu_transcoder));
10784 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10785 int vsync = I915_READ(VSYNC(cpu_transcoder));
10786 enum pipe pipe = intel_crtc->pipe;
10787
10788 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10789 if (!mode)
10790 return NULL;
10791
10792 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10793 if (!pipe_config) {
10794 kfree(mode);
10795 return NULL;
10796 }
10797
10798 /*
10799 * Construct a pipe_config sufficient for getting the clock info
10800 * back out of crtc_clock_get.
10801 *
10802 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10803 * to use a real value here instead.
10804 */
10805 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10806 pipe_config->pixel_multiplier = 1;
10807 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10808 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10809 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10810 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10811
10812 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10813 mode->hdisplay = (htot & 0xffff) + 1;
10814 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10815 mode->hsync_start = (hsync & 0xffff) + 1;
10816 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10817 mode->vdisplay = (vtot & 0xffff) + 1;
10818 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10819 mode->vsync_start = (vsync & 0xffff) + 1;
10820 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10821
10822 drm_mode_set_name(mode);
10823
10824 kfree(pipe_config);
10825
10826 return mode;
10827 }
10828
10829 void intel_mark_busy(struct drm_device *dev)
10830 {
10831 struct drm_i915_private *dev_priv = dev->dev_private;
10832
10833 if (dev_priv->mm.busy)
10834 return;
10835
10836 intel_runtime_pm_get(dev_priv);
10837 i915_update_gfx_val(dev_priv);
10838 if (INTEL_INFO(dev)->gen >= 6)
10839 gen6_rps_busy(dev_priv);
10840 dev_priv->mm.busy = true;
10841 }
10842
10843 void intel_mark_idle(struct drm_device *dev)
10844 {
10845 struct drm_i915_private *dev_priv = dev->dev_private;
10846
10847 if (!dev_priv->mm.busy)
10848 return;
10849
10850 dev_priv->mm.busy = false;
10851
10852 if (INTEL_INFO(dev)->gen >= 6)
10853 gen6_rps_idle(dev->dev_private);
10854
10855 intel_runtime_pm_put(dev_priv);
10856 }
10857
10858 static void intel_crtc_destroy(struct drm_crtc *crtc)
10859 {
10860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10861 struct drm_device *dev = crtc->dev;
10862 struct intel_unpin_work *work;
10863
10864 spin_lock_irq(&dev->event_lock);
10865 work = intel_crtc->unpin_work;
10866 intel_crtc->unpin_work = NULL;
10867 spin_unlock_irq(&dev->event_lock);
10868
10869 if (work) {
10870 cancel_work_sync(&work->work);
10871 kfree(work);
10872 }
10873
10874 drm_crtc_cleanup(crtc);
10875
10876 kfree(intel_crtc);
10877 }
10878
10879 static void intel_unpin_work_fn(struct work_struct *__work)
10880 {
10881 struct intel_unpin_work *work =
10882 container_of(__work, struct intel_unpin_work, work);
10883 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10884 struct drm_device *dev = crtc->base.dev;
10885 struct drm_plane *primary = crtc->base.primary;
10886
10887 mutex_lock(&dev->struct_mutex);
10888 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10889 drm_gem_object_unreference(&work->pending_flip_obj->base);
10890
10891 if (work->flip_queued_req)
10892 i915_gem_request_assign(&work->flip_queued_req, NULL);
10893 mutex_unlock(&dev->struct_mutex);
10894
10895 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10896 intel_fbc_post_update(crtc);
10897 drm_framebuffer_unreference(work->old_fb);
10898
10899 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10900 atomic_dec(&crtc->unpin_work_count);
10901
10902 kfree(work);
10903 }
10904
10905 static void do_intel_finish_page_flip(struct drm_device *dev,
10906 struct drm_crtc *crtc)
10907 {
10908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10909 struct intel_unpin_work *work;
10910 unsigned long flags;
10911
10912 /* Ignore early vblank irqs */
10913 if (intel_crtc == NULL)
10914 return;
10915
10916 /*
10917 * This is called both by irq handlers and the reset code (to complete
10918 * lost pageflips) so needs the full irqsave spinlocks.
10919 */
10920 spin_lock_irqsave(&dev->event_lock, flags);
10921 work = intel_crtc->unpin_work;
10922
10923 /* Ensure we don't miss a work->pending update ... */
10924 smp_rmb();
10925
10926 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10927 spin_unlock_irqrestore(&dev->event_lock, flags);
10928 return;
10929 }
10930
10931 page_flip_completed(intel_crtc);
10932
10933 spin_unlock_irqrestore(&dev->event_lock, flags);
10934 }
10935
10936 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10937 {
10938 struct drm_i915_private *dev_priv = dev->dev_private;
10939 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10940
10941 do_intel_finish_page_flip(dev, crtc);
10942 }
10943
10944 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10945 {
10946 struct drm_i915_private *dev_priv = dev->dev_private;
10947 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10948
10949 do_intel_finish_page_flip(dev, crtc);
10950 }
10951
10952 /* Is 'a' after or equal to 'b'? */
10953 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10954 {
10955 return !((a - b) & 0x80000000);
10956 }
10957
10958 static bool page_flip_finished(struct intel_crtc *crtc)
10959 {
10960 struct drm_device *dev = crtc->base.dev;
10961 struct drm_i915_private *dev_priv = dev->dev_private;
10962 unsigned reset_counter;
10963
10964 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10965 if (crtc->reset_counter != reset_counter)
10966 return true;
10967
10968 /*
10969 * The relevant registers doen't exist on pre-ctg.
10970 * As the flip done interrupt doesn't trigger for mmio
10971 * flips on gmch platforms, a flip count check isn't
10972 * really needed there. But since ctg has the registers,
10973 * include it in the check anyway.
10974 */
10975 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10976 return true;
10977
10978 /*
10979 * BDW signals flip done immediately if the plane
10980 * is disabled, even if the plane enable is already
10981 * armed to occur at the next vblank :(
10982 */
10983
10984 /*
10985 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10986 * used the same base address. In that case the mmio flip might
10987 * have completed, but the CS hasn't even executed the flip yet.
10988 *
10989 * A flip count check isn't enough as the CS might have updated
10990 * the base address just after start of vblank, but before we
10991 * managed to process the interrupt. This means we'd complete the
10992 * CS flip too soon.
10993 *
10994 * Combining both checks should get us a good enough result. It may
10995 * still happen that the CS flip has been executed, but has not
10996 * yet actually completed. But in case the base address is the same
10997 * anyway, we don't really care.
10998 */
10999 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11000 crtc->unpin_work->gtt_offset &&
11001 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11002 crtc->unpin_work->flip_count);
11003 }
11004
11005 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11006 {
11007 struct drm_i915_private *dev_priv = dev->dev_private;
11008 struct intel_crtc *intel_crtc =
11009 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11010 unsigned long flags;
11011
11012
11013 /*
11014 * This is called both by irq handlers and the reset code (to complete
11015 * lost pageflips) so needs the full irqsave spinlocks.
11016 *
11017 * NB: An MMIO update of the plane base pointer will also
11018 * generate a page-flip completion irq, i.e. every modeset
11019 * is also accompanied by a spurious intel_prepare_page_flip().
11020 */
11021 spin_lock_irqsave(&dev->event_lock, flags);
11022 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11023 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11024 spin_unlock_irqrestore(&dev->event_lock, flags);
11025 }
11026
11027 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11028 {
11029 /* Ensure that the work item is consistent when activating it ... */
11030 smp_wmb();
11031 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11032 /* and that it is marked active as soon as the irq could fire. */
11033 smp_wmb();
11034 }
11035
11036 static int intel_gen2_queue_flip(struct drm_device *dev,
11037 struct drm_crtc *crtc,
11038 struct drm_framebuffer *fb,
11039 struct drm_i915_gem_object *obj,
11040 struct drm_i915_gem_request *req,
11041 uint32_t flags)
11042 {
11043 struct intel_engine_cs *engine = req->engine;
11044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11045 u32 flip_mask;
11046 int ret;
11047
11048 ret = intel_ring_begin(req, 6);
11049 if (ret)
11050 return ret;
11051
11052 /* Can't queue multiple flips, so wait for the previous
11053 * one to finish before executing the next.
11054 */
11055 if (intel_crtc->plane)
11056 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11057 else
11058 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11059 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11060 intel_ring_emit(engine, MI_NOOP);
11061 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11063 intel_ring_emit(engine, fb->pitches[0]);
11064 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11065 intel_ring_emit(engine, 0); /* aux display base address, unused */
11066
11067 intel_mark_page_flip_active(intel_crtc->unpin_work);
11068 return 0;
11069 }
11070
11071 static int intel_gen3_queue_flip(struct drm_device *dev,
11072 struct drm_crtc *crtc,
11073 struct drm_framebuffer *fb,
11074 struct drm_i915_gem_object *obj,
11075 struct drm_i915_gem_request *req,
11076 uint32_t flags)
11077 {
11078 struct intel_engine_cs *engine = req->engine;
11079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11080 u32 flip_mask;
11081 int ret;
11082
11083 ret = intel_ring_begin(req, 6);
11084 if (ret)
11085 return ret;
11086
11087 if (intel_crtc->plane)
11088 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11089 else
11090 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11091 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11092 intel_ring_emit(engine, MI_NOOP);
11093 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11094 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11095 intel_ring_emit(engine, fb->pitches[0]);
11096 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11097 intel_ring_emit(engine, MI_NOOP);
11098
11099 intel_mark_page_flip_active(intel_crtc->unpin_work);
11100 return 0;
11101 }
11102
11103 static int intel_gen4_queue_flip(struct drm_device *dev,
11104 struct drm_crtc *crtc,
11105 struct drm_framebuffer *fb,
11106 struct drm_i915_gem_object *obj,
11107 struct drm_i915_gem_request *req,
11108 uint32_t flags)
11109 {
11110 struct intel_engine_cs *engine = req->engine;
11111 struct drm_i915_private *dev_priv = dev->dev_private;
11112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11113 uint32_t pf, pipesrc;
11114 int ret;
11115
11116 ret = intel_ring_begin(req, 4);
11117 if (ret)
11118 return ret;
11119
11120 /* i965+ uses the linear or tiled offsets from the
11121 * Display Registers (which do not change across a page-flip)
11122 * so we need only reprogram the base address.
11123 */
11124 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11125 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11126 intel_ring_emit(engine, fb->pitches[0]);
11127 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11128 obj->tiling_mode);
11129
11130 /* XXX Enabling the panel-fitter across page-flip is so far
11131 * untested on non-native modes, so ignore it for now.
11132 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11133 */
11134 pf = 0;
11135 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11136 intel_ring_emit(engine, pf | pipesrc);
11137
11138 intel_mark_page_flip_active(intel_crtc->unpin_work);
11139 return 0;
11140 }
11141
11142 static int intel_gen6_queue_flip(struct drm_device *dev,
11143 struct drm_crtc *crtc,
11144 struct drm_framebuffer *fb,
11145 struct drm_i915_gem_object *obj,
11146 struct drm_i915_gem_request *req,
11147 uint32_t flags)
11148 {
11149 struct intel_engine_cs *engine = req->engine;
11150 struct drm_i915_private *dev_priv = dev->dev_private;
11151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11152 uint32_t pf, pipesrc;
11153 int ret;
11154
11155 ret = intel_ring_begin(req, 4);
11156 if (ret)
11157 return ret;
11158
11159 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11160 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11161 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11162 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11163
11164 /* Contrary to the suggestions in the documentation,
11165 * "Enable Panel Fitter" does not seem to be required when page
11166 * flipping with a non-native mode, and worse causes a normal
11167 * modeset to fail.
11168 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11169 */
11170 pf = 0;
11171 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11172 intel_ring_emit(engine, pf | pipesrc);
11173
11174 intel_mark_page_flip_active(intel_crtc->unpin_work);
11175 return 0;
11176 }
11177
11178 static int intel_gen7_queue_flip(struct drm_device *dev,
11179 struct drm_crtc *crtc,
11180 struct drm_framebuffer *fb,
11181 struct drm_i915_gem_object *obj,
11182 struct drm_i915_gem_request *req,
11183 uint32_t flags)
11184 {
11185 struct intel_engine_cs *engine = req->engine;
11186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11187 uint32_t plane_bit = 0;
11188 int len, ret;
11189
11190 switch (intel_crtc->plane) {
11191 case PLANE_A:
11192 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11193 break;
11194 case PLANE_B:
11195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11196 break;
11197 case PLANE_C:
11198 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11199 break;
11200 default:
11201 WARN_ONCE(1, "unknown plane in flip command\n");
11202 return -ENODEV;
11203 }
11204
11205 len = 4;
11206 if (engine->id == RCS) {
11207 len += 6;
11208 /*
11209 * On Gen 8, SRM is now taking an extra dword to accommodate
11210 * 48bits addresses, and we need a NOOP for the batch size to
11211 * stay even.
11212 */
11213 if (IS_GEN8(dev))
11214 len += 2;
11215 }
11216
11217 /*
11218 * BSpec MI_DISPLAY_FLIP for IVB:
11219 * "The full packet must be contained within the same cache line."
11220 *
11221 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11222 * cacheline, if we ever start emitting more commands before
11223 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11224 * then do the cacheline alignment, and finally emit the
11225 * MI_DISPLAY_FLIP.
11226 */
11227 ret = intel_ring_cacheline_align(req);
11228 if (ret)
11229 return ret;
11230
11231 ret = intel_ring_begin(req, len);
11232 if (ret)
11233 return ret;
11234
11235 /* Unmask the flip-done completion message. Note that the bspec says that
11236 * we should do this for both the BCS and RCS, and that we must not unmask
11237 * more than one flip event at any time (or ensure that one flip message
11238 * can be sent by waiting for flip-done prior to queueing new flips).
11239 * Experimentation says that BCS works despite DERRMR masking all
11240 * flip-done completion events and that unmasking all planes at once
11241 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11242 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11243 */
11244 if (engine->id == RCS) {
11245 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11246 intel_ring_emit_reg(engine, DERRMR);
11247 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11248 DERRMR_PIPEB_PRI_FLIP_DONE |
11249 DERRMR_PIPEC_PRI_FLIP_DONE));
11250 if (IS_GEN8(dev))
11251 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11252 MI_SRM_LRM_GLOBAL_GTT);
11253 else
11254 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11255 MI_SRM_LRM_GLOBAL_GTT);
11256 intel_ring_emit_reg(engine, DERRMR);
11257 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11258 if (IS_GEN8(dev)) {
11259 intel_ring_emit(engine, 0);
11260 intel_ring_emit(engine, MI_NOOP);
11261 }
11262 }
11263
11264 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11265 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11266 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11267 intel_ring_emit(engine, (MI_NOOP));
11268
11269 intel_mark_page_flip_active(intel_crtc->unpin_work);
11270 return 0;
11271 }
11272
11273 static bool use_mmio_flip(struct intel_engine_cs *engine,
11274 struct drm_i915_gem_object *obj)
11275 {
11276 /*
11277 * This is not being used for older platforms, because
11278 * non-availability of flip done interrupt forces us to use
11279 * CS flips. Older platforms derive flip done using some clever
11280 * tricks involving the flip_pending status bits and vblank irqs.
11281 * So using MMIO flips there would disrupt this mechanism.
11282 */
11283
11284 if (engine == NULL)
11285 return true;
11286
11287 if (INTEL_INFO(engine->dev)->gen < 5)
11288 return false;
11289
11290 if (i915.use_mmio_flip < 0)
11291 return false;
11292 else if (i915.use_mmio_flip > 0)
11293 return true;
11294 else if (i915.enable_execlists)
11295 return true;
11296 else if (obj->base.dma_buf &&
11297 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11298 false))
11299 return true;
11300 else
11301 return engine != i915_gem_request_get_engine(obj->last_write_req);
11302 }
11303
11304 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11305 unsigned int rotation,
11306 struct intel_unpin_work *work)
11307 {
11308 struct drm_device *dev = intel_crtc->base.dev;
11309 struct drm_i915_private *dev_priv = dev->dev_private;
11310 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11311 const enum pipe pipe = intel_crtc->pipe;
11312 u32 ctl, stride, tile_height;
11313
11314 ctl = I915_READ(PLANE_CTL(pipe, 0));
11315 ctl &= ~PLANE_CTL_TILED_MASK;
11316 switch (fb->modifier[0]) {
11317 case DRM_FORMAT_MOD_NONE:
11318 break;
11319 case I915_FORMAT_MOD_X_TILED:
11320 ctl |= PLANE_CTL_TILED_X;
11321 break;
11322 case I915_FORMAT_MOD_Y_TILED:
11323 ctl |= PLANE_CTL_TILED_Y;
11324 break;
11325 case I915_FORMAT_MOD_Yf_TILED:
11326 ctl |= PLANE_CTL_TILED_YF;
11327 break;
11328 default:
11329 MISSING_CASE(fb->modifier[0]);
11330 }
11331
11332 /*
11333 * The stride is either expressed as a multiple of 64 bytes chunks for
11334 * linear buffers or in number of tiles for tiled buffers.
11335 */
11336 if (intel_rotation_90_or_270(rotation)) {
11337 /* stride = Surface height in tiles */
11338 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11339 stride = DIV_ROUND_UP(fb->height, tile_height);
11340 } else {
11341 stride = fb->pitches[0] /
11342 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11343 fb->pixel_format);
11344 }
11345
11346 /*
11347 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11348 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11349 */
11350 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11351 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11352
11353 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11354 POSTING_READ(PLANE_SURF(pipe, 0));
11355 }
11356
11357 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11358 struct intel_unpin_work *work)
11359 {
11360 struct drm_device *dev = intel_crtc->base.dev;
11361 struct drm_i915_private *dev_priv = dev->dev_private;
11362 struct intel_framebuffer *intel_fb =
11363 to_intel_framebuffer(intel_crtc->base.primary->fb);
11364 struct drm_i915_gem_object *obj = intel_fb->obj;
11365 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11366 u32 dspcntr;
11367
11368 dspcntr = I915_READ(reg);
11369
11370 if (obj->tiling_mode != I915_TILING_NONE)
11371 dspcntr |= DISPPLANE_TILED;
11372 else
11373 dspcntr &= ~DISPPLANE_TILED;
11374
11375 I915_WRITE(reg, dspcntr);
11376
11377 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11378 POSTING_READ(DSPSURF(intel_crtc->plane));
11379 }
11380
11381 /*
11382 * XXX: This is the temporary way to update the plane registers until we get
11383 * around to using the usual plane update functions for MMIO flips
11384 */
11385 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11386 {
11387 struct intel_crtc *crtc = mmio_flip->crtc;
11388 struct intel_unpin_work *work;
11389
11390 spin_lock_irq(&crtc->base.dev->event_lock);
11391 work = crtc->unpin_work;
11392 spin_unlock_irq(&crtc->base.dev->event_lock);
11393 if (work == NULL)
11394 return;
11395
11396 intel_mark_page_flip_active(work);
11397
11398 intel_pipe_update_start(crtc);
11399
11400 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11401 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11402 else
11403 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11404 ilk_do_mmio_flip(crtc, work);
11405
11406 intel_pipe_update_end(crtc);
11407 }
11408
11409 static void intel_mmio_flip_work_func(struct work_struct *work)
11410 {
11411 struct intel_mmio_flip *mmio_flip =
11412 container_of(work, struct intel_mmio_flip, work);
11413 struct intel_framebuffer *intel_fb =
11414 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11415 struct drm_i915_gem_object *obj = intel_fb->obj;
11416
11417 if (mmio_flip->req) {
11418 WARN_ON(__i915_wait_request(mmio_flip->req,
11419 false, NULL,
11420 &mmio_flip->i915->rps.mmioflips));
11421 i915_gem_request_unreference__unlocked(mmio_flip->req);
11422 }
11423
11424 /* For framebuffer backed by dmabuf, wait for fence */
11425 if (obj->base.dma_buf)
11426 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11427 false, false,
11428 MAX_SCHEDULE_TIMEOUT) < 0);
11429
11430 intel_do_mmio_flip(mmio_flip);
11431 kfree(mmio_flip);
11432 }
11433
11434 static int intel_queue_mmio_flip(struct drm_device *dev,
11435 struct drm_crtc *crtc,
11436 struct drm_i915_gem_object *obj)
11437 {
11438 struct intel_mmio_flip *mmio_flip;
11439
11440 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11441 if (mmio_flip == NULL)
11442 return -ENOMEM;
11443
11444 mmio_flip->i915 = to_i915(dev);
11445 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11446 mmio_flip->crtc = to_intel_crtc(crtc);
11447 mmio_flip->rotation = crtc->primary->state->rotation;
11448
11449 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11450 schedule_work(&mmio_flip->work);
11451
11452 return 0;
11453 }
11454
11455 static int intel_default_queue_flip(struct drm_device *dev,
11456 struct drm_crtc *crtc,
11457 struct drm_framebuffer *fb,
11458 struct drm_i915_gem_object *obj,
11459 struct drm_i915_gem_request *req,
11460 uint32_t flags)
11461 {
11462 return -ENODEV;
11463 }
11464
11465 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11466 struct drm_crtc *crtc)
11467 {
11468 struct drm_i915_private *dev_priv = dev->dev_private;
11469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11470 struct intel_unpin_work *work = intel_crtc->unpin_work;
11471 u32 addr;
11472
11473 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11474 return true;
11475
11476 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11477 return false;
11478
11479 if (!work->enable_stall_check)
11480 return false;
11481
11482 if (work->flip_ready_vblank == 0) {
11483 if (work->flip_queued_req &&
11484 !i915_gem_request_completed(work->flip_queued_req, true))
11485 return false;
11486
11487 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11488 }
11489
11490 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11491 return false;
11492
11493 /* Potential stall - if we see that the flip has happened,
11494 * assume a missed interrupt. */
11495 if (INTEL_INFO(dev)->gen >= 4)
11496 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11497 else
11498 addr = I915_READ(DSPADDR(intel_crtc->plane));
11499
11500 /* There is a potential issue here with a false positive after a flip
11501 * to the same address. We could address this by checking for a
11502 * non-incrementing frame counter.
11503 */
11504 return addr == work->gtt_offset;
11505 }
11506
11507 void intel_check_page_flip(struct drm_device *dev, int pipe)
11508 {
11509 struct drm_i915_private *dev_priv = dev->dev_private;
11510 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11512 struct intel_unpin_work *work;
11513
11514 WARN_ON(!in_interrupt());
11515
11516 if (crtc == NULL)
11517 return;
11518
11519 spin_lock(&dev->event_lock);
11520 work = intel_crtc->unpin_work;
11521 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11522 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11523 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11524 page_flip_completed(intel_crtc);
11525 work = NULL;
11526 }
11527 if (work != NULL &&
11528 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11529 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11530 spin_unlock(&dev->event_lock);
11531 }
11532
11533 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11534 struct drm_framebuffer *fb,
11535 struct drm_pending_vblank_event *event,
11536 uint32_t page_flip_flags)
11537 {
11538 struct drm_device *dev = crtc->dev;
11539 struct drm_i915_private *dev_priv = dev->dev_private;
11540 struct drm_framebuffer *old_fb = crtc->primary->fb;
11541 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11543 struct drm_plane *primary = crtc->primary;
11544 enum pipe pipe = intel_crtc->pipe;
11545 struct intel_unpin_work *work;
11546 struct intel_engine_cs *engine;
11547 bool mmio_flip;
11548 struct drm_i915_gem_request *request = NULL;
11549 int ret;
11550
11551 /*
11552 * drm_mode_page_flip_ioctl() should already catch this, but double
11553 * check to be safe. In the future we may enable pageflipping from
11554 * a disabled primary plane.
11555 */
11556 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11557 return -EBUSY;
11558
11559 /* Can't change pixel format via MI display flips. */
11560 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11561 return -EINVAL;
11562
11563 /*
11564 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11565 * Note that pitch changes could also affect these register.
11566 */
11567 if (INTEL_INFO(dev)->gen > 3 &&
11568 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11569 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11570 return -EINVAL;
11571
11572 if (i915_terminally_wedged(&dev_priv->gpu_error))
11573 goto out_hang;
11574
11575 work = kzalloc(sizeof(*work), GFP_KERNEL);
11576 if (work == NULL)
11577 return -ENOMEM;
11578
11579 work->event = event;
11580 work->crtc = crtc;
11581 work->old_fb = old_fb;
11582 INIT_WORK(&work->work, intel_unpin_work_fn);
11583
11584 ret = drm_crtc_vblank_get(crtc);
11585 if (ret)
11586 goto free_work;
11587
11588 /* We borrow the event spin lock for protecting unpin_work */
11589 spin_lock_irq(&dev->event_lock);
11590 if (intel_crtc->unpin_work) {
11591 /* Before declaring the flip queue wedged, check if
11592 * the hardware completed the operation behind our backs.
11593 */
11594 if (__intel_pageflip_stall_check(dev, crtc)) {
11595 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11596 page_flip_completed(intel_crtc);
11597 } else {
11598 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11599 spin_unlock_irq(&dev->event_lock);
11600
11601 drm_crtc_vblank_put(crtc);
11602 kfree(work);
11603 return -EBUSY;
11604 }
11605 }
11606 intel_crtc->unpin_work = work;
11607 spin_unlock_irq(&dev->event_lock);
11608
11609 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11610 flush_workqueue(dev_priv->wq);
11611
11612 /* Reference the objects for the scheduled work. */
11613 drm_framebuffer_reference(work->old_fb);
11614 drm_gem_object_reference(&obj->base);
11615
11616 crtc->primary->fb = fb;
11617 update_state_fb(crtc->primary);
11618 intel_fbc_pre_update(intel_crtc);
11619
11620 work->pending_flip_obj = obj;
11621
11622 ret = i915_mutex_lock_interruptible(dev);
11623 if (ret)
11624 goto cleanup;
11625
11626 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11627 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11628 ret = -EIO;
11629 goto cleanup;
11630 }
11631
11632 atomic_inc(&intel_crtc->unpin_work_count);
11633
11634 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11635 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11636
11637 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11638 engine = &dev_priv->engine[BCS];
11639 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11640 /* vlv: DISPLAY_FLIP fails to change tiling */
11641 engine = NULL;
11642 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11643 engine = &dev_priv->engine[BCS];
11644 } else if (INTEL_INFO(dev)->gen >= 7) {
11645 engine = i915_gem_request_get_engine(obj->last_write_req);
11646 if (engine == NULL || engine->id != RCS)
11647 engine = &dev_priv->engine[BCS];
11648 } else {
11649 engine = &dev_priv->engine[RCS];
11650 }
11651
11652 mmio_flip = use_mmio_flip(engine, obj);
11653
11654 /* When using CS flips, we want to emit semaphores between rings.
11655 * However, when using mmio flips we will create a task to do the
11656 * synchronisation, so all we want here is to pin the framebuffer
11657 * into the display plane and skip any waits.
11658 */
11659 if (!mmio_flip) {
11660 ret = i915_gem_object_sync(obj, engine, &request);
11661 if (ret)
11662 goto cleanup_pending;
11663 }
11664
11665 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11666 if (ret)
11667 goto cleanup_pending;
11668
11669 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11670 obj, 0);
11671 work->gtt_offset += intel_crtc->dspaddr_offset;
11672
11673 if (mmio_flip) {
11674 ret = intel_queue_mmio_flip(dev, crtc, obj);
11675 if (ret)
11676 goto cleanup_unpin;
11677
11678 i915_gem_request_assign(&work->flip_queued_req,
11679 obj->last_write_req);
11680 } else {
11681 if (!request) {
11682 request = i915_gem_request_alloc(engine, NULL);
11683 if (IS_ERR(request)) {
11684 ret = PTR_ERR(request);
11685 goto cleanup_unpin;
11686 }
11687 }
11688
11689 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11690 page_flip_flags);
11691 if (ret)
11692 goto cleanup_unpin;
11693
11694 i915_gem_request_assign(&work->flip_queued_req, request);
11695 }
11696
11697 if (request)
11698 i915_add_request_no_flush(request);
11699
11700 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11701 work->enable_stall_check = true;
11702
11703 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11704 to_intel_plane(primary)->frontbuffer_bit);
11705 mutex_unlock(&dev->struct_mutex);
11706
11707 intel_frontbuffer_flip_prepare(dev,
11708 to_intel_plane(primary)->frontbuffer_bit);
11709
11710 trace_i915_flip_request(intel_crtc->plane, obj);
11711
11712 return 0;
11713
11714 cleanup_unpin:
11715 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11716 cleanup_pending:
11717 if (!IS_ERR_OR_NULL(request))
11718 i915_add_request_no_flush(request);
11719 atomic_dec(&intel_crtc->unpin_work_count);
11720 mutex_unlock(&dev->struct_mutex);
11721 cleanup:
11722 crtc->primary->fb = old_fb;
11723 update_state_fb(crtc->primary);
11724
11725 drm_gem_object_unreference_unlocked(&obj->base);
11726 drm_framebuffer_unreference(work->old_fb);
11727
11728 spin_lock_irq(&dev->event_lock);
11729 intel_crtc->unpin_work = NULL;
11730 spin_unlock_irq(&dev->event_lock);
11731
11732 drm_crtc_vblank_put(crtc);
11733 free_work:
11734 kfree(work);
11735
11736 if (ret == -EIO) {
11737 struct drm_atomic_state *state;
11738 struct drm_plane_state *plane_state;
11739
11740 out_hang:
11741 state = drm_atomic_state_alloc(dev);
11742 if (!state)
11743 return -ENOMEM;
11744 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11745
11746 retry:
11747 plane_state = drm_atomic_get_plane_state(state, primary);
11748 ret = PTR_ERR_OR_ZERO(plane_state);
11749 if (!ret) {
11750 drm_atomic_set_fb_for_plane(plane_state, fb);
11751
11752 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11753 if (!ret)
11754 ret = drm_atomic_commit(state);
11755 }
11756
11757 if (ret == -EDEADLK) {
11758 drm_modeset_backoff(state->acquire_ctx);
11759 drm_atomic_state_clear(state);
11760 goto retry;
11761 }
11762
11763 if (ret)
11764 drm_atomic_state_free(state);
11765
11766 if (ret == 0 && event) {
11767 spin_lock_irq(&dev->event_lock);
11768 drm_crtc_send_vblank_event(crtc, event);
11769 spin_unlock_irq(&dev->event_lock);
11770 }
11771 }
11772 return ret;
11773 }
11774
11775
11776 /**
11777 * intel_wm_need_update - Check whether watermarks need updating
11778 * @plane: drm plane
11779 * @state: new plane state
11780 *
11781 * Check current plane state versus the new one to determine whether
11782 * watermarks need to be recalculated.
11783 *
11784 * Returns true or false.
11785 */
11786 static bool intel_wm_need_update(struct drm_plane *plane,
11787 struct drm_plane_state *state)
11788 {
11789 struct intel_plane_state *new = to_intel_plane_state(state);
11790 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11791
11792 /* Update watermarks on tiling or size changes. */
11793 if (new->visible != cur->visible)
11794 return true;
11795
11796 if (!cur->base.fb || !new->base.fb)
11797 return false;
11798
11799 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11800 cur->base.rotation != new->base.rotation ||
11801 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11802 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11803 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11804 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11805 return true;
11806
11807 return false;
11808 }
11809
11810 static bool needs_scaling(struct intel_plane_state *state)
11811 {
11812 int src_w = drm_rect_width(&state->src) >> 16;
11813 int src_h = drm_rect_height(&state->src) >> 16;
11814 int dst_w = drm_rect_width(&state->dst);
11815 int dst_h = drm_rect_height(&state->dst);
11816
11817 return (src_w != dst_w || src_h != dst_h);
11818 }
11819
11820 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11821 struct drm_plane_state *plane_state)
11822 {
11823 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11824 struct drm_crtc *crtc = crtc_state->crtc;
11825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11826 struct drm_plane *plane = plane_state->plane;
11827 struct drm_device *dev = crtc->dev;
11828 struct drm_i915_private *dev_priv = to_i915(dev);
11829 struct intel_plane_state *old_plane_state =
11830 to_intel_plane_state(plane->state);
11831 int idx = intel_crtc->base.base.id, ret;
11832 bool mode_changed = needs_modeset(crtc_state);
11833 bool was_crtc_enabled = crtc->state->active;
11834 bool is_crtc_enabled = crtc_state->active;
11835 bool turn_off, turn_on, visible, was_visible;
11836 struct drm_framebuffer *fb = plane_state->fb;
11837
11838 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11839 plane->type != DRM_PLANE_TYPE_CURSOR) {
11840 ret = skl_update_scaler_plane(
11841 to_intel_crtc_state(crtc_state),
11842 to_intel_plane_state(plane_state));
11843 if (ret)
11844 return ret;
11845 }
11846
11847 was_visible = old_plane_state->visible;
11848 visible = to_intel_plane_state(plane_state)->visible;
11849
11850 if (!was_crtc_enabled && WARN_ON(was_visible))
11851 was_visible = false;
11852
11853 /*
11854 * Visibility is calculated as if the crtc was on, but
11855 * after scaler setup everything depends on it being off
11856 * when the crtc isn't active.
11857 */
11858 if (!is_crtc_enabled)
11859 to_intel_plane_state(plane_state)->visible = visible = false;
11860
11861 if (!was_visible && !visible)
11862 return 0;
11863
11864 if (fb != old_plane_state->base.fb)
11865 pipe_config->fb_changed = true;
11866
11867 turn_off = was_visible && (!visible || mode_changed);
11868 turn_on = visible && (!was_visible || mode_changed);
11869
11870 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11871 plane->base.id, fb ? fb->base.id : -1);
11872
11873 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11874 plane->base.id, was_visible, visible,
11875 turn_off, turn_on, mode_changed);
11876
11877 if (turn_on) {
11878 pipe_config->update_wm_pre = true;
11879
11880 /* must disable cxsr around plane enable/disable */
11881 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11882 pipe_config->disable_cxsr = true;
11883 } else if (turn_off) {
11884 pipe_config->update_wm_post = true;
11885
11886 /* must disable cxsr around plane enable/disable */
11887 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11888 pipe_config->disable_cxsr = true;
11889 } else if (intel_wm_need_update(plane, plane_state)) {
11890 /* FIXME bollocks */
11891 pipe_config->update_wm_pre = true;
11892 pipe_config->update_wm_post = true;
11893 }
11894
11895 /* Pre-gen9 platforms need two-step watermark updates */
11896 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11897 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11898 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11899
11900 if (visible || was_visible)
11901 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11902
11903 /*
11904 * WaCxSRDisabledForSpriteScaling:ivb
11905 *
11906 * cstate->update_wm was already set above, so this flag will
11907 * take effect when we commit and program watermarks.
11908 */
11909 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11910 needs_scaling(to_intel_plane_state(plane_state)) &&
11911 !needs_scaling(old_plane_state))
11912 pipe_config->disable_lp_wm = true;
11913
11914 return 0;
11915 }
11916
11917 static bool encoders_cloneable(const struct intel_encoder *a,
11918 const struct intel_encoder *b)
11919 {
11920 /* masks could be asymmetric, so check both ways */
11921 return a == b || (a->cloneable & (1 << b->type) &&
11922 b->cloneable & (1 << a->type));
11923 }
11924
11925 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11926 struct intel_crtc *crtc,
11927 struct intel_encoder *encoder)
11928 {
11929 struct intel_encoder *source_encoder;
11930 struct drm_connector *connector;
11931 struct drm_connector_state *connector_state;
11932 int i;
11933
11934 for_each_connector_in_state(state, connector, connector_state, i) {
11935 if (connector_state->crtc != &crtc->base)
11936 continue;
11937
11938 source_encoder =
11939 to_intel_encoder(connector_state->best_encoder);
11940 if (!encoders_cloneable(encoder, source_encoder))
11941 return false;
11942 }
11943
11944 return true;
11945 }
11946
11947 static bool check_encoder_cloning(struct drm_atomic_state *state,
11948 struct intel_crtc *crtc)
11949 {
11950 struct intel_encoder *encoder;
11951 struct drm_connector *connector;
11952 struct drm_connector_state *connector_state;
11953 int i;
11954
11955 for_each_connector_in_state(state, connector, connector_state, i) {
11956 if (connector_state->crtc != &crtc->base)
11957 continue;
11958
11959 encoder = to_intel_encoder(connector_state->best_encoder);
11960 if (!check_single_encoder_cloning(state, crtc, encoder))
11961 return false;
11962 }
11963
11964 return true;
11965 }
11966
11967 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11968 struct drm_crtc_state *crtc_state)
11969 {
11970 struct drm_device *dev = crtc->dev;
11971 struct drm_i915_private *dev_priv = dev->dev_private;
11972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11973 struct intel_crtc_state *pipe_config =
11974 to_intel_crtc_state(crtc_state);
11975 struct drm_atomic_state *state = crtc_state->state;
11976 int ret;
11977 bool mode_changed = needs_modeset(crtc_state);
11978
11979 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11980 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11981 return -EINVAL;
11982 }
11983
11984 if (mode_changed && !crtc_state->active)
11985 pipe_config->update_wm_post = true;
11986
11987 if (mode_changed && crtc_state->enable &&
11988 dev_priv->display.crtc_compute_clock &&
11989 !WARN_ON(pipe_config->shared_dpll)) {
11990 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11991 pipe_config);
11992 if (ret)
11993 return ret;
11994 }
11995
11996 if (crtc_state->color_mgmt_changed) {
11997 ret = intel_color_check(crtc, crtc_state);
11998 if (ret)
11999 return ret;
12000 }
12001
12002 ret = 0;
12003 if (dev_priv->display.compute_pipe_wm) {
12004 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12005 if (ret) {
12006 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12007 return ret;
12008 }
12009 }
12010
12011 if (dev_priv->display.compute_intermediate_wm &&
12012 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12013 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12014 return 0;
12015
12016 /*
12017 * Calculate 'intermediate' watermarks that satisfy both the
12018 * old state and the new state. We can program these
12019 * immediately.
12020 */
12021 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12022 intel_crtc,
12023 pipe_config);
12024 if (ret) {
12025 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12026 return ret;
12027 }
12028 } else if (dev_priv->display.compute_intermediate_wm) {
12029 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12030 pipe_config->wm.intermediate = pipe_config->wm.optimal.ilk;
12031 }
12032
12033 if (INTEL_INFO(dev)->gen >= 9) {
12034 if (mode_changed)
12035 ret = skl_update_scaler_crtc(pipe_config);
12036
12037 if (!ret)
12038 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12039 pipe_config);
12040 }
12041
12042 return ret;
12043 }
12044
12045 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12046 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12047 .atomic_begin = intel_begin_crtc_commit,
12048 .atomic_flush = intel_finish_crtc_commit,
12049 .atomic_check = intel_crtc_atomic_check,
12050 };
12051
12052 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12053 {
12054 struct intel_connector *connector;
12055
12056 for_each_intel_connector(dev, connector) {
12057 if (connector->base.state->crtc)
12058 drm_connector_unreference(&connector->base);
12059
12060 if (connector->base.encoder) {
12061 connector->base.state->best_encoder =
12062 connector->base.encoder;
12063 connector->base.state->crtc =
12064 connector->base.encoder->crtc;
12065
12066 drm_connector_reference(&connector->base);
12067 } else {
12068 connector->base.state->best_encoder = NULL;
12069 connector->base.state->crtc = NULL;
12070 }
12071 }
12072 }
12073
12074 static void
12075 connected_sink_compute_bpp(struct intel_connector *connector,
12076 struct intel_crtc_state *pipe_config)
12077 {
12078 int bpp = pipe_config->pipe_bpp;
12079
12080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12081 connector->base.base.id,
12082 connector->base.name);
12083
12084 /* Don't use an invalid EDID bpc value */
12085 if (connector->base.display_info.bpc &&
12086 connector->base.display_info.bpc * 3 < bpp) {
12087 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12088 bpp, connector->base.display_info.bpc*3);
12089 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12090 }
12091
12092 /* Clamp bpp to default limit on screens without EDID 1.4 */
12093 if (connector->base.display_info.bpc == 0) {
12094 int type = connector->base.connector_type;
12095 int clamp_bpp = 24;
12096
12097 /* Fall back to 18 bpp when DP sink capability is unknown. */
12098 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12099 type == DRM_MODE_CONNECTOR_eDP)
12100 clamp_bpp = 18;
12101
12102 if (bpp > clamp_bpp) {
12103 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12104 bpp, clamp_bpp);
12105 pipe_config->pipe_bpp = clamp_bpp;
12106 }
12107 }
12108 }
12109
12110 static int
12111 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12112 struct intel_crtc_state *pipe_config)
12113 {
12114 struct drm_device *dev = crtc->base.dev;
12115 struct drm_atomic_state *state;
12116 struct drm_connector *connector;
12117 struct drm_connector_state *connector_state;
12118 int bpp, i;
12119
12120 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12121 bpp = 10*3;
12122 else if (INTEL_INFO(dev)->gen >= 5)
12123 bpp = 12*3;
12124 else
12125 bpp = 8*3;
12126
12127
12128 pipe_config->pipe_bpp = bpp;
12129
12130 state = pipe_config->base.state;
12131
12132 /* Clamp display bpp to EDID value */
12133 for_each_connector_in_state(state, connector, connector_state, i) {
12134 if (connector_state->crtc != &crtc->base)
12135 continue;
12136
12137 connected_sink_compute_bpp(to_intel_connector(connector),
12138 pipe_config);
12139 }
12140
12141 return bpp;
12142 }
12143
12144 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12145 {
12146 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12147 "type: 0x%x flags: 0x%x\n",
12148 mode->crtc_clock,
12149 mode->crtc_hdisplay, mode->crtc_hsync_start,
12150 mode->crtc_hsync_end, mode->crtc_htotal,
12151 mode->crtc_vdisplay, mode->crtc_vsync_start,
12152 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12153 }
12154
12155 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12156 struct intel_crtc_state *pipe_config,
12157 const char *context)
12158 {
12159 struct drm_device *dev = crtc->base.dev;
12160 struct drm_plane *plane;
12161 struct intel_plane *intel_plane;
12162 struct intel_plane_state *state;
12163 struct drm_framebuffer *fb;
12164
12165 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12166 context, pipe_config, pipe_name(crtc->pipe));
12167
12168 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12169 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12170 pipe_config->pipe_bpp, pipe_config->dither);
12171 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12172 pipe_config->has_pch_encoder,
12173 pipe_config->fdi_lanes,
12174 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12175 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12176 pipe_config->fdi_m_n.tu);
12177 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12178 pipe_config->has_dp_encoder,
12179 pipe_config->lane_count,
12180 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12181 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12182 pipe_config->dp_m_n.tu);
12183
12184 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12185 pipe_config->has_dp_encoder,
12186 pipe_config->lane_count,
12187 pipe_config->dp_m2_n2.gmch_m,
12188 pipe_config->dp_m2_n2.gmch_n,
12189 pipe_config->dp_m2_n2.link_m,
12190 pipe_config->dp_m2_n2.link_n,
12191 pipe_config->dp_m2_n2.tu);
12192
12193 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12194 pipe_config->has_audio,
12195 pipe_config->has_infoframe);
12196
12197 DRM_DEBUG_KMS("requested mode:\n");
12198 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12199 DRM_DEBUG_KMS("adjusted mode:\n");
12200 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12201 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12202 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12203 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12204 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12205 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12206 crtc->num_scalers,
12207 pipe_config->scaler_state.scaler_users,
12208 pipe_config->scaler_state.scaler_id);
12209 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12210 pipe_config->gmch_pfit.control,
12211 pipe_config->gmch_pfit.pgm_ratios,
12212 pipe_config->gmch_pfit.lvds_border_bits);
12213 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12214 pipe_config->pch_pfit.pos,
12215 pipe_config->pch_pfit.size,
12216 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12217 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12218 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12219
12220 if (IS_BROXTON(dev)) {
12221 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12222 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12223 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12224 pipe_config->ddi_pll_sel,
12225 pipe_config->dpll_hw_state.ebb0,
12226 pipe_config->dpll_hw_state.ebb4,
12227 pipe_config->dpll_hw_state.pll0,
12228 pipe_config->dpll_hw_state.pll1,
12229 pipe_config->dpll_hw_state.pll2,
12230 pipe_config->dpll_hw_state.pll3,
12231 pipe_config->dpll_hw_state.pll6,
12232 pipe_config->dpll_hw_state.pll8,
12233 pipe_config->dpll_hw_state.pll9,
12234 pipe_config->dpll_hw_state.pll10,
12235 pipe_config->dpll_hw_state.pcsdw12);
12236 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12237 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12238 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12239 pipe_config->ddi_pll_sel,
12240 pipe_config->dpll_hw_state.ctrl1,
12241 pipe_config->dpll_hw_state.cfgcr1,
12242 pipe_config->dpll_hw_state.cfgcr2);
12243 } else if (HAS_DDI(dev)) {
12244 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12245 pipe_config->ddi_pll_sel,
12246 pipe_config->dpll_hw_state.wrpll,
12247 pipe_config->dpll_hw_state.spll);
12248 } else {
12249 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12250 "fp0: 0x%x, fp1: 0x%x\n",
12251 pipe_config->dpll_hw_state.dpll,
12252 pipe_config->dpll_hw_state.dpll_md,
12253 pipe_config->dpll_hw_state.fp0,
12254 pipe_config->dpll_hw_state.fp1);
12255 }
12256
12257 DRM_DEBUG_KMS("planes on this crtc\n");
12258 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12259 intel_plane = to_intel_plane(plane);
12260 if (intel_plane->pipe != crtc->pipe)
12261 continue;
12262
12263 state = to_intel_plane_state(plane->state);
12264 fb = state->base.fb;
12265 if (!fb) {
12266 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12267 "disabled, scaler_id = %d\n",
12268 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12269 plane->base.id, intel_plane->pipe,
12270 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12271 drm_plane_index(plane), state->scaler_id);
12272 continue;
12273 }
12274
12275 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12276 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12277 plane->base.id, intel_plane->pipe,
12278 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12279 drm_plane_index(plane));
12280 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12281 fb->base.id, fb->width, fb->height, fb->pixel_format);
12282 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12283 state->scaler_id,
12284 state->src.x1 >> 16, state->src.y1 >> 16,
12285 drm_rect_width(&state->src) >> 16,
12286 drm_rect_height(&state->src) >> 16,
12287 state->dst.x1, state->dst.y1,
12288 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12289 }
12290 }
12291
12292 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12293 {
12294 struct drm_device *dev = state->dev;
12295 struct drm_connector *connector;
12296 unsigned int used_ports = 0;
12297
12298 /*
12299 * Walk the connector list instead of the encoder
12300 * list to detect the problem on ddi platforms
12301 * where there's just one encoder per digital port.
12302 */
12303 drm_for_each_connector(connector, dev) {
12304 struct drm_connector_state *connector_state;
12305 struct intel_encoder *encoder;
12306
12307 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12308 if (!connector_state)
12309 connector_state = connector->state;
12310
12311 if (!connector_state->best_encoder)
12312 continue;
12313
12314 encoder = to_intel_encoder(connector_state->best_encoder);
12315
12316 WARN_ON(!connector_state->crtc);
12317
12318 switch (encoder->type) {
12319 unsigned int port_mask;
12320 case INTEL_OUTPUT_UNKNOWN:
12321 if (WARN_ON(!HAS_DDI(dev)))
12322 break;
12323 case INTEL_OUTPUT_DISPLAYPORT:
12324 case INTEL_OUTPUT_HDMI:
12325 case INTEL_OUTPUT_EDP:
12326 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12327
12328 /* the same port mustn't appear more than once */
12329 if (used_ports & port_mask)
12330 return false;
12331
12332 used_ports |= port_mask;
12333 default:
12334 break;
12335 }
12336 }
12337
12338 return true;
12339 }
12340
12341 static void
12342 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12343 {
12344 struct drm_crtc_state tmp_state;
12345 struct intel_crtc_scaler_state scaler_state;
12346 struct intel_dpll_hw_state dpll_hw_state;
12347 struct intel_shared_dpll *shared_dpll;
12348 uint32_t ddi_pll_sel;
12349 bool force_thru;
12350
12351 /* FIXME: before the switch to atomic started, a new pipe_config was
12352 * kzalloc'd. Code that depends on any field being zero should be
12353 * fixed, so that the crtc_state can be safely duplicated. For now,
12354 * only fields that are know to not cause problems are preserved. */
12355
12356 tmp_state = crtc_state->base;
12357 scaler_state = crtc_state->scaler_state;
12358 shared_dpll = crtc_state->shared_dpll;
12359 dpll_hw_state = crtc_state->dpll_hw_state;
12360 ddi_pll_sel = crtc_state->ddi_pll_sel;
12361 force_thru = crtc_state->pch_pfit.force_thru;
12362
12363 memset(crtc_state, 0, sizeof *crtc_state);
12364
12365 crtc_state->base = tmp_state;
12366 crtc_state->scaler_state = scaler_state;
12367 crtc_state->shared_dpll = shared_dpll;
12368 crtc_state->dpll_hw_state = dpll_hw_state;
12369 crtc_state->ddi_pll_sel = ddi_pll_sel;
12370 crtc_state->pch_pfit.force_thru = force_thru;
12371 }
12372
12373 static int
12374 intel_modeset_pipe_config(struct drm_crtc *crtc,
12375 struct intel_crtc_state *pipe_config)
12376 {
12377 struct drm_atomic_state *state = pipe_config->base.state;
12378 struct intel_encoder *encoder;
12379 struct drm_connector *connector;
12380 struct drm_connector_state *connector_state;
12381 int base_bpp, ret = -EINVAL;
12382 int i;
12383 bool retry = true;
12384
12385 clear_intel_crtc_state(pipe_config);
12386
12387 pipe_config->cpu_transcoder =
12388 (enum transcoder) to_intel_crtc(crtc)->pipe;
12389
12390 /*
12391 * Sanitize sync polarity flags based on requested ones. If neither
12392 * positive or negative polarity is requested, treat this as meaning
12393 * negative polarity.
12394 */
12395 if (!(pipe_config->base.adjusted_mode.flags &
12396 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12397 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12398
12399 if (!(pipe_config->base.adjusted_mode.flags &
12400 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12401 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12402
12403 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12404 pipe_config);
12405 if (base_bpp < 0)
12406 goto fail;
12407
12408 /*
12409 * Determine the real pipe dimensions. Note that stereo modes can
12410 * increase the actual pipe size due to the frame doubling and
12411 * insertion of additional space for blanks between the frame. This
12412 * is stored in the crtc timings. We use the requested mode to do this
12413 * computation to clearly distinguish it from the adjusted mode, which
12414 * can be changed by the connectors in the below retry loop.
12415 */
12416 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12417 &pipe_config->pipe_src_w,
12418 &pipe_config->pipe_src_h);
12419
12420 encoder_retry:
12421 /* Ensure the port clock defaults are reset when retrying. */
12422 pipe_config->port_clock = 0;
12423 pipe_config->pixel_multiplier = 1;
12424
12425 /* Fill in default crtc timings, allow encoders to overwrite them. */
12426 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12427 CRTC_STEREO_DOUBLE);
12428
12429 /* Pass our mode to the connectors and the CRTC to give them a chance to
12430 * adjust it according to limitations or connector properties, and also
12431 * a chance to reject the mode entirely.
12432 */
12433 for_each_connector_in_state(state, connector, connector_state, i) {
12434 if (connector_state->crtc != crtc)
12435 continue;
12436
12437 encoder = to_intel_encoder(connector_state->best_encoder);
12438
12439 if (!(encoder->compute_config(encoder, pipe_config))) {
12440 DRM_DEBUG_KMS("Encoder config failure\n");
12441 goto fail;
12442 }
12443 }
12444
12445 /* Set default port clock if not overwritten by the encoder. Needs to be
12446 * done afterwards in case the encoder adjusts the mode. */
12447 if (!pipe_config->port_clock)
12448 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12449 * pipe_config->pixel_multiplier;
12450
12451 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12452 if (ret < 0) {
12453 DRM_DEBUG_KMS("CRTC fixup failed\n");
12454 goto fail;
12455 }
12456
12457 if (ret == RETRY) {
12458 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12459 ret = -EINVAL;
12460 goto fail;
12461 }
12462
12463 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12464 retry = false;
12465 goto encoder_retry;
12466 }
12467
12468 /* Dithering seems to not pass-through bits correctly when it should, so
12469 * only enable it on 6bpc panels. */
12470 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12471 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12472 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12473
12474 fail:
12475 return ret;
12476 }
12477
12478 static void
12479 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12480 {
12481 struct drm_crtc *crtc;
12482 struct drm_crtc_state *crtc_state;
12483 int i;
12484
12485 /* Double check state. */
12486 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12487 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12488
12489 /* Update hwmode for vblank functions */
12490 if (crtc->state->active)
12491 crtc->hwmode = crtc->state->adjusted_mode;
12492 else
12493 crtc->hwmode.crtc_clock = 0;
12494
12495 /*
12496 * Update legacy state to satisfy fbc code. This can
12497 * be removed when fbc uses the atomic state.
12498 */
12499 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12500 struct drm_plane_state *plane_state = crtc->primary->state;
12501
12502 crtc->primary->fb = plane_state->fb;
12503 crtc->x = plane_state->src_x >> 16;
12504 crtc->y = plane_state->src_y >> 16;
12505 }
12506 }
12507 }
12508
12509 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12510 {
12511 int diff;
12512
12513 if (clock1 == clock2)
12514 return true;
12515
12516 if (!clock1 || !clock2)
12517 return false;
12518
12519 diff = abs(clock1 - clock2);
12520
12521 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12522 return true;
12523
12524 return false;
12525 }
12526
12527 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12528 list_for_each_entry((intel_crtc), \
12529 &(dev)->mode_config.crtc_list, \
12530 base.head) \
12531 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12532
12533 static bool
12534 intel_compare_m_n(unsigned int m, unsigned int n,
12535 unsigned int m2, unsigned int n2,
12536 bool exact)
12537 {
12538 if (m == m2 && n == n2)
12539 return true;
12540
12541 if (exact || !m || !n || !m2 || !n2)
12542 return false;
12543
12544 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12545
12546 if (n > n2) {
12547 while (n > n2) {
12548 m2 <<= 1;
12549 n2 <<= 1;
12550 }
12551 } else if (n < n2) {
12552 while (n < n2) {
12553 m <<= 1;
12554 n <<= 1;
12555 }
12556 }
12557
12558 if (n != n2)
12559 return false;
12560
12561 return intel_fuzzy_clock_check(m, m2);
12562 }
12563
12564 static bool
12565 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12566 struct intel_link_m_n *m2_n2,
12567 bool adjust)
12568 {
12569 if (m_n->tu == m2_n2->tu &&
12570 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12571 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12572 intel_compare_m_n(m_n->link_m, m_n->link_n,
12573 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12574 if (adjust)
12575 *m2_n2 = *m_n;
12576
12577 return true;
12578 }
12579
12580 return false;
12581 }
12582
12583 static bool
12584 intel_pipe_config_compare(struct drm_device *dev,
12585 struct intel_crtc_state *current_config,
12586 struct intel_crtc_state *pipe_config,
12587 bool adjust)
12588 {
12589 bool ret = true;
12590
12591 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12592 do { \
12593 if (!adjust) \
12594 DRM_ERROR(fmt, ##__VA_ARGS__); \
12595 else \
12596 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12597 } while (0)
12598
12599 #define PIPE_CONF_CHECK_X(name) \
12600 if (current_config->name != pipe_config->name) { \
12601 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12602 "(expected 0x%08x, found 0x%08x)\n", \
12603 current_config->name, \
12604 pipe_config->name); \
12605 ret = false; \
12606 }
12607
12608 #define PIPE_CONF_CHECK_I(name) \
12609 if (current_config->name != pipe_config->name) { \
12610 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12611 "(expected %i, found %i)\n", \
12612 current_config->name, \
12613 pipe_config->name); \
12614 ret = false; \
12615 }
12616
12617 #define PIPE_CONF_CHECK_P(name) \
12618 if (current_config->name != pipe_config->name) { \
12619 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12620 "(expected %p, found %p)\n", \
12621 current_config->name, \
12622 pipe_config->name); \
12623 ret = false; \
12624 }
12625
12626 #define PIPE_CONF_CHECK_M_N(name) \
12627 if (!intel_compare_link_m_n(&current_config->name, \
12628 &pipe_config->name,\
12629 adjust)) { \
12630 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12631 "(expected tu %i gmch %i/%i link %i/%i, " \
12632 "found tu %i, gmch %i/%i link %i/%i)\n", \
12633 current_config->name.tu, \
12634 current_config->name.gmch_m, \
12635 current_config->name.gmch_n, \
12636 current_config->name.link_m, \
12637 current_config->name.link_n, \
12638 pipe_config->name.tu, \
12639 pipe_config->name.gmch_m, \
12640 pipe_config->name.gmch_n, \
12641 pipe_config->name.link_m, \
12642 pipe_config->name.link_n); \
12643 ret = false; \
12644 }
12645
12646 /* This is required for BDW+ where there is only one set of registers for
12647 * switching between high and low RR.
12648 * This macro can be used whenever a comparison has to be made between one
12649 * hw state and multiple sw state variables.
12650 */
12651 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12652 if (!intel_compare_link_m_n(&current_config->name, \
12653 &pipe_config->name, adjust) && \
12654 !intel_compare_link_m_n(&current_config->alt_name, \
12655 &pipe_config->name, adjust)) { \
12656 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12657 "(expected tu %i gmch %i/%i link %i/%i, " \
12658 "or tu %i gmch %i/%i link %i/%i, " \
12659 "found tu %i, gmch %i/%i link %i/%i)\n", \
12660 current_config->name.tu, \
12661 current_config->name.gmch_m, \
12662 current_config->name.gmch_n, \
12663 current_config->name.link_m, \
12664 current_config->name.link_n, \
12665 current_config->alt_name.tu, \
12666 current_config->alt_name.gmch_m, \
12667 current_config->alt_name.gmch_n, \
12668 current_config->alt_name.link_m, \
12669 current_config->alt_name.link_n, \
12670 pipe_config->name.tu, \
12671 pipe_config->name.gmch_m, \
12672 pipe_config->name.gmch_n, \
12673 pipe_config->name.link_m, \
12674 pipe_config->name.link_n); \
12675 ret = false; \
12676 }
12677
12678 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12679 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12680 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12681 "(expected %i, found %i)\n", \
12682 current_config->name & (mask), \
12683 pipe_config->name & (mask)); \
12684 ret = false; \
12685 }
12686
12687 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12688 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12689 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12690 "(expected %i, found %i)\n", \
12691 current_config->name, \
12692 pipe_config->name); \
12693 ret = false; \
12694 }
12695
12696 #define PIPE_CONF_QUIRK(quirk) \
12697 ((current_config->quirks | pipe_config->quirks) & (quirk))
12698
12699 PIPE_CONF_CHECK_I(cpu_transcoder);
12700
12701 PIPE_CONF_CHECK_I(has_pch_encoder);
12702 PIPE_CONF_CHECK_I(fdi_lanes);
12703 PIPE_CONF_CHECK_M_N(fdi_m_n);
12704
12705 PIPE_CONF_CHECK_I(has_dp_encoder);
12706 PIPE_CONF_CHECK_I(lane_count);
12707
12708 if (INTEL_INFO(dev)->gen < 8) {
12709 PIPE_CONF_CHECK_M_N(dp_m_n);
12710
12711 if (current_config->has_drrs)
12712 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12713 } else
12714 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12715
12716 PIPE_CONF_CHECK_I(has_dsi_encoder);
12717
12718 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12719 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12722 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12723 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12724
12725 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12726 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12727 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12728 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12729 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12730 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12731
12732 PIPE_CONF_CHECK_I(pixel_multiplier);
12733 PIPE_CONF_CHECK_I(has_hdmi_sink);
12734 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12735 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12736 PIPE_CONF_CHECK_I(limited_color_range);
12737 PIPE_CONF_CHECK_I(has_infoframe);
12738
12739 PIPE_CONF_CHECK_I(has_audio);
12740
12741 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12742 DRM_MODE_FLAG_INTERLACE);
12743
12744 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12745 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12746 DRM_MODE_FLAG_PHSYNC);
12747 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12748 DRM_MODE_FLAG_NHSYNC);
12749 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12750 DRM_MODE_FLAG_PVSYNC);
12751 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12752 DRM_MODE_FLAG_NVSYNC);
12753 }
12754
12755 PIPE_CONF_CHECK_X(gmch_pfit.control);
12756 /* pfit ratios are autocomputed by the hw on gen4+ */
12757 if (INTEL_INFO(dev)->gen < 4)
12758 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12759 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12760
12761 if (!adjust) {
12762 PIPE_CONF_CHECK_I(pipe_src_w);
12763 PIPE_CONF_CHECK_I(pipe_src_h);
12764
12765 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12766 if (current_config->pch_pfit.enabled) {
12767 PIPE_CONF_CHECK_X(pch_pfit.pos);
12768 PIPE_CONF_CHECK_X(pch_pfit.size);
12769 }
12770
12771 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12772 }
12773
12774 /* BDW+ don't expose a synchronous way to read the state */
12775 if (IS_HASWELL(dev))
12776 PIPE_CONF_CHECK_I(ips_enabled);
12777
12778 PIPE_CONF_CHECK_I(double_wide);
12779
12780 PIPE_CONF_CHECK_X(ddi_pll_sel);
12781
12782 PIPE_CONF_CHECK_P(shared_dpll);
12783 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12784 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12785 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12786 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12787 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12788 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12789 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12790 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12791 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12792
12793 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12794 PIPE_CONF_CHECK_X(dsi_pll.div);
12795
12796 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12797 PIPE_CONF_CHECK_I(pipe_bpp);
12798
12799 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12800 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12801
12802 #undef PIPE_CONF_CHECK_X
12803 #undef PIPE_CONF_CHECK_I
12804 #undef PIPE_CONF_CHECK_P
12805 #undef PIPE_CONF_CHECK_FLAGS
12806 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12807 #undef PIPE_CONF_QUIRK
12808 #undef INTEL_ERR_OR_DBG_KMS
12809
12810 return ret;
12811 }
12812
12813 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12814 const struct intel_crtc_state *pipe_config)
12815 {
12816 if (pipe_config->has_pch_encoder) {
12817 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12818 &pipe_config->fdi_m_n);
12819 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12820
12821 /*
12822 * FDI already provided one idea for the dotclock.
12823 * Yell if the encoder disagrees.
12824 */
12825 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12826 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12827 fdi_dotclock, dotclock);
12828 }
12829 }
12830
12831 static void verify_wm_state(struct drm_crtc *crtc,
12832 struct drm_crtc_state *new_state)
12833 {
12834 struct drm_device *dev = crtc->dev;
12835 struct drm_i915_private *dev_priv = dev->dev_private;
12836 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12837 struct skl_ddb_entry *hw_entry, *sw_entry;
12838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12839 const enum pipe pipe = intel_crtc->pipe;
12840 int plane;
12841
12842 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12843 return;
12844
12845 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12846 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12847
12848 /* planes */
12849 for_each_plane(dev_priv, pipe, plane) {
12850 hw_entry = &hw_ddb.plane[pipe][plane];
12851 sw_entry = &sw_ddb->plane[pipe][plane];
12852
12853 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12854 continue;
12855
12856 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12857 "(expected (%u,%u), found (%u,%u))\n",
12858 pipe_name(pipe), plane + 1,
12859 sw_entry->start, sw_entry->end,
12860 hw_entry->start, hw_entry->end);
12861 }
12862
12863 /* cursor */
12864 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12865 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12866
12867 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12868 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12869 "(expected (%u,%u), found (%u,%u))\n",
12870 pipe_name(pipe),
12871 sw_entry->start, sw_entry->end,
12872 hw_entry->start, hw_entry->end);
12873 }
12874 }
12875
12876 static void
12877 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12878 {
12879 struct drm_connector *connector;
12880
12881 drm_for_each_connector(connector, dev) {
12882 struct drm_encoder *encoder = connector->encoder;
12883 struct drm_connector_state *state = connector->state;
12884
12885 if (state->crtc != crtc)
12886 continue;
12887
12888 intel_connector_verify_state(to_intel_connector(connector));
12889
12890 I915_STATE_WARN(state->best_encoder != encoder,
12891 "connector's atomic encoder doesn't match legacy encoder\n");
12892 }
12893 }
12894
12895 static void
12896 verify_encoder_state(struct drm_device *dev)
12897 {
12898 struct intel_encoder *encoder;
12899 struct intel_connector *connector;
12900
12901 for_each_intel_encoder(dev, encoder) {
12902 bool enabled = false;
12903 enum pipe pipe;
12904
12905 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12906 encoder->base.base.id,
12907 encoder->base.name);
12908
12909 for_each_intel_connector(dev, connector) {
12910 if (connector->base.state->best_encoder != &encoder->base)
12911 continue;
12912 enabled = true;
12913
12914 I915_STATE_WARN(connector->base.state->crtc !=
12915 encoder->base.crtc,
12916 "connector's crtc doesn't match encoder crtc\n");
12917 }
12918
12919 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12920 "encoder's enabled state mismatch "
12921 "(expected %i, found %i)\n",
12922 !!encoder->base.crtc, enabled);
12923
12924 if (!encoder->base.crtc) {
12925 bool active;
12926
12927 active = encoder->get_hw_state(encoder, &pipe);
12928 I915_STATE_WARN(active,
12929 "encoder detached but still enabled on pipe %c.\n",
12930 pipe_name(pipe));
12931 }
12932 }
12933 }
12934
12935 static void
12936 verify_crtc_state(struct drm_crtc *crtc,
12937 struct drm_crtc_state *old_crtc_state,
12938 struct drm_crtc_state *new_crtc_state)
12939 {
12940 struct drm_device *dev = crtc->dev;
12941 struct drm_i915_private *dev_priv = dev->dev_private;
12942 struct intel_encoder *encoder;
12943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12944 struct intel_crtc_state *pipe_config, *sw_config;
12945 struct drm_atomic_state *old_state;
12946 bool active;
12947
12948 old_state = old_crtc_state->state;
12949 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12950 pipe_config = to_intel_crtc_state(old_crtc_state);
12951 memset(pipe_config, 0, sizeof(*pipe_config));
12952 pipe_config->base.crtc = crtc;
12953 pipe_config->base.state = old_state;
12954
12955 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12956
12957 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12958
12959 /* hw state is inconsistent with the pipe quirk */
12960 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12961 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12962 active = new_crtc_state->active;
12963
12964 I915_STATE_WARN(new_crtc_state->active != active,
12965 "crtc active state doesn't match with hw state "
12966 "(expected %i, found %i)\n", new_crtc_state->active, active);
12967
12968 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12969 "transitional active state does not match atomic hw state "
12970 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12971
12972 for_each_encoder_on_crtc(dev, crtc, encoder) {
12973 enum pipe pipe;
12974
12975 active = encoder->get_hw_state(encoder, &pipe);
12976 I915_STATE_WARN(active != new_crtc_state->active,
12977 "[ENCODER:%i] active %i with crtc active %i\n",
12978 encoder->base.base.id, active, new_crtc_state->active);
12979
12980 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12981 "Encoder connected to wrong pipe %c\n",
12982 pipe_name(pipe));
12983
12984 if (active)
12985 encoder->get_config(encoder, pipe_config);
12986 }
12987
12988 if (!new_crtc_state->active)
12989 return;
12990
12991 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12992
12993 sw_config = to_intel_crtc_state(crtc->state);
12994 if (!intel_pipe_config_compare(dev, sw_config,
12995 pipe_config, false)) {
12996 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12997 intel_dump_pipe_config(intel_crtc, pipe_config,
12998 "[hw state]");
12999 intel_dump_pipe_config(intel_crtc, sw_config,
13000 "[sw state]");
13001 }
13002 }
13003
13004 static void
13005 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13006 struct intel_shared_dpll *pll,
13007 struct drm_crtc *crtc,
13008 struct drm_crtc_state *new_state)
13009 {
13010 struct intel_dpll_hw_state dpll_hw_state;
13011 unsigned crtc_mask;
13012 bool active;
13013
13014 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13015
13016 DRM_DEBUG_KMS("%s\n", pll->name);
13017
13018 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13019
13020 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13021 I915_STATE_WARN(!pll->on && pll->active_mask,
13022 "pll in active use but not on in sw tracking\n");
13023 I915_STATE_WARN(pll->on && !pll->active_mask,
13024 "pll is on but not used by any active crtc\n");
13025 I915_STATE_WARN(pll->on != active,
13026 "pll on state mismatch (expected %i, found %i)\n",
13027 pll->on, active);
13028 }
13029
13030 if (!crtc) {
13031 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13032 "more active pll users than references: %x vs %x\n",
13033 pll->active_mask, pll->config.crtc_mask);
13034
13035 return;
13036 }
13037
13038 crtc_mask = 1 << drm_crtc_index(crtc);
13039
13040 if (new_state->active)
13041 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13042 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13043 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13044 else
13045 I915_STATE_WARN(pll->active_mask & crtc_mask,
13046 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13047 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13048
13049 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13050 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13051 crtc_mask, pll->config.crtc_mask);
13052
13053 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13054 &dpll_hw_state,
13055 sizeof(dpll_hw_state)),
13056 "pll hw state mismatch\n");
13057 }
13058
13059 static void
13060 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13061 struct drm_crtc_state *old_crtc_state,
13062 struct drm_crtc_state *new_crtc_state)
13063 {
13064 struct drm_i915_private *dev_priv = dev->dev_private;
13065 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13066 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13067
13068 if (new_state->shared_dpll)
13069 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13070
13071 if (old_state->shared_dpll &&
13072 old_state->shared_dpll != new_state->shared_dpll) {
13073 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13074 struct intel_shared_dpll *pll = old_state->shared_dpll;
13075
13076 I915_STATE_WARN(pll->active_mask & crtc_mask,
13077 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13078 pipe_name(drm_crtc_index(crtc)));
13079 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13080 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13081 pipe_name(drm_crtc_index(crtc)));
13082 }
13083 }
13084
13085 static void
13086 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13087 struct drm_crtc_state *old_state,
13088 struct drm_crtc_state *new_state)
13089 {
13090 if (!needs_modeset(new_state) &&
13091 !to_intel_crtc_state(new_state)->update_pipe)
13092 return;
13093
13094 verify_wm_state(crtc, new_state);
13095 verify_connector_state(crtc->dev, crtc);
13096 verify_crtc_state(crtc, old_state, new_state);
13097 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13098 }
13099
13100 static void
13101 verify_disabled_dpll_state(struct drm_device *dev)
13102 {
13103 struct drm_i915_private *dev_priv = dev->dev_private;
13104 int i;
13105
13106 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13107 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13108 }
13109
13110 static void
13111 intel_modeset_verify_disabled(struct drm_device *dev)
13112 {
13113 verify_encoder_state(dev);
13114 verify_connector_state(dev, NULL);
13115 verify_disabled_dpll_state(dev);
13116 }
13117
13118 static void update_scanline_offset(struct intel_crtc *crtc)
13119 {
13120 struct drm_device *dev = crtc->base.dev;
13121
13122 /*
13123 * The scanline counter increments at the leading edge of hsync.
13124 *
13125 * On most platforms it starts counting from vtotal-1 on the
13126 * first active line. That means the scanline counter value is
13127 * always one less than what we would expect. Ie. just after
13128 * start of vblank, which also occurs at start of hsync (on the
13129 * last active line), the scanline counter will read vblank_start-1.
13130 *
13131 * On gen2 the scanline counter starts counting from 1 instead
13132 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13133 * to keep the value positive), instead of adding one.
13134 *
13135 * On HSW+ the behaviour of the scanline counter depends on the output
13136 * type. For DP ports it behaves like most other platforms, but on HDMI
13137 * there's an extra 1 line difference. So we need to add two instead of
13138 * one to the value.
13139 */
13140 if (IS_GEN2(dev)) {
13141 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13142 int vtotal;
13143
13144 vtotal = adjusted_mode->crtc_vtotal;
13145 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13146 vtotal /= 2;
13147
13148 crtc->scanline_offset = vtotal - 1;
13149 } else if (HAS_DDI(dev) &&
13150 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13151 crtc->scanline_offset = 2;
13152 } else
13153 crtc->scanline_offset = 1;
13154 }
13155
13156 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13157 {
13158 struct drm_device *dev = state->dev;
13159 struct drm_i915_private *dev_priv = to_i915(dev);
13160 struct intel_shared_dpll_config *shared_dpll = NULL;
13161 struct drm_crtc *crtc;
13162 struct drm_crtc_state *crtc_state;
13163 int i;
13164
13165 if (!dev_priv->display.crtc_compute_clock)
13166 return;
13167
13168 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13170 struct intel_shared_dpll *old_dpll =
13171 to_intel_crtc_state(crtc->state)->shared_dpll;
13172
13173 if (!needs_modeset(crtc_state))
13174 continue;
13175
13176 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13177
13178 if (!old_dpll)
13179 continue;
13180
13181 if (!shared_dpll)
13182 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13183
13184 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13185 }
13186 }
13187
13188 /*
13189 * This implements the workaround described in the "notes" section of the mode
13190 * set sequence documentation. When going from no pipes or single pipe to
13191 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13192 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13193 */
13194 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13195 {
13196 struct drm_crtc_state *crtc_state;
13197 struct intel_crtc *intel_crtc;
13198 struct drm_crtc *crtc;
13199 struct intel_crtc_state *first_crtc_state = NULL;
13200 struct intel_crtc_state *other_crtc_state = NULL;
13201 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13202 int i;
13203
13204 /* look at all crtc's that are going to be enabled in during modeset */
13205 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13206 intel_crtc = to_intel_crtc(crtc);
13207
13208 if (!crtc_state->active || !needs_modeset(crtc_state))
13209 continue;
13210
13211 if (first_crtc_state) {
13212 other_crtc_state = to_intel_crtc_state(crtc_state);
13213 break;
13214 } else {
13215 first_crtc_state = to_intel_crtc_state(crtc_state);
13216 first_pipe = intel_crtc->pipe;
13217 }
13218 }
13219
13220 /* No workaround needed? */
13221 if (!first_crtc_state)
13222 return 0;
13223
13224 /* w/a possibly needed, check how many crtc's are already enabled. */
13225 for_each_intel_crtc(state->dev, intel_crtc) {
13226 struct intel_crtc_state *pipe_config;
13227
13228 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13229 if (IS_ERR(pipe_config))
13230 return PTR_ERR(pipe_config);
13231
13232 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13233
13234 if (!pipe_config->base.active ||
13235 needs_modeset(&pipe_config->base))
13236 continue;
13237
13238 /* 2 or more enabled crtcs means no need for w/a */
13239 if (enabled_pipe != INVALID_PIPE)
13240 return 0;
13241
13242 enabled_pipe = intel_crtc->pipe;
13243 }
13244
13245 if (enabled_pipe != INVALID_PIPE)
13246 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13247 else if (other_crtc_state)
13248 other_crtc_state->hsw_workaround_pipe = first_pipe;
13249
13250 return 0;
13251 }
13252
13253 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13254 {
13255 struct drm_crtc *crtc;
13256 struct drm_crtc_state *crtc_state;
13257 int ret = 0;
13258
13259 /* add all active pipes to the state */
13260 for_each_crtc(state->dev, crtc) {
13261 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13262 if (IS_ERR(crtc_state))
13263 return PTR_ERR(crtc_state);
13264
13265 if (!crtc_state->active || needs_modeset(crtc_state))
13266 continue;
13267
13268 crtc_state->mode_changed = true;
13269
13270 ret = drm_atomic_add_affected_connectors(state, crtc);
13271 if (ret)
13272 break;
13273
13274 ret = drm_atomic_add_affected_planes(state, crtc);
13275 if (ret)
13276 break;
13277 }
13278
13279 return ret;
13280 }
13281
13282 static int intel_modeset_checks(struct drm_atomic_state *state)
13283 {
13284 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13285 struct drm_i915_private *dev_priv = state->dev->dev_private;
13286 struct drm_crtc *crtc;
13287 struct drm_crtc_state *crtc_state;
13288 int ret = 0, i;
13289
13290 if (!check_digital_port_conflicts(state)) {
13291 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13292 return -EINVAL;
13293 }
13294
13295 intel_state->modeset = true;
13296 intel_state->active_crtcs = dev_priv->active_crtcs;
13297
13298 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13299 if (crtc_state->active)
13300 intel_state->active_crtcs |= 1 << i;
13301 else
13302 intel_state->active_crtcs &= ~(1 << i);
13303 }
13304
13305 /*
13306 * See if the config requires any additional preparation, e.g.
13307 * to adjust global state with pipes off. We need to do this
13308 * here so we can get the modeset_pipe updated config for the new
13309 * mode set on this crtc. For other crtcs we need to use the
13310 * adjusted_mode bits in the crtc directly.
13311 */
13312 if (dev_priv->display.modeset_calc_cdclk) {
13313 ret = dev_priv->display.modeset_calc_cdclk(state);
13314
13315 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13316 ret = intel_modeset_all_pipes(state);
13317
13318 if (ret < 0)
13319 return ret;
13320
13321 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13322 intel_state->cdclk, intel_state->dev_cdclk);
13323 } else
13324 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13325
13326 intel_modeset_clear_plls(state);
13327
13328 if (IS_HASWELL(dev_priv))
13329 return haswell_mode_set_planes_workaround(state);
13330
13331 return 0;
13332 }
13333
13334 /*
13335 * Handle calculation of various watermark data at the end of the atomic check
13336 * phase. The code here should be run after the per-crtc and per-plane 'check'
13337 * handlers to ensure that all derived state has been updated.
13338 */
13339 static void calc_watermark_data(struct drm_atomic_state *state)
13340 {
13341 struct drm_device *dev = state->dev;
13342 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13343 struct drm_crtc *crtc;
13344 struct drm_crtc_state *cstate;
13345 struct drm_plane *plane;
13346 struct drm_plane_state *pstate;
13347
13348 /*
13349 * Calculate watermark configuration details now that derived
13350 * plane/crtc state is all properly updated.
13351 */
13352 drm_for_each_crtc(crtc, dev) {
13353 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13354 crtc->state;
13355
13356 if (cstate->active)
13357 intel_state->wm_config.num_pipes_active++;
13358 }
13359 drm_for_each_legacy_plane(plane, dev) {
13360 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13361 plane->state;
13362
13363 if (!to_intel_plane_state(pstate)->visible)
13364 continue;
13365
13366 intel_state->wm_config.sprites_enabled = true;
13367 if (pstate->crtc_w != pstate->src_w >> 16 ||
13368 pstate->crtc_h != pstate->src_h >> 16)
13369 intel_state->wm_config.sprites_scaled = true;
13370 }
13371 }
13372
13373 /**
13374 * intel_atomic_check - validate state object
13375 * @dev: drm device
13376 * @state: state to validate
13377 */
13378 static int intel_atomic_check(struct drm_device *dev,
13379 struct drm_atomic_state *state)
13380 {
13381 struct drm_i915_private *dev_priv = to_i915(dev);
13382 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13383 struct drm_crtc *crtc;
13384 struct drm_crtc_state *crtc_state;
13385 int ret, i;
13386 bool any_ms = false;
13387
13388 ret = drm_atomic_helper_check_modeset(dev, state);
13389 if (ret)
13390 return ret;
13391
13392 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13393 struct intel_crtc_state *pipe_config =
13394 to_intel_crtc_state(crtc_state);
13395
13396 /* Catch I915_MODE_FLAG_INHERITED */
13397 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13398 crtc_state->mode_changed = true;
13399
13400 if (!crtc_state->enable) {
13401 if (needs_modeset(crtc_state))
13402 any_ms = true;
13403 continue;
13404 }
13405
13406 if (!needs_modeset(crtc_state))
13407 continue;
13408
13409 /* FIXME: For only active_changed we shouldn't need to do any
13410 * state recomputation at all. */
13411
13412 ret = drm_atomic_add_affected_connectors(state, crtc);
13413 if (ret)
13414 return ret;
13415
13416 ret = intel_modeset_pipe_config(crtc, pipe_config);
13417 if (ret)
13418 return ret;
13419
13420 if (i915.fastboot &&
13421 intel_pipe_config_compare(dev,
13422 to_intel_crtc_state(crtc->state),
13423 pipe_config, true)) {
13424 crtc_state->mode_changed = false;
13425 to_intel_crtc_state(crtc_state)->update_pipe = true;
13426 }
13427
13428 if (needs_modeset(crtc_state)) {
13429 any_ms = true;
13430
13431 ret = drm_atomic_add_affected_planes(state, crtc);
13432 if (ret)
13433 return ret;
13434 }
13435
13436 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13437 needs_modeset(crtc_state) ?
13438 "[modeset]" : "[fastset]");
13439 }
13440
13441 if (any_ms) {
13442 ret = intel_modeset_checks(state);
13443
13444 if (ret)
13445 return ret;
13446 } else
13447 intel_state->cdclk = dev_priv->cdclk_freq;
13448
13449 ret = drm_atomic_helper_check_planes(dev, state);
13450 if (ret)
13451 return ret;
13452
13453 intel_fbc_choose_crtc(dev_priv, state);
13454 calc_watermark_data(state);
13455
13456 return 0;
13457 }
13458
13459 static int intel_atomic_prepare_commit(struct drm_device *dev,
13460 struct drm_atomic_state *state,
13461 bool nonblock)
13462 {
13463 struct drm_i915_private *dev_priv = dev->dev_private;
13464 struct drm_plane_state *plane_state;
13465 struct drm_crtc_state *crtc_state;
13466 struct drm_plane *plane;
13467 struct drm_crtc *crtc;
13468 int i, ret;
13469
13470 if (nonblock) {
13471 DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n");
13472 return -EINVAL;
13473 }
13474
13475 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13476 if (state->legacy_cursor_update)
13477 continue;
13478
13479 ret = intel_crtc_wait_for_pending_flips(crtc);
13480 if (ret)
13481 return ret;
13482
13483 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13484 flush_workqueue(dev_priv->wq);
13485 }
13486
13487 ret = mutex_lock_interruptible(&dev->struct_mutex);
13488 if (ret)
13489 return ret;
13490
13491 ret = drm_atomic_helper_prepare_planes(dev, state);
13492 mutex_unlock(&dev->struct_mutex);
13493
13494 if (!ret && !nonblock) {
13495 for_each_plane_in_state(state, plane, plane_state, i) {
13496 struct intel_plane_state *intel_plane_state =
13497 to_intel_plane_state(plane_state);
13498
13499 if (!intel_plane_state->wait_req)
13500 continue;
13501
13502 ret = __i915_wait_request(intel_plane_state->wait_req,
13503 true, NULL, NULL);
13504 if (ret) {
13505 /* Any hang should be swallowed by the wait */
13506 WARN_ON(ret == -EIO);
13507 mutex_lock(&dev->struct_mutex);
13508 drm_atomic_helper_cleanup_planes(dev, state);
13509 mutex_unlock(&dev->struct_mutex);
13510 break;
13511 }
13512 }
13513 }
13514
13515 return ret;
13516 }
13517
13518 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13519 struct drm_i915_private *dev_priv,
13520 unsigned crtc_mask)
13521 {
13522 unsigned last_vblank_count[I915_MAX_PIPES];
13523 enum pipe pipe;
13524 int ret;
13525
13526 if (!crtc_mask)
13527 return;
13528
13529 for_each_pipe(dev_priv, pipe) {
13530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13531
13532 if (!((1 << pipe) & crtc_mask))
13533 continue;
13534
13535 ret = drm_crtc_vblank_get(crtc);
13536 if (WARN_ON(ret != 0)) {
13537 crtc_mask &= ~(1 << pipe);
13538 continue;
13539 }
13540
13541 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13542 }
13543
13544 for_each_pipe(dev_priv, pipe) {
13545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13546 long lret;
13547
13548 if (!((1 << pipe) & crtc_mask))
13549 continue;
13550
13551 lret = wait_event_timeout(dev->vblank[pipe].queue,
13552 last_vblank_count[pipe] !=
13553 drm_crtc_vblank_count(crtc),
13554 msecs_to_jiffies(50));
13555
13556 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13557
13558 drm_crtc_vblank_put(crtc);
13559 }
13560 }
13561
13562 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13563 {
13564 /* fb updated, need to unpin old fb */
13565 if (crtc_state->fb_changed)
13566 return true;
13567
13568 /* wm changes, need vblank before final wm's */
13569 if (crtc_state->update_wm_post)
13570 return true;
13571
13572 /*
13573 * cxsr is re-enabled after vblank.
13574 * This is already handled by crtc_state->update_wm_post,
13575 * but added for clarity.
13576 */
13577 if (crtc_state->disable_cxsr)
13578 return true;
13579
13580 return false;
13581 }
13582
13583 /**
13584 * intel_atomic_commit - commit validated state object
13585 * @dev: DRM device
13586 * @state: the top-level driver state object
13587 * @nonblock: nonblocking commit
13588 *
13589 * This function commits a top-level state object that has been validated
13590 * with drm_atomic_helper_check().
13591 *
13592 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13593 * we can only handle plane-related operations and do not yet support
13594 * nonblocking commit.
13595 *
13596 * RETURNS
13597 * Zero for success or -errno.
13598 */
13599 static int intel_atomic_commit(struct drm_device *dev,
13600 struct drm_atomic_state *state,
13601 bool nonblock)
13602 {
13603 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13604 struct drm_i915_private *dev_priv = dev->dev_private;
13605 struct drm_crtc_state *old_crtc_state;
13606 struct drm_crtc *crtc;
13607 struct intel_crtc_state *intel_cstate;
13608 int ret = 0, i;
13609 bool hw_check = intel_state->modeset;
13610 unsigned long put_domains[I915_MAX_PIPES] = {};
13611 unsigned crtc_vblank_mask = 0;
13612
13613 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13614 if (ret) {
13615 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13616 return ret;
13617 }
13618
13619 drm_atomic_helper_swap_state(dev, state);
13620 dev_priv->wm.config = intel_state->wm_config;
13621 intel_shared_dpll_commit(state);
13622
13623 if (intel_state->modeset) {
13624 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13625 sizeof(intel_state->min_pixclk));
13626 dev_priv->active_crtcs = intel_state->active_crtcs;
13627 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13628
13629 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13630 }
13631
13632 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13634
13635 if (needs_modeset(crtc->state) ||
13636 to_intel_crtc_state(crtc->state)->update_pipe) {
13637 hw_check = true;
13638
13639 put_domains[to_intel_crtc(crtc)->pipe] =
13640 modeset_get_crtc_power_domains(crtc,
13641 to_intel_crtc_state(crtc->state));
13642 }
13643
13644 if (!needs_modeset(crtc->state))
13645 continue;
13646
13647 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13648
13649 if (old_crtc_state->active) {
13650 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13651 dev_priv->display.crtc_disable(crtc);
13652 intel_crtc->active = false;
13653 intel_fbc_disable(intel_crtc);
13654 intel_disable_shared_dpll(intel_crtc);
13655
13656 /*
13657 * Underruns don't always raise
13658 * interrupts, so check manually.
13659 */
13660 intel_check_cpu_fifo_underruns(dev_priv);
13661 intel_check_pch_fifo_underruns(dev_priv);
13662
13663 if (!crtc->state->active)
13664 intel_update_watermarks(crtc);
13665 }
13666 }
13667
13668 /* Only after disabling all output pipelines that will be changed can we
13669 * update the the output configuration. */
13670 intel_modeset_update_crtc_state(state);
13671
13672 if (intel_state->modeset) {
13673 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13674
13675 if (dev_priv->display.modeset_commit_cdclk &&
13676 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13677 dev_priv->display.modeset_commit_cdclk(state);
13678
13679 intel_modeset_verify_disabled(dev);
13680 }
13681
13682 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13683 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13685 bool modeset = needs_modeset(crtc->state);
13686 struct intel_crtc_state *pipe_config =
13687 to_intel_crtc_state(crtc->state);
13688 bool update_pipe = !modeset && pipe_config->update_pipe;
13689
13690 if (modeset && crtc->state->active) {
13691 update_scanline_offset(to_intel_crtc(crtc));
13692 dev_priv->display.crtc_enable(crtc);
13693 }
13694
13695 if (!modeset)
13696 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13697
13698 if (crtc->state->active &&
13699 drm_atomic_get_existing_plane_state(state, crtc->primary))
13700 intel_fbc_enable(intel_crtc);
13701
13702 if (crtc->state->active &&
13703 (crtc->state->planes_changed || update_pipe))
13704 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13705
13706 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13707 crtc_vblank_mask |= 1 << i;
13708 }
13709
13710 /* FIXME: add subpixel order */
13711
13712 if (!state->legacy_cursor_update)
13713 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13714
13715 /*
13716 * Now that the vblank has passed, we can go ahead and program the
13717 * optimal watermarks on platforms that need two-step watermark
13718 * programming.
13719 *
13720 * TODO: Move this (and other cleanup) to an async worker eventually.
13721 */
13722 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13723 intel_cstate = to_intel_crtc_state(crtc->state);
13724
13725 if (dev_priv->display.optimize_watermarks)
13726 dev_priv->display.optimize_watermarks(intel_cstate);
13727 }
13728
13729 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13730 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13731
13732 if (put_domains[i])
13733 modeset_put_power_domains(dev_priv, put_domains[i]);
13734
13735 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13736 }
13737
13738 if (intel_state->modeset)
13739 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13740
13741 mutex_lock(&dev->struct_mutex);
13742 drm_atomic_helper_cleanup_planes(dev, state);
13743 mutex_unlock(&dev->struct_mutex);
13744
13745 drm_atomic_state_free(state);
13746
13747 /* As one of the primary mmio accessors, KMS has a high likelihood
13748 * of triggering bugs in unclaimed access. After we finish
13749 * modesetting, see if an error has been flagged, and if so
13750 * enable debugging for the next modeset - and hope we catch
13751 * the culprit.
13752 *
13753 * XXX note that we assume display power is on at this point.
13754 * This might hold true now but we need to add pm helper to check
13755 * unclaimed only when the hardware is on, as atomic commits
13756 * can happen also when the device is completely off.
13757 */
13758 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13759
13760 return 0;
13761 }
13762
13763 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13764 {
13765 struct drm_device *dev = crtc->dev;
13766 struct drm_atomic_state *state;
13767 struct drm_crtc_state *crtc_state;
13768 int ret;
13769
13770 state = drm_atomic_state_alloc(dev);
13771 if (!state) {
13772 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13773 crtc->base.id);
13774 return;
13775 }
13776
13777 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13778
13779 retry:
13780 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13781 ret = PTR_ERR_OR_ZERO(crtc_state);
13782 if (!ret) {
13783 if (!crtc_state->active)
13784 goto out;
13785
13786 crtc_state->mode_changed = true;
13787 ret = drm_atomic_commit(state);
13788 }
13789
13790 if (ret == -EDEADLK) {
13791 drm_atomic_state_clear(state);
13792 drm_modeset_backoff(state->acquire_ctx);
13793 goto retry;
13794 }
13795
13796 if (ret)
13797 out:
13798 drm_atomic_state_free(state);
13799 }
13800
13801 #undef for_each_intel_crtc_masked
13802
13803 static const struct drm_crtc_funcs intel_crtc_funcs = {
13804 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13805 .set_config = drm_atomic_helper_set_config,
13806 .set_property = drm_atomic_helper_crtc_set_property,
13807 .destroy = intel_crtc_destroy,
13808 .page_flip = intel_crtc_page_flip,
13809 .atomic_duplicate_state = intel_crtc_duplicate_state,
13810 .atomic_destroy_state = intel_crtc_destroy_state,
13811 };
13812
13813 /**
13814 * intel_prepare_plane_fb - Prepare fb for usage on plane
13815 * @plane: drm plane to prepare for
13816 * @fb: framebuffer to prepare for presentation
13817 *
13818 * Prepares a framebuffer for usage on a display plane. Generally this
13819 * involves pinning the underlying object and updating the frontbuffer tracking
13820 * bits. Some older platforms need special physical address handling for
13821 * cursor planes.
13822 *
13823 * Must be called with struct_mutex held.
13824 *
13825 * Returns 0 on success, negative error code on failure.
13826 */
13827 int
13828 intel_prepare_plane_fb(struct drm_plane *plane,
13829 const struct drm_plane_state *new_state)
13830 {
13831 struct drm_device *dev = plane->dev;
13832 struct drm_framebuffer *fb = new_state->fb;
13833 struct intel_plane *intel_plane = to_intel_plane(plane);
13834 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13835 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13836 int ret = 0;
13837
13838 if (!obj && !old_obj)
13839 return 0;
13840
13841 if (old_obj) {
13842 struct drm_crtc_state *crtc_state =
13843 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13844
13845 /* Big Hammer, we also need to ensure that any pending
13846 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13847 * current scanout is retired before unpinning the old
13848 * framebuffer. Note that we rely on userspace rendering
13849 * into the buffer attached to the pipe they are waiting
13850 * on. If not, userspace generates a GPU hang with IPEHR
13851 * point to the MI_WAIT_FOR_EVENT.
13852 *
13853 * This should only fail upon a hung GPU, in which case we
13854 * can safely continue.
13855 */
13856 if (needs_modeset(crtc_state))
13857 ret = i915_gem_object_wait_rendering(old_obj, true);
13858 if (ret) {
13859 /* GPU hangs should have been swallowed by the wait */
13860 WARN_ON(ret == -EIO);
13861 return ret;
13862 }
13863 }
13864
13865 /* For framebuffer backed by dmabuf, wait for fence */
13866 if (obj && obj->base.dma_buf) {
13867 long lret;
13868
13869 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13870 false, true,
13871 MAX_SCHEDULE_TIMEOUT);
13872 if (lret == -ERESTARTSYS)
13873 return lret;
13874
13875 WARN(lret < 0, "waiting returns %li\n", lret);
13876 }
13877
13878 if (!obj) {
13879 ret = 0;
13880 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13881 INTEL_INFO(dev)->cursor_needs_physical) {
13882 int align = IS_I830(dev) ? 16 * 1024 : 256;
13883 ret = i915_gem_object_attach_phys(obj, align);
13884 if (ret)
13885 DRM_DEBUG_KMS("failed to attach phys object\n");
13886 } else {
13887 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13888 }
13889
13890 if (ret == 0) {
13891 if (obj) {
13892 struct intel_plane_state *plane_state =
13893 to_intel_plane_state(new_state);
13894
13895 i915_gem_request_assign(&plane_state->wait_req,
13896 obj->last_write_req);
13897 }
13898
13899 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13900 }
13901
13902 return ret;
13903 }
13904
13905 /**
13906 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13907 * @plane: drm plane to clean up for
13908 * @fb: old framebuffer that was on plane
13909 *
13910 * Cleans up a framebuffer that has just been removed from a plane.
13911 *
13912 * Must be called with struct_mutex held.
13913 */
13914 void
13915 intel_cleanup_plane_fb(struct drm_plane *plane,
13916 const struct drm_plane_state *old_state)
13917 {
13918 struct drm_device *dev = plane->dev;
13919 struct intel_plane *intel_plane = to_intel_plane(plane);
13920 struct intel_plane_state *old_intel_state;
13921 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13922 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13923
13924 old_intel_state = to_intel_plane_state(old_state);
13925
13926 if (!obj && !old_obj)
13927 return;
13928
13929 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13930 !INTEL_INFO(dev)->cursor_needs_physical))
13931 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13932
13933 /* prepare_fb aborted? */
13934 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13935 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13936 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13937
13938 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13939 }
13940
13941 int
13942 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13943 {
13944 int max_scale;
13945 struct drm_device *dev;
13946 struct drm_i915_private *dev_priv;
13947 int crtc_clock, cdclk;
13948
13949 if (!intel_crtc || !crtc_state->base.enable)
13950 return DRM_PLANE_HELPER_NO_SCALING;
13951
13952 dev = intel_crtc->base.dev;
13953 dev_priv = dev->dev_private;
13954 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13955 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13956
13957 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13958 return DRM_PLANE_HELPER_NO_SCALING;
13959
13960 /*
13961 * skl max scale is lower of:
13962 * close to 3 but not 3, -1 is for that purpose
13963 * or
13964 * cdclk/crtc_clock
13965 */
13966 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13967
13968 return max_scale;
13969 }
13970
13971 static int
13972 intel_check_primary_plane(struct drm_plane *plane,
13973 struct intel_crtc_state *crtc_state,
13974 struct intel_plane_state *state)
13975 {
13976 struct drm_crtc *crtc = state->base.crtc;
13977 struct drm_framebuffer *fb = state->base.fb;
13978 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13979 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13980 bool can_position = false;
13981
13982 if (INTEL_INFO(plane->dev)->gen >= 9) {
13983 /* use scaler when colorkey is not required */
13984 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13985 min_scale = 1;
13986 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13987 }
13988 can_position = true;
13989 }
13990
13991 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13992 &state->dst, &state->clip,
13993 min_scale, max_scale,
13994 can_position, true,
13995 &state->visible);
13996 }
13997
13998 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13999 struct drm_crtc_state *old_crtc_state)
14000 {
14001 struct drm_device *dev = crtc->dev;
14002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14003 struct intel_crtc_state *old_intel_state =
14004 to_intel_crtc_state(old_crtc_state);
14005 bool modeset = needs_modeset(crtc->state);
14006
14007 /* Perform vblank evasion around commit operation */
14008 intel_pipe_update_start(intel_crtc);
14009
14010 if (modeset)
14011 return;
14012
14013 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14014 intel_color_set_csc(crtc->state);
14015 intel_color_load_luts(crtc->state);
14016 }
14017
14018 if (to_intel_crtc_state(crtc->state)->update_pipe)
14019 intel_update_pipe_config(intel_crtc, old_intel_state);
14020 else if (INTEL_INFO(dev)->gen >= 9)
14021 skl_detach_scalers(intel_crtc);
14022 }
14023
14024 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14025 struct drm_crtc_state *old_crtc_state)
14026 {
14027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14028
14029 intel_pipe_update_end(intel_crtc);
14030 }
14031
14032 /**
14033 * intel_plane_destroy - destroy a plane
14034 * @plane: plane to destroy
14035 *
14036 * Common destruction function for all types of planes (primary, cursor,
14037 * sprite).
14038 */
14039 void intel_plane_destroy(struct drm_plane *plane)
14040 {
14041 struct intel_plane *intel_plane = to_intel_plane(plane);
14042 drm_plane_cleanup(plane);
14043 kfree(intel_plane);
14044 }
14045
14046 const struct drm_plane_funcs intel_plane_funcs = {
14047 .update_plane = drm_atomic_helper_update_plane,
14048 .disable_plane = drm_atomic_helper_disable_plane,
14049 .destroy = intel_plane_destroy,
14050 .set_property = drm_atomic_helper_plane_set_property,
14051 .atomic_get_property = intel_plane_atomic_get_property,
14052 .atomic_set_property = intel_plane_atomic_set_property,
14053 .atomic_duplicate_state = intel_plane_duplicate_state,
14054 .atomic_destroy_state = intel_plane_destroy_state,
14055
14056 };
14057
14058 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14059 int pipe)
14060 {
14061 struct intel_plane *primary = NULL;
14062 struct intel_plane_state *state = NULL;
14063 const uint32_t *intel_primary_formats;
14064 unsigned int num_formats;
14065 int ret;
14066
14067 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14068 if (!primary)
14069 goto fail;
14070
14071 state = intel_create_plane_state(&primary->base);
14072 if (!state)
14073 goto fail;
14074 primary->base.state = &state->base;
14075
14076 primary->can_scale = false;
14077 primary->max_downscale = 1;
14078 if (INTEL_INFO(dev)->gen >= 9) {
14079 primary->can_scale = true;
14080 state->scaler_id = -1;
14081 }
14082 primary->pipe = pipe;
14083 primary->plane = pipe;
14084 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14085 primary->check_plane = intel_check_primary_plane;
14086 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14087 primary->plane = !pipe;
14088
14089 if (INTEL_INFO(dev)->gen >= 9) {
14090 intel_primary_formats = skl_primary_formats;
14091 num_formats = ARRAY_SIZE(skl_primary_formats);
14092
14093 primary->update_plane = skylake_update_primary_plane;
14094 primary->disable_plane = skylake_disable_primary_plane;
14095 } else if (HAS_PCH_SPLIT(dev)) {
14096 intel_primary_formats = i965_primary_formats;
14097 num_formats = ARRAY_SIZE(i965_primary_formats);
14098
14099 primary->update_plane = ironlake_update_primary_plane;
14100 primary->disable_plane = i9xx_disable_primary_plane;
14101 } else if (INTEL_INFO(dev)->gen >= 4) {
14102 intel_primary_formats = i965_primary_formats;
14103 num_formats = ARRAY_SIZE(i965_primary_formats);
14104
14105 primary->update_plane = i9xx_update_primary_plane;
14106 primary->disable_plane = i9xx_disable_primary_plane;
14107 } else {
14108 intel_primary_formats = i8xx_primary_formats;
14109 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14110
14111 primary->update_plane = i9xx_update_primary_plane;
14112 primary->disable_plane = i9xx_disable_primary_plane;
14113 }
14114
14115 ret = drm_universal_plane_init(dev, &primary->base, 0,
14116 &intel_plane_funcs,
14117 intel_primary_formats, num_formats,
14118 DRM_PLANE_TYPE_PRIMARY, NULL);
14119 if (ret)
14120 goto fail;
14121
14122 if (INTEL_INFO(dev)->gen >= 4)
14123 intel_create_rotation_property(dev, primary);
14124
14125 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14126
14127 return &primary->base;
14128
14129 fail:
14130 kfree(state);
14131 kfree(primary);
14132
14133 return NULL;
14134 }
14135
14136 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14137 {
14138 if (!dev->mode_config.rotation_property) {
14139 unsigned long flags = BIT(DRM_ROTATE_0) |
14140 BIT(DRM_ROTATE_180);
14141
14142 if (INTEL_INFO(dev)->gen >= 9)
14143 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14144
14145 dev->mode_config.rotation_property =
14146 drm_mode_create_rotation_property(dev, flags);
14147 }
14148 if (dev->mode_config.rotation_property)
14149 drm_object_attach_property(&plane->base.base,
14150 dev->mode_config.rotation_property,
14151 plane->base.state->rotation);
14152 }
14153
14154 static int
14155 intel_check_cursor_plane(struct drm_plane *plane,
14156 struct intel_crtc_state *crtc_state,
14157 struct intel_plane_state *state)
14158 {
14159 struct drm_crtc *crtc = crtc_state->base.crtc;
14160 struct drm_framebuffer *fb = state->base.fb;
14161 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14162 enum pipe pipe = to_intel_plane(plane)->pipe;
14163 unsigned stride;
14164 int ret;
14165
14166 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14167 &state->dst, &state->clip,
14168 DRM_PLANE_HELPER_NO_SCALING,
14169 DRM_PLANE_HELPER_NO_SCALING,
14170 true, true, &state->visible);
14171 if (ret)
14172 return ret;
14173
14174 /* if we want to turn off the cursor ignore width and height */
14175 if (!obj)
14176 return 0;
14177
14178 /* Check for which cursor types we support */
14179 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14180 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14181 state->base.crtc_w, state->base.crtc_h);
14182 return -EINVAL;
14183 }
14184
14185 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14186 if (obj->base.size < stride * state->base.crtc_h) {
14187 DRM_DEBUG_KMS("buffer is too small\n");
14188 return -ENOMEM;
14189 }
14190
14191 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14192 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14193 return -EINVAL;
14194 }
14195
14196 /*
14197 * There's something wrong with the cursor on CHV pipe C.
14198 * If it straddles the left edge of the screen then
14199 * moving it away from the edge or disabling it often
14200 * results in a pipe underrun, and often that can lead to
14201 * dead pipe (constant underrun reported, and it scans
14202 * out just a solid color). To recover from that, the
14203 * display power well must be turned off and on again.
14204 * Refuse the put the cursor into that compromised position.
14205 */
14206 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14207 state->visible && state->base.crtc_x < 0) {
14208 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14209 return -EINVAL;
14210 }
14211
14212 return 0;
14213 }
14214
14215 static void
14216 intel_disable_cursor_plane(struct drm_plane *plane,
14217 struct drm_crtc *crtc)
14218 {
14219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14220
14221 intel_crtc->cursor_addr = 0;
14222 intel_crtc_update_cursor(crtc, NULL);
14223 }
14224
14225 static void
14226 intel_update_cursor_plane(struct drm_plane *plane,
14227 const struct intel_crtc_state *crtc_state,
14228 const struct intel_plane_state *state)
14229 {
14230 struct drm_crtc *crtc = crtc_state->base.crtc;
14231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14232 struct drm_device *dev = plane->dev;
14233 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14234 uint32_t addr;
14235
14236 if (!obj)
14237 addr = 0;
14238 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14239 addr = i915_gem_obj_ggtt_offset(obj);
14240 else
14241 addr = obj->phys_handle->busaddr;
14242
14243 intel_crtc->cursor_addr = addr;
14244 intel_crtc_update_cursor(crtc, state);
14245 }
14246
14247 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14248 int pipe)
14249 {
14250 struct intel_plane *cursor = NULL;
14251 struct intel_plane_state *state = NULL;
14252 int ret;
14253
14254 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14255 if (!cursor)
14256 goto fail;
14257
14258 state = intel_create_plane_state(&cursor->base);
14259 if (!state)
14260 goto fail;
14261 cursor->base.state = &state->base;
14262
14263 cursor->can_scale = false;
14264 cursor->max_downscale = 1;
14265 cursor->pipe = pipe;
14266 cursor->plane = pipe;
14267 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14268 cursor->check_plane = intel_check_cursor_plane;
14269 cursor->update_plane = intel_update_cursor_plane;
14270 cursor->disable_plane = intel_disable_cursor_plane;
14271
14272 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14273 &intel_plane_funcs,
14274 intel_cursor_formats,
14275 ARRAY_SIZE(intel_cursor_formats),
14276 DRM_PLANE_TYPE_CURSOR, NULL);
14277 if (ret)
14278 goto fail;
14279
14280 if (INTEL_INFO(dev)->gen >= 4) {
14281 if (!dev->mode_config.rotation_property)
14282 dev->mode_config.rotation_property =
14283 drm_mode_create_rotation_property(dev,
14284 BIT(DRM_ROTATE_0) |
14285 BIT(DRM_ROTATE_180));
14286 if (dev->mode_config.rotation_property)
14287 drm_object_attach_property(&cursor->base.base,
14288 dev->mode_config.rotation_property,
14289 state->base.rotation);
14290 }
14291
14292 if (INTEL_INFO(dev)->gen >=9)
14293 state->scaler_id = -1;
14294
14295 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14296
14297 return &cursor->base;
14298
14299 fail:
14300 kfree(state);
14301 kfree(cursor);
14302
14303 return NULL;
14304 }
14305
14306 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14307 struct intel_crtc_state *crtc_state)
14308 {
14309 int i;
14310 struct intel_scaler *intel_scaler;
14311 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14312
14313 for (i = 0; i < intel_crtc->num_scalers; i++) {
14314 intel_scaler = &scaler_state->scalers[i];
14315 intel_scaler->in_use = 0;
14316 intel_scaler->mode = PS_SCALER_MODE_DYN;
14317 }
14318
14319 scaler_state->scaler_id = -1;
14320 }
14321
14322 static void intel_crtc_init(struct drm_device *dev, int pipe)
14323 {
14324 struct drm_i915_private *dev_priv = dev->dev_private;
14325 struct intel_crtc *intel_crtc;
14326 struct intel_crtc_state *crtc_state = NULL;
14327 struct drm_plane *primary = NULL;
14328 struct drm_plane *cursor = NULL;
14329 int ret;
14330
14331 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14332 if (intel_crtc == NULL)
14333 return;
14334
14335 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14336 if (!crtc_state)
14337 goto fail;
14338 intel_crtc->config = crtc_state;
14339 intel_crtc->base.state = &crtc_state->base;
14340 crtc_state->base.crtc = &intel_crtc->base;
14341
14342 /* initialize shared scalers */
14343 if (INTEL_INFO(dev)->gen >= 9) {
14344 if (pipe == PIPE_C)
14345 intel_crtc->num_scalers = 1;
14346 else
14347 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14348
14349 skl_init_scalers(dev, intel_crtc, crtc_state);
14350 }
14351
14352 primary = intel_primary_plane_create(dev, pipe);
14353 if (!primary)
14354 goto fail;
14355
14356 cursor = intel_cursor_plane_create(dev, pipe);
14357 if (!cursor)
14358 goto fail;
14359
14360 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14361 cursor, &intel_crtc_funcs, NULL);
14362 if (ret)
14363 goto fail;
14364
14365 /*
14366 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14367 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14368 */
14369 intel_crtc->pipe = pipe;
14370 intel_crtc->plane = pipe;
14371 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14372 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14373 intel_crtc->plane = !pipe;
14374 }
14375
14376 intel_crtc->cursor_base = ~0;
14377 intel_crtc->cursor_cntl = ~0;
14378 intel_crtc->cursor_size = ~0;
14379
14380 intel_crtc->wm.cxsr_allowed = true;
14381
14382 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14383 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14384 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14385 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14386
14387 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14388
14389 intel_color_init(&intel_crtc->base);
14390
14391 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14392 return;
14393
14394 fail:
14395 if (primary)
14396 drm_plane_cleanup(primary);
14397 if (cursor)
14398 drm_plane_cleanup(cursor);
14399 kfree(crtc_state);
14400 kfree(intel_crtc);
14401 }
14402
14403 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14404 {
14405 struct drm_encoder *encoder = connector->base.encoder;
14406 struct drm_device *dev = connector->base.dev;
14407
14408 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14409
14410 if (!encoder || WARN_ON(!encoder->crtc))
14411 return INVALID_PIPE;
14412
14413 return to_intel_crtc(encoder->crtc)->pipe;
14414 }
14415
14416 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14417 struct drm_file *file)
14418 {
14419 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14420 struct drm_crtc *drmmode_crtc;
14421 struct intel_crtc *crtc;
14422
14423 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14424
14425 if (!drmmode_crtc) {
14426 DRM_ERROR("no such CRTC id\n");
14427 return -ENOENT;
14428 }
14429
14430 crtc = to_intel_crtc(drmmode_crtc);
14431 pipe_from_crtc_id->pipe = crtc->pipe;
14432
14433 return 0;
14434 }
14435
14436 static int intel_encoder_clones(struct intel_encoder *encoder)
14437 {
14438 struct drm_device *dev = encoder->base.dev;
14439 struct intel_encoder *source_encoder;
14440 int index_mask = 0;
14441 int entry = 0;
14442
14443 for_each_intel_encoder(dev, source_encoder) {
14444 if (encoders_cloneable(encoder, source_encoder))
14445 index_mask |= (1 << entry);
14446
14447 entry++;
14448 }
14449
14450 return index_mask;
14451 }
14452
14453 static bool has_edp_a(struct drm_device *dev)
14454 {
14455 struct drm_i915_private *dev_priv = dev->dev_private;
14456
14457 if (!IS_MOBILE(dev))
14458 return false;
14459
14460 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14461 return false;
14462
14463 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14464 return false;
14465
14466 return true;
14467 }
14468
14469 static bool intel_crt_present(struct drm_device *dev)
14470 {
14471 struct drm_i915_private *dev_priv = dev->dev_private;
14472
14473 if (INTEL_INFO(dev)->gen >= 9)
14474 return false;
14475
14476 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14477 return false;
14478
14479 if (IS_CHERRYVIEW(dev))
14480 return false;
14481
14482 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14483 return false;
14484
14485 /* DDI E can't be used if DDI A requires 4 lanes */
14486 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14487 return false;
14488
14489 if (!dev_priv->vbt.int_crt_support)
14490 return false;
14491
14492 return true;
14493 }
14494
14495 static void intel_setup_outputs(struct drm_device *dev)
14496 {
14497 struct drm_i915_private *dev_priv = dev->dev_private;
14498 struct intel_encoder *encoder;
14499 bool dpd_is_edp = false;
14500
14501 intel_lvds_init(dev);
14502
14503 if (intel_crt_present(dev))
14504 intel_crt_init(dev);
14505
14506 if (IS_BROXTON(dev)) {
14507 /*
14508 * FIXME: Broxton doesn't support port detection via the
14509 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14510 * detect the ports.
14511 */
14512 intel_ddi_init(dev, PORT_A);
14513 intel_ddi_init(dev, PORT_B);
14514 intel_ddi_init(dev, PORT_C);
14515
14516 intel_dsi_init(dev);
14517 } else if (HAS_DDI(dev)) {
14518 int found;
14519
14520 /*
14521 * Haswell uses DDI functions to detect digital outputs.
14522 * On SKL pre-D0 the strap isn't connected, so we assume
14523 * it's there.
14524 */
14525 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14526 /* WaIgnoreDDIAStrap: skl */
14527 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14528 intel_ddi_init(dev, PORT_A);
14529
14530 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14531 * register */
14532 found = I915_READ(SFUSE_STRAP);
14533
14534 if (found & SFUSE_STRAP_DDIB_DETECTED)
14535 intel_ddi_init(dev, PORT_B);
14536 if (found & SFUSE_STRAP_DDIC_DETECTED)
14537 intel_ddi_init(dev, PORT_C);
14538 if (found & SFUSE_STRAP_DDID_DETECTED)
14539 intel_ddi_init(dev, PORT_D);
14540 /*
14541 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14542 */
14543 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14544 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14545 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14546 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14547 intel_ddi_init(dev, PORT_E);
14548
14549 } else if (HAS_PCH_SPLIT(dev)) {
14550 int found;
14551 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14552
14553 if (has_edp_a(dev))
14554 intel_dp_init(dev, DP_A, PORT_A);
14555
14556 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14557 /* PCH SDVOB multiplex with HDMIB */
14558 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14559 if (!found)
14560 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14561 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14562 intel_dp_init(dev, PCH_DP_B, PORT_B);
14563 }
14564
14565 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14566 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14567
14568 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14569 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14570
14571 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14572 intel_dp_init(dev, PCH_DP_C, PORT_C);
14573
14574 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14575 intel_dp_init(dev, PCH_DP_D, PORT_D);
14576 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14577 bool has_edp, has_port;
14578
14579 /*
14580 * The DP_DETECTED bit is the latched state of the DDC
14581 * SDA pin at boot. However since eDP doesn't require DDC
14582 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14583 * eDP ports may have been muxed to an alternate function.
14584 * Thus we can't rely on the DP_DETECTED bit alone to detect
14585 * eDP ports. Consult the VBT as well as DP_DETECTED to
14586 * detect eDP ports.
14587 *
14588 * Sadly the straps seem to be missing sometimes even for HDMI
14589 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14590 * and VBT for the presence of the port. Additionally we can't
14591 * trust the port type the VBT declares as we've seen at least
14592 * HDMI ports that the VBT claim are DP or eDP.
14593 */
14594 has_edp = intel_dp_is_edp(dev, PORT_B);
14595 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14596 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14597 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14598 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14599 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14600
14601 has_edp = intel_dp_is_edp(dev, PORT_C);
14602 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14603 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14604 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14605 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14606 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14607
14608 if (IS_CHERRYVIEW(dev)) {
14609 /*
14610 * eDP not supported on port D,
14611 * so no need to worry about it
14612 */
14613 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14614 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14615 intel_dp_init(dev, CHV_DP_D, PORT_D);
14616 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14617 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14618 }
14619
14620 intel_dsi_init(dev);
14621 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14622 bool found = false;
14623
14624 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14625 DRM_DEBUG_KMS("probing SDVOB\n");
14626 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14627 if (!found && IS_G4X(dev)) {
14628 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14629 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14630 }
14631
14632 if (!found && IS_G4X(dev))
14633 intel_dp_init(dev, DP_B, PORT_B);
14634 }
14635
14636 /* Before G4X SDVOC doesn't have its own detect register */
14637
14638 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14639 DRM_DEBUG_KMS("probing SDVOC\n");
14640 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14641 }
14642
14643 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14644
14645 if (IS_G4X(dev)) {
14646 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14647 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14648 }
14649 if (IS_G4X(dev))
14650 intel_dp_init(dev, DP_C, PORT_C);
14651 }
14652
14653 if (IS_G4X(dev) &&
14654 (I915_READ(DP_D) & DP_DETECTED))
14655 intel_dp_init(dev, DP_D, PORT_D);
14656 } else if (IS_GEN2(dev))
14657 intel_dvo_init(dev);
14658
14659 if (SUPPORTS_TV(dev))
14660 intel_tv_init(dev);
14661
14662 intel_psr_init(dev);
14663
14664 for_each_intel_encoder(dev, encoder) {
14665 encoder->base.possible_crtcs = encoder->crtc_mask;
14666 encoder->base.possible_clones =
14667 intel_encoder_clones(encoder);
14668 }
14669
14670 intel_init_pch_refclk(dev);
14671
14672 drm_helper_move_panel_connectors_to_head(dev);
14673 }
14674
14675 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14676 {
14677 struct drm_device *dev = fb->dev;
14678 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14679
14680 drm_framebuffer_cleanup(fb);
14681 mutex_lock(&dev->struct_mutex);
14682 WARN_ON(!intel_fb->obj->framebuffer_references--);
14683 drm_gem_object_unreference(&intel_fb->obj->base);
14684 mutex_unlock(&dev->struct_mutex);
14685 kfree(intel_fb);
14686 }
14687
14688 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14689 struct drm_file *file,
14690 unsigned int *handle)
14691 {
14692 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14693 struct drm_i915_gem_object *obj = intel_fb->obj;
14694
14695 if (obj->userptr.mm) {
14696 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14697 return -EINVAL;
14698 }
14699
14700 return drm_gem_handle_create(file, &obj->base, handle);
14701 }
14702
14703 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14704 struct drm_file *file,
14705 unsigned flags, unsigned color,
14706 struct drm_clip_rect *clips,
14707 unsigned num_clips)
14708 {
14709 struct drm_device *dev = fb->dev;
14710 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14711 struct drm_i915_gem_object *obj = intel_fb->obj;
14712
14713 mutex_lock(&dev->struct_mutex);
14714 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14715 mutex_unlock(&dev->struct_mutex);
14716
14717 return 0;
14718 }
14719
14720 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14721 .destroy = intel_user_framebuffer_destroy,
14722 .create_handle = intel_user_framebuffer_create_handle,
14723 .dirty = intel_user_framebuffer_dirty,
14724 };
14725
14726 static
14727 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14728 uint32_t pixel_format)
14729 {
14730 u32 gen = INTEL_INFO(dev)->gen;
14731
14732 if (gen >= 9) {
14733 int cpp = drm_format_plane_cpp(pixel_format, 0);
14734
14735 /* "The stride in bytes must not exceed the of the size of 8K
14736 * pixels and 32K bytes."
14737 */
14738 return min(8192 * cpp, 32768);
14739 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14740 return 32*1024;
14741 } else if (gen >= 4) {
14742 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14743 return 16*1024;
14744 else
14745 return 32*1024;
14746 } else if (gen >= 3) {
14747 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14748 return 8*1024;
14749 else
14750 return 16*1024;
14751 } else {
14752 /* XXX DSPC is limited to 4k tiled */
14753 return 8*1024;
14754 }
14755 }
14756
14757 static int intel_framebuffer_init(struct drm_device *dev,
14758 struct intel_framebuffer *intel_fb,
14759 struct drm_mode_fb_cmd2 *mode_cmd,
14760 struct drm_i915_gem_object *obj)
14761 {
14762 struct drm_i915_private *dev_priv = to_i915(dev);
14763 unsigned int aligned_height;
14764 int ret;
14765 u32 pitch_limit, stride_alignment;
14766
14767 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14768
14769 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14770 /* Enforce that fb modifier and tiling mode match, but only for
14771 * X-tiled. This is needed for FBC. */
14772 if (!!(obj->tiling_mode == I915_TILING_X) !=
14773 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14774 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14775 return -EINVAL;
14776 }
14777 } else {
14778 if (obj->tiling_mode == I915_TILING_X)
14779 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14780 else if (obj->tiling_mode == I915_TILING_Y) {
14781 DRM_DEBUG("No Y tiling for legacy addfb\n");
14782 return -EINVAL;
14783 }
14784 }
14785
14786 /* Passed in modifier sanity checking. */
14787 switch (mode_cmd->modifier[0]) {
14788 case I915_FORMAT_MOD_Y_TILED:
14789 case I915_FORMAT_MOD_Yf_TILED:
14790 if (INTEL_INFO(dev)->gen < 9) {
14791 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14792 mode_cmd->modifier[0]);
14793 return -EINVAL;
14794 }
14795 case DRM_FORMAT_MOD_NONE:
14796 case I915_FORMAT_MOD_X_TILED:
14797 break;
14798 default:
14799 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14800 mode_cmd->modifier[0]);
14801 return -EINVAL;
14802 }
14803
14804 stride_alignment = intel_fb_stride_alignment(dev_priv,
14805 mode_cmd->modifier[0],
14806 mode_cmd->pixel_format);
14807 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14808 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14809 mode_cmd->pitches[0], stride_alignment);
14810 return -EINVAL;
14811 }
14812
14813 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14814 mode_cmd->pixel_format);
14815 if (mode_cmd->pitches[0] > pitch_limit) {
14816 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14817 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14818 "tiled" : "linear",
14819 mode_cmd->pitches[0], pitch_limit);
14820 return -EINVAL;
14821 }
14822
14823 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14824 mode_cmd->pitches[0] != obj->stride) {
14825 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14826 mode_cmd->pitches[0], obj->stride);
14827 return -EINVAL;
14828 }
14829
14830 /* Reject formats not supported by any plane early. */
14831 switch (mode_cmd->pixel_format) {
14832 case DRM_FORMAT_C8:
14833 case DRM_FORMAT_RGB565:
14834 case DRM_FORMAT_XRGB8888:
14835 case DRM_FORMAT_ARGB8888:
14836 break;
14837 case DRM_FORMAT_XRGB1555:
14838 if (INTEL_INFO(dev)->gen > 3) {
14839 DRM_DEBUG("unsupported pixel format: %s\n",
14840 drm_get_format_name(mode_cmd->pixel_format));
14841 return -EINVAL;
14842 }
14843 break;
14844 case DRM_FORMAT_ABGR8888:
14845 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14846 INTEL_INFO(dev)->gen < 9) {
14847 DRM_DEBUG("unsupported pixel format: %s\n",
14848 drm_get_format_name(mode_cmd->pixel_format));
14849 return -EINVAL;
14850 }
14851 break;
14852 case DRM_FORMAT_XBGR8888:
14853 case DRM_FORMAT_XRGB2101010:
14854 case DRM_FORMAT_XBGR2101010:
14855 if (INTEL_INFO(dev)->gen < 4) {
14856 DRM_DEBUG("unsupported pixel format: %s\n",
14857 drm_get_format_name(mode_cmd->pixel_format));
14858 return -EINVAL;
14859 }
14860 break;
14861 case DRM_FORMAT_ABGR2101010:
14862 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14863 DRM_DEBUG("unsupported pixel format: %s\n",
14864 drm_get_format_name(mode_cmd->pixel_format));
14865 return -EINVAL;
14866 }
14867 break;
14868 case DRM_FORMAT_YUYV:
14869 case DRM_FORMAT_UYVY:
14870 case DRM_FORMAT_YVYU:
14871 case DRM_FORMAT_VYUY:
14872 if (INTEL_INFO(dev)->gen < 5) {
14873 DRM_DEBUG("unsupported pixel format: %s\n",
14874 drm_get_format_name(mode_cmd->pixel_format));
14875 return -EINVAL;
14876 }
14877 break;
14878 default:
14879 DRM_DEBUG("unsupported pixel format: %s\n",
14880 drm_get_format_name(mode_cmd->pixel_format));
14881 return -EINVAL;
14882 }
14883
14884 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14885 if (mode_cmd->offsets[0] != 0)
14886 return -EINVAL;
14887
14888 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14889 mode_cmd->pixel_format,
14890 mode_cmd->modifier[0]);
14891 /* FIXME drm helper for size checks (especially planar formats)? */
14892 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14893 return -EINVAL;
14894
14895 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14896 intel_fb->obj = obj;
14897
14898 intel_fill_fb_info(dev_priv, &intel_fb->base);
14899
14900 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14901 if (ret) {
14902 DRM_ERROR("framebuffer init failed %d\n", ret);
14903 return ret;
14904 }
14905
14906 intel_fb->obj->framebuffer_references++;
14907
14908 return 0;
14909 }
14910
14911 static struct drm_framebuffer *
14912 intel_user_framebuffer_create(struct drm_device *dev,
14913 struct drm_file *filp,
14914 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14915 {
14916 struct drm_framebuffer *fb;
14917 struct drm_i915_gem_object *obj;
14918 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14919
14920 obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
14921 if (&obj->base == NULL)
14922 return ERR_PTR(-ENOENT);
14923
14924 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14925 if (IS_ERR(fb))
14926 drm_gem_object_unreference_unlocked(&obj->base);
14927
14928 return fb;
14929 }
14930
14931 #ifndef CONFIG_DRM_FBDEV_EMULATION
14932 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14933 {
14934 }
14935 #endif
14936
14937 static const struct drm_mode_config_funcs intel_mode_funcs = {
14938 .fb_create = intel_user_framebuffer_create,
14939 .output_poll_changed = intel_fbdev_output_poll_changed,
14940 .atomic_check = intel_atomic_check,
14941 .atomic_commit = intel_atomic_commit,
14942 .atomic_state_alloc = intel_atomic_state_alloc,
14943 .atomic_state_clear = intel_atomic_state_clear,
14944 };
14945
14946 /**
14947 * intel_init_display_hooks - initialize the display modesetting hooks
14948 * @dev_priv: device private
14949 */
14950 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14951 {
14952 if (INTEL_INFO(dev_priv)->gen >= 9) {
14953 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14954 dev_priv->display.get_initial_plane_config =
14955 skylake_get_initial_plane_config;
14956 dev_priv->display.crtc_compute_clock =
14957 haswell_crtc_compute_clock;
14958 dev_priv->display.crtc_enable = haswell_crtc_enable;
14959 dev_priv->display.crtc_disable = haswell_crtc_disable;
14960 } else if (HAS_DDI(dev_priv)) {
14961 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14962 dev_priv->display.get_initial_plane_config =
14963 ironlake_get_initial_plane_config;
14964 dev_priv->display.crtc_compute_clock =
14965 haswell_crtc_compute_clock;
14966 dev_priv->display.crtc_enable = haswell_crtc_enable;
14967 dev_priv->display.crtc_disable = haswell_crtc_disable;
14968 } else if (HAS_PCH_SPLIT(dev_priv)) {
14969 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14970 dev_priv->display.get_initial_plane_config =
14971 ironlake_get_initial_plane_config;
14972 dev_priv->display.crtc_compute_clock =
14973 ironlake_crtc_compute_clock;
14974 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14975 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14976 } else if (IS_CHERRYVIEW(dev_priv)) {
14977 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14978 dev_priv->display.get_initial_plane_config =
14979 i9xx_get_initial_plane_config;
14980 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14981 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14982 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14983 } else if (IS_VALLEYVIEW(dev_priv)) {
14984 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14985 dev_priv->display.get_initial_plane_config =
14986 i9xx_get_initial_plane_config;
14987 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14988 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14989 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14990 } else if (IS_G4X(dev_priv)) {
14991 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14992 dev_priv->display.get_initial_plane_config =
14993 i9xx_get_initial_plane_config;
14994 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14995 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14996 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14997 } else if (IS_PINEVIEW(dev_priv)) {
14998 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14999 dev_priv->display.get_initial_plane_config =
15000 i9xx_get_initial_plane_config;
15001 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15002 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15003 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15004 } else if (!IS_GEN2(dev_priv)) {
15005 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15006 dev_priv->display.get_initial_plane_config =
15007 i9xx_get_initial_plane_config;
15008 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15009 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15010 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15011 } else {
15012 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15013 dev_priv->display.get_initial_plane_config =
15014 i9xx_get_initial_plane_config;
15015 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15016 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15017 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15018 }
15019
15020 /* Returns the core display clock speed */
15021 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15022 dev_priv->display.get_display_clock_speed =
15023 skylake_get_display_clock_speed;
15024 else if (IS_BROXTON(dev_priv))
15025 dev_priv->display.get_display_clock_speed =
15026 broxton_get_display_clock_speed;
15027 else if (IS_BROADWELL(dev_priv))
15028 dev_priv->display.get_display_clock_speed =
15029 broadwell_get_display_clock_speed;
15030 else if (IS_HASWELL(dev_priv))
15031 dev_priv->display.get_display_clock_speed =
15032 haswell_get_display_clock_speed;
15033 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15034 dev_priv->display.get_display_clock_speed =
15035 valleyview_get_display_clock_speed;
15036 else if (IS_GEN5(dev_priv))
15037 dev_priv->display.get_display_clock_speed =
15038 ilk_get_display_clock_speed;
15039 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15040 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15041 dev_priv->display.get_display_clock_speed =
15042 i945_get_display_clock_speed;
15043 else if (IS_GM45(dev_priv))
15044 dev_priv->display.get_display_clock_speed =
15045 gm45_get_display_clock_speed;
15046 else if (IS_CRESTLINE(dev_priv))
15047 dev_priv->display.get_display_clock_speed =
15048 i965gm_get_display_clock_speed;
15049 else if (IS_PINEVIEW(dev_priv))
15050 dev_priv->display.get_display_clock_speed =
15051 pnv_get_display_clock_speed;
15052 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15053 dev_priv->display.get_display_clock_speed =
15054 g33_get_display_clock_speed;
15055 else if (IS_I915G(dev_priv))
15056 dev_priv->display.get_display_clock_speed =
15057 i915_get_display_clock_speed;
15058 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15059 dev_priv->display.get_display_clock_speed =
15060 i9xx_misc_get_display_clock_speed;
15061 else if (IS_I915GM(dev_priv))
15062 dev_priv->display.get_display_clock_speed =
15063 i915gm_get_display_clock_speed;
15064 else if (IS_I865G(dev_priv))
15065 dev_priv->display.get_display_clock_speed =
15066 i865_get_display_clock_speed;
15067 else if (IS_I85X(dev_priv))
15068 dev_priv->display.get_display_clock_speed =
15069 i85x_get_display_clock_speed;
15070 else { /* 830 */
15071 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15072 dev_priv->display.get_display_clock_speed =
15073 i830_get_display_clock_speed;
15074 }
15075
15076 if (IS_GEN5(dev_priv)) {
15077 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15078 } else if (IS_GEN6(dev_priv)) {
15079 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15080 } else if (IS_IVYBRIDGE(dev_priv)) {
15081 /* FIXME: detect B0+ stepping and use auto training */
15082 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15083 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15084 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15085 if (IS_BROADWELL(dev_priv)) {
15086 dev_priv->display.modeset_commit_cdclk =
15087 broadwell_modeset_commit_cdclk;
15088 dev_priv->display.modeset_calc_cdclk =
15089 broadwell_modeset_calc_cdclk;
15090 }
15091 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15092 dev_priv->display.modeset_commit_cdclk =
15093 valleyview_modeset_commit_cdclk;
15094 dev_priv->display.modeset_calc_cdclk =
15095 valleyview_modeset_calc_cdclk;
15096 } else if (IS_BROXTON(dev_priv)) {
15097 dev_priv->display.modeset_commit_cdclk =
15098 broxton_modeset_commit_cdclk;
15099 dev_priv->display.modeset_calc_cdclk =
15100 broxton_modeset_calc_cdclk;
15101 }
15102
15103 switch (INTEL_INFO(dev_priv)->gen) {
15104 case 2:
15105 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15106 break;
15107
15108 case 3:
15109 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15110 break;
15111
15112 case 4:
15113 case 5:
15114 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15115 break;
15116
15117 case 6:
15118 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15119 break;
15120 case 7:
15121 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15122 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15123 break;
15124 case 9:
15125 /* Drop through - unsupported since execlist only. */
15126 default:
15127 /* Default just returns -ENODEV to indicate unsupported */
15128 dev_priv->display.queue_flip = intel_default_queue_flip;
15129 }
15130 }
15131
15132 /*
15133 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15134 * resume, or other times. This quirk makes sure that's the case for
15135 * affected systems.
15136 */
15137 static void quirk_pipea_force(struct drm_device *dev)
15138 {
15139 struct drm_i915_private *dev_priv = dev->dev_private;
15140
15141 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15142 DRM_INFO("applying pipe a force quirk\n");
15143 }
15144
15145 static void quirk_pipeb_force(struct drm_device *dev)
15146 {
15147 struct drm_i915_private *dev_priv = dev->dev_private;
15148
15149 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15150 DRM_INFO("applying pipe b force quirk\n");
15151 }
15152
15153 /*
15154 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15155 */
15156 static void quirk_ssc_force_disable(struct drm_device *dev)
15157 {
15158 struct drm_i915_private *dev_priv = dev->dev_private;
15159 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15160 DRM_INFO("applying lvds SSC disable quirk\n");
15161 }
15162
15163 /*
15164 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15165 * brightness value
15166 */
15167 static void quirk_invert_brightness(struct drm_device *dev)
15168 {
15169 struct drm_i915_private *dev_priv = dev->dev_private;
15170 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15171 DRM_INFO("applying inverted panel brightness quirk\n");
15172 }
15173
15174 /* Some VBT's incorrectly indicate no backlight is present */
15175 static void quirk_backlight_present(struct drm_device *dev)
15176 {
15177 struct drm_i915_private *dev_priv = dev->dev_private;
15178 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15179 DRM_INFO("applying backlight present quirk\n");
15180 }
15181
15182 struct intel_quirk {
15183 int device;
15184 int subsystem_vendor;
15185 int subsystem_device;
15186 void (*hook)(struct drm_device *dev);
15187 };
15188
15189 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15190 struct intel_dmi_quirk {
15191 void (*hook)(struct drm_device *dev);
15192 const struct dmi_system_id (*dmi_id_list)[];
15193 };
15194
15195 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15196 {
15197 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15198 return 1;
15199 }
15200
15201 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15202 {
15203 .dmi_id_list = &(const struct dmi_system_id[]) {
15204 {
15205 .callback = intel_dmi_reverse_brightness,
15206 .ident = "NCR Corporation",
15207 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15208 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15209 },
15210 },
15211 { } /* terminating entry */
15212 },
15213 .hook = quirk_invert_brightness,
15214 },
15215 };
15216
15217 static struct intel_quirk intel_quirks[] = {
15218 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15219 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15220
15221 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15222 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15223
15224 /* 830 needs to leave pipe A & dpll A up */
15225 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15226
15227 /* 830 needs to leave pipe B & dpll B up */
15228 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15229
15230 /* Lenovo U160 cannot use SSC on LVDS */
15231 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15232
15233 /* Sony Vaio Y cannot use SSC on LVDS */
15234 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15235
15236 /* Acer Aspire 5734Z must invert backlight brightness */
15237 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15238
15239 /* Acer/eMachines G725 */
15240 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15241
15242 /* Acer/eMachines e725 */
15243 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15244
15245 /* Acer/Packard Bell NCL20 */
15246 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15247
15248 /* Acer Aspire 4736Z */
15249 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15250
15251 /* Acer Aspire 5336 */
15252 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15253
15254 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15255 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15256
15257 /* Acer C720 Chromebook (Core i3 4005U) */
15258 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15259
15260 /* Apple Macbook 2,1 (Core 2 T7400) */
15261 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15262
15263 /* Apple Macbook 4,1 */
15264 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15265
15266 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15267 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15268
15269 /* HP Chromebook 14 (Celeron 2955U) */
15270 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15271
15272 /* Dell Chromebook 11 */
15273 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15274
15275 /* Dell Chromebook 11 (2015 version) */
15276 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15277 };
15278
15279 static void intel_init_quirks(struct drm_device *dev)
15280 {
15281 struct pci_dev *d = dev->pdev;
15282 int i;
15283
15284 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15285 struct intel_quirk *q = &intel_quirks[i];
15286
15287 if (d->device == q->device &&
15288 (d->subsystem_vendor == q->subsystem_vendor ||
15289 q->subsystem_vendor == PCI_ANY_ID) &&
15290 (d->subsystem_device == q->subsystem_device ||
15291 q->subsystem_device == PCI_ANY_ID))
15292 q->hook(dev);
15293 }
15294 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15295 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15296 intel_dmi_quirks[i].hook(dev);
15297 }
15298 }
15299
15300 /* Disable the VGA plane that we never use */
15301 static void i915_disable_vga(struct drm_device *dev)
15302 {
15303 struct drm_i915_private *dev_priv = dev->dev_private;
15304 u8 sr1;
15305 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15306
15307 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15308 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15309 outb(SR01, VGA_SR_INDEX);
15310 sr1 = inb(VGA_SR_DATA);
15311 outb(sr1 | 1<<5, VGA_SR_DATA);
15312 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15313 udelay(300);
15314
15315 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15316 POSTING_READ(vga_reg);
15317 }
15318
15319 void intel_modeset_init_hw(struct drm_device *dev)
15320 {
15321 struct drm_i915_private *dev_priv = dev->dev_private;
15322
15323 intel_update_cdclk(dev);
15324
15325 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15326
15327 intel_init_clock_gating(dev);
15328 intel_enable_gt_powersave(dev);
15329 }
15330
15331 /*
15332 * Calculate what we think the watermarks should be for the state we've read
15333 * out of the hardware and then immediately program those watermarks so that
15334 * we ensure the hardware settings match our internal state.
15335 *
15336 * We can calculate what we think WM's should be by creating a duplicate of the
15337 * current state (which was constructed during hardware readout) and running it
15338 * through the atomic check code to calculate new watermark values in the
15339 * state object.
15340 */
15341 static void sanitize_watermarks(struct drm_device *dev)
15342 {
15343 struct drm_i915_private *dev_priv = to_i915(dev);
15344 struct drm_atomic_state *state;
15345 struct drm_crtc *crtc;
15346 struct drm_crtc_state *cstate;
15347 struct drm_modeset_acquire_ctx ctx;
15348 int ret;
15349 int i;
15350
15351 /* Only supported on platforms that use atomic watermark design */
15352 if (!dev_priv->display.optimize_watermarks)
15353 return;
15354
15355 /*
15356 * We need to hold connection_mutex before calling duplicate_state so
15357 * that the connector loop is protected.
15358 */
15359 drm_modeset_acquire_init(&ctx, 0);
15360 retry:
15361 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15362 if (ret == -EDEADLK) {
15363 drm_modeset_backoff(&ctx);
15364 goto retry;
15365 } else if (WARN_ON(ret)) {
15366 goto fail;
15367 }
15368
15369 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15370 if (WARN_ON(IS_ERR(state)))
15371 goto fail;
15372
15373 /*
15374 * Hardware readout is the only time we don't want to calculate
15375 * intermediate watermarks (since we don't trust the current
15376 * watermarks).
15377 */
15378 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15379
15380 ret = intel_atomic_check(dev, state);
15381 if (ret) {
15382 /*
15383 * If we fail here, it means that the hardware appears to be
15384 * programmed in a way that shouldn't be possible, given our
15385 * understanding of watermark requirements. This might mean a
15386 * mistake in the hardware readout code or a mistake in the
15387 * watermark calculations for a given platform. Raise a WARN
15388 * so that this is noticeable.
15389 *
15390 * If this actually happens, we'll have to just leave the
15391 * BIOS-programmed watermarks untouched and hope for the best.
15392 */
15393 WARN(true, "Could not determine valid watermarks for inherited state\n");
15394 goto fail;
15395 }
15396
15397 /* Write calculated watermark values back */
15398 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15399 for_each_crtc_in_state(state, crtc, cstate, i) {
15400 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15401
15402 cs->wm.need_postvbl_update = true;
15403 dev_priv->display.optimize_watermarks(cs);
15404 }
15405
15406 drm_atomic_state_free(state);
15407 fail:
15408 drm_modeset_drop_locks(&ctx);
15409 drm_modeset_acquire_fini(&ctx);
15410 }
15411
15412 void intel_modeset_init(struct drm_device *dev)
15413 {
15414 struct drm_i915_private *dev_priv = to_i915(dev);
15415 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15416 int sprite, ret;
15417 enum pipe pipe;
15418 struct intel_crtc *crtc;
15419
15420 drm_mode_config_init(dev);
15421
15422 dev->mode_config.min_width = 0;
15423 dev->mode_config.min_height = 0;
15424
15425 dev->mode_config.preferred_depth = 24;
15426 dev->mode_config.prefer_shadow = 1;
15427
15428 dev->mode_config.allow_fb_modifiers = true;
15429
15430 dev->mode_config.funcs = &intel_mode_funcs;
15431
15432 intel_init_quirks(dev);
15433
15434 intel_init_pm(dev);
15435
15436 if (INTEL_INFO(dev)->num_pipes == 0)
15437 return;
15438
15439 /*
15440 * There may be no VBT; and if the BIOS enabled SSC we can
15441 * just keep using it to avoid unnecessary flicker. Whereas if the
15442 * BIOS isn't using it, don't assume it will work even if the VBT
15443 * indicates as much.
15444 */
15445 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15446 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15447 DREF_SSC1_ENABLE);
15448
15449 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15450 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15451 bios_lvds_use_ssc ? "en" : "dis",
15452 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15453 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15454 }
15455 }
15456
15457 if (IS_GEN2(dev)) {
15458 dev->mode_config.max_width = 2048;
15459 dev->mode_config.max_height = 2048;
15460 } else if (IS_GEN3(dev)) {
15461 dev->mode_config.max_width = 4096;
15462 dev->mode_config.max_height = 4096;
15463 } else {
15464 dev->mode_config.max_width = 8192;
15465 dev->mode_config.max_height = 8192;
15466 }
15467
15468 if (IS_845G(dev) || IS_I865G(dev)) {
15469 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15470 dev->mode_config.cursor_height = 1023;
15471 } else if (IS_GEN2(dev)) {
15472 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15473 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15474 } else {
15475 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15476 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15477 }
15478
15479 dev->mode_config.fb_base = ggtt->mappable_base;
15480
15481 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15482 INTEL_INFO(dev)->num_pipes,
15483 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15484
15485 for_each_pipe(dev_priv, pipe) {
15486 intel_crtc_init(dev, pipe);
15487 for_each_sprite(dev_priv, pipe, sprite) {
15488 ret = intel_plane_init(dev, pipe, sprite);
15489 if (ret)
15490 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15491 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15492 }
15493 }
15494
15495 intel_update_czclk(dev_priv);
15496 intel_update_rawclk(dev_priv);
15497 intel_update_cdclk(dev);
15498
15499 intel_shared_dpll_init(dev);
15500
15501 /* Just disable it once at startup */
15502 i915_disable_vga(dev);
15503 intel_setup_outputs(dev);
15504
15505 drm_modeset_lock_all(dev);
15506 intel_modeset_setup_hw_state(dev);
15507 drm_modeset_unlock_all(dev);
15508
15509 for_each_intel_crtc(dev, crtc) {
15510 struct intel_initial_plane_config plane_config = {};
15511
15512 if (!crtc->active)
15513 continue;
15514
15515 /*
15516 * Note that reserving the BIOS fb up front prevents us
15517 * from stuffing other stolen allocations like the ring
15518 * on top. This prevents some ugliness at boot time, and
15519 * can even allow for smooth boot transitions if the BIOS
15520 * fb is large enough for the active pipe configuration.
15521 */
15522 dev_priv->display.get_initial_plane_config(crtc,
15523 &plane_config);
15524
15525 /*
15526 * If the fb is shared between multiple heads, we'll
15527 * just get the first one.
15528 */
15529 intel_find_initial_plane_obj(crtc, &plane_config);
15530 }
15531
15532 /*
15533 * Make sure hardware watermarks really match the state we read out.
15534 * Note that we need to do this after reconstructing the BIOS fb's
15535 * since the watermark calculation done here will use pstate->fb.
15536 */
15537 sanitize_watermarks(dev);
15538 }
15539
15540 static void intel_enable_pipe_a(struct drm_device *dev)
15541 {
15542 struct intel_connector *connector;
15543 struct drm_connector *crt = NULL;
15544 struct intel_load_detect_pipe load_detect_temp;
15545 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15546
15547 /* We can't just switch on the pipe A, we need to set things up with a
15548 * proper mode and output configuration. As a gross hack, enable pipe A
15549 * by enabling the load detect pipe once. */
15550 for_each_intel_connector(dev, connector) {
15551 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15552 crt = &connector->base;
15553 break;
15554 }
15555 }
15556
15557 if (!crt)
15558 return;
15559
15560 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15561 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15562 }
15563
15564 static bool
15565 intel_check_plane_mapping(struct intel_crtc *crtc)
15566 {
15567 struct drm_device *dev = crtc->base.dev;
15568 struct drm_i915_private *dev_priv = dev->dev_private;
15569 u32 val;
15570
15571 if (INTEL_INFO(dev)->num_pipes == 1)
15572 return true;
15573
15574 val = I915_READ(DSPCNTR(!crtc->plane));
15575
15576 if ((val & DISPLAY_PLANE_ENABLE) &&
15577 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15578 return false;
15579
15580 return true;
15581 }
15582
15583 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15584 {
15585 struct drm_device *dev = crtc->base.dev;
15586 struct intel_encoder *encoder;
15587
15588 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15589 return true;
15590
15591 return false;
15592 }
15593
15594 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15595 {
15596 struct drm_device *dev = encoder->base.dev;
15597 struct intel_connector *connector;
15598
15599 for_each_connector_on_encoder(dev, &encoder->base, connector)
15600 return true;
15601
15602 return false;
15603 }
15604
15605 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15606 {
15607 struct drm_device *dev = crtc->base.dev;
15608 struct drm_i915_private *dev_priv = dev->dev_private;
15609 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15610
15611 /* Clear any frame start delays used for debugging left by the BIOS */
15612 if (!transcoder_is_dsi(cpu_transcoder)) {
15613 i915_reg_t reg = PIPECONF(cpu_transcoder);
15614
15615 I915_WRITE(reg,
15616 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15617 }
15618
15619 /* restore vblank interrupts to correct state */
15620 drm_crtc_vblank_reset(&crtc->base);
15621 if (crtc->active) {
15622 struct intel_plane *plane;
15623
15624 drm_crtc_vblank_on(&crtc->base);
15625
15626 /* Disable everything but the primary plane */
15627 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15628 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15629 continue;
15630
15631 plane->disable_plane(&plane->base, &crtc->base);
15632 }
15633 }
15634
15635 /* We need to sanitize the plane -> pipe mapping first because this will
15636 * disable the crtc (and hence change the state) if it is wrong. Note
15637 * that gen4+ has a fixed plane -> pipe mapping. */
15638 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15639 bool plane;
15640
15641 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15642 crtc->base.base.id);
15643
15644 /* Pipe has the wrong plane attached and the plane is active.
15645 * Temporarily change the plane mapping and disable everything
15646 * ... */
15647 plane = crtc->plane;
15648 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15649 crtc->plane = !plane;
15650 intel_crtc_disable_noatomic(&crtc->base);
15651 crtc->plane = plane;
15652 }
15653
15654 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15655 crtc->pipe == PIPE_A && !crtc->active) {
15656 /* BIOS forgot to enable pipe A, this mostly happens after
15657 * resume. Force-enable the pipe to fix this, the update_dpms
15658 * call below we restore the pipe to the right state, but leave
15659 * the required bits on. */
15660 intel_enable_pipe_a(dev);
15661 }
15662
15663 /* Adjust the state of the output pipe according to whether we
15664 * have active connectors/encoders. */
15665 if (crtc->active && !intel_crtc_has_encoders(crtc))
15666 intel_crtc_disable_noatomic(&crtc->base);
15667
15668 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15669 /*
15670 * We start out with underrun reporting disabled to avoid races.
15671 * For correct bookkeeping mark this on active crtcs.
15672 *
15673 * Also on gmch platforms we dont have any hardware bits to
15674 * disable the underrun reporting. Which means we need to start
15675 * out with underrun reporting disabled also on inactive pipes,
15676 * since otherwise we'll complain about the garbage we read when
15677 * e.g. coming up after runtime pm.
15678 *
15679 * No protection against concurrent access is required - at
15680 * worst a fifo underrun happens which also sets this to false.
15681 */
15682 crtc->cpu_fifo_underrun_disabled = true;
15683 crtc->pch_fifo_underrun_disabled = true;
15684 }
15685 }
15686
15687 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15688 {
15689 struct intel_connector *connector;
15690 struct drm_device *dev = encoder->base.dev;
15691
15692 /* We need to check both for a crtc link (meaning that the
15693 * encoder is active and trying to read from a pipe) and the
15694 * pipe itself being active. */
15695 bool has_active_crtc = encoder->base.crtc &&
15696 to_intel_crtc(encoder->base.crtc)->active;
15697
15698 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15699 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15700 encoder->base.base.id,
15701 encoder->base.name);
15702
15703 /* Connector is active, but has no active pipe. This is
15704 * fallout from our resume register restoring. Disable
15705 * the encoder manually again. */
15706 if (encoder->base.crtc) {
15707 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15708 encoder->base.base.id,
15709 encoder->base.name);
15710 encoder->disable(encoder);
15711 if (encoder->post_disable)
15712 encoder->post_disable(encoder);
15713 }
15714 encoder->base.crtc = NULL;
15715
15716 /* Inconsistent output/port/pipe state happens presumably due to
15717 * a bug in one of the get_hw_state functions. Or someplace else
15718 * in our code, like the register restore mess on resume. Clamp
15719 * things to off as a safer default. */
15720 for_each_intel_connector(dev, connector) {
15721 if (connector->encoder != encoder)
15722 continue;
15723 connector->base.dpms = DRM_MODE_DPMS_OFF;
15724 connector->base.encoder = NULL;
15725 }
15726 }
15727 /* Enabled encoders without active connectors will be fixed in
15728 * the crtc fixup. */
15729 }
15730
15731 void i915_redisable_vga_power_on(struct drm_device *dev)
15732 {
15733 struct drm_i915_private *dev_priv = dev->dev_private;
15734 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15735
15736 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15737 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15738 i915_disable_vga(dev);
15739 }
15740 }
15741
15742 void i915_redisable_vga(struct drm_device *dev)
15743 {
15744 struct drm_i915_private *dev_priv = dev->dev_private;
15745
15746 /* This function can be called both from intel_modeset_setup_hw_state or
15747 * at a very early point in our resume sequence, where the power well
15748 * structures are not yet restored. Since this function is at a very
15749 * paranoid "someone might have enabled VGA while we were not looking"
15750 * level, just check if the power well is enabled instead of trying to
15751 * follow the "don't touch the power well if we don't need it" policy
15752 * the rest of the driver uses. */
15753 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15754 return;
15755
15756 i915_redisable_vga_power_on(dev);
15757
15758 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15759 }
15760
15761 static bool primary_get_hw_state(struct intel_plane *plane)
15762 {
15763 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15764
15765 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15766 }
15767
15768 /* FIXME read out full plane state for all planes */
15769 static void readout_plane_state(struct intel_crtc *crtc)
15770 {
15771 struct drm_plane *primary = crtc->base.primary;
15772 struct intel_plane_state *plane_state =
15773 to_intel_plane_state(primary->state);
15774
15775 plane_state->visible = crtc->active &&
15776 primary_get_hw_state(to_intel_plane(primary));
15777
15778 if (plane_state->visible)
15779 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15780 }
15781
15782 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15783 {
15784 struct drm_i915_private *dev_priv = dev->dev_private;
15785 enum pipe pipe;
15786 struct intel_crtc *crtc;
15787 struct intel_encoder *encoder;
15788 struct intel_connector *connector;
15789 int i;
15790
15791 dev_priv->active_crtcs = 0;
15792
15793 for_each_intel_crtc(dev, crtc) {
15794 struct intel_crtc_state *crtc_state = crtc->config;
15795 int pixclk = 0;
15796
15797 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15798 memset(crtc_state, 0, sizeof(*crtc_state));
15799 crtc_state->base.crtc = &crtc->base;
15800
15801 crtc_state->base.active = crtc_state->base.enable =
15802 dev_priv->display.get_pipe_config(crtc, crtc_state);
15803
15804 crtc->base.enabled = crtc_state->base.enable;
15805 crtc->active = crtc_state->base.active;
15806
15807 if (crtc_state->base.active) {
15808 dev_priv->active_crtcs |= 1 << crtc->pipe;
15809
15810 if (IS_BROADWELL(dev_priv)) {
15811 pixclk = ilk_pipe_pixel_rate(crtc_state);
15812
15813 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15814 if (crtc_state->ips_enabled)
15815 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15816 } else if (IS_VALLEYVIEW(dev_priv) ||
15817 IS_CHERRYVIEW(dev_priv) ||
15818 IS_BROXTON(dev_priv))
15819 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15820 else
15821 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15822 }
15823
15824 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15825
15826 readout_plane_state(crtc);
15827
15828 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15829 crtc->base.base.id,
15830 crtc->active ? "enabled" : "disabled");
15831 }
15832
15833 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15834 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15835
15836 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15837 &pll->config.hw_state);
15838 pll->config.crtc_mask = 0;
15839 for_each_intel_crtc(dev, crtc) {
15840 if (crtc->active && crtc->config->shared_dpll == pll)
15841 pll->config.crtc_mask |= 1 << crtc->pipe;
15842 }
15843 pll->active_mask = pll->config.crtc_mask;
15844
15845 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15846 pll->name, pll->config.crtc_mask, pll->on);
15847 }
15848
15849 for_each_intel_encoder(dev, encoder) {
15850 pipe = 0;
15851
15852 if (encoder->get_hw_state(encoder, &pipe)) {
15853 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15854 encoder->base.crtc = &crtc->base;
15855 encoder->get_config(encoder, crtc->config);
15856 } else {
15857 encoder->base.crtc = NULL;
15858 }
15859
15860 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15861 encoder->base.base.id,
15862 encoder->base.name,
15863 encoder->base.crtc ? "enabled" : "disabled",
15864 pipe_name(pipe));
15865 }
15866
15867 for_each_intel_connector(dev, connector) {
15868 if (connector->get_hw_state(connector)) {
15869 connector->base.dpms = DRM_MODE_DPMS_ON;
15870
15871 encoder = connector->encoder;
15872 connector->base.encoder = &encoder->base;
15873
15874 if (encoder->base.crtc &&
15875 encoder->base.crtc->state->active) {
15876 /*
15877 * This has to be done during hardware readout
15878 * because anything calling .crtc_disable may
15879 * rely on the connector_mask being accurate.
15880 */
15881 encoder->base.crtc->state->connector_mask |=
15882 1 << drm_connector_index(&connector->base);
15883 encoder->base.crtc->state->encoder_mask |=
15884 1 << drm_encoder_index(&encoder->base);
15885 }
15886
15887 } else {
15888 connector->base.dpms = DRM_MODE_DPMS_OFF;
15889 connector->base.encoder = NULL;
15890 }
15891 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15892 connector->base.base.id,
15893 connector->base.name,
15894 connector->base.encoder ? "enabled" : "disabled");
15895 }
15896
15897 for_each_intel_crtc(dev, crtc) {
15898 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15899
15900 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15901 if (crtc->base.state->active) {
15902 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15903 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15904 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15905
15906 /*
15907 * The initial mode needs to be set in order to keep
15908 * the atomic core happy. It wants a valid mode if the
15909 * crtc's enabled, so we do the above call.
15910 *
15911 * At this point some state updated by the connectors
15912 * in their ->detect() callback has not run yet, so
15913 * no recalculation can be done yet.
15914 *
15915 * Even if we could do a recalculation and modeset
15916 * right now it would cause a double modeset if
15917 * fbdev or userspace chooses a different initial mode.
15918 *
15919 * If that happens, someone indicated they wanted a
15920 * mode change, which means it's safe to do a full
15921 * recalculation.
15922 */
15923 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15924
15925 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15926 update_scanline_offset(crtc);
15927 }
15928
15929 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15930 }
15931 }
15932
15933 /* Scan out the current hw modeset state,
15934 * and sanitizes it to the current state
15935 */
15936 static void
15937 intel_modeset_setup_hw_state(struct drm_device *dev)
15938 {
15939 struct drm_i915_private *dev_priv = dev->dev_private;
15940 enum pipe pipe;
15941 struct intel_crtc *crtc;
15942 struct intel_encoder *encoder;
15943 int i;
15944
15945 intel_modeset_readout_hw_state(dev);
15946
15947 /* HW state is read out, now we need to sanitize this mess. */
15948 for_each_intel_encoder(dev, encoder) {
15949 intel_sanitize_encoder(encoder);
15950 }
15951
15952 for_each_pipe(dev_priv, pipe) {
15953 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15954 intel_sanitize_crtc(crtc);
15955 intel_dump_pipe_config(crtc, crtc->config,
15956 "[setup_hw_state]");
15957 }
15958
15959 intel_modeset_update_connector_atomic_state(dev);
15960
15961 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15962 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15963
15964 if (!pll->on || pll->active_mask)
15965 continue;
15966
15967 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15968
15969 pll->funcs.disable(dev_priv, pll);
15970 pll->on = false;
15971 }
15972
15973 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15974 vlv_wm_get_hw_state(dev);
15975 else if (IS_GEN9(dev))
15976 skl_wm_get_hw_state(dev);
15977 else if (HAS_PCH_SPLIT(dev))
15978 ilk_wm_get_hw_state(dev);
15979
15980 for_each_intel_crtc(dev, crtc) {
15981 unsigned long put_domains;
15982
15983 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15984 if (WARN_ON(put_domains))
15985 modeset_put_power_domains(dev_priv, put_domains);
15986 }
15987 intel_display_set_init_power(dev_priv, false);
15988
15989 intel_fbc_init_pipe_state(dev_priv);
15990 }
15991
15992 void intel_display_resume(struct drm_device *dev)
15993 {
15994 struct drm_i915_private *dev_priv = to_i915(dev);
15995 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15996 struct drm_modeset_acquire_ctx ctx;
15997 int ret;
15998 bool setup = false;
15999
16000 dev_priv->modeset_restore_state = NULL;
16001
16002 /*
16003 * This is a cludge because with real atomic modeset mode_config.mutex
16004 * won't be taken. Unfortunately some probed state like
16005 * audio_codec_enable is still protected by mode_config.mutex, so lock
16006 * it here for now.
16007 */
16008 mutex_lock(&dev->mode_config.mutex);
16009 drm_modeset_acquire_init(&ctx, 0);
16010
16011 retry:
16012 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16013
16014 if (ret == 0 && !setup) {
16015 setup = true;
16016
16017 intel_modeset_setup_hw_state(dev);
16018 i915_redisable_vga(dev);
16019 }
16020
16021 if (ret == 0 && state) {
16022 struct drm_crtc_state *crtc_state;
16023 struct drm_crtc *crtc;
16024 int i;
16025
16026 state->acquire_ctx = &ctx;
16027
16028 /* ignore any reset values/BIOS leftovers in the WM registers */
16029 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16030
16031 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16032 /*
16033 * Force recalculation even if we restore
16034 * current state. With fast modeset this may not result
16035 * in a modeset when the state is compatible.
16036 */
16037 crtc_state->mode_changed = true;
16038 }
16039
16040 ret = drm_atomic_commit(state);
16041 }
16042
16043 if (ret == -EDEADLK) {
16044 drm_modeset_backoff(&ctx);
16045 goto retry;
16046 }
16047
16048 drm_modeset_drop_locks(&ctx);
16049 drm_modeset_acquire_fini(&ctx);
16050 mutex_unlock(&dev->mode_config.mutex);
16051
16052 if (ret) {
16053 DRM_ERROR("Restoring old state failed with %i\n", ret);
16054 drm_atomic_state_free(state);
16055 }
16056 }
16057
16058 void intel_modeset_gem_init(struct drm_device *dev)
16059 {
16060 struct drm_crtc *c;
16061 struct drm_i915_gem_object *obj;
16062 int ret;
16063
16064 intel_init_gt_powersave(dev);
16065
16066 intel_modeset_init_hw(dev);
16067
16068 intel_setup_overlay(dev);
16069
16070 /*
16071 * Make sure any fbs we allocated at startup are properly
16072 * pinned & fenced. When we do the allocation it's too early
16073 * for this.
16074 */
16075 for_each_crtc(dev, c) {
16076 obj = intel_fb_obj(c->primary->fb);
16077 if (obj == NULL)
16078 continue;
16079
16080 mutex_lock(&dev->struct_mutex);
16081 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16082 c->primary->state->rotation);
16083 mutex_unlock(&dev->struct_mutex);
16084 if (ret) {
16085 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16086 to_intel_crtc(c)->pipe);
16087 drm_framebuffer_unreference(c->primary->fb);
16088 c->primary->fb = NULL;
16089 c->primary->crtc = c->primary->state->crtc = NULL;
16090 update_state_fb(c->primary);
16091 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16092 }
16093 }
16094
16095 intel_backlight_register(dev);
16096 }
16097
16098 void intel_connector_unregister(struct intel_connector *intel_connector)
16099 {
16100 struct drm_connector *connector = &intel_connector->base;
16101
16102 intel_panel_destroy_backlight(connector);
16103 drm_connector_unregister(connector);
16104 }
16105
16106 void intel_modeset_cleanup(struct drm_device *dev)
16107 {
16108 struct drm_i915_private *dev_priv = dev->dev_private;
16109 struct intel_connector *connector;
16110
16111 intel_disable_gt_powersave(dev);
16112
16113 intel_backlight_unregister(dev);
16114
16115 /*
16116 * Interrupts and polling as the first thing to avoid creating havoc.
16117 * Too much stuff here (turning of connectors, ...) would
16118 * experience fancy races otherwise.
16119 */
16120 intel_irq_uninstall(dev_priv);
16121
16122 /*
16123 * Due to the hpd irq storm handling the hotplug work can re-arm the
16124 * poll handlers. Hence disable polling after hpd handling is shut down.
16125 */
16126 drm_kms_helper_poll_fini(dev);
16127
16128 intel_unregister_dsm_handler();
16129
16130 intel_fbc_global_disable(dev_priv);
16131
16132 /* flush any delayed tasks or pending work */
16133 flush_scheduled_work();
16134
16135 /* destroy the backlight and sysfs files before encoders/connectors */
16136 for_each_intel_connector(dev, connector)
16137 connector->unregister(connector);
16138
16139 drm_mode_config_cleanup(dev);
16140
16141 intel_cleanup_overlay(dev);
16142
16143 intel_cleanup_gt_powersave(dev);
16144
16145 intel_teardown_gmbus(dev);
16146 }
16147
16148 /*
16149 * Return which encoder is currently attached for connector.
16150 */
16151 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16152 {
16153 return &intel_attached_encoder(connector)->base;
16154 }
16155
16156 void intel_connector_attach_encoder(struct intel_connector *connector,
16157 struct intel_encoder *encoder)
16158 {
16159 connector->encoder = encoder;
16160 drm_mode_connector_attach_encoder(&connector->base,
16161 &encoder->base);
16162 }
16163
16164 /*
16165 * set vga decode state - true == enable VGA decode
16166 */
16167 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16168 {
16169 struct drm_i915_private *dev_priv = dev->dev_private;
16170 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16171 u16 gmch_ctrl;
16172
16173 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16174 DRM_ERROR("failed to read control word\n");
16175 return -EIO;
16176 }
16177
16178 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16179 return 0;
16180
16181 if (state)
16182 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16183 else
16184 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16185
16186 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16187 DRM_ERROR("failed to write control word\n");
16188 return -EIO;
16189 }
16190
16191 return 0;
16192 }
16193
16194 struct intel_display_error_state {
16195
16196 u32 power_well_driver;
16197
16198 int num_transcoders;
16199
16200 struct intel_cursor_error_state {
16201 u32 control;
16202 u32 position;
16203 u32 base;
16204 u32 size;
16205 } cursor[I915_MAX_PIPES];
16206
16207 struct intel_pipe_error_state {
16208 bool power_domain_on;
16209 u32 source;
16210 u32 stat;
16211 } pipe[I915_MAX_PIPES];
16212
16213 struct intel_plane_error_state {
16214 u32 control;
16215 u32 stride;
16216 u32 size;
16217 u32 pos;
16218 u32 addr;
16219 u32 surface;
16220 u32 tile_offset;
16221 } plane[I915_MAX_PIPES];
16222
16223 struct intel_transcoder_error_state {
16224 bool power_domain_on;
16225 enum transcoder cpu_transcoder;
16226
16227 u32 conf;
16228
16229 u32 htotal;
16230 u32 hblank;
16231 u32 hsync;
16232 u32 vtotal;
16233 u32 vblank;
16234 u32 vsync;
16235 } transcoder[4];
16236 };
16237
16238 struct intel_display_error_state *
16239 intel_display_capture_error_state(struct drm_device *dev)
16240 {
16241 struct drm_i915_private *dev_priv = dev->dev_private;
16242 struct intel_display_error_state *error;
16243 int transcoders[] = {
16244 TRANSCODER_A,
16245 TRANSCODER_B,
16246 TRANSCODER_C,
16247 TRANSCODER_EDP,
16248 };
16249 int i;
16250
16251 if (INTEL_INFO(dev)->num_pipes == 0)
16252 return NULL;
16253
16254 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16255 if (error == NULL)
16256 return NULL;
16257
16258 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16259 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16260
16261 for_each_pipe(dev_priv, i) {
16262 error->pipe[i].power_domain_on =
16263 __intel_display_power_is_enabled(dev_priv,
16264 POWER_DOMAIN_PIPE(i));
16265 if (!error->pipe[i].power_domain_on)
16266 continue;
16267
16268 error->cursor[i].control = I915_READ(CURCNTR(i));
16269 error->cursor[i].position = I915_READ(CURPOS(i));
16270 error->cursor[i].base = I915_READ(CURBASE(i));
16271
16272 error->plane[i].control = I915_READ(DSPCNTR(i));
16273 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16274 if (INTEL_INFO(dev)->gen <= 3) {
16275 error->plane[i].size = I915_READ(DSPSIZE(i));
16276 error->plane[i].pos = I915_READ(DSPPOS(i));
16277 }
16278 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16279 error->plane[i].addr = I915_READ(DSPADDR(i));
16280 if (INTEL_INFO(dev)->gen >= 4) {
16281 error->plane[i].surface = I915_READ(DSPSURF(i));
16282 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16283 }
16284
16285 error->pipe[i].source = I915_READ(PIPESRC(i));
16286
16287 if (HAS_GMCH_DISPLAY(dev))
16288 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16289 }
16290
16291 /* Note: this does not include DSI transcoders. */
16292 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16293 if (HAS_DDI(dev_priv))
16294 error->num_transcoders++; /* Account for eDP. */
16295
16296 for (i = 0; i < error->num_transcoders; i++) {
16297 enum transcoder cpu_transcoder = transcoders[i];
16298
16299 error->transcoder[i].power_domain_on =
16300 __intel_display_power_is_enabled(dev_priv,
16301 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16302 if (!error->transcoder[i].power_domain_on)
16303 continue;
16304
16305 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16306
16307 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16308 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16309 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16310 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16311 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16312 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16313 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16314 }
16315
16316 return error;
16317 }
16318
16319 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16320
16321 void
16322 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16323 struct drm_device *dev,
16324 struct intel_display_error_state *error)
16325 {
16326 struct drm_i915_private *dev_priv = dev->dev_private;
16327 int i;
16328
16329 if (!error)
16330 return;
16331
16332 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16333 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16334 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16335 error->power_well_driver);
16336 for_each_pipe(dev_priv, i) {
16337 err_printf(m, "Pipe [%d]:\n", i);
16338 err_printf(m, " Power: %s\n",
16339 onoff(error->pipe[i].power_domain_on));
16340 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16341 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16342
16343 err_printf(m, "Plane [%d]:\n", i);
16344 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16345 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16346 if (INTEL_INFO(dev)->gen <= 3) {
16347 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16348 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16349 }
16350 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16351 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16352 if (INTEL_INFO(dev)->gen >= 4) {
16353 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16354 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16355 }
16356
16357 err_printf(m, "Cursor [%d]:\n", i);
16358 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16359 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16360 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16361 }
16362
16363 for (i = 0; i < error->num_transcoders; i++) {
16364 err_printf(m, "CPU transcoder: %s\n",
16365 transcoder_name(error->transcoder[i].cpu_transcoder));
16366 err_printf(m, " Power: %s\n",
16367 onoff(error->transcoder[i].power_domain_on));
16368 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16369 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16370 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16371 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16372 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16373 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16374 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16375 }
16376 }
Linux kernel - Deliverables
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