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drm/i915: Set crtc->new_config to NULL for pipes that are about to be disabled
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
56 typedef struct {
57 int min, max;
58 } intel_range_t;
59
60 typedef struct {
61 int dot_limit;
62 int p2_slow, p2_fast;
63 } intel_p2_t;
64
65 typedef struct intel_limit intel_limit_t;
66 struct intel_limit {
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
69 };
70
71 int
72 intel_pch_rawclk(struct drm_device *dev)
73 {
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79 }
80
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
83 {
84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
89 }
90
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 908000, .max = 1512000 },
94 .n = { .min = 2, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
102 };
103
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 908000, .max = 1512000 },
107 .n = { .min = 2, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115 };
116
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 908000, .max = 1512000 },
120 .n = { .min = 2, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
128 };
129
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
141 };
142
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
154 };
155
156
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
169 },
170 };
171
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
183 };
184
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
196 },
197 };
198
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
210 },
211 };
212
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
239 };
240
241 /* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
257 };
258
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
270 };
271
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
283 };
284
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 };
311
312 static const intel_limit_t intel_limits_vlv = {
313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
326 };
327
328 static void vlv_clock(int refclk, intel_clock_t *clock)
329 {
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 if (WARN_ON(clock->n == 0 || clock->p == 0))
333 return;
334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
336 }
337
338 /**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342 {
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351 }
352
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
355 {
356 struct drm_device *dev = crtc->dev;
357 const intel_limit_t *limit;
358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360 if (intel_is_dual_link_lvds(dev)) {
361 if (refclk == 100000)
362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
366 if (refclk == 100000)
367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
371 } else
372 limit = &intel_limits_ironlake_dac;
373
374 return limit;
375 }
376
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378 {
379 struct drm_device *dev = crtc->dev;
380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383 if (intel_is_dual_link_lvds(dev))
384 limit = &intel_limits_g4x_dual_channel_lvds;
385 else
386 limit = &intel_limits_g4x_single_channel_lvds;
387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389 limit = &intel_limits_g4x_hdmi;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391 limit = &intel_limits_g4x_sdvo;
392 } else /* The option is for other outputs */
393 limit = &intel_limits_i9xx_sdvo;
394
395 return limit;
396 }
397
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
399 {
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
403 if (HAS_PCH_SPLIT(dev))
404 limit = intel_ironlake_limit(crtc, refclk);
405 else if (IS_G4X(dev)) {
406 limit = intel_g4x_limit(crtc);
407 } else if (IS_PINEVIEW(dev)) {
408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409 limit = &intel_limits_pineview_lvds;
410 else
411 limit = &intel_limits_pineview_sdvo;
412 } else if (IS_VALLEYVIEW(dev)) {
413 limit = &intel_limits_vlv;
414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
417 else
418 limit = &intel_limits_i9xx_sdvo;
419 } else {
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421 limit = &intel_limits_i8xx_lvds;
422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423 limit = &intel_limits_i8xx_dvo;
424 else
425 limit = &intel_limits_i8xx_dac;
426 }
427 return limit;
428 }
429
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
432 {
433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
435 if (WARN_ON(clock->n == 0 || clock->p == 0))
436 return;
437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
439 }
440
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
442 {
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
444 }
445
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
447 {
448 clock->m = i9xx_dpll_compute_m(clock);
449 clock->p = clock->p1 * clock->p2;
450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
451 return;
452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
454 }
455
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 /**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
465 {
466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
478
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
484 }
485
486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
490 */
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492 INTELPllInvalid("dot out of range\n");
493
494 return true;
495 }
496
497 static bool
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
501 {
502 struct drm_device *dev = crtc->dev;
503 intel_clock_t clock;
504 int err = target;
505
506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
507 /*
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
511 */
512 if (intel_is_dual_link_lvds(dev))
513 clock.p2 = limit->p2.p2_fast;
514 else
515 clock.p2 = limit->p2.p2_slow;
516 } else {
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
519 else
520 clock.p2 = limit->p2.p2_fast;
521 }
522
523 memset(best_clock, 0, sizeof(*best_clock));
524
525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
526 clock.m1++) {
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
529 if (clock.m2 >= clock.m1)
530 break;
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
535 int this_err;
536
537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
539 &clock))
540 continue;
541 if (match_clock &&
542 clock.p != match_clock->p)
543 continue;
544
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
547 *best_clock = clock;
548 err = this_err;
549 }
550 }
551 }
552 }
553 }
554
555 return (err != target);
556 }
557
558 static bool
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
562 {
563 struct drm_device *dev = crtc->dev;
564 intel_clock_t clock;
565 int err = target;
566
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
568 /*
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
572 */
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
575 else
576 clock.p2 = limit->p2.p2_slow;
577 } else {
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
580 else
581 clock.p2 = limit->p2.p2_fast;
582 }
583
584 memset(best_clock, 0, sizeof(*best_clock));
585
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
587 clock.m1++) {
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
594 int this_err;
595
596 pineview_clock(refclk, &clock);
597 if (!intel_PLL_is_valid(dev, limit,
598 &clock))
599 continue;
600 if (match_clock &&
601 clock.p != match_clock->p)
602 continue;
603
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
606 *best_clock = clock;
607 err = this_err;
608 }
609 }
610 }
611 }
612 }
613
614 return (err != target);
615 }
616
617 static bool
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
621 {
622 struct drm_device *dev = crtc->dev;
623 intel_clock_t clock;
624 int max_n;
625 bool found;
626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
628 found = false;
629
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631 if (intel_is_dual_link_lvds(dev))
632 clock.p2 = limit->p2.p2_fast;
633 else
634 clock.p2 = limit->p2.p2_slow;
635 } else {
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
638 else
639 clock.p2 = limit->p2.p2_fast;
640 }
641
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
653 int this_err;
654
655 i9xx_clock(refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
657 &clock))
658 continue;
659
660 this_err = abs(clock.dot - target);
661 if (this_err < err_most) {
662 *best_clock = clock;
663 err_most = this_err;
664 max_n = clock.n;
665 found = true;
666 }
667 }
668 }
669 }
670 }
671 return found;
672 }
673
674 static bool
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678 {
679 struct drm_device *dev = crtc->dev;
680 intel_clock_t clock;
681 unsigned int bestppm = 1000000;
682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
684 bool found = false;
685
686 target *= 5; /* fast clock */
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695 clock.p = clock.p1 * clock.p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698 unsigned int ppm, diff;
699
700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
701 refclk * clock.m1);
702
703 vlv_clock(refclk, &clock);
704
705 if (!intel_PLL_is_valid(dev, limit,
706 &clock))
707 continue;
708
709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
711
712 if (ppm < 100 && clock.p > best_clock->p) {
713 bestppm = 0;
714 *best_clock = clock;
715 found = true;
716 }
717
718 if (bestppm >= 10 && ppm < bestppm - 10) {
719 bestppm = ppm;
720 *best_clock = clock;
721 found = true;
722 }
723 }
724 }
725 }
726 }
727
728 return found;
729 }
730
731 bool intel_crtc_active(struct drm_crtc *crtc)
732 {
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
737 *
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
740 *
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
743 */
744 return intel_crtc->active && crtc->fb &&
745 intel_crtc->config.adjusted_mode.crtc_clock;
746 }
747
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
749 enum pipe pipe)
750 {
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
753
754 return intel_crtc->config.cpu_transcoder;
755 }
756
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
758 {
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
761
762 frame = I915_READ(frame_reg);
763
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
766 }
767
768 /**
769 * intel_wait_for_vblank - wait for vblank on a given pipe
770 * @dev: drm device
771 * @pipe: pipe to wait for
772 *
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
774 * mode setting code.
775 */
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
777 {
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 int pipestat_reg = PIPESTAT(pipe);
780
781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
783 return;
784 }
785
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
788 *
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
795 * vblanks...
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
798 */
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
801
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
805 50))
806 DRM_DEBUG_KMS("vblank wait timed out\n");
807 }
808
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
810 {
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
813 u32 line1, line2;
814 u32 line_mask;
815
816 if (IS_GEN2(dev))
817 line_mask = DSL_LINEMASK_GEN2;
818 else
819 line_mask = DSL_LINEMASK_GEN3;
820
821 line1 = I915_READ(reg) & line_mask;
822 mdelay(5);
823 line2 = I915_READ(reg) & line_mask;
824
825 return line1 == line2;
826 }
827
828 /*
829 * intel_wait_for_pipe_off - wait for pipe to turn off
830 * @dev: drm device
831 * @pipe: pipe to wait for
832 *
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
836 *
837 * On Gen4 and above:
838 * wait for the pipe register state bit to turn off
839 *
840 * Otherwise:
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
843 *
844 */
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
846 {
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
849 pipe);
850
851 if (INTEL_INFO(dev)->gen >= 4) {
852 int reg = PIPECONF(cpu_transcoder);
853
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856 100))
857 WARN(1, "pipe_off wait timed out\n");
858 } else {
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861 WARN(1, "pipe_off wait timed out\n");
862 }
863 }
864
865 /*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874 {
875 u32 bit;
876
877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
905 }
906
907 return I915_READ(SDEISR) & bit;
908 }
909
910 static const char *state_string(bool enabled)
911 {
912 return enabled ? "on" : "off";
913 }
914
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
918 {
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929 }
930
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933 {
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945 }
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951 {
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
954 if (crtc->config.shared_dpll < 0)
955 return NULL;
956
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
958 }
959
960 /* For ILK+ */
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
964 {
965 bool cur_state;
966 struct intel_dpll_hw_state hw_state;
967
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
973 if (WARN (!pll,
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
975 return;
976
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
981 }
982
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985 {
986 int reg;
987 u32 val;
988 bool cur_state;
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
991
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011 {
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028 {
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1038 return;
1039
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062 {
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
1066 bool locked = true;
1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1086 pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091 {
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1111 {
1112 int reg;
1113 u32 val;
1114 bool cur_state;
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
1117
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1138 {
1139 int reg;
1140 u32 val;
1141 bool cur_state;
1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156 {
1157 struct drm_device *dev = dev_priv->dev;
1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
1169 return;
1170 }
1171
1172 /* Need to check both planes against the pipe */
1173 for_each_pipe(i) {
1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1181 }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186 {
1187 struct drm_device *dev = dev_priv->dev;
1188 int reg, i;
1189 u32 val;
1190
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1211 }
1212 }
1213
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216 u32 val;
1217 bool enabled;
1218
1219 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1220
1221 val = I915_READ(PCH_DREF_CONTROL);
1222 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223 DREF_SUPERSPREAD_SOURCE_MASK));
1224 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225 }
1226
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229 {
1230 int reg;
1231 u32 val;
1232 bool enabled;
1233
1234 reg = PCH_TRANSCONF(pipe);
1235 val = I915_READ(reg);
1236 enabled = !!(val & TRANS_ENABLE);
1237 WARN(enabled,
1238 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239 pipe_name(pipe));
1240 }
1241
1242 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 port_sel, u32 val)
1244 {
1245 if ((val & DP_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252 return false;
1253 } else {
1254 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255 return false;
1256 }
1257 return true;
1258 }
1259
1260 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe, u32 val)
1262 {
1263 if ((val & SDVO_ENABLE) == 0)
1264 return false;
1265
1266 if (HAS_PCH_CPT(dev_priv->dev)) {
1267 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1268 return false;
1269 } else {
1270 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1271 return false;
1272 }
1273 return true;
1274 }
1275
1276 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, u32 val)
1278 {
1279 if ((val & LVDS_PORT_EN) == 0)
1280 return false;
1281
1282 if (HAS_PCH_CPT(dev_priv->dev)) {
1283 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284 return false;
1285 } else {
1286 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287 return false;
1288 }
1289 return true;
1290 }
1291
1292 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, u32 val)
1294 {
1295 if ((val & ADPA_DAC_ENABLE) == 0)
1296 return false;
1297 if (HAS_PCH_CPT(dev_priv->dev)) {
1298 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299 return false;
1300 } else {
1301 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302 return false;
1303 }
1304 return true;
1305 }
1306
1307 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, int reg, u32 port_sel)
1309 {
1310 u32 val = I915_READ(reg);
1311 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1312 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313 reg, pipe_name(pipe));
1314
1315 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316 && (val & DP_PIPEB_SELECT),
1317 "IBX PCH dp port still using transcoder B\n");
1318 }
1319
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, int reg)
1322 {
1323 u32 val = I915_READ(reg);
1324 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1325 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326 reg, pipe_name(pipe));
1327
1328 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1329 && (val & SDVO_PIPE_B_SELECT),
1330 "IBX PCH hdmi port still using transcoder B\n");
1331 }
1332
1333 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334 enum pipe pipe)
1335 {
1336 int reg;
1337 u32 val;
1338
1339 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1342
1343 reg = PCH_ADPA;
1344 val = I915_READ(reg);
1345 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1346 "PCH VGA enabled on transcoder %c, should be disabled\n",
1347 pipe_name(pipe));
1348
1349 reg = PCH_LVDS;
1350 val = I915_READ(reg);
1351 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1352 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1353 pipe_name(pipe));
1354
1355 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1358 }
1359
1360 static void intel_init_dpio(struct drm_device *dev)
1361 {
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363
1364 if (!IS_VALLEYVIEW(dev))
1365 return;
1366
1367 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1368 }
1369
1370 static void intel_reset_dpio(struct drm_device *dev)
1371 {
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373
1374 if (!IS_VALLEYVIEW(dev))
1375 return;
1376
1377 /*
1378 * Enable the CRI clock source so we can get at the display and the
1379 * reference clock for VGA hotplug / manual detection.
1380 */
1381 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1382 DPLL_REFA_CLK_ENABLE_VLV |
1383 DPLL_INTEGRATED_CRI_CLK_VLV);
1384
1385 /*
1386 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1388 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389 * b. The other bits such as sfr settings / modesel may all be set
1390 * to 0.
1391 *
1392 * This should only be done on init and resume from S3 with both
1393 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394 */
1395 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1396 }
1397
1398 static void vlv_enable_pll(struct intel_crtc *crtc)
1399 {
1400 struct drm_device *dev = crtc->base.dev;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 int reg = DPLL(crtc->pipe);
1403 u32 dpll = crtc->config.dpll_hw_state.dpll;
1404
1405 assert_pipe_disabled(dev_priv, crtc->pipe);
1406
1407 /* No really, not for ILK+ */
1408 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409
1410 /* PLL is protected by panel, make sure we can write it */
1411 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1412 assert_panel_unlocked(dev_priv, crtc->pipe);
1413
1414 I915_WRITE(reg, dpll);
1415 POSTING_READ(reg);
1416 udelay(150);
1417
1418 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1419 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420
1421 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1422 POSTING_READ(DPLL_MD(crtc->pipe));
1423
1424 /* We do this three times for luck */
1425 I915_WRITE(reg, dpll);
1426 POSTING_READ(reg);
1427 udelay(150); /* wait for warmup */
1428 I915_WRITE(reg, dpll);
1429 POSTING_READ(reg);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg, dpll);
1432 POSTING_READ(reg);
1433 udelay(150); /* wait for warmup */
1434 }
1435
1436 static void i9xx_enable_pll(struct intel_crtc *crtc)
1437 {
1438 struct drm_device *dev = crtc->base.dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440 int reg = DPLL(crtc->pipe);
1441 u32 dpll = crtc->config.dpll_hw_state.dpll;
1442
1443 assert_pipe_disabled(dev_priv, crtc->pipe);
1444
1445 /* No really, not for ILK+ */
1446 BUG_ON(dev_priv->info->gen >= 5);
1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev) && !IS_I830(dev))
1450 assert_panel_unlocked(dev_priv, crtc->pipe);
1451
1452 I915_WRITE(reg, dpll);
1453
1454 /* Wait for the clocks to stabilize. */
1455 POSTING_READ(reg);
1456 udelay(150);
1457
1458 if (INTEL_INFO(dev)->gen >= 4) {
1459 I915_WRITE(DPLL_MD(crtc->pipe),
1460 crtc->config.dpll_hw_state.dpll_md);
1461 } else {
1462 /* The pixel multiplier can only be updated once the
1463 * DPLL is enabled and the clocks are stable.
1464 *
1465 * So write it again.
1466 */
1467 I915_WRITE(reg, dpll);
1468 }
1469
1470 /* We do this three times for luck */
1471 I915_WRITE(reg, dpll);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, dpll);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg, dpll);
1478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480 }
1481
1482 /**
1483 * i9xx_disable_pll - disable a PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to disable
1486 *
1487 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 *
1489 * Note! This is for pre-ILK only.
1490 */
1491 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1492 {
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 I915_WRITE(DPLL(pipe), 0);
1501 POSTING_READ(DPLL(pipe));
1502 }
1503
1504 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506 u32 val = 0;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 /*
1512 * Leave integrated clock source and reference clock enabled for pipe B.
1513 * The latter is needed for VGA hotplug / manual detection.
1514 */
1515 if (pipe == PIPE_B)
1516 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1517 I915_WRITE(DPLL(pipe), val);
1518 POSTING_READ(DPLL(pipe));
1519 }
1520
1521 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1522 struct intel_digital_port *dport)
1523 {
1524 u32 port_mask;
1525
1526 switch (dport->port) {
1527 case PORT_B:
1528 port_mask = DPLL_PORTB_READY_MASK;
1529 break;
1530 case PORT_C:
1531 port_mask = DPLL_PORTC_READY_MASK;
1532 break;
1533 default:
1534 BUG();
1535 }
1536
1537 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1538 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539 port_name(dport->port), I915_READ(DPLL(0)));
1540 }
1541
1542 /**
1543 * ironlake_enable_shared_dpll - enable PCH PLL
1544 * @dev_priv: i915 private structure
1545 * @pipe: pipe PLL to enable
1546 *
1547 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548 * drives the transcoder clock.
1549 */
1550 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1551 {
1552 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1553 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1554
1555 /* PCH PLLs only available on ILK, SNB and IVB */
1556 BUG_ON(dev_priv->info->gen < 5);
1557 if (WARN_ON(pll == NULL))
1558 return;
1559
1560 if (WARN_ON(pll->refcount == 0))
1561 return;
1562
1563 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564 pll->name, pll->active, pll->on,
1565 crtc->base.base.id);
1566
1567 if (pll->active++) {
1568 WARN_ON(!pll->on);
1569 assert_shared_dpll_enabled(dev_priv, pll);
1570 return;
1571 }
1572 WARN_ON(pll->on);
1573
1574 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1575 pll->enable(dev_priv, pll);
1576 pll->on = true;
1577 }
1578
1579 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1580 {
1581 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1582 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1583
1584 /* PCH only available on ILK+ */
1585 BUG_ON(dev_priv->info->gen < 5);
1586 if (WARN_ON(pll == NULL))
1587 return;
1588
1589 if (WARN_ON(pll->refcount == 0))
1590 return;
1591
1592 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593 pll->name, pll->active, pll->on,
1594 crtc->base.base.id);
1595
1596 if (WARN_ON(pll->active == 0)) {
1597 assert_shared_dpll_disabled(dev_priv, pll);
1598 return;
1599 }
1600
1601 assert_shared_dpll_enabled(dev_priv, pll);
1602 WARN_ON(!pll->on);
1603 if (--pll->active)
1604 return;
1605
1606 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1607 pll->disable(dev_priv, pll);
1608 pll->on = false;
1609 }
1610
1611 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1612 enum pipe pipe)
1613 {
1614 struct drm_device *dev = dev_priv->dev;
1615 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617 uint32_t reg, val, pipeconf_val;
1618
1619 /* PCH only available on ILK+ */
1620 BUG_ON(dev_priv->info->gen < 5);
1621
1622 /* Make sure PCH DPLL is enabled */
1623 assert_shared_dpll_enabled(dev_priv,
1624 intel_crtc_to_shared_dpll(intel_crtc));
1625
1626 /* FDI must be feeding us bits for PCH ports */
1627 assert_fdi_tx_enabled(dev_priv, pipe);
1628 assert_fdi_rx_enabled(dev_priv, pipe);
1629
1630 if (HAS_PCH_CPT(dev)) {
1631 /* Workaround: Set the timing override bit before enabling the
1632 * pch transcoder. */
1633 reg = TRANS_CHICKEN2(pipe);
1634 val = I915_READ(reg);
1635 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1636 I915_WRITE(reg, val);
1637 }
1638
1639 reg = PCH_TRANSCONF(pipe);
1640 val = I915_READ(reg);
1641 pipeconf_val = I915_READ(PIPECONF(pipe));
1642
1643 if (HAS_PCH_IBX(dev_priv->dev)) {
1644 /*
1645 * make the BPC in transcoder be consistent with
1646 * that in pipeconf reg.
1647 */
1648 val &= ~PIPECONF_BPC_MASK;
1649 val |= pipeconf_val & PIPECONF_BPC_MASK;
1650 }
1651
1652 val &= ~TRANS_INTERLACE_MASK;
1653 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1654 if (HAS_PCH_IBX(dev_priv->dev) &&
1655 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1656 val |= TRANS_LEGACY_INTERLACED_ILK;
1657 else
1658 val |= TRANS_INTERLACED;
1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
1662 I915_WRITE(reg, val | TRANS_ENABLE);
1663 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1665 }
1666
1667 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum transcoder cpu_transcoder)
1669 {
1670 u32 val, pipeconf_val;
1671
1672 /* PCH only available on ILK+ */
1673 BUG_ON(dev_priv->info->gen < 5);
1674
1675 /* FDI must be feeding us bits for PCH ports */
1676 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1677 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1678
1679 /* Workaround: set timing override bit. */
1680 val = I915_READ(_TRANSA_CHICKEN2);
1681 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1682 I915_WRITE(_TRANSA_CHICKEN2, val);
1683
1684 val = TRANS_ENABLE;
1685 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1686
1687 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1688 PIPECONF_INTERLACED_ILK)
1689 val |= TRANS_INTERLACED;
1690 else
1691 val |= TRANS_PROGRESSIVE;
1692
1693 I915_WRITE(LPT_TRANSCONF, val);
1694 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1695 DRM_ERROR("Failed to enable PCH transcoder\n");
1696 }
1697
1698 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1699 enum pipe pipe)
1700 {
1701 struct drm_device *dev = dev_priv->dev;
1702 uint32_t reg, val;
1703
1704 /* FDI relies on the transcoder */
1705 assert_fdi_tx_disabled(dev_priv, pipe);
1706 assert_fdi_rx_disabled(dev_priv, pipe);
1707
1708 /* Ports must be off as well */
1709 assert_pch_ports_disabled(dev_priv, pipe);
1710
1711 reg = PCH_TRANSCONF(pipe);
1712 val = I915_READ(reg);
1713 val &= ~TRANS_ENABLE;
1714 I915_WRITE(reg, val);
1715 /* wait for PCH transcoder off, transcoder state */
1716 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1717 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1718
1719 if (!HAS_PCH_IBX(dev)) {
1720 /* Workaround: Clear the timing override chicken bit again. */
1721 reg = TRANS_CHICKEN2(pipe);
1722 val = I915_READ(reg);
1723 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1724 I915_WRITE(reg, val);
1725 }
1726 }
1727
1728 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1729 {
1730 u32 val;
1731
1732 val = I915_READ(LPT_TRANSCONF);
1733 val &= ~TRANS_ENABLE;
1734 I915_WRITE(LPT_TRANSCONF, val);
1735 /* wait for PCH transcoder off, transcoder state */
1736 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1737 DRM_ERROR("Failed to disable PCH transcoder\n");
1738
1739 /* Workaround: clear timing override bit. */
1740 val = I915_READ(_TRANSA_CHICKEN2);
1741 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1742 I915_WRITE(_TRANSA_CHICKEN2, val);
1743 }
1744
1745 /**
1746 * intel_enable_pipe - enable a pipe, asserting requirements
1747 * @dev_priv: i915 private structure
1748 * @pipe: pipe to enable
1749 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1750 *
1751 * Enable @pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1753 *
1754 * @pipe should be %PIPE_A or %PIPE_B.
1755 *
1756 * Will wait until the pipe is actually running (i.e. first vblank) before
1757 * returning.
1758 */
1759 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1760 bool pch_port, bool dsi)
1761 {
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
1764 enum pipe pch_transcoder;
1765 int reg;
1766 u32 val;
1767
1768 assert_planes_disabled(dev_priv, pipe);
1769 assert_cursor_disabled(dev_priv, pipe);
1770 assert_sprites_disabled(dev_priv, pipe);
1771
1772 if (HAS_PCH_LPT(dev_priv->dev))
1773 pch_transcoder = TRANSCODER_A;
1774 else
1775 pch_transcoder = pipe;
1776
1777 /*
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1780 * need the check.
1781 */
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (dsi)
1784 assert_dsi_pll_enabled(dev_priv);
1785 else
1786 assert_pll_enabled(dev_priv, pipe);
1787 else {
1788 if (pch_port) {
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
1793 }
1794 /* FIXME: assert CPU port conditions for SNB+ */
1795 }
1796
1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE)
1800 return;
1801
1802 I915_WRITE(reg, val | PIPECONF_ENABLE);
1803 intel_wait_for_vblank(dev_priv->dev, pipe);
1804 }
1805
1806 /**
1807 * intel_disable_pipe - disable a pipe, asserting requirements
1808 * @dev_priv: i915 private structure
1809 * @pipe: pipe to disable
1810 *
1811 * Disable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1813 *
1814 * @pipe should be %PIPE_A or %PIPE_B.
1815 *
1816 * Will wait until the pipe has shut down before returning.
1817 */
1818 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1819 enum pipe pipe)
1820 {
1821 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1822 pipe);
1823 int reg;
1824 u32 val;
1825
1826 /*
1827 * Make sure planes won't keep trying to pump pixels to us,
1828 * or we might hang the display.
1829 */
1830 assert_planes_disabled(dev_priv, pipe);
1831 assert_cursor_disabled(dev_priv, pipe);
1832 assert_sprites_disabled(dev_priv, pipe);
1833
1834 /* Don't disable pipe A or pipe A PLLs if needed */
1835 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1836 return;
1837
1838 reg = PIPECONF(cpu_transcoder);
1839 val = I915_READ(reg);
1840 if ((val & PIPECONF_ENABLE) == 0)
1841 return;
1842
1843 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1844 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1845 }
1846
1847 /*
1848 * Plane regs are double buffered, going from enabled->disabled needs a
1849 * trigger in order to latch. The display address reg provides this.
1850 */
1851 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane)
1853 {
1854 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1855
1856 I915_WRITE(reg, I915_READ(reg));
1857 POSTING_READ(reg);
1858 }
1859
1860 /**
1861 * intel_enable_primary_plane - enable the primary plane on a given pipe
1862 * @dev_priv: i915 private structure
1863 * @plane: plane to enable
1864 * @pipe: pipe being fed
1865 *
1866 * Enable @plane on @pipe, making sure that @pipe is running first.
1867 */
1868 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1869 enum plane plane, enum pipe pipe)
1870 {
1871 struct intel_crtc *intel_crtc =
1872 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1873 int reg;
1874 u32 val;
1875
1876 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877 assert_pipe_enabled(dev_priv, pipe);
1878
1879 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1880
1881 intel_crtc->primary_enabled = true;
1882
1883 reg = DSPCNTR(plane);
1884 val = I915_READ(reg);
1885 if (val & DISPLAY_PLANE_ENABLE)
1886 return;
1887
1888 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1889 intel_flush_primary_plane(dev_priv, plane);
1890 intel_wait_for_vblank(dev_priv->dev, pipe);
1891 }
1892
1893 /**
1894 * intel_disable_primary_plane - disable the primary plane
1895 * @dev_priv: i915 private structure
1896 * @plane: plane to disable
1897 * @pipe: pipe consuming the data
1898 *
1899 * Disable @plane; should be an independent operation.
1900 */
1901 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1902 enum plane plane, enum pipe pipe)
1903 {
1904 struct intel_crtc *intel_crtc =
1905 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1906 int reg;
1907 u32 val;
1908
1909 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1910
1911 intel_crtc->primary_enabled = false;
1912
1913 reg = DSPCNTR(plane);
1914 val = I915_READ(reg);
1915 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1916 return;
1917
1918 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1919 intel_flush_primary_plane(dev_priv, plane);
1920 intel_wait_for_vblank(dev_priv->dev, pipe);
1921 }
1922
1923 static bool need_vtd_wa(struct drm_device *dev)
1924 {
1925 #ifdef CONFIG_INTEL_IOMMU
1926 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1927 return true;
1928 #endif
1929 return false;
1930 }
1931
1932 int
1933 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1934 struct drm_i915_gem_object *obj,
1935 struct intel_ring_buffer *pipelined)
1936 {
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 u32 alignment;
1939 int ret;
1940
1941 switch (obj->tiling_mode) {
1942 case I915_TILING_NONE:
1943 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1944 alignment = 128 * 1024;
1945 else if (INTEL_INFO(dev)->gen >= 4)
1946 alignment = 4 * 1024;
1947 else
1948 alignment = 64 * 1024;
1949 break;
1950 case I915_TILING_X:
1951 /* pin() will align the object as required by fence */
1952 alignment = 0;
1953 break;
1954 case I915_TILING_Y:
1955 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1956 return -EINVAL;
1957 default:
1958 BUG();
1959 }
1960
1961 /* Note that the w/a also requires 64 PTE of padding following the
1962 * bo. We currently fill all unused PTE with the shadow page and so
1963 * we should always have valid PTE following the scanout preventing
1964 * the VT-d warning.
1965 */
1966 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1967 alignment = 256 * 1024;
1968
1969 dev_priv->mm.interruptible = false;
1970 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1971 if (ret)
1972 goto err_interruptible;
1973
1974 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975 * fence, whereas 965+ only requires a fence if using
1976 * framebuffer compression. For simplicity, we always install
1977 * a fence as the cost is not that onerous.
1978 */
1979 ret = i915_gem_object_get_fence(obj);
1980 if (ret)
1981 goto err_unpin;
1982
1983 i915_gem_object_pin_fence(obj);
1984
1985 dev_priv->mm.interruptible = true;
1986 return 0;
1987
1988 err_unpin:
1989 i915_gem_object_unpin_from_display_plane(obj);
1990 err_interruptible:
1991 dev_priv->mm.interruptible = true;
1992 return ret;
1993 }
1994
1995 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1996 {
1997 i915_gem_object_unpin_fence(obj);
1998 i915_gem_object_unpin_from_display_plane(obj);
1999 }
2000
2001 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002 * is assumed to be a power-of-two. */
2003 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2004 unsigned int tiling_mode,
2005 unsigned int cpp,
2006 unsigned int pitch)
2007 {
2008 if (tiling_mode != I915_TILING_NONE) {
2009 unsigned int tile_rows, tiles;
2010
2011 tile_rows = *y / 8;
2012 *y %= 8;
2013
2014 tiles = *x / (512/cpp);
2015 *x %= 512/cpp;
2016
2017 return tile_rows * pitch * 8 + tiles * 4096;
2018 } else {
2019 unsigned int offset;
2020
2021 offset = *y * pitch + *x * cpp;
2022 *y = 0;
2023 *x = (offset & 4095) / cpp;
2024 return offset & -4096;
2025 }
2026 }
2027
2028 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2029 int x, int y)
2030 {
2031 struct drm_device *dev = crtc->dev;
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2034 struct intel_framebuffer *intel_fb;
2035 struct drm_i915_gem_object *obj;
2036 int plane = intel_crtc->plane;
2037 unsigned long linear_offset;
2038 u32 dspcntr;
2039 u32 reg;
2040
2041 switch (plane) {
2042 case 0:
2043 case 1:
2044 break;
2045 default:
2046 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2047 return -EINVAL;
2048 }
2049
2050 intel_fb = to_intel_framebuffer(fb);
2051 obj = intel_fb->obj;
2052
2053 reg = DSPCNTR(plane);
2054 dspcntr = I915_READ(reg);
2055 /* Mask out pixel format bits in case we change it */
2056 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2057 switch (fb->pixel_format) {
2058 case DRM_FORMAT_C8:
2059 dspcntr |= DISPPLANE_8BPP;
2060 break;
2061 case DRM_FORMAT_XRGB1555:
2062 case DRM_FORMAT_ARGB1555:
2063 dspcntr |= DISPPLANE_BGRX555;
2064 break;
2065 case DRM_FORMAT_RGB565:
2066 dspcntr |= DISPPLANE_BGRX565;
2067 break;
2068 case DRM_FORMAT_XRGB8888:
2069 case DRM_FORMAT_ARGB8888:
2070 dspcntr |= DISPPLANE_BGRX888;
2071 break;
2072 case DRM_FORMAT_XBGR8888:
2073 case DRM_FORMAT_ABGR8888:
2074 dspcntr |= DISPPLANE_RGBX888;
2075 break;
2076 case DRM_FORMAT_XRGB2101010:
2077 case DRM_FORMAT_ARGB2101010:
2078 dspcntr |= DISPPLANE_BGRX101010;
2079 break;
2080 case DRM_FORMAT_XBGR2101010:
2081 case DRM_FORMAT_ABGR2101010:
2082 dspcntr |= DISPPLANE_RGBX101010;
2083 break;
2084 default:
2085 BUG();
2086 }
2087
2088 if (INTEL_INFO(dev)->gen >= 4) {
2089 if (obj->tiling_mode != I915_TILING_NONE)
2090 dspcntr |= DISPPLANE_TILED;
2091 else
2092 dspcntr &= ~DISPPLANE_TILED;
2093 }
2094
2095 if (IS_G4X(dev))
2096 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
2098 I915_WRITE(reg, dspcntr);
2099
2100 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102 if (INTEL_INFO(dev)->gen >= 4) {
2103 intel_crtc->dspaddr_offset =
2104 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2105 fb->bits_per_pixel / 8,
2106 fb->pitches[0]);
2107 linear_offset -= intel_crtc->dspaddr_offset;
2108 } else {
2109 intel_crtc->dspaddr_offset = linear_offset;
2110 }
2111
2112 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2114 fb->pitches[0]);
2115 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2116 if (INTEL_INFO(dev)->gen >= 4) {
2117 I915_WRITE(DSPSURF(plane),
2118 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2119 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2120 I915_WRITE(DSPLINOFF(plane), linear_offset);
2121 } else
2122 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2123 POSTING_READ(reg);
2124
2125 return 0;
2126 }
2127
2128 static int ironlake_update_plane(struct drm_crtc *crtc,
2129 struct drm_framebuffer *fb, int x, int y)
2130 {
2131 struct drm_device *dev = crtc->dev;
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134 struct intel_framebuffer *intel_fb;
2135 struct drm_i915_gem_object *obj;
2136 int plane = intel_crtc->plane;
2137 unsigned long linear_offset;
2138 u32 dspcntr;
2139 u32 reg;
2140
2141 switch (plane) {
2142 case 0:
2143 case 1:
2144 case 2:
2145 break;
2146 default:
2147 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2148 return -EINVAL;
2149 }
2150
2151 intel_fb = to_intel_framebuffer(fb);
2152 obj = intel_fb->obj;
2153
2154 reg = DSPCNTR(plane);
2155 dspcntr = I915_READ(reg);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2158 switch (fb->pixel_format) {
2159 case DRM_FORMAT_C8:
2160 dspcntr |= DISPPLANE_8BPP;
2161 break;
2162 case DRM_FORMAT_RGB565:
2163 dspcntr |= DISPPLANE_BGRX565;
2164 break;
2165 case DRM_FORMAT_XRGB8888:
2166 case DRM_FORMAT_ARGB8888:
2167 dspcntr |= DISPPLANE_BGRX888;
2168 break;
2169 case DRM_FORMAT_XBGR8888:
2170 case DRM_FORMAT_ABGR8888:
2171 dspcntr |= DISPPLANE_RGBX888;
2172 break;
2173 case DRM_FORMAT_XRGB2101010:
2174 case DRM_FORMAT_ARGB2101010:
2175 dspcntr |= DISPPLANE_BGRX101010;
2176 break;
2177 case DRM_FORMAT_XBGR2101010:
2178 case DRM_FORMAT_ABGR2101010:
2179 dspcntr |= DISPPLANE_RGBX101010;
2180 break;
2181 default:
2182 BUG();
2183 }
2184
2185 if (obj->tiling_mode != I915_TILING_NONE)
2186 dspcntr |= DISPPLANE_TILED;
2187 else
2188 dspcntr &= ~DISPPLANE_TILED;
2189
2190 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2191 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2192 else
2193 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2194
2195 I915_WRITE(reg, dspcntr);
2196
2197 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2198 intel_crtc->dspaddr_offset =
2199 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2200 fb->bits_per_pixel / 8,
2201 fb->pitches[0]);
2202 linear_offset -= intel_crtc->dspaddr_offset;
2203
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2206 fb->pitches[0]);
2207 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208 I915_WRITE(DSPSURF(plane),
2209 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2210 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2211 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212 } else {
2213 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215 }
2216 POSTING_READ(reg);
2217
2218 return 0;
2219 }
2220
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2222 static int
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 int x, int y, enum mode_set_atomic state)
2225 {
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229 if (dev_priv->display.disable_fbc)
2230 dev_priv->display.disable_fbc(dev);
2231 intel_increase_pllclock(crtc);
2232
2233 return dev_priv->display.update_plane(crtc, fb, x, y);
2234 }
2235
2236 void intel_display_handle_reset(struct drm_device *dev)
2237 {
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct drm_crtc *crtc;
2240
2241 /*
2242 * Flips in the rings have been nuked by the reset,
2243 * so complete all pending flips so that user space
2244 * will get its events and not get stuck.
2245 *
2246 * Also update the base address of all primary
2247 * planes to the the last fb to make sure we're
2248 * showing the correct fb after a reset.
2249 *
2250 * Need to make two loops over the crtcs so that we
2251 * don't try to grab a crtc mutex before the
2252 * pending_flip_queue really got woken up.
2253 */
2254
2255 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257 enum plane plane = intel_crtc->plane;
2258
2259 intel_prepare_page_flip(dev, plane);
2260 intel_finish_page_flip_plane(dev, plane);
2261 }
2262
2263 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266 mutex_lock(&crtc->mutex);
2267 /*
2268 * FIXME: Once we have proper support for primary planes (and
2269 * disabling them without disabling the entire crtc) allow again
2270 * a NULL crtc->fb.
2271 */
2272 if (intel_crtc->active && crtc->fb)
2273 dev_priv->display.update_plane(crtc, crtc->fb,
2274 crtc->x, crtc->y);
2275 mutex_unlock(&crtc->mutex);
2276 }
2277 }
2278
2279 static int
2280 intel_finish_fb(struct drm_framebuffer *old_fb)
2281 {
2282 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2283 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284 bool was_interruptible = dev_priv->mm.interruptible;
2285 int ret;
2286
2287 /* Big Hammer, we also need to ensure that any pending
2288 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289 * current scanout is retired before unpinning the old
2290 * framebuffer.
2291 *
2292 * This should only fail upon a hung GPU, in which case we
2293 * can safely continue.
2294 */
2295 dev_priv->mm.interruptible = false;
2296 ret = i915_gem_object_finish_gpu(obj);
2297 dev_priv->mm.interruptible = was_interruptible;
2298
2299 return ret;
2300 }
2301
2302 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2303 {
2304 struct drm_device *dev = crtc->dev;
2305 struct drm_i915_master_private *master_priv;
2306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307
2308 if (!dev->primary->master)
2309 return;
2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
2313 return;
2314
2315 switch (intel_crtc->pipe) {
2316 case 0:
2317 master_priv->sarea_priv->pipeA_x = x;
2318 master_priv->sarea_priv->pipeA_y = y;
2319 break;
2320 case 1:
2321 master_priv->sarea_priv->pipeB_x = x;
2322 master_priv->sarea_priv->pipeB_y = y;
2323 break;
2324 default:
2325 break;
2326 }
2327 }
2328
2329 static int
2330 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2331 struct drm_framebuffer *fb)
2332 {
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 struct drm_framebuffer *old_fb;
2337 int ret;
2338
2339 /* no fb bound */
2340 if (!fb) {
2341 DRM_ERROR("No FB bound\n");
2342 return 0;
2343 }
2344
2345 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2346 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347 plane_name(intel_crtc->plane),
2348 INTEL_INFO(dev)->num_pipes);
2349 return -EINVAL;
2350 }
2351
2352 mutex_lock(&dev->struct_mutex);
2353 ret = intel_pin_and_fence_fb_obj(dev,
2354 to_intel_framebuffer(fb)->obj,
2355 NULL);
2356 if (ret != 0) {
2357 mutex_unlock(&dev->struct_mutex);
2358 DRM_ERROR("pin & fence failed\n");
2359 return ret;
2360 }
2361
2362 /*
2363 * Update pipe size and adjust fitter if needed: the reason for this is
2364 * that in compute_mode_changes we check the native mode (not the pfit
2365 * mode) to see if we can flip rather than do a full mode set. In the
2366 * fastboot case, we'll flip, but if we don't update the pipesrc and
2367 * pfit state, we'll end up with a big fb scanned out into the wrong
2368 * sized surface.
2369 *
2370 * To fix this properly, we need to hoist the checks up into
2371 * compute_mode_changes (or above), check the actual pfit state and
2372 * whether the platform allows pfit disable with pipe active, and only
2373 * then update the pipesrc and pfit state, even on the flip path.
2374 */
2375 if (i915_fastboot) {
2376 const struct drm_display_mode *adjusted_mode =
2377 &intel_crtc->config.adjusted_mode;
2378
2379 I915_WRITE(PIPESRC(intel_crtc->pipe),
2380 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2381 (adjusted_mode->crtc_vdisplay - 1));
2382 if (!intel_crtc->config.pch_pfit.enabled &&
2383 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2384 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2385 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2386 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2387 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2388 }
2389 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2390 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2391 }
2392
2393 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2394 if (ret) {
2395 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2396 mutex_unlock(&dev->struct_mutex);
2397 DRM_ERROR("failed to update base address\n");
2398 return ret;
2399 }
2400
2401 old_fb = crtc->fb;
2402 crtc->fb = fb;
2403 crtc->x = x;
2404 crtc->y = y;
2405
2406 if (old_fb) {
2407 if (intel_crtc->active && old_fb != fb)
2408 intel_wait_for_vblank(dev, intel_crtc->pipe);
2409 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2410 }
2411
2412 intel_update_fbc(dev);
2413 intel_edp_psr_update(dev);
2414 mutex_unlock(&dev->struct_mutex);
2415
2416 intel_crtc_update_sarea_pos(crtc, x, y);
2417
2418 return 0;
2419 }
2420
2421 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2422 {
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
2427 u32 reg, temp;
2428
2429 /* enable normal train */
2430 reg = FDI_TX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 if (IS_IVYBRIDGE(dev)) {
2433 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2434 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2435 } else {
2436 temp &= ~FDI_LINK_TRAIN_NONE;
2437 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2438 }
2439 I915_WRITE(reg, temp);
2440
2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
2443 if (HAS_PCH_CPT(dev)) {
2444 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2446 } else {
2447 temp &= ~FDI_LINK_TRAIN_NONE;
2448 temp |= FDI_LINK_TRAIN_NONE;
2449 }
2450 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2451
2452 /* wait one idle pattern time */
2453 POSTING_READ(reg);
2454 udelay(1000);
2455
2456 /* IVB wants error correction enabled */
2457 if (IS_IVYBRIDGE(dev))
2458 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2459 FDI_FE_ERRC_ENABLE);
2460 }
2461
2462 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2463 {
2464 return crtc->base.enabled && crtc->active &&
2465 crtc->config.has_pch_encoder;
2466 }
2467
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /*
2478 * When everything is off disable fdi C so that we could enable fdi B
2479 * with all lanes. Note that we don't care about enabled pipes without
2480 * an enabled pch encoder.
2481 */
2482 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2483 !pipe_has_enabled_pch(pipe_C_crtc)) {
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2485 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2486
2487 temp = I915_READ(SOUTH_CHICKEN1);
2488 temp &= ~FDI_BC_BIFURCATION_SELECT;
2489 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490 I915_WRITE(SOUTH_CHICKEN1, temp);
2491 }
2492 }
2493
2494 /* The FDI link training functions for ILK/Ibexpeak. */
2495 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2496 {
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 int pipe = intel_crtc->pipe;
2501 int plane = intel_crtc->plane;
2502 u32 reg, temp, tries;
2503
2504 /* FDI needs bits from pipe & plane first */
2505 assert_pipe_enabled(dev_priv, pipe);
2506 assert_plane_enabled(dev_priv, plane);
2507
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
2514 I915_WRITE(reg, temp);
2515 I915_READ(reg);
2516 udelay(150);
2517
2518 /* enable CPU FDI TX and PCH FDI RX */
2519 reg = FDI_TX_CTL(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2522 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_1;
2525 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2526
2527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2532
2533 POSTING_READ(reg);
2534 udelay(150);
2535
2536 /* Ironlake workaround, enable clock pointer after FDI enable*/
2537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2538 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2539 FDI_RX_PHASE_SYNC_POINTER_EN);
2540
2541 reg = FDI_RX_IIR(pipe);
2542 for (tries = 0; tries < 5; tries++) {
2543 temp = I915_READ(reg);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546 if ((temp & FDI_RX_BIT_LOCK)) {
2547 DRM_DEBUG_KMS("FDI train 1 done.\n");
2548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549 break;
2550 }
2551 }
2552 if (tries == 5)
2553 DRM_ERROR("FDI train 1 fail!\n");
2554
2555 /* Train 2 */
2556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560 I915_WRITE(reg, temp);
2561
2562 reg = FDI_RX_CTL(pipe);
2563 temp = I915_READ(reg);
2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
2566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
2569 udelay(150);
2570
2571 reg = FDI_RX_IIR(pipe);
2572 for (tries = 0; tries < 5; tries++) {
2573 temp = I915_READ(reg);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576 if (temp & FDI_RX_SYMBOL_LOCK) {
2577 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2578 DRM_DEBUG_KMS("FDI train 2 done.\n");
2579 break;
2580 }
2581 }
2582 if (tries == 5)
2583 DRM_ERROR("FDI train 2 fail!\n");
2584
2585 DRM_DEBUG_KMS("FDI train done\n");
2586
2587 }
2588
2589 static const int snb_b_fdi_train_param[] = {
2590 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2591 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2592 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2593 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2594 };
2595
2596 /* The FDI link training functions for SNB/Cougarpoint. */
2597 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2598 {
2599 struct drm_device *dev = crtc->dev;
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 int pipe = intel_crtc->pipe;
2603 u32 reg, temp, i, retry;
2604
2605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606 for train result */
2607 reg = FDI_RX_IMR(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_RX_SYMBOL_LOCK;
2610 temp &= ~FDI_RX_BIT_LOCK;
2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
2614 udelay(150);
2615
2616 /* enable CPU FDI TX and PCH FDI RX */
2617 reg = FDI_TX_CTL(pipe);
2618 temp = I915_READ(reg);
2619 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2620 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2621 temp &= ~FDI_LINK_TRAIN_NONE;
2622 temp |= FDI_LINK_TRAIN_PATTERN_1;
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 /* SNB-B */
2625 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628 I915_WRITE(FDI_RX_MISC(pipe),
2629 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 if (HAS_PCH_CPT(dev)) {
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636 } else {
2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_1;
2639 }
2640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642 POSTING_READ(reg);
2643 udelay(150);
2644
2645 for (i = 0; i < 4; i++) {
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(500);
2654
2655 for (retry = 0; retry < 5; retry++) {
2656 reg = FDI_RX_IIR(pipe);
2657 temp = I915_READ(reg);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659 if (temp & FDI_RX_BIT_LOCK) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 udelay(50);
2665 }
2666 if (retry < 5)
2667 break;
2668 }
2669 if (i == 4)
2670 DRM_ERROR("FDI train 1 fail!\n");
2671
2672 /* Train 2 */
2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_NONE;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2;
2677 if (IS_GEN6(dev)) {
2678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679 /* SNB-B */
2680 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681 }
2682 I915_WRITE(reg, temp);
2683
2684 reg = FDI_RX_CTL(pipe);
2685 temp = I915_READ(reg);
2686 if (HAS_PCH_CPT(dev)) {
2687 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2689 } else {
2690 temp &= ~FDI_LINK_TRAIN_NONE;
2691 temp |= FDI_LINK_TRAIN_PATTERN_2;
2692 }
2693 I915_WRITE(reg, temp);
2694
2695 POSTING_READ(reg);
2696 udelay(150);
2697
2698 for (i = 0; i < 4; i++) {
2699 reg = FDI_TX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702 temp |= snb_b_fdi_train_param[i];
2703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
2706 udelay(500);
2707
2708 for (retry = 0; retry < 5; retry++) {
2709 reg = FDI_RX_IIR(pipe);
2710 temp = I915_READ(reg);
2711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2712 if (temp & FDI_RX_SYMBOL_LOCK) {
2713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2714 DRM_DEBUG_KMS("FDI train 2 done.\n");
2715 break;
2716 }
2717 udelay(50);
2718 }
2719 if (retry < 5)
2720 break;
2721 }
2722 if (i == 4)
2723 DRM_ERROR("FDI train 2 fail!\n");
2724
2725 DRM_DEBUG_KMS("FDI train done.\n");
2726 }
2727
2728 /* Manual link training for Ivy Bridge A0 parts */
2729 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2730 {
2731 struct drm_device *dev = crtc->dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2734 int pipe = intel_crtc->pipe;
2735 u32 reg, temp, i, j;
2736
2737 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2738 for train result */
2739 reg = FDI_RX_IMR(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_RX_SYMBOL_LOCK;
2742 temp &= ~FDI_RX_BIT_LOCK;
2743 I915_WRITE(reg, temp);
2744
2745 POSTING_READ(reg);
2746 udelay(150);
2747
2748 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749 I915_READ(FDI_RX_IIR(pipe)));
2750
2751 /* Try each vswing and preemphasis setting twice before moving on */
2752 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2753 /* disable first in case we need to retry */
2754 reg = FDI_TX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2757 temp &= ~FDI_TX_ENABLE;
2758 I915_WRITE(reg, temp);
2759
2760 reg = FDI_RX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 temp &= ~FDI_LINK_TRAIN_AUTO;
2763 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764 temp &= ~FDI_RX_ENABLE;
2765 I915_WRITE(reg, temp);
2766
2767 /* enable CPU FDI TX and PCH FDI RX */
2768 reg = FDI_TX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2771 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2772 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2773 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2774 temp |= snb_b_fdi_train_param[j/2];
2775 temp |= FDI_COMPOSITE_SYNC;
2776 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2777
2778 I915_WRITE(FDI_RX_MISC(pipe),
2779 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2780
2781 reg = FDI_RX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2784 temp |= FDI_COMPOSITE_SYNC;
2785 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2786
2787 POSTING_READ(reg);
2788 udelay(1); /* should be 0.5us */
2789
2790 for (i = 0; i < 4; i++) {
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795 if (temp & FDI_RX_BIT_LOCK ||
2796 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2798 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2799 i);
2800 break;
2801 }
2802 udelay(1); /* should be 0.5us */
2803 }
2804 if (i == 4) {
2805 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2806 continue;
2807 }
2808
2809 /* Train 2 */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2813 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2814 I915_WRITE(reg, temp);
2815
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820 I915_WRITE(reg, temp);
2821
2822 POSTING_READ(reg);
2823 udelay(2); /* should be 1.5us */
2824
2825 for (i = 0; i < 4; i++) {
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK ||
2831 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2832 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2833 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2834 i);
2835 goto train_done;
2836 }
2837 udelay(2); /* should be 1.5us */
2838 }
2839 if (i == 4)
2840 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2841 }
2842
2843 train_done:
2844 DRM_DEBUG_KMS("FDI train done.\n");
2845 }
2846
2847 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2848 {
2849 struct drm_device *dev = intel_crtc->base.dev;
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp;
2853
2854
2855 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2856 reg = FDI_RX_CTL(pipe);
2857 temp = I915_READ(reg);
2858 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2859 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(200);
2865
2866 /* Switch from Rawclk to PCDclk */
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp | FDI_PCDCLK);
2869
2870 POSTING_READ(reg);
2871 udelay(200);
2872
2873 /* Enable CPU FDI TX PLL, always on for Ironlake */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2877 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2878
2879 POSTING_READ(reg);
2880 udelay(100);
2881 }
2882 }
2883
2884 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2885 {
2886 struct drm_device *dev = intel_crtc->base.dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 int pipe = intel_crtc->pipe;
2889 u32 reg, temp;
2890
2891 /* Switch from PCDclk to Rawclk */
2892 reg = FDI_RX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2895
2896 /* Disable CPU FDI TX PLL */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2900
2901 POSTING_READ(reg);
2902 udelay(100);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2907
2908 /* Wait for the clocks to turn off. */
2909 POSTING_READ(reg);
2910 udelay(100);
2911 }
2912
2913 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2914 {
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918 int pipe = intel_crtc->pipe;
2919 u32 reg, temp;
2920
2921 /* disable CPU FDI tx and PCH FDI rx */
2922 reg = FDI_TX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2925 POSTING_READ(reg);
2926
2927 reg = FDI_RX_CTL(pipe);
2928 temp = I915_READ(reg);
2929 temp &= ~(0x7 << 16);
2930 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2931 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2932
2933 POSTING_READ(reg);
2934 udelay(100);
2935
2936 /* Ironlake workaround, disable clock pointer after downing FDI */
2937 if (HAS_PCH_IBX(dev)) {
2938 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2939 }
2940
2941 /* still set train pattern 1 */
2942 reg = FDI_TX_CTL(pipe);
2943 temp = I915_READ(reg);
2944 temp &= ~FDI_LINK_TRAIN_NONE;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1;
2946 I915_WRITE(reg, temp);
2947
2948 reg = FDI_RX_CTL(pipe);
2949 temp = I915_READ(reg);
2950 if (HAS_PCH_CPT(dev)) {
2951 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2953 } else {
2954 temp &= ~FDI_LINK_TRAIN_NONE;
2955 temp |= FDI_LINK_TRAIN_PATTERN_1;
2956 }
2957 /* BPC in FDI rx is consistent with that in PIPECONF */
2958 temp &= ~(0x07 << 16);
2959 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2960 I915_WRITE(reg, temp);
2961
2962 POSTING_READ(reg);
2963 udelay(100);
2964 }
2965
2966 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2967 {
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 unsigned long flags;
2972 bool pending;
2973
2974 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2975 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2976 return false;
2977
2978 spin_lock_irqsave(&dev->event_lock, flags);
2979 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2980 spin_unlock_irqrestore(&dev->event_lock, flags);
2981
2982 return pending;
2983 }
2984
2985 bool intel_has_pending_fb_unpin(struct drm_device *dev)
2986 {
2987 struct intel_crtc *crtc;
2988
2989 /* Note that we don't need to be called with mode_config.lock here
2990 * as our list of CRTC objects is static for the lifetime of the
2991 * device and so cannot disappear as we iterate. Similarly, we can
2992 * happily treat the predicates as racy, atomic checks as userspace
2993 * cannot claim and pin a new fb without at least acquring the
2994 * struct_mutex and so serialising with us.
2995 */
2996 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2997 if (atomic_read(&crtc->unpin_work_count) == 0)
2998 continue;
2999
3000 if (crtc->unpin_work)
3001 intel_wait_for_vblank(dev, crtc->pipe);
3002
3003 return true;
3004 }
3005
3006 return false;
3007 }
3008
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3010 {
3011 struct drm_device *dev = crtc->dev;
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013
3014 if (crtc->fb == NULL)
3015 return;
3016
3017 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3018
3019 wait_event(dev_priv->pending_flip_queue,
3020 !intel_crtc_has_pending_flip(crtc));
3021
3022 mutex_lock(&dev->struct_mutex);
3023 intel_finish_fb(crtc->fb);
3024 mutex_unlock(&dev->struct_mutex);
3025 }
3026
3027 /* Program iCLKIP clock to the desired frequency */
3028 static void lpt_program_iclkip(struct drm_crtc *crtc)
3029 {
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3033 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3034 u32 temp;
3035
3036 mutex_lock(&dev_priv->dpio_lock);
3037
3038 /* It is necessary to ungate the pixclk gate prior to programming
3039 * the divisors, and gate it back when it is done.
3040 */
3041 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3042
3043 /* Disable SSCCTL */
3044 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3045 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3046 SBI_SSCCTL_DISABLE,
3047 SBI_ICLK);
3048
3049 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3050 if (clock == 20000) {
3051 auxdiv = 1;
3052 divsel = 0x41;
3053 phaseinc = 0x20;
3054 } else {
3055 /* The iCLK virtual clock root frequency is in MHz,
3056 * but the adjusted_mode->crtc_clock in in KHz. To get the
3057 * divisors, it is necessary to divide one by another, so we
3058 * convert the virtual clock precision to KHz here for higher
3059 * precision.
3060 */
3061 u32 iclk_virtual_root_freq = 172800 * 1000;
3062 u32 iclk_pi_range = 64;
3063 u32 desired_divisor, msb_divisor_value, pi_value;
3064
3065 desired_divisor = (iclk_virtual_root_freq / clock);
3066 msb_divisor_value = desired_divisor / iclk_pi_range;
3067 pi_value = desired_divisor % iclk_pi_range;
3068
3069 auxdiv = 0;
3070 divsel = msb_divisor_value - 2;
3071 phaseinc = pi_value;
3072 }
3073
3074 /* This should not happen with any sane values */
3075 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3076 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3077 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3078 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3079
3080 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3081 clock,
3082 auxdiv,
3083 divsel,
3084 phasedir,
3085 phaseinc);
3086
3087 /* Program SSCDIVINTPHASE6 */
3088 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3089 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3090 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3091 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3092 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3093 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3094 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3095 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3096
3097 /* Program SSCAUXDIV */
3098 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3099 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3100 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3101 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3102
3103 /* Enable modulator and associated divider */
3104 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3105 temp &= ~SBI_SSCCTL_DISABLE;
3106 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3107
3108 /* Wait for initialization time */
3109 udelay(24);
3110
3111 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3112
3113 mutex_unlock(&dev_priv->dpio_lock);
3114 }
3115
3116 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3117 enum pipe pch_transcoder)
3118 {
3119 struct drm_device *dev = crtc->base.dev;
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3122
3123 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3124 I915_READ(HTOTAL(cpu_transcoder)));
3125 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3126 I915_READ(HBLANK(cpu_transcoder)));
3127 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3128 I915_READ(HSYNC(cpu_transcoder)));
3129
3130 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3131 I915_READ(VTOTAL(cpu_transcoder)));
3132 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3133 I915_READ(VBLANK(cpu_transcoder)));
3134 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3135 I915_READ(VSYNC(cpu_transcoder)));
3136 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3137 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3138 }
3139
3140 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3141 {
3142 struct drm_i915_private *dev_priv = dev->dev_private;
3143 uint32_t temp;
3144
3145 temp = I915_READ(SOUTH_CHICKEN1);
3146 if (temp & FDI_BC_BIFURCATION_SELECT)
3147 return;
3148
3149 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3150 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3151
3152 temp |= FDI_BC_BIFURCATION_SELECT;
3153 DRM_DEBUG_KMS("enabling fdi C rx\n");
3154 I915_WRITE(SOUTH_CHICKEN1, temp);
3155 POSTING_READ(SOUTH_CHICKEN1);
3156 }
3157
3158 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3159 {
3160 struct drm_device *dev = intel_crtc->base.dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162
3163 switch (intel_crtc->pipe) {
3164 case PIPE_A:
3165 break;
3166 case PIPE_B:
3167 if (intel_crtc->config.fdi_lanes > 2)
3168 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3169 else
3170 cpt_enable_fdi_bc_bifurcation(dev);
3171
3172 break;
3173 case PIPE_C:
3174 cpt_enable_fdi_bc_bifurcation(dev);
3175
3176 break;
3177 default:
3178 BUG();
3179 }
3180 }
3181
3182 /*
3183 * Enable PCH resources required for PCH ports:
3184 * - PCH PLLs
3185 * - FDI training & RX/TX
3186 * - update transcoder timings
3187 * - DP transcoding bits
3188 * - transcoder
3189 */
3190 static void ironlake_pch_enable(struct drm_crtc *crtc)
3191 {
3192 struct drm_device *dev = crtc->dev;
3193 struct drm_i915_private *dev_priv = dev->dev_private;
3194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3195 int pipe = intel_crtc->pipe;
3196 u32 reg, temp;
3197
3198 assert_pch_transcoder_disabled(dev_priv, pipe);
3199
3200 if (IS_IVYBRIDGE(dev))
3201 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3202
3203 /* Write the TU size bits before fdi link training, so that error
3204 * detection works. */
3205 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3206 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3207
3208 /* For PCH output, training FDI link */
3209 dev_priv->display.fdi_link_train(crtc);
3210
3211 /* We need to program the right clock selection before writing the pixel
3212 * mutliplier into the DPLL. */
3213 if (HAS_PCH_CPT(dev)) {
3214 u32 sel;
3215
3216 temp = I915_READ(PCH_DPLL_SEL);
3217 temp |= TRANS_DPLL_ENABLE(pipe);
3218 sel = TRANS_DPLLB_SEL(pipe);
3219 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3220 temp |= sel;
3221 else
3222 temp &= ~sel;
3223 I915_WRITE(PCH_DPLL_SEL, temp);
3224 }
3225
3226 /* XXX: pch pll's can be enabled any time before we enable the PCH
3227 * transcoder, and we actually should do this to not upset any PCH
3228 * transcoder that already use the clock when we share it.
3229 *
3230 * Note that enable_shared_dpll tries to do the right thing, but
3231 * get_shared_dpll unconditionally resets the pll - we need that to have
3232 * the right LVDS enable sequence. */
3233 ironlake_enable_shared_dpll(intel_crtc);
3234
3235 /* set transcoder timing, panel must allow it */
3236 assert_panel_unlocked(dev_priv, pipe);
3237 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3238
3239 intel_fdi_normal_train(crtc);
3240
3241 /* For PCH DP, enable TRANS_DP_CTL */
3242 if (HAS_PCH_CPT(dev) &&
3243 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3244 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3245 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3246 reg = TRANS_DP_CTL(pipe);
3247 temp = I915_READ(reg);
3248 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3249 TRANS_DP_SYNC_MASK |
3250 TRANS_DP_BPC_MASK);
3251 temp |= (TRANS_DP_OUTPUT_ENABLE |
3252 TRANS_DP_ENH_FRAMING);
3253 temp |= bpc << 9; /* same format but at 11:9 */
3254
3255 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3256 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3257 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3258 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3259
3260 switch (intel_trans_dp_port_sel(crtc)) {
3261 case PCH_DP_B:
3262 temp |= TRANS_DP_PORT_SEL_B;
3263 break;
3264 case PCH_DP_C:
3265 temp |= TRANS_DP_PORT_SEL_C;
3266 break;
3267 case PCH_DP_D:
3268 temp |= TRANS_DP_PORT_SEL_D;
3269 break;
3270 default:
3271 BUG();
3272 }
3273
3274 I915_WRITE(reg, temp);
3275 }
3276
3277 ironlake_enable_pch_transcoder(dev_priv, pipe);
3278 }
3279
3280 static void lpt_pch_enable(struct drm_crtc *crtc)
3281 {
3282 struct drm_device *dev = crtc->dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3286
3287 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3288
3289 lpt_program_iclkip(crtc);
3290
3291 /* Set transcoder timing. */
3292 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3293
3294 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3295 }
3296
3297 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3298 {
3299 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3300
3301 if (pll == NULL)
3302 return;
3303
3304 if (pll->refcount == 0) {
3305 WARN(1, "bad %s refcount\n", pll->name);
3306 return;
3307 }
3308
3309 if (--pll->refcount == 0) {
3310 WARN_ON(pll->on);
3311 WARN_ON(pll->active);
3312 }
3313
3314 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3315 }
3316
3317 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3318 {
3319 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3320 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3321 enum intel_dpll_id i;
3322
3323 if (pll) {
3324 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3325 crtc->base.base.id, pll->name);
3326 intel_put_shared_dpll(crtc);
3327 }
3328
3329 if (HAS_PCH_IBX(dev_priv->dev)) {
3330 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3331 i = (enum intel_dpll_id) crtc->pipe;
3332 pll = &dev_priv->shared_dplls[i];
3333
3334 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3335 crtc->base.base.id, pll->name);
3336
3337 goto found;
3338 }
3339
3340 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3341 pll = &dev_priv->shared_dplls[i];
3342
3343 /* Only want to check enabled timings first */
3344 if (pll->refcount == 0)
3345 continue;
3346
3347 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3348 sizeof(pll->hw_state)) == 0) {
3349 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3350 crtc->base.base.id,
3351 pll->name, pll->refcount, pll->active);
3352
3353 goto found;
3354 }
3355 }
3356
3357 /* Ok no matching timings, maybe there's a free one? */
3358 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3359 pll = &dev_priv->shared_dplls[i];
3360 if (pll->refcount == 0) {
3361 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3362 crtc->base.base.id, pll->name);
3363 goto found;
3364 }
3365 }
3366
3367 return NULL;
3368
3369 found:
3370 crtc->config.shared_dpll = i;
3371 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3372 pipe_name(crtc->pipe));
3373
3374 if (pll->active == 0) {
3375 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3376 sizeof(pll->hw_state));
3377
3378 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3379 WARN_ON(pll->on);
3380 assert_shared_dpll_disabled(dev_priv, pll);
3381
3382 pll->mode_set(dev_priv, pll);
3383 }
3384 pll->refcount++;
3385
3386 return pll;
3387 }
3388
3389 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3390 {
3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392 int dslreg = PIPEDSL(pipe);
3393 u32 temp;
3394
3395 temp = I915_READ(dslreg);
3396 udelay(500);
3397 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3398 if (wait_for(I915_READ(dslreg) != temp, 5))
3399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3400 }
3401 }
3402
3403 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3404 {
3405 struct drm_device *dev = crtc->base.dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 int pipe = crtc->pipe;
3408
3409 if (crtc->config.pch_pfit.enabled) {
3410 /* Force use of hard-coded filter coefficients
3411 * as some pre-programmed values are broken,
3412 * e.g. x201.
3413 */
3414 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3415 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3416 PF_PIPE_SEL_IVB(pipe));
3417 else
3418 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3419 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3420 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3421 }
3422 }
3423
3424 static void intel_enable_planes(struct drm_crtc *crtc)
3425 {
3426 struct drm_device *dev = crtc->dev;
3427 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3428 struct intel_plane *intel_plane;
3429
3430 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3431 if (intel_plane->pipe == pipe)
3432 intel_plane_restore(&intel_plane->base);
3433 }
3434
3435 static void intel_disable_planes(struct drm_crtc *crtc)
3436 {
3437 struct drm_device *dev = crtc->dev;
3438 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3439 struct intel_plane *intel_plane;
3440
3441 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3442 if (intel_plane->pipe == pipe)
3443 intel_plane_disable(&intel_plane->base);
3444 }
3445
3446 void hsw_enable_ips(struct intel_crtc *crtc)
3447 {
3448 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3449
3450 if (!crtc->config.ips_enabled)
3451 return;
3452
3453 /* We can only enable IPS after we enable a plane and wait for a vblank.
3454 * We guarantee that the plane is enabled by calling intel_enable_ips
3455 * only after intel_enable_plane. And intel_enable_plane already waits
3456 * for a vblank, so all we need to do here is to enable the IPS bit. */
3457 assert_plane_enabled(dev_priv, crtc->plane);
3458 if (IS_BROADWELL(crtc->base.dev)) {
3459 mutex_lock(&dev_priv->rps.hw_lock);
3460 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3461 mutex_unlock(&dev_priv->rps.hw_lock);
3462 /* Quoting Art Runyan: "its not safe to expect any particular
3463 * value in IPS_CTL bit 31 after enabling IPS through the
3464 * mailbox." Moreover, the mailbox may return a bogus state,
3465 * so we need to just enable it and continue on.
3466 */
3467 } else {
3468 I915_WRITE(IPS_CTL, IPS_ENABLE);
3469 /* The bit only becomes 1 in the next vblank, so this wait here
3470 * is essentially intel_wait_for_vblank. If we don't have this
3471 * and don't wait for vblanks until the end of crtc_enable, then
3472 * the HW state readout code will complain that the expected
3473 * IPS_CTL value is not the one we read. */
3474 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3475 DRM_ERROR("Timed out waiting for IPS enable\n");
3476 }
3477 }
3478
3479 void hsw_disable_ips(struct intel_crtc *crtc)
3480 {
3481 struct drm_device *dev = crtc->base.dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483
3484 if (!crtc->config.ips_enabled)
3485 return;
3486
3487 assert_plane_enabled(dev_priv, crtc->plane);
3488 if (IS_BROADWELL(crtc->base.dev)) {
3489 mutex_lock(&dev_priv->rps.hw_lock);
3490 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3491 mutex_unlock(&dev_priv->rps.hw_lock);
3492 } else {
3493 I915_WRITE(IPS_CTL, 0);
3494 POSTING_READ(IPS_CTL);
3495 }
3496
3497 /* We need to wait for a vblank before we can disable the plane. */
3498 intel_wait_for_vblank(dev, crtc->pipe);
3499 }
3500
3501 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3502 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3503 {
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507 enum pipe pipe = intel_crtc->pipe;
3508 int palreg = PALETTE(pipe);
3509 int i;
3510 bool reenable_ips = false;
3511
3512 /* The clocks have to be on to load the palette. */
3513 if (!crtc->enabled || !intel_crtc->active)
3514 return;
3515
3516 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3517 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3518 assert_dsi_pll_enabled(dev_priv);
3519 else
3520 assert_pll_enabled(dev_priv, pipe);
3521 }
3522
3523 /* use legacy palette for Ironlake */
3524 if (HAS_PCH_SPLIT(dev))
3525 palreg = LGC_PALETTE(pipe);
3526
3527 /* Workaround : Do not read or write the pipe palette/gamma data while
3528 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3529 */
3530 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3531 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3532 GAMMA_MODE_MODE_SPLIT)) {
3533 hsw_disable_ips(intel_crtc);
3534 reenable_ips = true;
3535 }
3536
3537 for (i = 0; i < 256; i++) {
3538 I915_WRITE(palreg + 4 * i,
3539 (intel_crtc->lut_r[i] << 16) |
3540 (intel_crtc->lut_g[i] << 8) |
3541 intel_crtc->lut_b[i]);
3542 }
3543
3544 if (reenable_ips)
3545 hsw_enable_ips(intel_crtc);
3546 }
3547
3548 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3549 {
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 struct intel_encoder *encoder;
3554 int pipe = intel_crtc->pipe;
3555 int plane = intel_crtc->plane;
3556
3557 WARN_ON(!crtc->enabled);
3558
3559 if (intel_crtc->active)
3560 return;
3561
3562 intel_crtc->active = true;
3563
3564 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3565 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3566
3567 for_each_encoder_on_crtc(dev, crtc, encoder)
3568 if (encoder->pre_enable)
3569 encoder->pre_enable(encoder);
3570
3571 if (intel_crtc->config.has_pch_encoder) {
3572 /* Note: FDI PLL enabling _must_ be done before we enable the
3573 * cpu pipes, hence this is separate from all the other fdi/pch
3574 * enabling. */
3575 ironlake_fdi_pll_enable(intel_crtc);
3576 } else {
3577 assert_fdi_tx_disabled(dev_priv, pipe);
3578 assert_fdi_rx_disabled(dev_priv, pipe);
3579 }
3580
3581 ironlake_pfit_enable(intel_crtc);
3582
3583 /*
3584 * On ILK+ LUT must be loaded before the pipe is running but with
3585 * clocks enabled
3586 */
3587 intel_crtc_load_lut(crtc);
3588
3589 intel_update_watermarks(crtc);
3590 intel_enable_pipe(dev_priv, pipe,
3591 intel_crtc->config.has_pch_encoder, false);
3592 intel_enable_primary_plane(dev_priv, plane, pipe);
3593 intel_enable_planes(crtc);
3594 intel_crtc_update_cursor(crtc, true);
3595
3596 if (intel_crtc->config.has_pch_encoder)
3597 ironlake_pch_enable(crtc);
3598
3599 mutex_lock(&dev->struct_mutex);
3600 intel_update_fbc(dev);
3601 mutex_unlock(&dev->struct_mutex);
3602
3603 for_each_encoder_on_crtc(dev, crtc, encoder)
3604 encoder->enable(encoder);
3605
3606 if (HAS_PCH_CPT(dev))
3607 cpt_verify_modeset(dev, intel_crtc->pipe);
3608
3609 /*
3610 * There seems to be a race in PCH platform hw (at least on some
3611 * outputs) where an enabled pipe still completes any pageflip right
3612 * away (as if the pipe is off) instead of waiting for vblank. As soon
3613 * as the first vblank happend, everything works as expected. Hence just
3614 * wait for one vblank before returning to avoid strange things
3615 * happening.
3616 */
3617 intel_wait_for_vblank(dev, intel_crtc->pipe);
3618 }
3619
3620 /* IPS only exists on ULT machines and is tied to pipe A. */
3621 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3622 {
3623 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3624 }
3625
3626 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3627 {
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 int pipe = intel_crtc->pipe;
3632 int plane = intel_crtc->plane;
3633
3634 intel_enable_primary_plane(dev_priv, plane, pipe);
3635 intel_enable_planes(crtc);
3636 intel_crtc_update_cursor(crtc, true);
3637
3638 hsw_enable_ips(intel_crtc);
3639
3640 mutex_lock(&dev->struct_mutex);
3641 intel_update_fbc(dev);
3642 mutex_unlock(&dev->struct_mutex);
3643 }
3644
3645 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3646 {
3647 struct drm_device *dev = crtc->dev;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650 int pipe = intel_crtc->pipe;
3651 int plane = intel_crtc->plane;
3652
3653 intel_crtc_wait_for_pending_flips(crtc);
3654 drm_vblank_off(dev, pipe);
3655
3656 /* FBC must be disabled before disabling the plane on HSW. */
3657 if (dev_priv->fbc.plane == plane)
3658 intel_disable_fbc(dev);
3659
3660 hsw_disable_ips(intel_crtc);
3661
3662 intel_crtc_update_cursor(crtc, false);
3663 intel_disable_planes(crtc);
3664 intel_disable_primary_plane(dev_priv, plane, pipe);
3665 }
3666
3667 /*
3668 * This implements the workaround described in the "notes" section of the mode
3669 * set sequence documentation. When going from no pipes or single pipe to
3670 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3671 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3672 */
3673 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3674 {
3675 struct drm_device *dev = crtc->base.dev;
3676 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3677
3678 /* We want to get the other_active_crtc only if there's only 1 other
3679 * active crtc. */
3680 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3681 if (!crtc_it->active || crtc_it == crtc)
3682 continue;
3683
3684 if (other_active_crtc)
3685 return;
3686
3687 other_active_crtc = crtc_it;
3688 }
3689 if (!other_active_crtc)
3690 return;
3691
3692 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3693 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3694 }
3695
3696 static void haswell_crtc_enable(struct drm_crtc *crtc)
3697 {
3698 struct drm_device *dev = crtc->dev;
3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701 struct intel_encoder *encoder;
3702 int pipe = intel_crtc->pipe;
3703
3704 WARN_ON(!crtc->enabled);
3705
3706 if (intel_crtc->active)
3707 return;
3708
3709 intel_crtc->active = true;
3710
3711 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3712 if (intel_crtc->config.has_pch_encoder)
3713 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3714
3715 if (intel_crtc->config.has_pch_encoder)
3716 dev_priv->display.fdi_link_train(crtc);
3717
3718 for_each_encoder_on_crtc(dev, crtc, encoder)
3719 if (encoder->pre_enable)
3720 encoder->pre_enable(encoder);
3721
3722 intel_ddi_enable_pipe_clock(intel_crtc);
3723
3724 ironlake_pfit_enable(intel_crtc);
3725
3726 /*
3727 * On ILK+ LUT must be loaded before the pipe is running but with
3728 * clocks enabled
3729 */
3730 intel_crtc_load_lut(crtc);
3731
3732 intel_ddi_set_pipe_settings(crtc);
3733 intel_ddi_enable_transcoder_func(crtc);
3734
3735 intel_update_watermarks(crtc);
3736 intel_enable_pipe(dev_priv, pipe,
3737 intel_crtc->config.has_pch_encoder, false);
3738
3739 if (intel_crtc->config.has_pch_encoder)
3740 lpt_pch_enable(crtc);
3741
3742 for_each_encoder_on_crtc(dev, crtc, encoder) {
3743 encoder->enable(encoder);
3744 intel_opregion_notify_encoder(encoder, true);
3745 }
3746
3747 /* If we change the relative order between pipe/planes enabling, we need
3748 * to change the workaround. */
3749 haswell_mode_set_planes_workaround(intel_crtc);
3750 haswell_crtc_enable_planes(crtc);
3751
3752 /*
3753 * There seems to be a race in PCH platform hw (at least on some
3754 * outputs) where an enabled pipe still completes any pageflip right
3755 * away (as if the pipe is off) instead of waiting for vblank. As soon
3756 * as the first vblank happend, everything works as expected. Hence just
3757 * wait for one vblank before returning to avoid strange things
3758 * happening.
3759 */
3760 intel_wait_for_vblank(dev, intel_crtc->pipe);
3761 }
3762
3763 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3764 {
3765 struct drm_device *dev = crtc->base.dev;
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 int pipe = crtc->pipe;
3768
3769 /* To avoid upsetting the power well on haswell only disable the pfit if
3770 * it's in use. The hw state code will make sure we get this right. */
3771 if (crtc->config.pch_pfit.enabled) {
3772 I915_WRITE(PF_CTL(pipe), 0);
3773 I915_WRITE(PF_WIN_POS(pipe), 0);
3774 I915_WRITE(PF_WIN_SZ(pipe), 0);
3775 }
3776 }
3777
3778 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3779 {
3780 struct drm_device *dev = crtc->dev;
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783 struct intel_encoder *encoder;
3784 int pipe = intel_crtc->pipe;
3785 int plane = intel_crtc->plane;
3786 u32 reg, temp;
3787
3788
3789 if (!intel_crtc->active)
3790 return;
3791
3792 for_each_encoder_on_crtc(dev, crtc, encoder)
3793 encoder->disable(encoder);
3794
3795 intel_crtc_wait_for_pending_flips(crtc);
3796 drm_vblank_off(dev, pipe);
3797
3798 if (dev_priv->fbc.plane == plane)
3799 intel_disable_fbc(dev);
3800
3801 intel_crtc_update_cursor(crtc, false);
3802 intel_disable_planes(crtc);
3803 intel_disable_primary_plane(dev_priv, plane, pipe);
3804
3805 if (intel_crtc->config.has_pch_encoder)
3806 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3807
3808 intel_disable_pipe(dev_priv, pipe);
3809
3810 ironlake_pfit_disable(intel_crtc);
3811
3812 for_each_encoder_on_crtc(dev, crtc, encoder)
3813 if (encoder->post_disable)
3814 encoder->post_disable(encoder);
3815
3816 if (intel_crtc->config.has_pch_encoder) {
3817 ironlake_fdi_disable(crtc);
3818
3819 ironlake_disable_pch_transcoder(dev_priv, pipe);
3820 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3821
3822 if (HAS_PCH_CPT(dev)) {
3823 /* disable TRANS_DP_CTL */
3824 reg = TRANS_DP_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3827 TRANS_DP_PORT_SEL_MASK);
3828 temp |= TRANS_DP_PORT_SEL_NONE;
3829 I915_WRITE(reg, temp);
3830
3831 /* disable DPLL_SEL */
3832 temp = I915_READ(PCH_DPLL_SEL);
3833 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3834 I915_WRITE(PCH_DPLL_SEL, temp);
3835 }
3836
3837 /* disable PCH DPLL */
3838 intel_disable_shared_dpll(intel_crtc);
3839
3840 ironlake_fdi_pll_disable(intel_crtc);
3841 }
3842
3843 intel_crtc->active = false;
3844 intel_update_watermarks(crtc);
3845
3846 mutex_lock(&dev->struct_mutex);
3847 intel_update_fbc(dev);
3848 mutex_unlock(&dev->struct_mutex);
3849 }
3850
3851 static void haswell_crtc_disable(struct drm_crtc *crtc)
3852 {
3853 struct drm_device *dev = crtc->dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856 struct intel_encoder *encoder;
3857 int pipe = intel_crtc->pipe;
3858 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3859
3860 if (!intel_crtc->active)
3861 return;
3862
3863 haswell_crtc_disable_planes(crtc);
3864
3865 for_each_encoder_on_crtc(dev, crtc, encoder) {
3866 intel_opregion_notify_encoder(encoder, false);
3867 encoder->disable(encoder);
3868 }
3869
3870 if (intel_crtc->config.has_pch_encoder)
3871 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3872 intel_disable_pipe(dev_priv, pipe);
3873
3874 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3875
3876 ironlake_pfit_disable(intel_crtc);
3877
3878 intel_ddi_disable_pipe_clock(intel_crtc);
3879
3880 for_each_encoder_on_crtc(dev, crtc, encoder)
3881 if (encoder->post_disable)
3882 encoder->post_disable(encoder);
3883
3884 if (intel_crtc->config.has_pch_encoder) {
3885 lpt_disable_pch_transcoder(dev_priv);
3886 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3887 intel_ddi_fdi_disable(crtc);
3888 }
3889
3890 intel_crtc->active = false;
3891 intel_update_watermarks(crtc);
3892
3893 mutex_lock(&dev->struct_mutex);
3894 intel_update_fbc(dev);
3895 mutex_unlock(&dev->struct_mutex);
3896 }
3897
3898 static void ironlake_crtc_off(struct drm_crtc *crtc)
3899 {
3900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3901 intel_put_shared_dpll(intel_crtc);
3902 }
3903
3904 static void haswell_crtc_off(struct drm_crtc *crtc)
3905 {
3906 intel_ddi_put_crtc_pll(crtc);
3907 }
3908
3909 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3910 {
3911 if (!enable && intel_crtc->overlay) {
3912 struct drm_device *dev = intel_crtc->base.dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914
3915 mutex_lock(&dev->struct_mutex);
3916 dev_priv->mm.interruptible = false;
3917 (void) intel_overlay_switch_off(intel_crtc->overlay);
3918 dev_priv->mm.interruptible = true;
3919 mutex_unlock(&dev->struct_mutex);
3920 }
3921
3922 /* Let userspace switch the overlay on again. In most cases userspace
3923 * has to recompute where to put it anyway.
3924 */
3925 }
3926
3927 /**
3928 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3929 * cursor plane briefly if not already running after enabling the display
3930 * plane.
3931 * This workaround avoids occasional blank screens when self refresh is
3932 * enabled.
3933 */
3934 static void
3935 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3936 {
3937 u32 cntl = I915_READ(CURCNTR(pipe));
3938
3939 if ((cntl & CURSOR_MODE) == 0) {
3940 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3941
3942 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3943 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3944 intel_wait_for_vblank(dev_priv->dev, pipe);
3945 I915_WRITE(CURCNTR(pipe), cntl);
3946 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3947 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3948 }
3949 }
3950
3951 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3952 {
3953 struct drm_device *dev = crtc->base.dev;
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955 struct intel_crtc_config *pipe_config = &crtc->config;
3956
3957 if (!crtc->config.gmch_pfit.control)
3958 return;
3959
3960 /*
3961 * The panel fitter should only be adjusted whilst the pipe is disabled,
3962 * according to register description and PRM.
3963 */
3964 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3965 assert_pipe_disabled(dev_priv, crtc->pipe);
3966
3967 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3968 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3969
3970 /* Border color in case we don't scale up to the full screen. Black by
3971 * default, change to something else for debugging. */
3972 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3973 }
3974
3975 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3976 {
3977 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3978
3979 /* Obtain SKU information */
3980 mutex_lock(&dev_priv->dpio_lock);
3981 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3982 CCK_FUSE_HPLL_FREQ_MASK;
3983 mutex_unlock(&dev_priv->dpio_lock);
3984
3985 return vco_freq[hpll_freq];
3986 }
3987
3988 /* Adjust CDclk dividers to allow high res or save power if possible */
3989 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3990 {
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 u32 val, cmd;
3993
3994 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3995 cmd = 2;
3996 else if (cdclk == 266)
3997 cmd = 1;
3998 else
3999 cmd = 0;
4000
4001 mutex_lock(&dev_priv->rps.hw_lock);
4002 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4003 val &= ~DSPFREQGUAR_MASK;
4004 val |= (cmd << DSPFREQGUAR_SHIFT);
4005 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4006 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4007 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4008 50)) {
4009 DRM_ERROR("timed out waiting for CDclk change\n");
4010 }
4011 mutex_unlock(&dev_priv->rps.hw_lock);
4012
4013 if (cdclk == 400) {
4014 u32 divider, vco;
4015
4016 vco = valleyview_get_vco(dev_priv);
4017 divider = ((vco << 1) / cdclk) - 1;
4018
4019 mutex_lock(&dev_priv->dpio_lock);
4020 /* adjust cdclk divider */
4021 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4022 val &= ~0xf;
4023 val |= divider;
4024 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4025 mutex_unlock(&dev_priv->dpio_lock);
4026 }
4027
4028 mutex_lock(&dev_priv->dpio_lock);
4029 /* adjust self-refresh exit latency value */
4030 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4031 val &= ~0x7f;
4032
4033 /*
4034 * For high bandwidth configs, we set a higher latency in the bunit
4035 * so that the core display fetch happens in time to avoid underruns.
4036 */
4037 if (cdclk == 400)
4038 val |= 4500 / 250; /* 4.5 usec */
4039 else
4040 val |= 3000 / 250; /* 3.0 usec */
4041 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4042 mutex_unlock(&dev_priv->dpio_lock);
4043
4044 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4045 intel_i2c_reset(dev);
4046 }
4047
4048 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4049 {
4050 int cur_cdclk, vco;
4051 int divider;
4052
4053 vco = valleyview_get_vco(dev_priv);
4054
4055 mutex_lock(&dev_priv->dpio_lock);
4056 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4057 mutex_unlock(&dev_priv->dpio_lock);
4058
4059 divider &= 0xf;
4060
4061 cur_cdclk = (vco << 1) / (divider + 1);
4062
4063 return cur_cdclk;
4064 }
4065
4066 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4067 int max_pixclk)
4068 {
4069 int cur_cdclk;
4070
4071 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4072
4073 /*
4074 * Really only a few cases to deal with, as only 4 CDclks are supported:
4075 * 200MHz
4076 * 267MHz
4077 * 320MHz
4078 * 400MHz
4079 * So we check to see whether we're above 90% of the lower bin and
4080 * adjust if needed.
4081 */
4082 if (max_pixclk > 288000) {
4083 return 400;
4084 } else if (max_pixclk > 240000) {
4085 return 320;
4086 } else
4087 return 266;
4088 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4089 }
4090
4091 /* compute the max pixel clock for new configuration */
4092 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4093 {
4094 struct drm_device *dev = dev_priv->dev;
4095 struct intel_crtc *intel_crtc;
4096 int max_pixclk = 0;
4097
4098 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4099 base.head) {
4100 if (intel_crtc->new_enabled)
4101 max_pixclk = max(max_pixclk,
4102 intel_crtc->new_config->adjusted_mode.crtc_clock);
4103 }
4104
4105 return max_pixclk;
4106 }
4107
4108 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4109 unsigned *prepare_pipes)
4110 {
4111 struct drm_i915_private *dev_priv = dev->dev_private;
4112 struct intel_crtc *intel_crtc;
4113 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4114 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4115
4116 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4117 return;
4118
4119 /* disable/enable all currently active pipes while we change cdclk */
4120 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4121 base.head)
4122 if (intel_crtc->base.enabled)
4123 *prepare_pipes |= (1 << intel_crtc->pipe);
4124 }
4125
4126 static void valleyview_modeset_global_resources(struct drm_device *dev)
4127 {
4128 struct drm_i915_private *dev_priv = dev->dev_private;
4129 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4130 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4131 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4132
4133 if (req_cdclk != cur_cdclk)
4134 valleyview_set_cdclk(dev, req_cdclk);
4135 }
4136
4137 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4138 {
4139 struct drm_device *dev = crtc->dev;
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4142 struct intel_encoder *encoder;
4143 int pipe = intel_crtc->pipe;
4144 int plane = intel_crtc->plane;
4145 bool is_dsi;
4146
4147 WARN_ON(!crtc->enabled);
4148
4149 if (intel_crtc->active)
4150 return;
4151
4152 intel_crtc->active = true;
4153
4154 for_each_encoder_on_crtc(dev, crtc, encoder)
4155 if (encoder->pre_pll_enable)
4156 encoder->pre_pll_enable(encoder);
4157
4158 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4159
4160 if (!is_dsi)
4161 vlv_enable_pll(intel_crtc);
4162
4163 for_each_encoder_on_crtc(dev, crtc, encoder)
4164 if (encoder->pre_enable)
4165 encoder->pre_enable(encoder);
4166
4167 i9xx_pfit_enable(intel_crtc);
4168
4169 intel_crtc_load_lut(crtc);
4170
4171 intel_update_watermarks(crtc);
4172 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4173 intel_enable_primary_plane(dev_priv, plane, pipe);
4174 intel_enable_planes(crtc);
4175 intel_crtc_update_cursor(crtc, true);
4176
4177 intel_update_fbc(dev);
4178
4179 for_each_encoder_on_crtc(dev, crtc, encoder)
4180 encoder->enable(encoder);
4181 }
4182
4183 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4184 {
4185 struct drm_device *dev = crtc->dev;
4186 struct drm_i915_private *dev_priv = dev->dev_private;
4187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4188 struct intel_encoder *encoder;
4189 int pipe = intel_crtc->pipe;
4190 int plane = intel_crtc->plane;
4191
4192 WARN_ON(!crtc->enabled);
4193
4194 if (intel_crtc->active)
4195 return;
4196
4197 intel_crtc->active = true;
4198
4199 for_each_encoder_on_crtc(dev, crtc, encoder)
4200 if (encoder->pre_enable)
4201 encoder->pre_enable(encoder);
4202
4203 i9xx_enable_pll(intel_crtc);
4204
4205 i9xx_pfit_enable(intel_crtc);
4206
4207 intel_crtc_load_lut(crtc);
4208
4209 intel_update_watermarks(crtc);
4210 intel_enable_pipe(dev_priv, pipe, false, false);
4211 intel_enable_primary_plane(dev_priv, plane, pipe);
4212 intel_enable_planes(crtc);
4213 /* The fixup needs to happen before cursor is enabled */
4214 if (IS_G4X(dev))
4215 g4x_fixup_plane(dev_priv, pipe);
4216 intel_crtc_update_cursor(crtc, true);
4217
4218 /* Give the overlay scaler a chance to enable if it's on this pipe */
4219 intel_crtc_dpms_overlay(intel_crtc, true);
4220
4221 intel_update_fbc(dev);
4222
4223 for_each_encoder_on_crtc(dev, crtc, encoder)
4224 encoder->enable(encoder);
4225 }
4226
4227 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4228 {
4229 struct drm_device *dev = crtc->base.dev;
4230 struct drm_i915_private *dev_priv = dev->dev_private;
4231
4232 if (!crtc->config.gmch_pfit.control)
4233 return;
4234
4235 assert_pipe_disabled(dev_priv, crtc->pipe);
4236
4237 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4238 I915_READ(PFIT_CONTROL));
4239 I915_WRITE(PFIT_CONTROL, 0);
4240 }
4241
4242 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4243 {
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4247 struct intel_encoder *encoder;
4248 int pipe = intel_crtc->pipe;
4249 int plane = intel_crtc->plane;
4250
4251 if (!intel_crtc->active)
4252 return;
4253
4254 for_each_encoder_on_crtc(dev, crtc, encoder)
4255 encoder->disable(encoder);
4256
4257 /* Give the overlay scaler a chance to disable if it's on this pipe */
4258 intel_crtc_wait_for_pending_flips(crtc);
4259 drm_vblank_off(dev, pipe);
4260
4261 if (dev_priv->fbc.plane == plane)
4262 intel_disable_fbc(dev);
4263
4264 intel_crtc_dpms_overlay(intel_crtc, false);
4265 intel_crtc_update_cursor(crtc, false);
4266 intel_disable_planes(crtc);
4267 intel_disable_primary_plane(dev_priv, plane, pipe);
4268
4269 intel_disable_pipe(dev_priv, pipe);
4270
4271 i9xx_pfit_disable(intel_crtc);
4272
4273 for_each_encoder_on_crtc(dev, crtc, encoder)
4274 if (encoder->post_disable)
4275 encoder->post_disable(encoder);
4276
4277 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4278 vlv_disable_pll(dev_priv, pipe);
4279 else if (!IS_VALLEYVIEW(dev))
4280 i9xx_disable_pll(dev_priv, pipe);
4281
4282 intel_crtc->active = false;
4283 intel_update_watermarks(crtc);
4284
4285 intel_update_fbc(dev);
4286 }
4287
4288 static void i9xx_crtc_off(struct drm_crtc *crtc)
4289 {
4290 }
4291
4292 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4293 bool enabled)
4294 {
4295 struct drm_device *dev = crtc->dev;
4296 struct drm_i915_master_private *master_priv;
4297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4298 int pipe = intel_crtc->pipe;
4299
4300 if (!dev->primary->master)
4301 return;
4302
4303 master_priv = dev->primary->master->driver_priv;
4304 if (!master_priv->sarea_priv)
4305 return;
4306
4307 switch (pipe) {
4308 case 0:
4309 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4310 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4311 break;
4312 case 1:
4313 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4314 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4315 break;
4316 default:
4317 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4318 break;
4319 }
4320 }
4321
4322 /**
4323 * Sets the power management mode of the pipe and plane.
4324 */
4325 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4326 {
4327 struct drm_device *dev = crtc->dev;
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4329 struct intel_encoder *intel_encoder;
4330 bool enable = false;
4331
4332 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4333 enable |= intel_encoder->connectors_active;
4334
4335 if (enable)
4336 dev_priv->display.crtc_enable(crtc);
4337 else
4338 dev_priv->display.crtc_disable(crtc);
4339
4340 intel_crtc_update_sarea(crtc, enable);
4341 }
4342
4343 static void intel_crtc_disable(struct drm_crtc *crtc)
4344 {
4345 struct drm_device *dev = crtc->dev;
4346 struct drm_connector *connector;
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4349
4350 /* crtc should still be enabled when we disable it. */
4351 WARN_ON(!crtc->enabled);
4352
4353 dev_priv->display.crtc_disable(crtc);
4354 intel_crtc->eld_vld = false;
4355 intel_crtc_update_sarea(crtc, false);
4356 dev_priv->display.off(crtc);
4357
4358 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4359 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4360 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4361
4362 if (crtc->fb) {
4363 mutex_lock(&dev->struct_mutex);
4364 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4365 mutex_unlock(&dev->struct_mutex);
4366 crtc->fb = NULL;
4367 }
4368
4369 /* Update computed state. */
4370 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4371 if (!connector->encoder || !connector->encoder->crtc)
4372 continue;
4373
4374 if (connector->encoder->crtc != crtc)
4375 continue;
4376
4377 connector->dpms = DRM_MODE_DPMS_OFF;
4378 to_intel_encoder(connector->encoder)->connectors_active = false;
4379 }
4380 }
4381
4382 void intel_encoder_destroy(struct drm_encoder *encoder)
4383 {
4384 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4385
4386 drm_encoder_cleanup(encoder);
4387 kfree(intel_encoder);
4388 }
4389
4390 /* Simple dpms helper for encoders with just one connector, no cloning and only
4391 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4392 * state of the entire output pipe. */
4393 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4394 {
4395 if (mode == DRM_MODE_DPMS_ON) {
4396 encoder->connectors_active = true;
4397
4398 intel_crtc_update_dpms(encoder->base.crtc);
4399 } else {
4400 encoder->connectors_active = false;
4401
4402 intel_crtc_update_dpms(encoder->base.crtc);
4403 }
4404 }
4405
4406 /* Cross check the actual hw state with our own modeset state tracking (and it's
4407 * internal consistency). */
4408 static void intel_connector_check_state(struct intel_connector *connector)
4409 {
4410 if (connector->get_hw_state(connector)) {
4411 struct intel_encoder *encoder = connector->encoder;
4412 struct drm_crtc *crtc;
4413 bool encoder_enabled;
4414 enum pipe pipe;
4415
4416 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4417 connector->base.base.id,
4418 drm_get_connector_name(&connector->base));
4419
4420 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4421 "wrong connector dpms state\n");
4422 WARN(connector->base.encoder != &encoder->base,
4423 "active connector not linked to encoder\n");
4424 WARN(!encoder->connectors_active,
4425 "encoder->connectors_active not set\n");
4426
4427 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4428 WARN(!encoder_enabled, "encoder not enabled\n");
4429 if (WARN_ON(!encoder->base.crtc))
4430 return;
4431
4432 crtc = encoder->base.crtc;
4433
4434 WARN(!crtc->enabled, "crtc not enabled\n");
4435 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4436 WARN(pipe != to_intel_crtc(crtc)->pipe,
4437 "encoder active on the wrong pipe\n");
4438 }
4439 }
4440
4441 /* Even simpler default implementation, if there's really no special case to
4442 * consider. */
4443 void intel_connector_dpms(struct drm_connector *connector, int mode)
4444 {
4445 /* All the simple cases only support two dpms states. */
4446 if (mode != DRM_MODE_DPMS_ON)
4447 mode = DRM_MODE_DPMS_OFF;
4448
4449 if (mode == connector->dpms)
4450 return;
4451
4452 connector->dpms = mode;
4453
4454 /* Only need to change hw state when actually enabled */
4455 if (connector->encoder)
4456 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4457
4458 intel_modeset_check_state(connector->dev);
4459 }
4460
4461 /* Simple connector->get_hw_state implementation for encoders that support only
4462 * one connector and no cloning and hence the encoder state determines the state
4463 * of the connector. */
4464 bool intel_connector_get_hw_state(struct intel_connector *connector)
4465 {
4466 enum pipe pipe = 0;
4467 struct intel_encoder *encoder = connector->encoder;
4468
4469 return encoder->get_hw_state(encoder, &pipe);
4470 }
4471
4472 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4473 struct intel_crtc_config *pipe_config)
4474 {
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 struct intel_crtc *pipe_B_crtc =
4477 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4478
4479 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4480 pipe_name(pipe), pipe_config->fdi_lanes);
4481 if (pipe_config->fdi_lanes > 4) {
4482 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4483 pipe_name(pipe), pipe_config->fdi_lanes);
4484 return false;
4485 }
4486
4487 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4488 if (pipe_config->fdi_lanes > 2) {
4489 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4490 pipe_config->fdi_lanes);
4491 return false;
4492 } else {
4493 return true;
4494 }
4495 }
4496
4497 if (INTEL_INFO(dev)->num_pipes == 2)
4498 return true;
4499
4500 /* Ivybridge 3 pipe is really complicated */
4501 switch (pipe) {
4502 case PIPE_A:
4503 return true;
4504 case PIPE_B:
4505 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4506 pipe_config->fdi_lanes > 2) {
4507 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4508 pipe_name(pipe), pipe_config->fdi_lanes);
4509 return false;
4510 }
4511 return true;
4512 case PIPE_C:
4513 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4514 pipe_B_crtc->config.fdi_lanes <= 2) {
4515 if (pipe_config->fdi_lanes > 2) {
4516 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4517 pipe_name(pipe), pipe_config->fdi_lanes);
4518 return false;
4519 }
4520 } else {
4521 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4522 return false;
4523 }
4524 return true;
4525 default:
4526 BUG();
4527 }
4528 }
4529
4530 #define RETRY 1
4531 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4532 struct intel_crtc_config *pipe_config)
4533 {
4534 struct drm_device *dev = intel_crtc->base.dev;
4535 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4536 int lane, link_bw, fdi_dotclock;
4537 bool setup_ok, needs_recompute = false;
4538
4539 retry:
4540 /* FDI is a binary signal running at ~2.7GHz, encoding
4541 * each output octet as 10 bits. The actual frequency
4542 * is stored as a divider into a 100MHz clock, and the
4543 * mode pixel clock is stored in units of 1KHz.
4544 * Hence the bw of each lane in terms of the mode signal
4545 * is:
4546 */
4547 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4548
4549 fdi_dotclock = adjusted_mode->crtc_clock;
4550
4551 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4552 pipe_config->pipe_bpp);
4553
4554 pipe_config->fdi_lanes = lane;
4555
4556 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4557 link_bw, &pipe_config->fdi_m_n);
4558
4559 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4560 intel_crtc->pipe, pipe_config);
4561 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4562 pipe_config->pipe_bpp -= 2*3;
4563 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4564 pipe_config->pipe_bpp);
4565 needs_recompute = true;
4566 pipe_config->bw_constrained = true;
4567
4568 goto retry;
4569 }
4570
4571 if (needs_recompute)
4572 return RETRY;
4573
4574 return setup_ok ? 0 : -EINVAL;
4575 }
4576
4577 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4578 struct intel_crtc_config *pipe_config)
4579 {
4580 pipe_config->ips_enabled = i915_enable_ips &&
4581 hsw_crtc_supports_ips(crtc) &&
4582 pipe_config->pipe_bpp <= 24;
4583 }
4584
4585 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4586 struct intel_crtc_config *pipe_config)
4587 {
4588 struct drm_device *dev = crtc->base.dev;
4589 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4590
4591 /* FIXME should check pixel clock limits on all platforms */
4592 if (INTEL_INFO(dev)->gen < 4) {
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 int clock_limit =
4595 dev_priv->display.get_display_clock_speed(dev);
4596
4597 /*
4598 * Enable pixel doubling when the dot clock
4599 * is > 90% of the (display) core speed.
4600 *
4601 * GDG double wide on either pipe,
4602 * otherwise pipe A only.
4603 */
4604 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4605 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4606 clock_limit *= 2;
4607 pipe_config->double_wide = true;
4608 }
4609
4610 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4611 return -EINVAL;
4612 }
4613
4614 /*
4615 * Pipe horizontal size must be even in:
4616 * - DVO ganged mode
4617 * - LVDS dual channel mode
4618 * - Double wide pipe
4619 */
4620 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4621 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4622 pipe_config->pipe_src_w &= ~1;
4623
4624 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4625 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4626 */
4627 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4628 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4629 return -EINVAL;
4630
4631 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4632 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4633 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4634 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4635 * for lvds. */
4636 pipe_config->pipe_bpp = 8*3;
4637 }
4638
4639 if (HAS_IPS(dev))
4640 hsw_compute_ips_config(crtc, pipe_config);
4641
4642 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4643 * clock survives for now. */
4644 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4645 pipe_config->shared_dpll = crtc->config.shared_dpll;
4646
4647 if (pipe_config->has_pch_encoder)
4648 return ironlake_fdi_compute_config(crtc, pipe_config);
4649
4650 return 0;
4651 }
4652
4653 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4654 {
4655 return 400000; /* FIXME */
4656 }
4657
4658 static int i945_get_display_clock_speed(struct drm_device *dev)
4659 {
4660 return 400000;
4661 }
4662
4663 static int i915_get_display_clock_speed(struct drm_device *dev)
4664 {
4665 return 333000;
4666 }
4667
4668 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4669 {
4670 return 200000;
4671 }
4672
4673 static int pnv_get_display_clock_speed(struct drm_device *dev)
4674 {
4675 u16 gcfgc = 0;
4676
4677 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4678
4679 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4680 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4681 return 267000;
4682 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4683 return 333000;
4684 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4685 return 444000;
4686 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4687 return 200000;
4688 default:
4689 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4690 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4691 return 133000;
4692 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4693 return 167000;
4694 }
4695 }
4696
4697 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4698 {
4699 u16 gcfgc = 0;
4700
4701 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4702
4703 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4704 return 133000;
4705 else {
4706 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4707 case GC_DISPLAY_CLOCK_333_MHZ:
4708 return 333000;
4709 default:
4710 case GC_DISPLAY_CLOCK_190_200_MHZ:
4711 return 190000;
4712 }
4713 }
4714 }
4715
4716 static int i865_get_display_clock_speed(struct drm_device *dev)
4717 {
4718 return 266000;
4719 }
4720
4721 static int i855_get_display_clock_speed(struct drm_device *dev)
4722 {
4723 u16 hpllcc = 0;
4724 /* Assume that the hardware is in the high speed state. This
4725 * should be the default.
4726 */
4727 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4728 case GC_CLOCK_133_200:
4729 case GC_CLOCK_100_200:
4730 return 200000;
4731 case GC_CLOCK_166_250:
4732 return 250000;
4733 case GC_CLOCK_100_133:
4734 return 133000;
4735 }
4736
4737 /* Shouldn't happen */
4738 return 0;
4739 }
4740
4741 static int i830_get_display_clock_speed(struct drm_device *dev)
4742 {
4743 return 133000;
4744 }
4745
4746 static void
4747 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4748 {
4749 while (*num > DATA_LINK_M_N_MASK ||
4750 *den > DATA_LINK_M_N_MASK) {
4751 *num >>= 1;
4752 *den >>= 1;
4753 }
4754 }
4755
4756 static void compute_m_n(unsigned int m, unsigned int n,
4757 uint32_t *ret_m, uint32_t *ret_n)
4758 {
4759 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4760 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4761 intel_reduce_m_n_ratio(ret_m, ret_n);
4762 }
4763
4764 void
4765 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4766 int pixel_clock, int link_clock,
4767 struct intel_link_m_n *m_n)
4768 {
4769 m_n->tu = 64;
4770
4771 compute_m_n(bits_per_pixel * pixel_clock,
4772 link_clock * nlanes * 8,
4773 &m_n->gmch_m, &m_n->gmch_n);
4774
4775 compute_m_n(pixel_clock, link_clock,
4776 &m_n->link_m, &m_n->link_n);
4777 }
4778
4779 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4780 {
4781 if (i915_panel_use_ssc >= 0)
4782 return i915_panel_use_ssc != 0;
4783 return dev_priv->vbt.lvds_use_ssc
4784 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4785 }
4786
4787 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4788 {
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 int refclk;
4792
4793 if (IS_VALLEYVIEW(dev)) {
4794 refclk = 100000;
4795 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4796 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4797 refclk = dev_priv->vbt.lvds_ssc_freq;
4798 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4799 } else if (!IS_GEN2(dev)) {
4800 refclk = 96000;
4801 } else {
4802 refclk = 48000;
4803 }
4804
4805 return refclk;
4806 }
4807
4808 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4809 {
4810 return (1 << dpll->n) << 16 | dpll->m2;
4811 }
4812
4813 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4814 {
4815 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4816 }
4817
4818 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4819 intel_clock_t *reduced_clock)
4820 {
4821 struct drm_device *dev = crtc->base.dev;
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 int pipe = crtc->pipe;
4824 u32 fp, fp2 = 0;
4825
4826 if (IS_PINEVIEW(dev)) {
4827 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4828 if (reduced_clock)
4829 fp2 = pnv_dpll_compute_fp(reduced_clock);
4830 } else {
4831 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4832 if (reduced_clock)
4833 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4834 }
4835
4836 I915_WRITE(FP0(pipe), fp);
4837 crtc->config.dpll_hw_state.fp0 = fp;
4838
4839 crtc->lowfreq_avail = false;
4840 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4841 reduced_clock && i915_powersave) {
4842 I915_WRITE(FP1(pipe), fp2);
4843 crtc->config.dpll_hw_state.fp1 = fp2;
4844 crtc->lowfreq_avail = true;
4845 } else {
4846 I915_WRITE(FP1(pipe), fp);
4847 crtc->config.dpll_hw_state.fp1 = fp;
4848 }
4849 }
4850
4851 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4852 pipe)
4853 {
4854 u32 reg_val;
4855
4856 /*
4857 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4858 * and set it to a reasonable value instead.
4859 */
4860 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4861 reg_val &= 0xffffff00;
4862 reg_val |= 0x00000030;
4863 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4864
4865 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4866 reg_val &= 0x8cffffff;
4867 reg_val = 0x8c000000;
4868 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4869
4870 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4871 reg_val &= 0xffffff00;
4872 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4873
4874 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4875 reg_val &= 0x00ffffff;
4876 reg_val |= 0xb0000000;
4877 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4878 }
4879
4880 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4881 struct intel_link_m_n *m_n)
4882 {
4883 struct drm_device *dev = crtc->base.dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 int pipe = crtc->pipe;
4886
4887 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4888 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4889 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4890 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4891 }
4892
4893 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4894 struct intel_link_m_n *m_n)
4895 {
4896 struct drm_device *dev = crtc->base.dev;
4897 struct drm_i915_private *dev_priv = dev->dev_private;
4898 int pipe = crtc->pipe;
4899 enum transcoder transcoder = crtc->config.cpu_transcoder;
4900
4901 if (INTEL_INFO(dev)->gen >= 5) {
4902 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4903 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4904 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4905 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4906 } else {
4907 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4908 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4909 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4910 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4911 }
4912 }
4913
4914 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4915 {
4916 if (crtc->config.has_pch_encoder)
4917 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4918 else
4919 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4920 }
4921
4922 static void vlv_update_pll(struct intel_crtc *crtc)
4923 {
4924 struct drm_device *dev = crtc->base.dev;
4925 struct drm_i915_private *dev_priv = dev->dev_private;
4926 int pipe = crtc->pipe;
4927 u32 dpll, mdiv;
4928 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4929 u32 coreclk, reg_val, dpll_md;
4930
4931 mutex_lock(&dev_priv->dpio_lock);
4932
4933 bestn = crtc->config.dpll.n;
4934 bestm1 = crtc->config.dpll.m1;
4935 bestm2 = crtc->config.dpll.m2;
4936 bestp1 = crtc->config.dpll.p1;
4937 bestp2 = crtc->config.dpll.p2;
4938
4939 /* See eDP HDMI DPIO driver vbios notes doc */
4940
4941 /* PLL B needs special handling */
4942 if (pipe)
4943 vlv_pllb_recal_opamp(dev_priv, pipe);
4944
4945 /* Set up Tx target for periodic Rcomp update */
4946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4947
4948 /* Disable target IRef on PLL */
4949 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4950 reg_val &= 0x00ffffff;
4951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4952
4953 /* Disable fast lock */
4954 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4955
4956 /* Set idtafcrecal before PLL is enabled */
4957 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4958 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4959 mdiv |= ((bestn << DPIO_N_SHIFT));
4960 mdiv |= (1 << DPIO_K_SHIFT);
4961
4962 /*
4963 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4964 * but we don't support that).
4965 * Note: don't use the DAC post divider as it seems unstable.
4966 */
4967 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4969
4970 mdiv |= DPIO_ENABLE_CALIBRATION;
4971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4972
4973 /* Set HBR and RBR LPF coefficients */
4974 if (crtc->config.port_clock == 162000 ||
4975 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4976 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4977 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4978 0x009f0003);
4979 else
4980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4981 0x00d0000f);
4982
4983 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4984 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4985 /* Use SSC source */
4986 if (!pipe)
4987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4988 0x0df40000);
4989 else
4990 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4991 0x0df70000);
4992 } else { /* HDMI or VGA */
4993 /* Use bend source */
4994 if (!pipe)
4995 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4996 0x0df70000);
4997 else
4998 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4999 0x0df40000);
5000 }
5001
5002 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5003 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5004 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5005 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5006 coreclk |= 0x01000000;
5007 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5008
5009 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5010
5011 /*
5012 * Enable DPIO clock input. We should never disable the reference
5013 * clock for pipe B, since VGA hotplug / manual detection depends
5014 * on it.
5015 */
5016 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5017 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5018 /* We should never disable this, set it here for state tracking */
5019 if (pipe == PIPE_B)
5020 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5021 dpll |= DPLL_VCO_ENABLE;
5022 crtc->config.dpll_hw_state.dpll = dpll;
5023
5024 dpll_md = (crtc->config.pixel_multiplier - 1)
5025 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5026 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5027
5028 if (crtc->config.has_dp_encoder)
5029 intel_dp_set_m_n(crtc);
5030
5031 mutex_unlock(&dev_priv->dpio_lock);
5032 }
5033
5034 static void i9xx_update_pll(struct intel_crtc *crtc,
5035 intel_clock_t *reduced_clock,
5036 int num_connectors)
5037 {
5038 struct drm_device *dev = crtc->base.dev;
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 u32 dpll;
5041 bool is_sdvo;
5042 struct dpll *clock = &crtc->config.dpll;
5043
5044 i9xx_update_pll_dividers(crtc, reduced_clock);
5045
5046 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5047 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5048
5049 dpll = DPLL_VGA_MODE_DIS;
5050
5051 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5052 dpll |= DPLLB_MODE_LVDS;
5053 else
5054 dpll |= DPLLB_MODE_DAC_SERIAL;
5055
5056 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5057 dpll |= (crtc->config.pixel_multiplier - 1)
5058 << SDVO_MULTIPLIER_SHIFT_HIRES;
5059 }
5060
5061 if (is_sdvo)
5062 dpll |= DPLL_SDVO_HIGH_SPEED;
5063
5064 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5065 dpll |= DPLL_SDVO_HIGH_SPEED;
5066
5067 /* compute bitmask from p1 value */
5068 if (IS_PINEVIEW(dev))
5069 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5070 else {
5071 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5072 if (IS_G4X(dev) && reduced_clock)
5073 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5074 }
5075 switch (clock->p2) {
5076 case 5:
5077 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5078 break;
5079 case 7:
5080 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5081 break;
5082 case 10:
5083 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5084 break;
5085 case 14:
5086 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5087 break;
5088 }
5089 if (INTEL_INFO(dev)->gen >= 4)
5090 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5091
5092 if (crtc->config.sdvo_tv_clock)
5093 dpll |= PLL_REF_INPUT_TVCLKINBC;
5094 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5095 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5096 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5097 else
5098 dpll |= PLL_REF_INPUT_DREFCLK;
5099
5100 dpll |= DPLL_VCO_ENABLE;
5101 crtc->config.dpll_hw_state.dpll = dpll;
5102
5103 if (INTEL_INFO(dev)->gen >= 4) {
5104 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5105 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5106 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5107 }
5108
5109 if (crtc->config.has_dp_encoder)
5110 intel_dp_set_m_n(crtc);
5111 }
5112
5113 static void i8xx_update_pll(struct intel_crtc *crtc,
5114 intel_clock_t *reduced_clock,
5115 int num_connectors)
5116 {
5117 struct drm_device *dev = crtc->base.dev;
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 u32 dpll;
5120 struct dpll *clock = &crtc->config.dpll;
5121
5122 i9xx_update_pll_dividers(crtc, reduced_clock);
5123
5124 dpll = DPLL_VGA_MODE_DIS;
5125
5126 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5127 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5128 } else {
5129 if (clock->p1 == 2)
5130 dpll |= PLL_P1_DIVIDE_BY_TWO;
5131 else
5132 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5133 if (clock->p2 == 4)
5134 dpll |= PLL_P2_DIVIDE_BY_4;
5135 }
5136
5137 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5138 dpll |= DPLL_DVO_2X_MODE;
5139
5140 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5141 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5142 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5143 else
5144 dpll |= PLL_REF_INPUT_DREFCLK;
5145
5146 dpll |= DPLL_VCO_ENABLE;
5147 crtc->config.dpll_hw_state.dpll = dpll;
5148 }
5149
5150 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5151 {
5152 struct drm_device *dev = intel_crtc->base.dev;
5153 struct drm_i915_private *dev_priv = dev->dev_private;
5154 enum pipe pipe = intel_crtc->pipe;
5155 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5156 struct drm_display_mode *adjusted_mode =
5157 &intel_crtc->config.adjusted_mode;
5158 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5159
5160 /* We need to be careful not to changed the adjusted mode, for otherwise
5161 * the hw state checker will get angry at the mismatch. */
5162 crtc_vtotal = adjusted_mode->crtc_vtotal;
5163 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5164
5165 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5166 /* the chip adds 2 halflines automatically */
5167 crtc_vtotal -= 1;
5168 crtc_vblank_end -= 1;
5169 vsyncshift = adjusted_mode->crtc_hsync_start
5170 - adjusted_mode->crtc_htotal / 2;
5171 } else {
5172 vsyncshift = 0;
5173 }
5174
5175 if (INTEL_INFO(dev)->gen > 3)
5176 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5177
5178 I915_WRITE(HTOTAL(cpu_transcoder),
5179 (adjusted_mode->crtc_hdisplay - 1) |
5180 ((adjusted_mode->crtc_htotal - 1) << 16));
5181 I915_WRITE(HBLANK(cpu_transcoder),
5182 (adjusted_mode->crtc_hblank_start - 1) |
5183 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5184 I915_WRITE(HSYNC(cpu_transcoder),
5185 (adjusted_mode->crtc_hsync_start - 1) |
5186 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5187
5188 I915_WRITE(VTOTAL(cpu_transcoder),
5189 (adjusted_mode->crtc_vdisplay - 1) |
5190 ((crtc_vtotal - 1) << 16));
5191 I915_WRITE(VBLANK(cpu_transcoder),
5192 (adjusted_mode->crtc_vblank_start - 1) |
5193 ((crtc_vblank_end - 1) << 16));
5194 I915_WRITE(VSYNC(cpu_transcoder),
5195 (adjusted_mode->crtc_vsync_start - 1) |
5196 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5197
5198 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5199 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5200 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5201 * bits. */
5202 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5203 (pipe == PIPE_B || pipe == PIPE_C))
5204 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5205
5206 /* pipesrc controls the size that is scaled from, which should
5207 * always be the user's requested size.
5208 */
5209 I915_WRITE(PIPESRC(pipe),
5210 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5211 (intel_crtc->config.pipe_src_h - 1));
5212 }
5213
5214 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5215 struct intel_crtc_config *pipe_config)
5216 {
5217 struct drm_device *dev = crtc->base.dev;
5218 struct drm_i915_private *dev_priv = dev->dev_private;
5219 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5220 uint32_t tmp;
5221
5222 tmp = I915_READ(HTOTAL(cpu_transcoder));
5223 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5224 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5225 tmp = I915_READ(HBLANK(cpu_transcoder));
5226 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5227 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5228 tmp = I915_READ(HSYNC(cpu_transcoder));
5229 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5230 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5231
5232 tmp = I915_READ(VTOTAL(cpu_transcoder));
5233 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5234 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5235 tmp = I915_READ(VBLANK(cpu_transcoder));
5236 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5237 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5238 tmp = I915_READ(VSYNC(cpu_transcoder));
5239 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5240 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5241
5242 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5243 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5244 pipe_config->adjusted_mode.crtc_vtotal += 1;
5245 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5246 }
5247
5248 tmp = I915_READ(PIPESRC(crtc->pipe));
5249 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5250 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5251
5252 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5253 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5254 }
5255
5256 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5257 struct intel_crtc_config *pipe_config)
5258 {
5259 struct drm_crtc *crtc = &intel_crtc->base;
5260
5261 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5262 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5263 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5264 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5265
5266 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5267 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5268 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5269 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5270
5271 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5272
5273 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5274 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5275 }
5276
5277 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5278 {
5279 struct drm_device *dev = intel_crtc->base.dev;
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281 uint32_t pipeconf;
5282
5283 pipeconf = 0;
5284
5285 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5286 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5287 pipeconf |= PIPECONF_ENABLE;
5288
5289 if (intel_crtc->config.double_wide)
5290 pipeconf |= PIPECONF_DOUBLE_WIDE;
5291
5292 /* only g4x and later have fancy bpc/dither controls */
5293 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5294 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5295 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5296 pipeconf |= PIPECONF_DITHER_EN |
5297 PIPECONF_DITHER_TYPE_SP;
5298
5299 switch (intel_crtc->config.pipe_bpp) {
5300 case 18:
5301 pipeconf |= PIPECONF_6BPC;
5302 break;
5303 case 24:
5304 pipeconf |= PIPECONF_8BPC;
5305 break;
5306 case 30:
5307 pipeconf |= PIPECONF_10BPC;
5308 break;
5309 default:
5310 /* Case prevented by intel_choose_pipe_bpp_dither. */
5311 BUG();
5312 }
5313 }
5314
5315 if (HAS_PIPE_CXSR(dev)) {
5316 if (intel_crtc->lowfreq_avail) {
5317 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5318 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5319 } else {
5320 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5321 }
5322 }
5323
5324 if (!IS_GEN2(dev) &&
5325 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5326 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5327 else
5328 pipeconf |= PIPECONF_PROGRESSIVE;
5329
5330 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5331 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5332
5333 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5334 POSTING_READ(PIPECONF(intel_crtc->pipe));
5335 }
5336
5337 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5338 int x, int y,
5339 struct drm_framebuffer *fb)
5340 {
5341 struct drm_device *dev = crtc->dev;
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5344 int pipe = intel_crtc->pipe;
5345 int plane = intel_crtc->plane;
5346 int refclk, num_connectors = 0;
5347 intel_clock_t clock, reduced_clock;
5348 u32 dspcntr;
5349 bool ok, has_reduced_clock = false;
5350 bool is_lvds = false, is_dsi = false;
5351 struct intel_encoder *encoder;
5352 const intel_limit_t *limit;
5353 int ret;
5354
5355 for_each_encoder_on_crtc(dev, crtc, encoder) {
5356 switch (encoder->type) {
5357 case INTEL_OUTPUT_LVDS:
5358 is_lvds = true;
5359 break;
5360 case INTEL_OUTPUT_DSI:
5361 is_dsi = true;
5362 break;
5363 }
5364
5365 num_connectors++;
5366 }
5367
5368 if (is_dsi)
5369 goto skip_dpll;
5370
5371 if (!intel_crtc->config.clock_set) {
5372 refclk = i9xx_get_refclk(crtc, num_connectors);
5373
5374 /*
5375 * Returns a set of divisors for the desired target clock with
5376 * the given refclk, or FALSE. The returned values represent
5377 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5378 * 2) / p1 / p2.
5379 */
5380 limit = intel_limit(crtc, refclk);
5381 ok = dev_priv->display.find_dpll(limit, crtc,
5382 intel_crtc->config.port_clock,
5383 refclk, NULL, &clock);
5384 if (!ok) {
5385 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5386 return -EINVAL;
5387 }
5388
5389 if (is_lvds && dev_priv->lvds_downclock_avail) {
5390 /*
5391 * Ensure we match the reduced clock's P to the target
5392 * clock. If the clocks don't match, we can't switch
5393 * the display clock by using the FP0/FP1. In such case
5394 * we will disable the LVDS downclock feature.
5395 */
5396 has_reduced_clock =
5397 dev_priv->display.find_dpll(limit, crtc,
5398 dev_priv->lvds_downclock,
5399 refclk, &clock,
5400 &reduced_clock);
5401 }
5402 /* Compat-code for transition, will disappear. */
5403 intel_crtc->config.dpll.n = clock.n;
5404 intel_crtc->config.dpll.m1 = clock.m1;
5405 intel_crtc->config.dpll.m2 = clock.m2;
5406 intel_crtc->config.dpll.p1 = clock.p1;
5407 intel_crtc->config.dpll.p2 = clock.p2;
5408 }
5409
5410 if (IS_GEN2(dev)) {
5411 i8xx_update_pll(intel_crtc,
5412 has_reduced_clock ? &reduced_clock : NULL,
5413 num_connectors);
5414 } else if (IS_VALLEYVIEW(dev)) {
5415 vlv_update_pll(intel_crtc);
5416 } else {
5417 i9xx_update_pll(intel_crtc,
5418 has_reduced_clock ? &reduced_clock : NULL,
5419 num_connectors);
5420 }
5421
5422 skip_dpll:
5423 /* Set up the display plane register */
5424 dspcntr = DISPPLANE_GAMMA_ENABLE;
5425
5426 if (!IS_VALLEYVIEW(dev)) {
5427 if (pipe == 0)
5428 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5429 else
5430 dspcntr |= DISPPLANE_SEL_PIPE_B;
5431 }
5432
5433 intel_set_pipe_timings(intel_crtc);
5434
5435 /* pipesrc and dspsize control the size that is scaled from,
5436 * which should always be the user's requested size.
5437 */
5438 I915_WRITE(DSPSIZE(plane),
5439 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5440 (intel_crtc->config.pipe_src_w - 1));
5441 I915_WRITE(DSPPOS(plane), 0);
5442
5443 i9xx_set_pipeconf(intel_crtc);
5444
5445 I915_WRITE(DSPCNTR(plane), dspcntr);
5446 POSTING_READ(DSPCNTR(plane));
5447
5448 ret = intel_pipe_set_base(crtc, x, y, fb);
5449
5450 return ret;
5451 }
5452
5453 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5454 struct intel_crtc_config *pipe_config)
5455 {
5456 struct drm_device *dev = crtc->base.dev;
5457 struct drm_i915_private *dev_priv = dev->dev_private;
5458 uint32_t tmp;
5459
5460 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5461 return;
5462
5463 tmp = I915_READ(PFIT_CONTROL);
5464 if (!(tmp & PFIT_ENABLE))
5465 return;
5466
5467 /* Check whether the pfit is attached to our pipe. */
5468 if (INTEL_INFO(dev)->gen < 4) {
5469 if (crtc->pipe != PIPE_B)
5470 return;
5471 } else {
5472 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5473 return;
5474 }
5475
5476 pipe_config->gmch_pfit.control = tmp;
5477 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5478 if (INTEL_INFO(dev)->gen < 5)
5479 pipe_config->gmch_pfit.lvds_border_bits =
5480 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5481 }
5482
5483 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5484 struct intel_crtc_config *pipe_config)
5485 {
5486 struct drm_device *dev = crtc->base.dev;
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 int pipe = pipe_config->cpu_transcoder;
5489 intel_clock_t clock;
5490 u32 mdiv;
5491 int refclk = 100000;
5492
5493 mutex_lock(&dev_priv->dpio_lock);
5494 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5495 mutex_unlock(&dev_priv->dpio_lock);
5496
5497 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5498 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5499 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5500 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5501 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5502
5503 vlv_clock(refclk, &clock);
5504
5505 /* clock.dot is the fast clock */
5506 pipe_config->port_clock = clock.dot / 5;
5507 }
5508
5509 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5510 struct intel_crtc_config *pipe_config)
5511 {
5512 struct drm_device *dev = crtc->base.dev;
5513 struct drm_i915_private *dev_priv = dev->dev_private;
5514 uint32_t tmp;
5515
5516 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5517 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5518
5519 tmp = I915_READ(PIPECONF(crtc->pipe));
5520 if (!(tmp & PIPECONF_ENABLE))
5521 return false;
5522
5523 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5524 switch (tmp & PIPECONF_BPC_MASK) {
5525 case PIPECONF_6BPC:
5526 pipe_config->pipe_bpp = 18;
5527 break;
5528 case PIPECONF_8BPC:
5529 pipe_config->pipe_bpp = 24;
5530 break;
5531 case PIPECONF_10BPC:
5532 pipe_config->pipe_bpp = 30;
5533 break;
5534 default:
5535 break;
5536 }
5537 }
5538
5539 if (INTEL_INFO(dev)->gen < 4)
5540 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5541
5542 intel_get_pipe_timings(crtc, pipe_config);
5543
5544 i9xx_get_pfit_config(crtc, pipe_config);
5545
5546 if (INTEL_INFO(dev)->gen >= 4) {
5547 tmp = I915_READ(DPLL_MD(crtc->pipe));
5548 pipe_config->pixel_multiplier =
5549 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5550 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5551 pipe_config->dpll_hw_state.dpll_md = tmp;
5552 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5553 tmp = I915_READ(DPLL(crtc->pipe));
5554 pipe_config->pixel_multiplier =
5555 ((tmp & SDVO_MULTIPLIER_MASK)
5556 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5557 } else {
5558 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5559 * port and will be fixed up in the encoder->get_config
5560 * function. */
5561 pipe_config->pixel_multiplier = 1;
5562 }
5563 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5564 if (!IS_VALLEYVIEW(dev)) {
5565 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5566 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5567 } else {
5568 /* Mask out read-only status bits. */
5569 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5570 DPLL_PORTC_READY_MASK |
5571 DPLL_PORTB_READY_MASK);
5572 }
5573
5574 if (IS_VALLEYVIEW(dev))
5575 vlv_crtc_clock_get(crtc, pipe_config);
5576 else
5577 i9xx_crtc_clock_get(crtc, pipe_config);
5578
5579 return true;
5580 }
5581
5582 static void ironlake_init_pch_refclk(struct drm_device *dev)
5583 {
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 struct drm_mode_config *mode_config = &dev->mode_config;
5586 struct intel_encoder *encoder;
5587 u32 val, final;
5588 bool has_lvds = false;
5589 bool has_cpu_edp = false;
5590 bool has_panel = false;
5591 bool has_ck505 = false;
5592 bool can_ssc = false;
5593
5594 /* We need to take the global config into account */
5595 list_for_each_entry(encoder, &mode_config->encoder_list,
5596 base.head) {
5597 switch (encoder->type) {
5598 case INTEL_OUTPUT_LVDS:
5599 has_panel = true;
5600 has_lvds = true;
5601 break;
5602 case INTEL_OUTPUT_EDP:
5603 has_panel = true;
5604 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5605 has_cpu_edp = true;
5606 break;
5607 }
5608 }
5609
5610 if (HAS_PCH_IBX(dev)) {
5611 has_ck505 = dev_priv->vbt.display_clock_mode;
5612 can_ssc = has_ck505;
5613 } else {
5614 has_ck505 = false;
5615 can_ssc = true;
5616 }
5617
5618 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5619 has_panel, has_lvds, has_ck505);
5620
5621 /* Ironlake: try to setup display ref clock before DPLL
5622 * enabling. This is only under driver's control after
5623 * PCH B stepping, previous chipset stepping should be
5624 * ignoring this setting.
5625 */
5626 val = I915_READ(PCH_DREF_CONTROL);
5627
5628 /* As we must carefully and slowly disable/enable each source in turn,
5629 * compute the final state we want first and check if we need to
5630 * make any changes at all.
5631 */
5632 final = val;
5633 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5634 if (has_ck505)
5635 final |= DREF_NONSPREAD_CK505_ENABLE;
5636 else
5637 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5638
5639 final &= ~DREF_SSC_SOURCE_MASK;
5640 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5641 final &= ~DREF_SSC1_ENABLE;
5642
5643 if (has_panel) {
5644 final |= DREF_SSC_SOURCE_ENABLE;
5645
5646 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5647 final |= DREF_SSC1_ENABLE;
5648
5649 if (has_cpu_edp) {
5650 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5651 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5652 else
5653 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5654 } else
5655 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5656 } else {
5657 final |= DREF_SSC_SOURCE_DISABLE;
5658 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5659 }
5660
5661 if (final == val)
5662 return;
5663
5664 /* Always enable nonspread source */
5665 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5666
5667 if (has_ck505)
5668 val |= DREF_NONSPREAD_CK505_ENABLE;
5669 else
5670 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5671
5672 if (has_panel) {
5673 val &= ~DREF_SSC_SOURCE_MASK;
5674 val |= DREF_SSC_SOURCE_ENABLE;
5675
5676 /* SSC must be turned on before enabling the CPU output */
5677 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5678 DRM_DEBUG_KMS("Using SSC on panel\n");
5679 val |= DREF_SSC1_ENABLE;
5680 } else
5681 val &= ~DREF_SSC1_ENABLE;
5682
5683 /* Get SSC going before enabling the outputs */
5684 I915_WRITE(PCH_DREF_CONTROL, val);
5685 POSTING_READ(PCH_DREF_CONTROL);
5686 udelay(200);
5687
5688 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5689
5690 /* Enable CPU source on CPU attached eDP */
5691 if (has_cpu_edp) {
5692 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5693 DRM_DEBUG_KMS("Using SSC on eDP\n");
5694 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5695 }
5696 else
5697 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5698 } else
5699 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5700
5701 I915_WRITE(PCH_DREF_CONTROL, val);
5702 POSTING_READ(PCH_DREF_CONTROL);
5703 udelay(200);
5704 } else {
5705 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5706
5707 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5708
5709 /* Turn off CPU output */
5710 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5711
5712 I915_WRITE(PCH_DREF_CONTROL, val);
5713 POSTING_READ(PCH_DREF_CONTROL);
5714 udelay(200);
5715
5716 /* Turn off the SSC source */
5717 val &= ~DREF_SSC_SOURCE_MASK;
5718 val |= DREF_SSC_SOURCE_DISABLE;
5719
5720 /* Turn off SSC1 */
5721 val &= ~DREF_SSC1_ENABLE;
5722
5723 I915_WRITE(PCH_DREF_CONTROL, val);
5724 POSTING_READ(PCH_DREF_CONTROL);
5725 udelay(200);
5726 }
5727
5728 BUG_ON(val != final);
5729 }
5730
5731 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5732 {
5733 uint32_t tmp;
5734
5735 tmp = I915_READ(SOUTH_CHICKEN2);
5736 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5737 I915_WRITE(SOUTH_CHICKEN2, tmp);
5738
5739 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5740 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5741 DRM_ERROR("FDI mPHY reset assert timeout\n");
5742
5743 tmp = I915_READ(SOUTH_CHICKEN2);
5744 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5745 I915_WRITE(SOUTH_CHICKEN2, tmp);
5746
5747 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5748 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5749 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5750 }
5751
5752 /* WaMPhyProgramming:hsw */
5753 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5754 {
5755 uint32_t tmp;
5756
5757 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5758 tmp &= ~(0xFF << 24);
5759 tmp |= (0x12 << 24);
5760 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5761
5762 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5763 tmp |= (1 << 11);
5764 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5765
5766 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5767 tmp |= (1 << 11);
5768 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5769
5770 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5771 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5772 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5773
5774 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5775 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5776 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5777
5778 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5779 tmp &= ~(7 << 13);
5780 tmp |= (5 << 13);
5781 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5782
5783 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5784 tmp &= ~(7 << 13);
5785 tmp |= (5 << 13);
5786 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5787
5788 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5789 tmp &= ~0xFF;
5790 tmp |= 0x1C;
5791 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5792
5793 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5794 tmp &= ~0xFF;
5795 tmp |= 0x1C;
5796 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5797
5798 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5799 tmp &= ~(0xFF << 16);
5800 tmp |= (0x1C << 16);
5801 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5802
5803 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5804 tmp &= ~(0xFF << 16);
5805 tmp |= (0x1C << 16);
5806 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5807
5808 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5809 tmp |= (1 << 27);
5810 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5811
5812 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5813 tmp |= (1 << 27);
5814 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5815
5816 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5817 tmp &= ~(0xF << 28);
5818 tmp |= (4 << 28);
5819 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5820
5821 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5822 tmp &= ~(0xF << 28);
5823 tmp |= (4 << 28);
5824 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5825 }
5826
5827 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5828 * Programming" based on the parameters passed:
5829 * - Sequence to enable CLKOUT_DP
5830 * - Sequence to enable CLKOUT_DP without spread
5831 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5832 */
5833 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5834 bool with_fdi)
5835 {
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 uint32_t reg, tmp;
5838
5839 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5840 with_spread = true;
5841 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5842 with_fdi, "LP PCH doesn't have FDI\n"))
5843 with_fdi = false;
5844
5845 mutex_lock(&dev_priv->dpio_lock);
5846
5847 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5848 tmp &= ~SBI_SSCCTL_DISABLE;
5849 tmp |= SBI_SSCCTL_PATHALT;
5850 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5851
5852 udelay(24);
5853
5854 if (with_spread) {
5855 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5856 tmp &= ~SBI_SSCCTL_PATHALT;
5857 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5858
5859 if (with_fdi) {
5860 lpt_reset_fdi_mphy(dev_priv);
5861 lpt_program_fdi_mphy(dev_priv);
5862 }
5863 }
5864
5865 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5866 SBI_GEN0 : SBI_DBUFF0;
5867 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5868 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5869 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5870
5871 mutex_unlock(&dev_priv->dpio_lock);
5872 }
5873
5874 /* Sequence to disable CLKOUT_DP */
5875 static void lpt_disable_clkout_dp(struct drm_device *dev)
5876 {
5877 struct drm_i915_private *dev_priv = dev->dev_private;
5878 uint32_t reg, tmp;
5879
5880 mutex_lock(&dev_priv->dpio_lock);
5881
5882 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5883 SBI_GEN0 : SBI_DBUFF0;
5884 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5885 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5886 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5887
5888 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5889 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5890 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5891 tmp |= SBI_SSCCTL_PATHALT;
5892 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5893 udelay(32);
5894 }
5895 tmp |= SBI_SSCCTL_DISABLE;
5896 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5897 }
5898
5899 mutex_unlock(&dev_priv->dpio_lock);
5900 }
5901
5902 static void lpt_init_pch_refclk(struct drm_device *dev)
5903 {
5904 struct drm_mode_config *mode_config = &dev->mode_config;
5905 struct intel_encoder *encoder;
5906 bool has_vga = false;
5907
5908 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5909 switch (encoder->type) {
5910 case INTEL_OUTPUT_ANALOG:
5911 has_vga = true;
5912 break;
5913 }
5914 }
5915
5916 if (has_vga)
5917 lpt_enable_clkout_dp(dev, true, true);
5918 else
5919 lpt_disable_clkout_dp(dev);
5920 }
5921
5922 /*
5923 * Initialize reference clocks when the driver loads
5924 */
5925 void intel_init_pch_refclk(struct drm_device *dev)
5926 {
5927 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5928 ironlake_init_pch_refclk(dev);
5929 else if (HAS_PCH_LPT(dev))
5930 lpt_init_pch_refclk(dev);
5931 }
5932
5933 static int ironlake_get_refclk(struct drm_crtc *crtc)
5934 {
5935 struct drm_device *dev = crtc->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 struct intel_encoder *encoder;
5938 int num_connectors = 0;
5939 bool is_lvds = false;
5940
5941 for_each_encoder_on_crtc(dev, crtc, encoder) {
5942 switch (encoder->type) {
5943 case INTEL_OUTPUT_LVDS:
5944 is_lvds = true;
5945 break;
5946 }
5947 num_connectors++;
5948 }
5949
5950 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5951 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5952 dev_priv->vbt.lvds_ssc_freq);
5953 return dev_priv->vbt.lvds_ssc_freq;
5954 }
5955
5956 return 120000;
5957 }
5958
5959 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5960 {
5961 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5963 int pipe = intel_crtc->pipe;
5964 uint32_t val;
5965
5966 val = 0;
5967
5968 switch (intel_crtc->config.pipe_bpp) {
5969 case 18:
5970 val |= PIPECONF_6BPC;
5971 break;
5972 case 24:
5973 val |= PIPECONF_8BPC;
5974 break;
5975 case 30:
5976 val |= PIPECONF_10BPC;
5977 break;
5978 case 36:
5979 val |= PIPECONF_12BPC;
5980 break;
5981 default:
5982 /* Case prevented by intel_choose_pipe_bpp_dither. */
5983 BUG();
5984 }
5985
5986 if (intel_crtc->config.dither)
5987 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5988
5989 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5990 val |= PIPECONF_INTERLACED_ILK;
5991 else
5992 val |= PIPECONF_PROGRESSIVE;
5993
5994 if (intel_crtc->config.limited_color_range)
5995 val |= PIPECONF_COLOR_RANGE_SELECT;
5996
5997 I915_WRITE(PIPECONF(pipe), val);
5998 POSTING_READ(PIPECONF(pipe));
5999 }
6000
6001 /*
6002 * Set up the pipe CSC unit.
6003 *
6004 * Currently only full range RGB to limited range RGB conversion
6005 * is supported, but eventually this should handle various
6006 * RGB<->YCbCr scenarios as well.
6007 */
6008 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6009 {
6010 struct drm_device *dev = crtc->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6013 int pipe = intel_crtc->pipe;
6014 uint16_t coeff = 0x7800; /* 1.0 */
6015
6016 /*
6017 * TODO: Check what kind of values actually come out of the pipe
6018 * with these coeff/postoff values and adjust to get the best
6019 * accuracy. Perhaps we even need to take the bpc value into
6020 * consideration.
6021 */
6022
6023 if (intel_crtc->config.limited_color_range)
6024 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6025
6026 /*
6027 * GY/GU and RY/RU should be the other way around according
6028 * to BSpec, but reality doesn't agree. Just set them up in
6029 * a way that results in the correct picture.
6030 */
6031 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6032 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6033
6034 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6035 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6036
6037 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6038 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6039
6040 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6041 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6042 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6043
6044 if (INTEL_INFO(dev)->gen > 6) {
6045 uint16_t postoff = 0;
6046
6047 if (intel_crtc->config.limited_color_range)
6048 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6049
6050 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6051 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6052 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6053
6054 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6055 } else {
6056 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6057
6058 if (intel_crtc->config.limited_color_range)
6059 mode |= CSC_BLACK_SCREEN_OFFSET;
6060
6061 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6062 }
6063 }
6064
6065 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6066 {
6067 struct drm_device *dev = crtc->dev;
6068 struct drm_i915_private *dev_priv = dev->dev_private;
6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070 enum pipe pipe = intel_crtc->pipe;
6071 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6072 uint32_t val;
6073
6074 val = 0;
6075
6076 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6077 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6078
6079 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6080 val |= PIPECONF_INTERLACED_ILK;
6081 else
6082 val |= PIPECONF_PROGRESSIVE;
6083
6084 I915_WRITE(PIPECONF(cpu_transcoder), val);
6085 POSTING_READ(PIPECONF(cpu_transcoder));
6086
6087 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6088 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6089
6090 if (IS_BROADWELL(dev)) {
6091 val = 0;
6092
6093 switch (intel_crtc->config.pipe_bpp) {
6094 case 18:
6095 val |= PIPEMISC_DITHER_6_BPC;
6096 break;
6097 case 24:
6098 val |= PIPEMISC_DITHER_8_BPC;
6099 break;
6100 case 30:
6101 val |= PIPEMISC_DITHER_10_BPC;
6102 break;
6103 case 36:
6104 val |= PIPEMISC_DITHER_12_BPC;
6105 break;
6106 default:
6107 /* Case prevented by pipe_config_set_bpp. */
6108 BUG();
6109 }
6110
6111 if (intel_crtc->config.dither)
6112 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6113
6114 I915_WRITE(PIPEMISC(pipe), val);
6115 }
6116 }
6117
6118 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6119 intel_clock_t *clock,
6120 bool *has_reduced_clock,
6121 intel_clock_t *reduced_clock)
6122 {
6123 struct drm_device *dev = crtc->dev;
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6125 struct intel_encoder *intel_encoder;
6126 int refclk;
6127 const intel_limit_t *limit;
6128 bool ret, is_lvds = false;
6129
6130 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6131 switch (intel_encoder->type) {
6132 case INTEL_OUTPUT_LVDS:
6133 is_lvds = true;
6134 break;
6135 }
6136 }
6137
6138 refclk = ironlake_get_refclk(crtc);
6139
6140 /*
6141 * Returns a set of divisors for the desired target clock with the given
6142 * refclk, or FALSE. The returned values represent the clock equation:
6143 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6144 */
6145 limit = intel_limit(crtc, refclk);
6146 ret = dev_priv->display.find_dpll(limit, crtc,
6147 to_intel_crtc(crtc)->config.port_clock,
6148 refclk, NULL, clock);
6149 if (!ret)
6150 return false;
6151
6152 if (is_lvds && dev_priv->lvds_downclock_avail) {
6153 /*
6154 * Ensure we match the reduced clock's P to the target clock.
6155 * If the clocks don't match, we can't switch the display clock
6156 * by using the FP0/FP1. In such case we will disable the LVDS
6157 * downclock feature.
6158 */
6159 *has_reduced_clock =
6160 dev_priv->display.find_dpll(limit, crtc,
6161 dev_priv->lvds_downclock,
6162 refclk, clock,
6163 reduced_clock);
6164 }
6165
6166 return true;
6167 }
6168
6169 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6170 {
6171 /*
6172 * Account for spread spectrum to avoid
6173 * oversubscribing the link. Max center spread
6174 * is 2.5%; use 5% for safety's sake.
6175 */
6176 u32 bps = target_clock * bpp * 21 / 20;
6177 return bps / (link_bw * 8) + 1;
6178 }
6179
6180 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6181 {
6182 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6183 }
6184
6185 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6186 u32 *fp,
6187 intel_clock_t *reduced_clock, u32 *fp2)
6188 {
6189 struct drm_crtc *crtc = &intel_crtc->base;
6190 struct drm_device *dev = crtc->dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 struct intel_encoder *intel_encoder;
6193 uint32_t dpll;
6194 int factor, num_connectors = 0;
6195 bool is_lvds = false, is_sdvo = false;
6196
6197 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6198 switch (intel_encoder->type) {
6199 case INTEL_OUTPUT_LVDS:
6200 is_lvds = true;
6201 break;
6202 case INTEL_OUTPUT_SDVO:
6203 case INTEL_OUTPUT_HDMI:
6204 is_sdvo = true;
6205 break;
6206 }
6207
6208 num_connectors++;
6209 }
6210
6211 /* Enable autotuning of the PLL clock (if permissible) */
6212 factor = 21;
6213 if (is_lvds) {
6214 if ((intel_panel_use_ssc(dev_priv) &&
6215 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6216 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6217 factor = 25;
6218 } else if (intel_crtc->config.sdvo_tv_clock)
6219 factor = 20;
6220
6221 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6222 *fp |= FP_CB_TUNE;
6223
6224 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6225 *fp2 |= FP_CB_TUNE;
6226
6227 dpll = 0;
6228
6229 if (is_lvds)
6230 dpll |= DPLLB_MODE_LVDS;
6231 else
6232 dpll |= DPLLB_MODE_DAC_SERIAL;
6233
6234 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6235 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6236
6237 if (is_sdvo)
6238 dpll |= DPLL_SDVO_HIGH_SPEED;
6239 if (intel_crtc->config.has_dp_encoder)
6240 dpll |= DPLL_SDVO_HIGH_SPEED;
6241
6242 /* compute bitmask from p1 value */
6243 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6244 /* also FPA1 */
6245 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6246
6247 switch (intel_crtc->config.dpll.p2) {
6248 case 5:
6249 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6250 break;
6251 case 7:
6252 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6253 break;
6254 case 10:
6255 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6256 break;
6257 case 14:
6258 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6259 break;
6260 }
6261
6262 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6263 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6264 else
6265 dpll |= PLL_REF_INPUT_DREFCLK;
6266
6267 return dpll | DPLL_VCO_ENABLE;
6268 }
6269
6270 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6271 int x, int y,
6272 struct drm_framebuffer *fb)
6273 {
6274 struct drm_device *dev = crtc->dev;
6275 struct drm_i915_private *dev_priv = dev->dev_private;
6276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6277 int pipe = intel_crtc->pipe;
6278 int plane = intel_crtc->plane;
6279 int num_connectors = 0;
6280 intel_clock_t clock, reduced_clock;
6281 u32 dpll = 0, fp = 0, fp2 = 0;
6282 bool ok, has_reduced_clock = false;
6283 bool is_lvds = false;
6284 struct intel_encoder *encoder;
6285 struct intel_shared_dpll *pll;
6286 int ret;
6287
6288 for_each_encoder_on_crtc(dev, crtc, encoder) {
6289 switch (encoder->type) {
6290 case INTEL_OUTPUT_LVDS:
6291 is_lvds = true;
6292 break;
6293 }
6294
6295 num_connectors++;
6296 }
6297
6298 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6299 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6300
6301 ok = ironlake_compute_clocks(crtc, &clock,
6302 &has_reduced_clock, &reduced_clock);
6303 if (!ok && !intel_crtc->config.clock_set) {
6304 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6305 return -EINVAL;
6306 }
6307 /* Compat-code for transition, will disappear. */
6308 if (!intel_crtc->config.clock_set) {
6309 intel_crtc->config.dpll.n = clock.n;
6310 intel_crtc->config.dpll.m1 = clock.m1;
6311 intel_crtc->config.dpll.m2 = clock.m2;
6312 intel_crtc->config.dpll.p1 = clock.p1;
6313 intel_crtc->config.dpll.p2 = clock.p2;
6314 }
6315
6316 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6317 if (intel_crtc->config.has_pch_encoder) {
6318 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6319 if (has_reduced_clock)
6320 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6321
6322 dpll = ironlake_compute_dpll(intel_crtc,
6323 &fp, &reduced_clock,
6324 has_reduced_clock ? &fp2 : NULL);
6325
6326 intel_crtc->config.dpll_hw_state.dpll = dpll;
6327 intel_crtc->config.dpll_hw_state.fp0 = fp;
6328 if (has_reduced_clock)
6329 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6330 else
6331 intel_crtc->config.dpll_hw_state.fp1 = fp;
6332
6333 pll = intel_get_shared_dpll(intel_crtc);
6334 if (pll == NULL) {
6335 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6336 pipe_name(pipe));
6337 return -EINVAL;
6338 }
6339 } else
6340 intel_put_shared_dpll(intel_crtc);
6341
6342 if (intel_crtc->config.has_dp_encoder)
6343 intel_dp_set_m_n(intel_crtc);
6344
6345 if (is_lvds && has_reduced_clock && i915_powersave)
6346 intel_crtc->lowfreq_avail = true;
6347 else
6348 intel_crtc->lowfreq_avail = false;
6349
6350 intel_set_pipe_timings(intel_crtc);
6351
6352 if (intel_crtc->config.has_pch_encoder) {
6353 intel_cpu_transcoder_set_m_n(intel_crtc,
6354 &intel_crtc->config.fdi_m_n);
6355 }
6356
6357 ironlake_set_pipeconf(crtc);
6358
6359 /* Set up the display plane register */
6360 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6361 POSTING_READ(DSPCNTR(plane));
6362
6363 ret = intel_pipe_set_base(crtc, x, y, fb);
6364
6365 return ret;
6366 }
6367
6368 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6369 struct intel_link_m_n *m_n)
6370 {
6371 struct drm_device *dev = crtc->base.dev;
6372 struct drm_i915_private *dev_priv = dev->dev_private;
6373 enum pipe pipe = crtc->pipe;
6374
6375 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6376 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6377 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6378 & ~TU_SIZE_MASK;
6379 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6380 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6381 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6382 }
6383
6384 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6385 enum transcoder transcoder,
6386 struct intel_link_m_n *m_n)
6387 {
6388 struct drm_device *dev = crtc->base.dev;
6389 struct drm_i915_private *dev_priv = dev->dev_private;
6390 enum pipe pipe = crtc->pipe;
6391
6392 if (INTEL_INFO(dev)->gen >= 5) {
6393 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6394 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6395 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6396 & ~TU_SIZE_MASK;
6397 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6398 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6399 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6400 } else {
6401 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6402 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6403 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6404 & ~TU_SIZE_MASK;
6405 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6406 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6407 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6408 }
6409 }
6410
6411 void intel_dp_get_m_n(struct intel_crtc *crtc,
6412 struct intel_crtc_config *pipe_config)
6413 {
6414 if (crtc->config.has_pch_encoder)
6415 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6416 else
6417 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6418 &pipe_config->dp_m_n);
6419 }
6420
6421 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6422 struct intel_crtc_config *pipe_config)
6423 {
6424 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6425 &pipe_config->fdi_m_n);
6426 }
6427
6428 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6429 struct intel_crtc_config *pipe_config)
6430 {
6431 struct drm_device *dev = crtc->base.dev;
6432 struct drm_i915_private *dev_priv = dev->dev_private;
6433 uint32_t tmp;
6434
6435 tmp = I915_READ(PF_CTL(crtc->pipe));
6436
6437 if (tmp & PF_ENABLE) {
6438 pipe_config->pch_pfit.enabled = true;
6439 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6440 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6441
6442 /* We currently do not free assignements of panel fitters on
6443 * ivb/hsw (since we don't use the higher upscaling modes which
6444 * differentiates them) so just WARN about this case for now. */
6445 if (IS_GEN7(dev)) {
6446 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6447 PF_PIPE_SEL_IVB(crtc->pipe));
6448 }
6449 }
6450 }
6451
6452 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6453 struct intel_crtc_config *pipe_config)
6454 {
6455 struct drm_device *dev = crtc->base.dev;
6456 struct drm_i915_private *dev_priv = dev->dev_private;
6457 uint32_t tmp;
6458
6459 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6460 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6461
6462 tmp = I915_READ(PIPECONF(crtc->pipe));
6463 if (!(tmp & PIPECONF_ENABLE))
6464 return false;
6465
6466 switch (tmp & PIPECONF_BPC_MASK) {
6467 case PIPECONF_6BPC:
6468 pipe_config->pipe_bpp = 18;
6469 break;
6470 case PIPECONF_8BPC:
6471 pipe_config->pipe_bpp = 24;
6472 break;
6473 case PIPECONF_10BPC:
6474 pipe_config->pipe_bpp = 30;
6475 break;
6476 case PIPECONF_12BPC:
6477 pipe_config->pipe_bpp = 36;
6478 break;
6479 default:
6480 break;
6481 }
6482
6483 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6484 struct intel_shared_dpll *pll;
6485
6486 pipe_config->has_pch_encoder = true;
6487
6488 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6489 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6490 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6491
6492 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6493
6494 if (HAS_PCH_IBX(dev_priv->dev)) {
6495 pipe_config->shared_dpll =
6496 (enum intel_dpll_id) crtc->pipe;
6497 } else {
6498 tmp = I915_READ(PCH_DPLL_SEL);
6499 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6500 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6501 else
6502 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6503 }
6504
6505 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6506
6507 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6508 &pipe_config->dpll_hw_state));
6509
6510 tmp = pipe_config->dpll_hw_state.dpll;
6511 pipe_config->pixel_multiplier =
6512 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6513 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6514
6515 ironlake_pch_clock_get(crtc, pipe_config);
6516 } else {
6517 pipe_config->pixel_multiplier = 1;
6518 }
6519
6520 intel_get_pipe_timings(crtc, pipe_config);
6521
6522 ironlake_get_pfit_config(crtc, pipe_config);
6523
6524 return true;
6525 }
6526
6527 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6528 {
6529 struct drm_device *dev = dev_priv->dev;
6530 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6531 struct intel_crtc *crtc;
6532 unsigned long irqflags;
6533 uint32_t val;
6534
6535 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6536 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6537 pipe_name(crtc->pipe));
6538
6539 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6540 WARN(plls->spll_refcount, "SPLL enabled\n");
6541 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6542 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6543 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6544 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6545 "CPU PWM1 enabled\n");
6546 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6547 "CPU PWM2 enabled\n");
6548 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6549 "PCH PWM1 enabled\n");
6550 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6551 "Utility pin enabled\n");
6552 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6553
6554 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6555 val = I915_READ(DEIMR);
6556 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6557 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6558 val = I915_READ(SDEIMR);
6559 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6560 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6561 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6562 }
6563
6564 /*
6565 * This function implements pieces of two sequences from BSpec:
6566 * - Sequence for display software to disable LCPLL
6567 * - Sequence for display software to allow package C8+
6568 * The steps implemented here are just the steps that actually touch the LCPLL
6569 * register. Callers should take care of disabling all the display engine
6570 * functions, doing the mode unset, fixing interrupts, etc.
6571 */
6572 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6573 bool switch_to_fclk, bool allow_power_down)
6574 {
6575 uint32_t val;
6576
6577 assert_can_disable_lcpll(dev_priv);
6578
6579 val = I915_READ(LCPLL_CTL);
6580
6581 if (switch_to_fclk) {
6582 val |= LCPLL_CD_SOURCE_FCLK;
6583 I915_WRITE(LCPLL_CTL, val);
6584
6585 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6586 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6587 DRM_ERROR("Switching to FCLK failed\n");
6588
6589 val = I915_READ(LCPLL_CTL);
6590 }
6591
6592 val |= LCPLL_PLL_DISABLE;
6593 I915_WRITE(LCPLL_CTL, val);
6594 POSTING_READ(LCPLL_CTL);
6595
6596 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6597 DRM_ERROR("LCPLL still locked\n");
6598
6599 val = I915_READ(D_COMP);
6600 val |= D_COMP_COMP_DISABLE;
6601 mutex_lock(&dev_priv->rps.hw_lock);
6602 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6603 DRM_ERROR("Failed to disable D_COMP\n");
6604 mutex_unlock(&dev_priv->rps.hw_lock);
6605 POSTING_READ(D_COMP);
6606 ndelay(100);
6607
6608 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6609 DRM_ERROR("D_COMP RCOMP still in progress\n");
6610
6611 if (allow_power_down) {
6612 val = I915_READ(LCPLL_CTL);
6613 val |= LCPLL_POWER_DOWN_ALLOW;
6614 I915_WRITE(LCPLL_CTL, val);
6615 POSTING_READ(LCPLL_CTL);
6616 }
6617 }
6618
6619 /*
6620 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6621 * source.
6622 */
6623 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6624 {
6625 uint32_t val;
6626
6627 val = I915_READ(LCPLL_CTL);
6628
6629 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6630 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6631 return;
6632
6633 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6634 * we'll hang the machine! */
6635 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6636
6637 if (val & LCPLL_POWER_DOWN_ALLOW) {
6638 val &= ~LCPLL_POWER_DOWN_ALLOW;
6639 I915_WRITE(LCPLL_CTL, val);
6640 POSTING_READ(LCPLL_CTL);
6641 }
6642
6643 val = I915_READ(D_COMP);
6644 val |= D_COMP_COMP_FORCE;
6645 val &= ~D_COMP_COMP_DISABLE;
6646 mutex_lock(&dev_priv->rps.hw_lock);
6647 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6648 DRM_ERROR("Failed to enable D_COMP\n");
6649 mutex_unlock(&dev_priv->rps.hw_lock);
6650 POSTING_READ(D_COMP);
6651
6652 val = I915_READ(LCPLL_CTL);
6653 val &= ~LCPLL_PLL_DISABLE;
6654 I915_WRITE(LCPLL_CTL, val);
6655
6656 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6657 DRM_ERROR("LCPLL not locked yet\n");
6658
6659 if (val & LCPLL_CD_SOURCE_FCLK) {
6660 val = I915_READ(LCPLL_CTL);
6661 val &= ~LCPLL_CD_SOURCE_FCLK;
6662 I915_WRITE(LCPLL_CTL, val);
6663
6664 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6665 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6666 DRM_ERROR("Switching back to LCPLL failed\n");
6667 }
6668
6669 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6670 }
6671
6672 void hsw_enable_pc8_work(struct work_struct *__work)
6673 {
6674 struct drm_i915_private *dev_priv =
6675 container_of(to_delayed_work(__work), struct drm_i915_private,
6676 pc8.enable_work);
6677 struct drm_device *dev = dev_priv->dev;
6678 uint32_t val;
6679
6680 WARN_ON(!HAS_PC8(dev));
6681
6682 if (dev_priv->pc8.enabled)
6683 return;
6684
6685 DRM_DEBUG_KMS("Enabling package C8+\n");
6686
6687 dev_priv->pc8.enabled = true;
6688
6689 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6690 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6691 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6692 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6693 }
6694
6695 lpt_disable_clkout_dp(dev);
6696 hsw_pc8_disable_interrupts(dev);
6697 hsw_disable_lcpll(dev_priv, true, true);
6698
6699 intel_runtime_pm_put(dev_priv);
6700 }
6701
6702 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6703 {
6704 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6705 WARN(dev_priv->pc8.disable_count < 1,
6706 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6707
6708 dev_priv->pc8.disable_count--;
6709 if (dev_priv->pc8.disable_count != 0)
6710 return;
6711
6712 schedule_delayed_work(&dev_priv->pc8.enable_work,
6713 msecs_to_jiffies(i915_pc8_timeout));
6714 }
6715
6716 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6717 {
6718 struct drm_device *dev = dev_priv->dev;
6719 uint32_t val;
6720
6721 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6722 WARN(dev_priv->pc8.disable_count < 0,
6723 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6724
6725 dev_priv->pc8.disable_count++;
6726 if (dev_priv->pc8.disable_count != 1)
6727 return;
6728
6729 WARN_ON(!HAS_PC8(dev));
6730
6731 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6732 if (!dev_priv->pc8.enabled)
6733 return;
6734
6735 DRM_DEBUG_KMS("Disabling package C8+\n");
6736
6737 intel_runtime_pm_get(dev_priv);
6738
6739 hsw_restore_lcpll(dev_priv);
6740 hsw_pc8_restore_interrupts(dev);
6741 lpt_init_pch_refclk(dev);
6742
6743 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6744 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6745 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6746 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6747 }
6748
6749 intel_prepare_ddi(dev);
6750 i915_gem_init_swizzling(dev);
6751 mutex_lock(&dev_priv->rps.hw_lock);
6752 gen6_update_ring_freq(dev);
6753 mutex_unlock(&dev_priv->rps.hw_lock);
6754 dev_priv->pc8.enabled = false;
6755 }
6756
6757 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6758 {
6759 if (!HAS_PC8(dev_priv->dev))
6760 return;
6761
6762 mutex_lock(&dev_priv->pc8.lock);
6763 __hsw_enable_package_c8(dev_priv);
6764 mutex_unlock(&dev_priv->pc8.lock);
6765 }
6766
6767 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6768 {
6769 if (!HAS_PC8(dev_priv->dev))
6770 return;
6771
6772 mutex_lock(&dev_priv->pc8.lock);
6773 __hsw_disable_package_c8(dev_priv);
6774 mutex_unlock(&dev_priv->pc8.lock);
6775 }
6776
6777 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6778 {
6779 struct drm_device *dev = dev_priv->dev;
6780 struct intel_crtc *crtc;
6781 uint32_t val;
6782
6783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6784 if (crtc->base.enabled)
6785 return false;
6786
6787 /* This case is still possible since we have the i915.disable_power_well
6788 * parameter and also the KVMr or something else might be requesting the
6789 * power well. */
6790 val = I915_READ(HSW_PWR_WELL_DRIVER);
6791 if (val != 0) {
6792 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6793 return false;
6794 }
6795
6796 return true;
6797 }
6798
6799 /* Since we're called from modeset_global_resources there's no way to
6800 * symmetrically increase and decrease the refcount, so we use
6801 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6802 * or not.
6803 */
6804 static void hsw_update_package_c8(struct drm_device *dev)
6805 {
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 bool allow;
6808
6809 if (!HAS_PC8(dev_priv->dev))
6810 return;
6811
6812 if (!i915_enable_pc8)
6813 return;
6814
6815 mutex_lock(&dev_priv->pc8.lock);
6816
6817 allow = hsw_can_enable_package_c8(dev_priv);
6818
6819 if (allow == dev_priv->pc8.requirements_met)
6820 goto done;
6821
6822 dev_priv->pc8.requirements_met = allow;
6823
6824 if (allow)
6825 __hsw_enable_package_c8(dev_priv);
6826 else
6827 __hsw_disable_package_c8(dev_priv);
6828
6829 done:
6830 mutex_unlock(&dev_priv->pc8.lock);
6831 }
6832
6833 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6834 {
6835 if (!HAS_PC8(dev_priv->dev))
6836 return;
6837
6838 mutex_lock(&dev_priv->pc8.lock);
6839 if (!dev_priv->pc8.gpu_idle) {
6840 dev_priv->pc8.gpu_idle = true;
6841 __hsw_enable_package_c8(dev_priv);
6842 }
6843 mutex_unlock(&dev_priv->pc8.lock);
6844 }
6845
6846 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6847 {
6848 if (!HAS_PC8(dev_priv->dev))
6849 return;
6850
6851 mutex_lock(&dev_priv->pc8.lock);
6852 if (dev_priv->pc8.gpu_idle) {
6853 dev_priv->pc8.gpu_idle = false;
6854 __hsw_disable_package_c8(dev_priv);
6855 }
6856 mutex_unlock(&dev_priv->pc8.lock);
6857 }
6858
6859 #define for_each_power_domain(domain, mask) \
6860 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6861 if ((1 << (domain)) & (mask))
6862
6863 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6864 enum pipe pipe, bool pfit_enabled)
6865 {
6866 unsigned long mask;
6867 enum transcoder transcoder;
6868
6869 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6870
6871 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6872 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6873 if (pfit_enabled)
6874 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6875
6876 return mask;
6877 }
6878
6879 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6880 {
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882
6883 if (dev_priv->power_domains.init_power_on == enable)
6884 return;
6885
6886 if (enable)
6887 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6888 else
6889 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6890
6891 dev_priv->power_domains.init_power_on = enable;
6892 }
6893
6894 static void modeset_update_power_wells(struct drm_device *dev)
6895 {
6896 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6897 struct intel_crtc *crtc;
6898
6899 /*
6900 * First get all needed power domains, then put all unneeded, to avoid
6901 * any unnecessary toggling of the power wells.
6902 */
6903 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6904 enum intel_display_power_domain domain;
6905
6906 if (!crtc->base.enabled)
6907 continue;
6908
6909 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6910 crtc->pipe,
6911 crtc->config.pch_pfit.enabled);
6912
6913 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6914 intel_display_power_get(dev, domain);
6915 }
6916
6917 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6918 enum intel_display_power_domain domain;
6919
6920 for_each_power_domain(domain, crtc->enabled_power_domains)
6921 intel_display_power_put(dev, domain);
6922
6923 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6924 }
6925
6926 intel_display_set_init_power(dev, false);
6927 }
6928
6929 static void haswell_modeset_global_resources(struct drm_device *dev)
6930 {
6931 modeset_update_power_wells(dev);
6932 hsw_update_package_c8(dev);
6933 }
6934
6935 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6936 int x, int y,
6937 struct drm_framebuffer *fb)
6938 {
6939 struct drm_device *dev = crtc->dev;
6940 struct drm_i915_private *dev_priv = dev->dev_private;
6941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6942 int plane = intel_crtc->plane;
6943 int ret;
6944
6945 if (!intel_ddi_pll_select(intel_crtc))
6946 return -EINVAL;
6947 intel_ddi_pll_enable(intel_crtc);
6948
6949 if (intel_crtc->config.has_dp_encoder)
6950 intel_dp_set_m_n(intel_crtc);
6951
6952 intel_crtc->lowfreq_avail = false;
6953
6954 intel_set_pipe_timings(intel_crtc);
6955
6956 if (intel_crtc->config.has_pch_encoder) {
6957 intel_cpu_transcoder_set_m_n(intel_crtc,
6958 &intel_crtc->config.fdi_m_n);
6959 }
6960
6961 haswell_set_pipeconf(crtc);
6962
6963 intel_set_pipe_csc(crtc);
6964
6965 /* Set up the display plane register */
6966 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6967 POSTING_READ(DSPCNTR(plane));
6968
6969 ret = intel_pipe_set_base(crtc, x, y, fb);
6970
6971 return ret;
6972 }
6973
6974 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6975 struct intel_crtc_config *pipe_config)
6976 {
6977 struct drm_device *dev = crtc->base.dev;
6978 struct drm_i915_private *dev_priv = dev->dev_private;
6979 enum intel_display_power_domain pfit_domain;
6980 uint32_t tmp;
6981
6982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6984
6985 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6986 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6987 enum pipe trans_edp_pipe;
6988 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6989 default:
6990 WARN(1, "unknown pipe linked to edp transcoder\n");
6991 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6992 case TRANS_DDI_EDP_INPUT_A_ON:
6993 trans_edp_pipe = PIPE_A;
6994 break;
6995 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6996 trans_edp_pipe = PIPE_B;
6997 break;
6998 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6999 trans_edp_pipe = PIPE_C;
7000 break;
7001 }
7002
7003 if (trans_edp_pipe == crtc->pipe)
7004 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7005 }
7006
7007 if (!intel_display_power_enabled(dev,
7008 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7009 return false;
7010
7011 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7012 if (!(tmp & PIPECONF_ENABLE))
7013 return false;
7014
7015 /*
7016 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7017 * DDI E. So just check whether this pipe is wired to DDI E and whether
7018 * the PCH transcoder is on.
7019 */
7020 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7021 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7022 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7023 pipe_config->has_pch_encoder = true;
7024
7025 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7026 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7027 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7028
7029 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7030 }
7031
7032 intel_get_pipe_timings(crtc, pipe_config);
7033
7034 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7035 if (intel_display_power_enabled(dev, pfit_domain))
7036 ironlake_get_pfit_config(crtc, pipe_config);
7037
7038 if (IS_HASWELL(dev))
7039 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7040 (I915_READ(IPS_CTL) & IPS_ENABLE);
7041
7042 pipe_config->pixel_multiplier = 1;
7043
7044 return true;
7045 }
7046
7047 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7048 int x, int y,
7049 struct drm_framebuffer *fb)
7050 {
7051 struct drm_device *dev = crtc->dev;
7052 struct drm_i915_private *dev_priv = dev->dev_private;
7053 struct intel_encoder *encoder;
7054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7055 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7056 int pipe = intel_crtc->pipe;
7057 int ret;
7058
7059 drm_vblank_pre_modeset(dev, pipe);
7060
7061 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7062
7063 drm_vblank_post_modeset(dev, pipe);
7064
7065 if (ret != 0)
7066 return ret;
7067
7068 for_each_encoder_on_crtc(dev, crtc, encoder) {
7069 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7070 encoder->base.base.id,
7071 drm_get_encoder_name(&encoder->base),
7072 mode->base.id, mode->name);
7073 encoder->mode_set(encoder);
7074 }
7075
7076 return 0;
7077 }
7078
7079 static struct {
7080 int clock;
7081 u32 config;
7082 } hdmi_audio_clock[] = {
7083 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7084 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7085 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7086 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7087 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7088 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7089 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7090 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7091 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7092 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7093 };
7094
7095 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7096 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7097 {
7098 int i;
7099
7100 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7101 if (mode->clock == hdmi_audio_clock[i].clock)
7102 break;
7103 }
7104
7105 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7106 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7107 i = 1;
7108 }
7109
7110 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7111 hdmi_audio_clock[i].clock,
7112 hdmi_audio_clock[i].config);
7113
7114 return hdmi_audio_clock[i].config;
7115 }
7116
7117 static bool intel_eld_uptodate(struct drm_connector *connector,
7118 int reg_eldv, uint32_t bits_eldv,
7119 int reg_elda, uint32_t bits_elda,
7120 int reg_edid)
7121 {
7122 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7123 uint8_t *eld = connector->eld;
7124 uint32_t i;
7125
7126 i = I915_READ(reg_eldv);
7127 i &= bits_eldv;
7128
7129 if (!eld[0])
7130 return !i;
7131
7132 if (!i)
7133 return false;
7134
7135 i = I915_READ(reg_elda);
7136 i &= ~bits_elda;
7137 I915_WRITE(reg_elda, i);
7138
7139 for (i = 0; i < eld[2]; i++)
7140 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7141 return false;
7142
7143 return true;
7144 }
7145
7146 static void g4x_write_eld(struct drm_connector *connector,
7147 struct drm_crtc *crtc,
7148 struct drm_display_mode *mode)
7149 {
7150 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7151 uint8_t *eld = connector->eld;
7152 uint32_t eldv;
7153 uint32_t len;
7154 uint32_t i;
7155
7156 i = I915_READ(G4X_AUD_VID_DID);
7157
7158 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7159 eldv = G4X_ELDV_DEVCL_DEVBLC;
7160 else
7161 eldv = G4X_ELDV_DEVCTG;
7162
7163 if (intel_eld_uptodate(connector,
7164 G4X_AUD_CNTL_ST, eldv,
7165 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7166 G4X_HDMIW_HDMIEDID))
7167 return;
7168
7169 i = I915_READ(G4X_AUD_CNTL_ST);
7170 i &= ~(eldv | G4X_ELD_ADDR);
7171 len = (i >> 9) & 0x1f; /* ELD buffer size */
7172 I915_WRITE(G4X_AUD_CNTL_ST, i);
7173
7174 if (!eld[0])
7175 return;
7176
7177 len = min_t(uint8_t, eld[2], len);
7178 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7179 for (i = 0; i < len; i++)
7180 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7181
7182 i = I915_READ(G4X_AUD_CNTL_ST);
7183 i |= eldv;
7184 I915_WRITE(G4X_AUD_CNTL_ST, i);
7185 }
7186
7187 static void haswell_write_eld(struct drm_connector *connector,
7188 struct drm_crtc *crtc,
7189 struct drm_display_mode *mode)
7190 {
7191 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7192 uint8_t *eld = connector->eld;
7193 struct drm_device *dev = crtc->dev;
7194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195 uint32_t eldv;
7196 uint32_t i;
7197 int len;
7198 int pipe = to_intel_crtc(crtc)->pipe;
7199 int tmp;
7200
7201 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7202 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7203 int aud_config = HSW_AUD_CFG(pipe);
7204 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7205
7206
7207 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7208
7209 /* Audio output enable */
7210 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7211 tmp = I915_READ(aud_cntrl_st2);
7212 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7213 I915_WRITE(aud_cntrl_st2, tmp);
7214
7215 /* Wait for 1 vertical blank */
7216 intel_wait_for_vblank(dev, pipe);
7217
7218 /* Set ELD valid state */
7219 tmp = I915_READ(aud_cntrl_st2);
7220 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7221 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7222 I915_WRITE(aud_cntrl_st2, tmp);
7223 tmp = I915_READ(aud_cntrl_st2);
7224 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7225
7226 /* Enable HDMI mode */
7227 tmp = I915_READ(aud_config);
7228 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7229 /* clear N_programing_enable and N_value_index */
7230 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7231 I915_WRITE(aud_config, tmp);
7232
7233 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7234
7235 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7236 intel_crtc->eld_vld = true;
7237
7238 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7239 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7240 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7241 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7242 } else {
7243 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7244 }
7245
7246 if (intel_eld_uptodate(connector,
7247 aud_cntrl_st2, eldv,
7248 aud_cntl_st, IBX_ELD_ADDRESS,
7249 hdmiw_hdmiedid))
7250 return;
7251
7252 i = I915_READ(aud_cntrl_st2);
7253 i &= ~eldv;
7254 I915_WRITE(aud_cntrl_st2, i);
7255
7256 if (!eld[0])
7257 return;
7258
7259 i = I915_READ(aud_cntl_st);
7260 i &= ~IBX_ELD_ADDRESS;
7261 I915_WRITE(aud_cntl_st, i);
7262 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7263 DRM_DEBUG_DRIVER("port num:%d\n", i);
7264
7265 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7266 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7267 for (i = 0; i < len; i++)
7268 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7269
7270 i = I915_READ(aud_cntrl_st2);
7271 i |= eldv;
7272 I915_WRITE(aud_cntrl_st2, i);
7273
7274 }
7275
7276 static void ironlake_write_eld(struct drm_connector *connector,
7277 struct drm_crtc *crtc,
7278 struct drm_display_mode *mode)
7279 {
7280 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7281 uint8_t *eld = connector->eld;
7282 uint32_t eldv;
7283 uint32_t i;
7284 int len;
7285 int hdmiw_hdmiedid;
7286 int aud_config;
7287 int aud_cntl_st;
7288 int aud_cntrl_st2;
7289 int pipe = to_intel_crtc(crtc)->pipe;
7290
7291 if (HAS_PCH_IBX(connector->dev)) {
7292 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7293 aud_config = IBX_AUD_CFG(pipe);
7294 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7295 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7296 } else if (IS_VALLEYVIEW(connector->dev)) {
7297 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7298 aud_config = VLV_AUD_CFG(pipe);
7299 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7300 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7301 } else {
7302 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7303 aud_config = CPT_AUD_CFG(pipe);
7304 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7305 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7306 }
7307
7308 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7309
7310 if (IS_VALLEYVIEW(connector->dev)) {
7311 struct intel_encoder *intel_encoder;
7312 struct intel_digital_port *intel_dig_port;
7313
7314 intel_encoder = intel_attached_encoder(connector);
7315 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7316 i = intel_dig_port->port;
7317 } else {
7318 i = I915_READ(aud_cntl_st);
7319 i = (i >> 29) & DIP_PORT_SEL_MASK;
7320 /* DIP_Port_Select, 0x1 = PortB */
7321 }
7322
7323 if (!i) {
7324 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7325 /* operate blindly on all ports */
7326 eldv = IBX_ELD_VALIDB;
7327 eldv |= IBX_ELD_VALIDB << 4;
7328 eldv |= IBX_ELD_VALIDB << 8;
7329 } else {
7330 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7331 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7332 }
7333
7334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7335 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7336 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7337 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7338 } else {
7339 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7340 }
7341
7342 if (intel_eld_uptodate(connector,
7343 aud_cntrl_st2, eldv,
7344 aud_cntl_st, IBX_ELD_ADDRESS,
7345 hdmiw_hdmiedid))
7346 return;
7347
7348 i = I915_READ(aud_cntrl_st2);
7349 i &= ~eldv;
7350 I915_WRITE(aud_cntrl_st2, i);
7351
7352 if (!eld[0])
7353 return;
7354
7355 i = I915_READ(aud_cntl_st);
7356 i &= ~IBX_ELD_ADDRESS;
7357 I915_WRITE(aud_cntl_st, i);
7358
7359 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7360 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7361 for (i = 0; i < len; i++)
7362 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7363
7364 i = I915_READ(aud_cntrl_st2);
7365 i |= eldv;
7366 I915_WRITE(aud_cntrl_st2, i);
7367 }
7368
7369 void intel_write_eld(struct drm_encoder *encoder,
7370 struct drm_display_mode *mode)
7371 {
7372 struct drm_crtc *crtc = encoder->crtc;
7373 struct drm_connector *connector;
7374 struct drm_device *dev = encoder->dev;
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376
7377 connector = drm_select_eld(encoder, mode);
7378 if (!connector)
7379 return;
7380
7381 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7382 connector->base.id,
7383 drm_get_connector_name(connector),
7384 connector->encoder->base.id,
7385 drm_get_encoder_name(connector->encoder));
7386
7387 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7388
7389 if (dev_priv->display.write_eld)
7390 dev_priv->display.write_eld(connector, crtc, mode);
7391 }
7392
7393 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7394 {
7395 struct drm_device *dev = crtc->dev;
7396 struct drm_i915_private *dev_priv = dev->dev_private;
7397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398 bool visible = base != 0;
7399 u32 cntl;
7400
7401 if (intel_crtc->cursor_visible == visible)
7402 return;
7403
7404 cntl = I915_READ(_CURACNTR);
7405 if (visible) {
7406 /* On these chipsets we can only modify the base whilst
7407 * the cursor is disabled.
7408 */
7409 I915_WRITE(_CURABASE, base);
7410
7411 cntl &= ~(CURSOR_FORMAT_MASK);
7412 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7413 cntl |= CURSOR_ENABLE |
7414 CURSOR_GAMMA_ENABLE |
7415 CURSOR_FORMAT_ARGB;
7416 } else
7417 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7418 I915_WRITE(_CURACNTR, cntl);
7419
7420 intel_crtc->cursor_visible = visible;
7421 }
7422
7423 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7424 {
7425 struct drm_device *dev = crtc->dev;
7426 struct drm_i915_private *dev_priv = dev->dev_private;
7427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428 int pipe = intel_crtc->pipe;
7429 bool visible = base != 0;
7430
7431 if (intel_crtc->cursor_visible != visible) {
7432 uint32_t cntl = I915_READ(CURCNTR(pipe));
7433 if (base) {
7434 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7435 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7436 cntl |= pipe << 28; /* Connect to correct pipe */
7437 } else {
7438 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7439 cntl |= CURSOR_MODE_DISABLE;
7440 }
7441 I915_WRITE(CURCNTR(pipe), cntl);
7442
7443 intel_crtc->cursor_visible = visible;
7444 }
7445 /* and commit changes on next vblank */
7446 POSTING_READ(CURCNTR(pipe));
7447 I915_WRITE(CURBASE(pipe), base);
7448 POSTING_READ(CURBASE(pipe));
7449 }
7450
7451 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7452 {
7453 struct drm_device *dev = crtc->dev;
7454 struct drm_i915_private *dev_priv = dev->dev_private;
7455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7456 int pipe = intel_crtc->pipe;
7457 bool visible = base != 0;
7458
7459 if (intel_crtc->cursor_visible != visible) {
7460 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7461 if (base) {
7462 cntl &= ~CURSOR_MODE;
7463 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7464 } else {
7465 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7466 cntl |= CURSOR_MODE_DISABLE;
7467 }
7468 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7469 cntl |= CURSOR_PIPE_CSC_ENABLE;
7470 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7471 }
7472 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7473
7474 intel_crtc->cursor_visible = visible;
7475 }
7476 /* and commit changes on next vblank */
7477 POSTING_READ(CURCNTR_IVB(pipe));
7478 I915_WRITE(CURBASE_IVB(pipe), base);
7479 POSTING_READ(CURBASE_IVB(pipe));
7480 }
7481
7482 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7483 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7484 bool on)
7485 {
7486 struct drm_device *dev = crtc->dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7489 int pipe = intel_crtc->pipe;
7490 int x = intel_crtc->cursor_x;
7491 int y = intel_crtc->cursor_y;
7492 u32 base = 0, pos = 0;
7493 bool visible;
7494
7495 if (on)
7496 base = intel_crtc->cursor_addr;
7497
7498 if (x >= intel_crtc->config.pipe_src_w)
7499 base = 0;
7500
7501 if (y >= intel_crtc->config.pipe_src_h)
7502 base = 0;
7503
7504 if (x < 0) {
7505 if (x + intel_crtc->cursor_width <= 0)
7506 base = 0;
7507
7508 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7509 x = -x;
7510 }
7511 pos |= x << CURSOR_X_SHIFT;
7512
7513 if (y < 0) {
7514 if (y + intel_crtc->cursor_height <= 0)
7515 base = 0;
7516
7517 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7518 y = -y;
7519 }
7520 pos |= y << CURSOR_Y_SHIFT;
7521
7522 visible = base != 0;
7523 if (!visible && !intel_crtc->cursor_visible)
7524 return;
7525
7526 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7527 I915_WRITE(CURPOS_IVB(pipe), pos);
7528 ivb_update_cursor(crtc, base);
7529 } else {
7530 I915_WRITE(CURPOS(pipe), pos);
7531 if (IS_845G(dev) || IS_I865G(dev))
7532 i845_update_cursor(crtc, base);
7533 else
7534 i9xx_update_cursor(crtc, base);
7535 }
7536 }
7537
7538 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7539 struct drm_file *file,
7540 uint32_t handle,
7541 uint32_t width, uint32_t height)
7542 {
7543 struct drm_device *dev = crtc->dev;
7544 struct drm_i915_private *dev_priv = dev->dev_private;
7545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7546 struct drm_i915_gem_object *obj;
7547 uint32_t addr;
7548 int ret;
7549
7550 /* if we want to turn off the cursor ignore width and height */
7551 if (!handle) {
7552 DRM_DEBUG_KMS("cursor off\n");
7553 addr = 0;
7554 obj = NULL;
7555 mutex_lock(&dev->struct_mutex);
7556 goto finish;
7557 }
7558
7559 /* Currently we only support 64x64 cursors */
7560 if (width != 64 || height != 64) {
7561 DRM_ERROR("we currently only support 64x64 cursors\n");
7562 return -EINVAL;
7563 }
7564
7565 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7566 if (&obj->base == NULL)
7567 return -ENOENT;
7568
7569 if (obj->base.size < width * height * 4) {
7570 DRM_ERROR("buffer is to small\n");
7571 ret = -ENOMEM;
7572 goto fail;
7573 }
7574
7575 /* we only need to pin inside GTT if cursor is non-phy */
7576 mutex_lock(&dev->struct_mutex);
7577 if (!dev_priv->info->cursor_needs_physical) {
7578 unsigned alignment;
7579
7580 if (obj->tiling_mode) {
7581 DRM_ERROR("cursor cannot be tiled\n");
7582 ret = -EINVAL;
7583 goto fail_locked;
7584 }
7585
7586 /* Note that the w/a also requires 2 PTE of padding following
7587 * the bo. We currently fill all unused PTE with the shadow
7588 * page and so we should always have valid PTE following the
7589 * cursor preventing the VT-d warning.
7590 */
7591 alignment = 0;
7592 if (need_vtd_wa(dev))
7593 alignment = 64*1024;
7594
7595 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7596 if (ret) {
7597 DRM_ERROR("failed to move cursor bo into the GTT\n");
7598 goto fail_locked;
7599 }
7600
7601 ret = i915_gem_object_put_fence(obj);
7602 if (ret) {
7603 DRM_ERROR("failed to release fence for cursor");
7604 goto fail_unpin;
7605 }
7606
7607 addr = i915_gem_obj_ggtt_offset(obj);
7608 } else {
7609 int align = IS_I830(dev) ? 16 * 1024 : 256;
7610 ret = i915_gem_attach_phys_object(dev, obj,
7611 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7612 align);
7613 if (ret) {
7614 DRM_ERROR("failed to attach phys object\n");
7615 goto fail_locked;
7616 }
7617 addr = obj->phys_obj->handle->busaddr;
7618 }
7619
7620 if (IS_GEN2(dev))
7621 I915_WRITE(CURSIZE, (height << 12) | width);
7622
7623 finish:
7624 if (intel_crtc->cursor_bo) {
7625 if (dev_priv->info->cursor_needs_physical) {
7626 if (intel_crtc->cursor_bo != obj)
7627 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7628 } else
7629 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7630 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7631 }
7632
7633 mutex_unlock(&dev->struct_mutex);
7634
7635 intel_crtc->cursor_addr = addr;
7636 intel_crtc->cursor_bo = obj;
7637 intel_crtc->cursor_width = width;
7638 intel_crtc->cursor_height = height;
7639
7640 if (intel_crtc->active)
7641 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7642
7643 return 0;
7644 fail_unpin:
7645 i915_gem_object_unpin_from_display_plane(obj);
7646 fail_locked:
7647 mutex_unlock(&dev->struct_mutex);
7648 fail:
7649 drm_gem_object_unreference_unlocked(&obj->base);
7650 return ret;
7651 }
7652
7653 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7654 {
7655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7656
7657 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7658 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7659
7660 if (intel_crtc->active)
7661 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7662
7663 return 0;
7664 }
7665
7666 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7667 u16 *blue, uint32_t start, uint32_t size)
7668 {
7669 int end = (start + size > 256) ? 256 : start + size, i;
7670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7671
7672 for (i = start; i < end; i++) {
7673 intel_crtc->lut_r[i] = red[i] >> 8;
7674 intel_crtc->lut_g[i] = green[i] >> 8;
7675 intel_crtc->lut_b[i] = blue[i] >> 8;
7676 }
7677
7678 intel_crtc_load_lut(crtc);
7679 }
7680
7681 /* VESA 640x480x72Hz mode to set on the pipe */
7682 static struct drm_display_mode load_detect_mode = {
7683 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7684 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7685 };
7686
7687 static struct drm_framebuffer *
7688 intel_framebuffer_create(struct drm_device *dev,
7689 struct drm_mode_fb_cmd2 *mode_cmd,
7690 struct drm_i915_gem_object *obj)
7691 {
7692 struct intel_framebuffer *intel_fb;
7693 int ret;
7694
7695 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7696 if (!intel_fb) {
7697 drm_gem_object_unreference_unlocked(&obj->base);
7698 return ERR_PTR(-ENOMEM);
7699 }
7700
7701 ret = i915_mutex_lock_interruptible(dev);
7702 if (ret)
7703 goto err;
7704
7705 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7706 mutex_unlock(&dev->struct_mutex);
7707 if (ret)
7708 goto err;
7709
7710 return &intel_fb->base;
7711 err:
7712 drm_gem_object_unreference_unlocked(&obj->base);
7713 kfree(intel_fb);
7714
7715 return ERR_PTR(ret);
7716 }
7717
7718 static u32
7719 intel_framebuffer_pitch_for_width(int width, int bpp)
7720 {
7721 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7722 return ALIGN(pitch, 64);
7723 }
7724
7725 static u32
7726 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7727 {
7728 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7729 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7730 }
7731
7732 static struct drm_framebuffer *
7733 intel_framebuffer_create_for_mode(struct drm_device *dev,
7734 struct drm_display_mode *mode,
7735 int depth, int bpp)
7736 {
7737 struct drm_i915_gem_object *obj;
7738 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7739
7740 obj = i915_gem_alloc_object(dev,
7741 intel_framebuffer_size_for_mode(mode, bpp));
7742 if (obj == NULL)
7743 return ERR_PTR(-ENOMEM);
7744
7745 mode_cmd.width = mode->hdisplay;
7746 mode_cmd.height = mode->vdisplay;
7747 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7748 bpp);
7749 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7750
7751 return intel_framebuffer_create(dev, &mode_cmd, obj);
7752 }
7753
7754 static struct drm_framebuffer *
7755 mode_fits_in_fbdev(struct drm_device *dev,
7756 struct drm_display_mode *mode)
7757 {
7758 #ifdef CONFIG_DRM_I915_FBDEV
7759 struct drm_i915_private *dev_priv = dev->dev_private;
7760 struct drm_i915_gem_object *obj;
7761 struct drm_framebuffer *fb;
7762
7763 if (dev_priv->fbdev == NULL)
7764 return NULL;
7765
7766 obj = dev_priv->fbdev->ifb.obj;
7767 if (obj == NULL)
7768 return NULL;
7769
7770 fb = &dev_priv->fbdev->ifb.base;
7771 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7772 fb->bits_per_pixel))
7773 return NULL;
7774
7775 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7776 return NULL;
7777
7778 return fb;
7779 #else
7780 return NULL;
7781 #endif
7782 }
7783
7784 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7785 struct drm_display_mode *mode,
7786 struct intel_load_detect_pipe *old)
7787 {
7788 struct intel_crtc *intel_crtc;
7789 struct intel_encoder *intel_encoder =
7790 intel_attached_encoder(connector);
7791 struct drm_crtc *possible_crtc;
7792 struct drm_encoder *encoder = &intel_encoder->base;
7793 struct drm_crtc *crtc = NULL;
7794 struct drm_device *dev = encoder->dev;
7795 struct drm_framebuffer *fb;
7796 int i = -1;
7797
7798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7799 connector->base.id, drm_get_connector_name(connector),
7800 encoder->base.id, drm_get_encoder_name(encoder));
7801
7802 /*
7803 * Algorithm gets a little messy:
7804 *
7805 * - if the connector already has an assigned crtc, use it (but make
7806 * sure it's on first)
7807 *
7808 * - try to find the first unused crtc that can drive this connector,
7809 * and use that if we find one
7810 */
7811
7812 /* See if we already have a CRTC for this connector */
7813 if (encoder->crtc) {
7814 crtc = encoder->crtc;
7815
7816 mutex_lock(&crtc->mutex);
7817
7818 old->dpms_mode = connector->dpms;
7819 old->load_detect_temp = false;
7820
7821 /* Make sure the crtc and connector are running */
7822 if (connector->dpms != DRM_MODE_DPMS_ON)
7823 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7824
7825 return true;
7826 }
7827
7828 /* Find an unused one (if possible) */
7829 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7830 i++;
7831 if (!(encoder->possible_crtcs & (1 << i)))
7832 continue;
7833 if (!possible_crtc->enabled) {
7834 crtc = possible_crtc;
7835 break;
7836 }
7837 }
7838
7839 /*
7840 * If we didn't find an unused CRTC, don't use any.
7841 */
7842 if (!crtc) {
7843 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7844 return false;
7845 }
7846
7847 mutex_lock(&crtc->mutex);
7848 intel_encoder->new_crtc = to_intel_crtc(crtc);
7849 to_intel_connector(connector)->new_encoder = intel_encoder;
7850
7851 intel_crtc = to_intel_crtc(crtc);
7852 old->dpms_mode = connector->dpms;
7853 old->load_detect_temp = true;
7854 old->release_fb = NULL;
7855
7856 if (!mode)
7857 mode = &load_detect_mode;
7858
7859 /* We need a framebuffer large enough to accommodate all accesses
7860 * that the plane may generate whilst we perform load detection.
7861 * We can not rely on the fbcon either being present (we get called
7862 * during its initialisation to detect all boot displays, or it may
7863 * not even exist) or that it is large enough to satisfy the
7864 * requested mode.
7865 */
7866 fb = mode_fits_in_fbdev(dev, mode);
7867 if (fb == NULL) {
7868 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7869 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7870 old->release_fb = fb;
7871 } else
7872 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7873 if (IS_ERR(fb)) {
7874 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7875 mutex_unlock(&crtc->mutex);
7876 return false;
7877 }
7878
7879 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7880 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7881 if (old->release_fb)
7882 old->release_fb->funcs->destroy(old->release_fb);
7883 mutex_unlock(&crtc->mutex);
7884 return false;
7885 }
7886
7887 /* let the connector get through one full cycle before testing */
7888 intel_wait_for_vblank(dev, intel_crtc->pipe);
7889 return true;
7890 }
7891
7892 void intel_release_load_detect_pipe(struct drm_connector *connector,
7893 struct intel_load_detect_pipe *old)
7894 {
7895 struct intel_encoder *intel_encoder =
7896 intel_attached_encoder(connector);
7897 struct drm_encoder *encoder = &intel_encoder->base;
7898 struct drm_crtc *crtc = encoder->crtc;
7899
7900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7901 connector->base.id, drm_get_connector_name(connector),
7902 encoder->base.id, drm_get_encoder_name(encoder));
7903
7904 if (old->load_detect_temp) {
7905 to_intel_connector(connector)->new_encoder = NULL;
7906 intel_encoder->new_crtc = NULL;
7907 intel_set_mode(crtc, NULL, 0, 0, NULL);
7908
7909 if (old->release_fb) {
7910 drm_framebuffer_unregister_private(old->release_fb);
7911 drm_framebuffer_unreference(old->release_fb);
7912 }
7913
7914 mutex_unlock(&crtc->mutex);
7915 return;
7916 }
7917
7918 /* Switch crtc and encoder back off if necessary */
7919 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7920 connector->funcs->dpms(connector, old->dpms_mode);
7921
7922 mutex_unlock(&crtc->mutex);
7923 }
7924
7925 static int i9xx_pll_refclk(struct drm_device *dev,
7926 const struct intel_crtc_config *pipe_config)
7927 {
7928 struct drm_i915_private *dev_priv = dev->dev_private;
7929 u32 dpll = pipe_config->dpll_hw_state.dpll;
7930
7931 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7932 return dev_priv->vbt.lvds_ssc_freq;
7933 else if (HAS_PCH_SPLIT(dev))
7934 return 120000;
7935 else if (!IS_GEN2(dev))
7936 return 96000;
7937 else
7938 return 48000;
7939 }
7940
7941 /* Returns the clock of the currently programmed mode of the given pipe. */
7942 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7943 struct intel_crtc_config *pipe_config)
7944 {
7945 struct drm_device *dev = crtc->base.dev;
7946 struct drm_i915_private *dev_priv = dev->dev_private;
7947 int pipe = pipe_config->cpu_transcoder;
7948 u32 dpll = pipe_config->dpll_hw_state.dpll;
7949 u32 fp;
7950 intel_clock_t clock;
7951 int refclk = i9xx_pll_refclk(dev, pipe_config);
7952
7953 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7954 fp = pipe_config->dpll_hw_state.fp0;
7955 else
7956 fp = pipe_config->dpll_hw_state.fp1;
7957
7958 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7959 if (IS_PINEVIEW(dev)) {
7960 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7961 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7962 } else {
7963 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7964 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7965 }
7966
7967 if (!IS_GEN2(dev)) {
7968 if (IS_PINEVIEW(dev))
7969 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7970 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7971 else
7972 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7973 DPLL_FPA01_P1_POST_DIV_SHIFT);
7974
7975 switch (dpll & DPLL_MODE_MASK) {
7976 case DPLLB_MODE_DAC_SERIAL:
7977 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7978 5 : 10;
7979 break;
7980 case DPLLB_MODE_LVDS:
7981 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7982 7 : 14;
7983 break;
7984 default:
7985 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7986 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7987 return;
7988 }
7989
7990 if (IS_PINEVIEW(dev))
7991 pineview_clock(refclk, &clock);
7992 else
7993 i9xx_clock(refclk, &clock);
7994 } else {
7995 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
7996 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7997
7998 if (is_lvds) {
7999 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8000 DPLL_FPA01_P1_POST_DIV_SHIFT);
8001
8002 if (lvds & LVDS_CLKB_POWER_UP)
8003 clock.p2 = 7;
8004 else
8005 clock.p2 = 14;
8006 } else {
8007 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8008 clock.p1 = 2;
8009 else {
8010 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8011 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8012 }
8013 if (dpll & PLL_P2_DIVIDE_BY_4)
8014 clock.p2 = 4;
8015 else
8016 clock.p2 = 2;
8017 }
8018
8019 i9xx_clock(refclk, &clock);
8020 }
8021
8022 /*
8023 * This value includes pixel_multiplier. We will use
8024 * port_clock to compute adjusted_mode.crtc_clock in the
8025 * encoder's get_config() function.
8026 */
8027 pipe_config->port_clock = clock.dot;
8028 }
8029
8030 int intel_dotclock_calculate(int link_freq,
8031 const struct intel_link_m_n *m_n)
8032 {
8033 /*
8034 * The calculation for the data clock is:
8035 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8036 * But we want to avoid losing precison if possible, so:
8037 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8038 *
8039 * and the link clock is simpler:
8040 * link_clock = (m * link_clock) / n
8041 */
8042
8043 if (!m_n->link_n)
8044 return 0;
8045
8046 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8047 }
8048
8049 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8050 struct intel_crtc_config *pipe_config)
8051 {
8052 struct drm_device *dev = crtc->base.dev;
8053
8054 /* read out port_clock from the DPLL */
8055 i9xx_crtc_clock_get(crtc, pipe_config);
8056
8057 /*
8058 * This value does not include pixel_multiplier.
8059 * We will check that port_clock and adjusted_mode.crtc_clock
8060 * agree once we know their relationship in the encoder's
8061 * get_config() function.
8062 */
8063 pipe_config->adjusted_mode.crtc_clock =
8064 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8065 &pipe_config->fdi_m_n);
8066 }
8067
8068 /** Returns the currently programmed mode of the given pipe. */
8069 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8070 struct drm_crtc *crtc)
8071 {
8072 struct drm_i915_private *dev_priv = dev->dev_private;
8073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8074 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8075 struct drm_display_mode *mode;
8076 struct intel_crtc_config pipe_config;
8077 int htot = I915_READ(HTOTAL(cpu_transcoder));
8078 int hsync = I915_READ(HSYNC(cpu_transcoder));
8079 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8080 int vsync = I915_READ(VSYNC(cpu_transcoder));
8081 enum pipe pipe = intel_crtc->pipe;
8082
8083 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8084 if (!mode)
8085 return NULL;
8086
8087 /*
8088 * Construct a pipe_config sufficient for getting the clock info
8089 * back out of crtc_clock_get.
8090 *
8091 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8092 * to use a real value here instead.
8093 */
8094 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8095 pipe_config.pixel_multiplier = 1;
8096 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8097 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8098 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8099 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8100
8101 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8102 mode->hdisplay = (htot & 0xffff) + 1;
8103 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8104 mode->hsync_start = (hsync & 0xffff) + 1;
8105 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8106 mode->vdisplay = (vtot & 0xffff) + 1;
8107 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8108 mode->vsync_start = (vsync & 0xffff) + 1;
8109 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8110
8111 drm_mode_set_name(mode);
8112
8113 return mode;
8114 }
8115
8116 static void intel_increase_pllclock(struct drm_crtc *crtc)
8117 {
8118 struct drm_device *dev = crtc->dev;
8119 drm_i915_private_t *dev_priv = dev->dev_private;
8120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8121 int pipe = intel_crtc->pipe;
8122 int dpll_reg = DPLL(pipe);
8123 int dpll;
8124
8125 if (HAS_PCH_SPLIT(dev))
8126 return;
8127
8128 if (!dev_priv->lvds_downclock_avail)
8129 return;
8130
8131 dpll = I915_READ(dpll_reg);
8132 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8133 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8134
8135 assert_panel_unlocked(dev_priv, pipe);
8136
8137 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8138 I915_WRITE(dpll_reg, dpll);
8139 intel_wait_for_vblank(dev, pipe);
8140
8141 dpll = I915_READ(dpll_reg);
8142 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8143 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8144 }
8145 }
8146
8147 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8148 {
8149 struct drm_device *dev = crtc->dev;
8150 drm_i915_private_t *dev_priv = dev->dev_private;
8151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8152
8153 if (HAS_PCH_SPLIT(dev))
8154 return;
8155
8156 if (!dev_priv->lvds_downclock_avail)
8157 return;
8158
8159 /*
8160 * Since this is called by a timer, we should never get here in
8161 * the manual case.
8162 */
8163 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8164 int pipe = intel_crtc->pipe;
8165 int dpll_reg = DPLL(pipe);
8166 int dpll;
8167
8168 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8169
8170 assert_panel_unlocked(dev_priv, pipe);
8171
8172 dpll = I915_READ(dpll_reg);
8173 dpll |= DISPLAY_RATE_SELECT_FPA1;
8174 I915_WRITE(dpll_reg, dpll);
8175 intel_wait_for_vblank(dev, pipe);
8176 dpll = I915_READ(dpll_reg);
8177 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8178 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8179 }
8180
8181 }
8182
8183 void intel_mark_busy(struct drm_device *dev)
8184 {
8185 struct drm_i915_private *dev_priv = dev->dev_private;
8186
8187 hsw_package_c8_gpu_busy(dev_priv);
8188 i915_update_gfx_val(dev_priv);
8189 }
8190
8191 void intel_mark_idle(struct drm_device *dev)
8192 {
8193 struct drm_i915_private *dev_priv = dev->dev_private;
8194 struct drm_crtc *crtc;
8195
8196 hsw_package_c8_gpu_idle(dev_priv);
8197
8198 if (!i915_powersave)
8199 return;
8200
8201 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8202 if (!crtc->fb)
8203 continue;
8204
8205 intel_decrease_pllclock(crtc);
8206 }
8207
8208 if (dev_priv->info->gen >= 6)
8209 gen6_rps_idle(dev->dev_private);
8210 }
8211
8212 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8213 struct intel_ring_buffer *ring)
8214 {
8215 struct drm_device *dev = obj->base.dev;
8216 struct drm_crtc *crtc;
8217
8218 if (!i915_powersave)
8219 return;
8220
8221 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8222 if (!crtc->fb)
8223 continue;
8224
8225 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8226 continue;
8227
8228 intel_increase_pllclock(crtc);
8229 if (ring && intel_fbc_enabled(dev))
8230 ring->fbc_dirty = true;
8231 }
8232 }
8233
8234 static void intel_crtc_destroy(struct drm_crtc *crtc)
8235 {
8236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8237 struct drm_device *dev = crtc->dev;
8238 struct intel_unpin_work *work;
8239 unsigned long flags;
8240
8241 spin_lock_irqsave(&dev->event_lock, flags);
8242 work = intel_crtc->unpin_work;
8243 intel_crtc->unpin_work = NULL;
8244 spin_unlock_irqrestore(&dev->event_lock, flags);
8245
8246 if (work) {
8247 cancel_work_sync(&work->work);
8248 kfree(work);
8249 }
8250
8251 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8252
8253 drm_crtc_cleanup(crtc);
8254
8255 kfree(intel_crtc);
8256 }
8257
8258 static void intel_unpin_work_fn(struct work_struct *__work)
8259 {
8260 struct intel_unpin_work *work =
8261 container_of(__work, struct intel_unpin_work, work);
8262 struct drm_device *dev = work->crtc->dev;
8263
8264 mutex_lock(&dev->struct_mutex);
8265 intel_unpin_fb_obj(work->old_fb_obj);
8266 drm_gem_object_unreference(&work->pending_flip_obj->base);
8267 drm_gem_object_unreference(&work->old_fb_obj->base);
8268
8269 intel_update_fbc(dev);
8270 mutex_unlock(&dev->struct_mutex);
8271
8272 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8273 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8274
8275 kfree(work);
8276 }
8277
8278 static void do_intel_finish_page_flip(struct drm_device *dev,
8279 struct drm_crtc *crtc)
8280 {
8281 drm_i915_private_t *dev_priv = dev->dev_private;
8282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8283 struct intel_unpin_work *work;
8284 unsigned long flags;
8285
8286 /* Ignore early vblank irqs */
8287 if (intel_crtc == NULL)
8288 return;
8289
8290 spin_lock_irqsave(&dev->event_lock, flags);
8291 work = intel_crtc->unpin_work;
8292
8293 /* Ensure we don't miss a work->pending update ... */
8294 smp_rmb();
8295
8296 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8297 spin_unlock_irqrestore(&dev->event_lock, flags);
8298 return;
8299 }
8300
8301 /* and that the unpin work is consistent wrt ->pending. */
8302 smp_rmb();
8303
8304 intel_crtc->unpin_work = NULL;
8305
8306 if (work->event)
8307 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8308
8309 drm_vblank_put(dev, intel_crtc->pipe);
8310
8311 spin_unlock_irqrestore(&dev->event_lock, flags);
8312
8313 wake_up_all(&dev_priv->pending_flip_queue);
8314
8315 queue_work(dev_priv->wq, &work->work);
8316
8317 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8318 }
8319
8320 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8321 {
8322 drm_i915_private_t *dev_priv = dev->dev_private;
8323 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8324
8325 do_intel_finish_page_flip(dev, crtc);
8326 }
8327
8328 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8329 {
8330 drm_i915_private_t *dev_priv = dev->dev_private;
8331 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8332
8333 do_intel_finish_page_flip(dev, crtc);
8334 }
8335
8336 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8337 {
8338 drm_i915_private_t *dev_priv = dev->dev_private;
8339 struct intel_crtc *intel_crtc =
8340 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8341 unsigned long flags;
8342
8343 /* NB: An MMIO update of the plane base pointer will also
8344 * generate a page-flip completion irq, i.e. every modeset
8345 * is also accompanied by a spurious intel_prepare_page_flip().
8346 */
8347 spin_lock_irqsave(&dev->event_lock, flags);
8348 if (intel_crtc->unpin_work)
8349 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8350 spin_unlock_irqrestore(&dev->event_lock, flags);
8351 }
8352
8353 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8354 {
8355 /* Ensure that the work item is consistent when activating it ... */
8356 smp_wmb();
8357 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8358 /* and that it is marked active as soon as the irq could fire. */
8359 smp_wmb();
8360 }
8361
8362 static int intel_gen2_queue_flip(struct drm_device *dev,
8363 struct drm_crtc *crtc,
8364 struct drm_framebuffer *fb,
8365 struct drm_i915_gem_object *obj,
8366 uint32_t flags)
8367 {
8368 struct drm_i915_private *dev_priv = dev->dev_private;
8369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8370 u32 flip_mask;
8371 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8372 int ret;
8373
8374 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8375 if (ret)
8376 goto err;
8377
8378 ret = intel_ring_begin(ring, 6);
8379 if (ret)
8380 goto err_unpin;
8381
8382 /* Can't queue multiple flips, so wait for the previous
8383 * one to finish before executing the next.
8384 */
8385 if (intel_crtc->plane)
8386 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8387 else
8388 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8389 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8390 intel_ring_emit(ring, MI_NOOP);
8391 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8392 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8393 intel_ring_emit(ring, fb->pitches[0]);
8394 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8395 intel_ring_emit(ring, 0); /* aux display base address, unused */
8396
8397 intel_mark_page_flip_active(intel_crtc);
8398 __intel_ring_advance(ring);
8399 return 0;
8400
8401 err_unpin:
8402 intel_unpin_fb_obj(obj);
8403 err:
8404 return ret;
8405 }
8406
8407 static int intel_gen3_queue_flip(struct drm_device *dev,
8408 struct drm_crtc *crtc,
8409 struct drm_framebuffer *fb,
8410 struct drm_i915_gem_object *obj,
8411 uint32_t flags)
8412 {
8413 struct drm_i915_private *dev_priv = dev->dev_private;
8414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8415 u32 flip_mask;
8416 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8417 int ret;
8418
8419 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8420 if (ret)
8421 goto err;
8422
8423 ret = intel_ring_begin(ring, 6);
8424 if (ret)
8425 goto err_unpin;
8426
8427 if (intel_crtc->plane)
8428 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8429 else
8430 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8431 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8432 intel_ring_emit(ring, MI_NOOP);
8433 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8434 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8435 intel_ring_emit(ring, fb->pitches[0]);
8436 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8437 intel_ring_emit(ring, MI_NOOP);
8438
8439 intel_mark_page_flip_active(intel_crtc);
8440 __intel_ring_advance(ring);
8441 return 0;
8442
8443 err_unpin:
8444 intel_unpin_fb_obj(obj);
8445 err:
8446 return ret;
8447 }
8448
8449 static int intel_gen4_queue_flip(struct drm_device *dev,
8450 struct drm_crtc *crtc,
8451 struct drm_framebuffer *fb,
8452 struct drm_i915_gem_object *obj,
8453 uint32_t flags)
8454 {
8455 struct drm_i915_private *dev_priv = dev->dev_private;
8456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8457 uint32_t pf, pipesrc;
8458 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8459 int ret;
8460
8461 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8462 if (ret)
8463 goto err;
8464
8465 ret = intel_ring_begin(ring, 4);
8466 if (ret)
8467 goto err_unpin;
8468
8469 /* i965+ uses the linear or tiled offsets from the
8470 * Display Registers (which do not change across a page-flip)
8471 * so we need only reprogram the base address.
8472 */
8473 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8474 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8475 intel_ring_emit(ring, fb->pitches[0]);
8476 intel_ring_emit(ring,
8477 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8478 obj->tiling_mode);
8479
8480 /* XXX Enabling the panel-fitter across page-flip is so far
8481 * untested on non-native modes, so ignore it for now.
8482 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8483 */
8484 pf = 0;
8485 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8486 intel_ring_emit(ring, pf | pipesrc);
8487
8488 intel_mark_page_flip_active(intel_crtc);
8489 __intel_ring_advance(ring);
8490 return 0;
8491
8492 err_unpin:
8493 intel_unpin_fb_obj(obj);
8494 err:
8495 return ret;
8496 }
8497
8498 static int intel_gen6_queue_flip(struct drm_device *dev,
8499 struct drm_crtc *crtc,
8500 struct drm_framebuffer *fb,
8501 struct drm_i915_gem_object *obj,
8502 uint32_t flags)
8503 {
8504 struct drm_i915_private *dev_priv = dev->dev_private;
8505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8506 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8507 uint32_t pf, pipesrc;
8508 int ret;
8509
8510 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8511 if (ret)
8512 goto err;
8513
8514 ret = intel_ring_begin(ring, 4);
8515 if (ret)
8516 goto err_unpin;
8517
8518 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8519 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8520 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8521 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8522
8523 /* Contrary to the suggestions in the documentation,
8524 * "Enable Panel Fitter" does not seem to be required when page
8525 * flipping with a non-native mode, and worse causes a normal
8526 * modeset to fail.
8527 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8528 */
8529 pf = 0;
8530 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8531 intel_ring_emit(ring, pf | pipesrc);
8532
8533 intel_mark_page_flip_active(intel_crtc);
8534 __intel_ring_advance(ring);
8535 return 0;
8536
8537 err_unpin:
8538 intel_unpin_fb_obj(obj);
8539 err:
8540 return ret;
8541 }
8542
8543 static int intel_gen7_queue_flip(struct drm_device *dev,
8544 struct drm_crtc *crtc,
8545 struct drm_framebuffer *fb,
8546 struct drm_i915_gem_object *obj,
8547 uint32_t flags)
8548 {
8549 struct drm_i915_private *dev_priv = dev->dev_private;
8550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8551 struct intel_ring_buffer *ring;
8552 uint32_t plane_bit = 0;
8553 int len, ret;
8554
8555 ring = obj->ring;
8556 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8557 ring = &dev_priv->ring[BCS];
8558
8559 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8560 if (ret)
8561 goto err;
8562
8563 switch(intel_crtc->plane) {
8564 case PLANE_A:
8565 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8566 break;
8567 case PLANE_B:
8568 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8569 break;
8570 case PLANE_C:
8571 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8572 break;
8573 default:
8574 WARN_ONCE(1, "unknown plane in flip command\n");
8575 ret = -ENODEV;
8576 goto err_unpin;
8577 }
8578
8579 len = 4;
8580 if (ring->id == RCS)
8581 len += 6;
8582
8583 ret = intel_ring_begin(ring, len);
8584 if (ret)
8585 goto err_unpin;
8586
8587 /* Unmask the flip-done completion message. Note that the bspec says that
8588 * we should do this for both the BCS and RCS, and that we must not unmask
8589 * more than one flip event at any time (or ensure that one flip message
8590 * can be sent by waiting for flip-done prior to queueing new flips).
8591 * Experimentation says that BCS works despite DERRMR masking all
8592 * flip-done completion events and that unmasking all planes at once
8593 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8594 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8595 */
8596 if (ring->id == RCS) {
8597 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8598 intel_ring_emit(ring, DERRMR);
8599 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8600 DERRMR_PIPEB_PRI_FLIP_DONE |
8601 DERRMR_PIPEC_PRI_FLIP_DONE));
8602 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8603 MI_SRM_LRM_GLOBAL_GTT);
8604 intel_ring_emit(ring, DERRMR);
8605 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8606 }
8607
8608 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8609 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8610 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8611 intel_ring_emit(ring, (MI_NOOP));
8612
8613 intel_mark_page_flip_active(intel_crtc);
8614 __intel_ring_advance(ring);
8615 return 0;
8616
8617 err_unpin:
8618 intel_unpin_fb_obj(obj);
8619 err:
8620 return ret;
8621 }
8622
8623 static int intel_default_queue_flip(struct drm_device *dev,
8624 struct drm_crtc *crtc,
8625 struct drm_framebuffer *fb,
8626 struct drm_i915_gem_object *obj,
8627 uint32_t flags)
8628 {
8629 return -ENODEV;
8630 }
8631
8632 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8633 struct drm_framebuffer *fb,
8634 struct drm_pending_vblank_event *event,
8635 uint32_t page_flip_flags)
8636 {
8637 struct drm_device *dev = crtc->dev;
8638 struct drm_i915_private *dev_priv = dev->dev_private;
8639 struct drm_framebuffer *old_fb = crtc->fb;
8640 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8642 struct intel_unpin_work *work;
8643 unsigned long flags;
8644 int ret;
8645
8646 /* Can't change pixel format via MI display flips. */
8647 if (fb->pixel_format != crtc->fb->pixel_format)
8648 return -EINVAL;
8649
8650 /*
8651 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8652 * Note that pitch changes could also affect these register.
8653 */
8654 if (INTEL_INFO(dev)->gen > 3 &&
8655 (fb->offsets[0] != crtc->fb->offsets[0] ||
8656 fb->pitches[0] != crtc->fb->pitches[0]))
8657 return -EINVAL;
8658
8659 work = kzalloc(sizeof(*work), GFP_KERNEL);
8660 if (work == NULL)
8661 return -ENOMEM;
8662
8663 work->event = event;
8664 work->crtc = crtc;
8665 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8666 INIT_WORK(&work->work, intel_unpin_work_fn);
8667
8668 ret = drm_vblank_get(dev, intel_crtc->pipe);
8669 if (ret)
8670 goto free_work;
8671
8672 /* We borrow the event spin lock for protecting unpin_work */
8673 spin_lock_irqsave(&dev->event_lock, flags);
8674 if (intel_crtc->unpin_work) {
8675 spin_unlock_irqrestore(&dev->event_lock, flags);
8676 kfree(work);
8677 drm_vblank_put(dev, intel_crtc->pipe);
8678
8679 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8680 return -EBUSY;
8681 }
8682 intel_crtc->unpin_work = work;
8683 spin_unlock_irqrestore(&dev->event_lock, flags);
8684
8685 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8686 flush_workqueue(dev_priv->wq);
8687
8688 ret = i915_mutex_lock_interruptible(dev);
8689 if (ret)
8690 goto cleanup;
8691
8692 /* Reference the objects for the scheduled work. */
8693 drm_gem_object_reference(&work->old_fb_obj->base);
8694 drm_gem_object_reference(&obj->base);
8695
8696 crtc->fb = fb;
8697
8698 work->pending_flip_obj = obj;
8699
8700 work->enable_stall_check = true;
8701
8702 atomic_inc(&intel_crtc->unpin_work_count);
8703 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8704
8705 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8706 if (ret)
8707 goto cleanup_pending;
8708
8709 intel_disable_fbc(dev);
8710 intel_mark_fb_busy(obj, NULL);
8711 mutex_unlock(&dev->struct_mutex);
8712
8713 trace_i915_flip_request(intel_crtc->plane, obj);
8714
8715 return 0;
8716
8717 cleanup_pending:
8718 atomic_dec(&intel_crtc->unpin_work_count);
8719 crtc->fb = old_fb;
8720 drm_gem_object_unreference(&work->old_fb_obj->base);
8721 drm_gem_object_unreference(&obj->base);
8722 mutex_unlock(&dev->struct_mutex);
8723
8724 cleanup:
8725 spin_lock_irqsave(&dev->event_lock, flags);
8726 intel_crtc->unpin_work = NULL;
8727 spin_unlock_irqrestore(&dev->event_lock, flags);
8728
8729 drm_vblank_put(dev, intel_crtc->pipe);
8730 free_work:
8731 kfree(work);
8732
8733 return ret;
8734 }
8735
8736 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8737 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8738 .load_lut = intel_crtc_load_lut,
8739 };
8740
8741 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8742 struct drm_crtc *crtc)
8743 {
8744 struct drm_device *dev;
8745 struct drm_crtc *tmp;
8746 int crtc_mask = 1;
8747
8748 WARN(!crtc, "checking null crtc?\n");
8749
8750 dev = crtc->dev;
8751
8752 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8753 if (tmp == crtc)
8754 break;
8755 crtc_mask <<= 1;
8756 }
8757
8758 if (encoder->possible_crtcs & crtc_mask)
8759 return true;
8760 return false;
8761 }
8762
8763 /**
8764 * intel_modeset_update_staged_output_state
8765 *
8766 * Updates the staged output configuration state, e.g. after we've read out the
8767 * current hw state.
8768 */
8769 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8770 {
8771 struct intel_crtc *crtc;
8772 struct intel_encoder *encoder;
8773 struct intel_connector *connector;
8774
8775 list_for_each_entry(connector, &dev->mode_config.connector_list,
8776 base.head) {
8777 connector->new_encoder =
8778 to_intel_encoder(connector->base.encoder);
8779 }
8780
8781 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8782 base.head) {
8783 encoder->new_crtc =
8784 to_intel_crtc(encoder->base.crtc);
8785 }
8786
8787 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8788 base.head) {
8789 crtc->new_enabled = crtc->base.enabled;
8790
8791 if (crtc->new_enabled)
8792 crtc->new_config = &crtc->config;
8793 else
8794 crtc->new_config = NULL;
8795 }
8796 }
8797
8798 /**
8799 * intel_modeset_commit_output_state
8800 *
8801 * This function copies the stage display pipe configuration to the real one.
8802 */
8803 static void intel_modeset_commit_output_state(struct drm_device *dev)
8804 {
8805 struct intel_crtc *crtc;
8806 struct intel_encoder *encoder;
8807 struct intel_connector *connector;
8808
8809 list_for_each_entry(connector, &dev->mode_config.connector_list,
8810 base.head) {
8811 connector->base.encoder = &connector->new_encoder->base;
8812 }
8813
8814 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8815 base.head) {
8816 encoder->base.crtc = &encoder->new_crtc->base;
8817 }
8818
8819 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8820 base.head) {
8821 crtc->base.enabled = crtc->new_enabled;
8822 }
8823 }
8824
8825 static void
8826 connected_sink_compute_bpp(struct intel_connector * connector,
8827 struct intel_crtc_config *pipe_config)
8828 {
8829 int bpp = pipe_config->pipe_bpp;
8830
8831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8832 connector->base.base.id,
8833 drm_get_connector_name(&connector->base));
8834
8835 /* Don't use an invalid EDID bpc value */
8836 if (connector->base.display_info.bpc &&
8837 connector->base.display_info.bpc * 3 < bpp) {
8838 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8839 bpp, connector->base.display_info.bpc*3);
8840 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8841 }
8842
8843 /* Clamp bpp to 8 on screens without EDID 1.4 */
8844 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8845 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8846 bpp);
8847 pipe_config->pipe_bpp = 24;
8848 }
8849 }
8850
8851 static int
8852 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8853 struct drm_framebuffer *fb,
8854 struct intel_crtc_config *pipe_config)
8855 {
8856 struct drm_device *dev = crtc->base.dev;
8857 struct intel_connector *connector;
8858 int bpp;
8859
8860 switch (fb->pixel_format) {
8861 case DRM_FORMAT_C8:
8862 bpp = 8*3; /* since we go through a colormap */
8863 break;
8864 case DRM_FORMAT_XRGB1555:
8865 case DRM_FORMAT_ARGB1555:
8866 /* checked in intel_framebuffer_init already */
8867 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8868 return -EINVAL;
8869 case DRM_FORMAT_RGB565:
8870 bpp = 6*3; /* min is 18bpp */
8871 break;
8872 case DRM_FORMAT_XBGR8888:
8873 case DRM_FORMAT_ABGR8888:
8874 /* checked in intel_framebuffer_init already */
8875 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8876 return -EINVAL;
8877 case DRM_FORMAT_XRGB8888:
8878 case DRM_FORMAT_ARGB8888:
8879 bpp = 8*3;
8880 break;
8881 case DRM_FORMAT_XRGB2101010:
8882 case DRM_FORMAT_ARGB2101010:
8883 case DRM_FORMAT_XBGR2101010:
8884 case DRM_FORMAT_ABGR2101010:
8885 /* checked in intel_framebuffer_init already */
8886 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8887 return -EINVAL;
8888 bpp = 10*3;
8889 break;
8890 /* TODO: gen4+ supports 16 bpc floating point, too. */
8891 default:
8892 DRM_DEBUG_KMS("unsupported depth\n");
8893 return -EINVAL;
8894 }
8895
8896 pipe_config->pipe_bpp = bpp;
8897
8898 /* Clamp display bpp to EDID value */
8899 list_for_each_entry(connector, &dev->mode_config.connector_list,
8900 base.head) {
8901 if (!connector->new_encoder ||
8902 connector->new_encoder->new_crtc != crtc)
8903 continue;
8904
8905 connected_sink_compute_bpp(connector, pipe_config);
8906 }
8907
8908 return bpp;
8909 }
8910
8911 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8912 {
8913 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8914 "type: 0x%x flags: 0x%x\n",
8915 mode->crtc_clock,
8916 mode->crtc_hdisplay, mode->crtc_hsync_start,
8917 mode->crtc_hsync_end, mode->crtc_htotal,
8918 mode->crtc_vdisplay, mode->crtc_vsync_start,
8919 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8920 }
8921
8922 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8923 struct intel_crtc_config *pipe_config,
8924 const char *context)
8925 {
8926 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8927 context, pipe_name(crtc->pipe));
8928
8929 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8930 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8931 pipe_config->pipe_bpp, pipe_config->dither);
8932 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8933 pipe_config->has_pch_encoder,
8934 pipe_config->fdi_lanes,
8935 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8936 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8937 pipe_config->fdi_m_n.tu);
8938 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8939 pipe_config->has_dp_encoder,
8940 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8941 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8942 pipe_config->dp_m_n.tu);
8943 DRM_DEBUG_KMS("requested mode:\n");
8944 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8945 DRM_DEBUG_KMS("adjusted mode:\n");
8946 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8947 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8948 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8949 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8950 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8951 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8952 pipe_config->gmch_pfit.control,
8953 pipe_config->gmch_pfit.pgm_ratios,
8954 pipe_config->gmch_pfit.lvds_border_bits);
8955 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8956 pipe_config->pch_pfit.pos,
8957 pipe_config->pch_pfit.size,
8958 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8959 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8960 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8961 }
8962
8963 static bool check_encoder_cloning(struct drm_crtc *crtc)
8964 {
8965 int num_encoders = 0;
8966 bool uncloneable_encoders = false;
8967 struct intel_encoder *encoder;
8968
8969 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8970 base.head) {
8971 if (&encoder->new_crtc->base != crtc)
8972 continue;
8973
8974 num_encoders++;
8975 if (!encoder->cloneable)
8976 uncloneable_encoders = true;
8977 }
8978
8979 return !(num_encoders > 1 && uncloneable_encoders);
8980 }
8981
8982 static struct intel_crtc_config *
8983 intel_modeset_pipe_config(struct drm_crtc *crtc,
8984 struct drm_framebuffer *fb,
8985 struct drm_display_mode *mode)
8986 {
8987 struct drm_device *dev = crtc->dev;
8988 struct intel_encoder *encoder;
8989 struct intel_crtc_config *pipe_config;
8990 int plane_bpp, ret = -EINVAL;
8991 bool retry = true;
8992
8993 if (!check_encoder_cloning(crtc)) {
8994 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8995 return ERR_PTR(-EINVAL);
8996 }
8997
8998 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8999 if (!pipe_config)
9000 return ERR_PTR(-ENOMEM);
9001
9002 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9003 drm_mode_copy(&pipe_config->requested_mode, mode);
9004
9005 pipe_config->cpu_transcoder =
9006 (enum transcoder) to_intel_crtc(crtc)->pipe;
9007 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9008
9009 /*
9010 * Sanitize sync polarity flags based on requested ones. If neither
9011 * positive or negative polarity is requested, treat this as meaning
9012 * negative polarity.
9013 */
9014 if (!(pipe_config->adjusted_mode.flags &
9015 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9016 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9017
9018 if (!(pipe_config->adjusted_mode.flags &
9019 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9020 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9021
9022 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9023 * plane pixel format and any sink constraints into account. Returns the
9024 * source plane bpp so that dithering can be selected on mismatches
9025 * after encoders and crtc also have had their say. */
9026 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9027 fb, pipe_config);
9028 if (plane_bpp < 0)
9029 goto fail;
9030
9031 /*
9032 * Determine the real pipe dimensions. Note that stereo modes can
9033 * increase the actual pipe size due to the frame doubling and
9034 * insertion of additional space for blanks between the frame. This
9035 * is stored in the crtc timings. We use the requested mode to do this
9036 * computation to clearly distinguish it from the adjusted mode, which
9037 * can be changed by the connectors in the below retry loop.
9038 */
9039 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9040 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9041 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9042
9043 encoder_retry:
9044 /* Ensure the port clock defaults are reset when retrying. */
9045 pipe_config->port_clock = 0;
9046 pipe_config->pixel_multiplier = 1;
9047
9048 /* Fill in default crtc timings, allow encoders to overwrite them. */
9049 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9050
9051 /* Pass our mode to the connectors and the CRTC to give them a chance to
9052 * adjust it according to limitations or connector properties, and also
9053 * a chance to reject the mode entirely.
9054 */
9055 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9056 base.head) {
9057
9058 if (&encoder->new_crtc->base != crtc)
9059 continue;
9060
9061 if (!(encoder->compute_config(encoder, pipe_config))) {
9062 DRM_DEBUG_KMS("Encoder config failure\n");
9063 goto fail;
9064 }
9065 }
9066
9067 /* Set default port clock if not overwritten by the encoder. Needs to be
9068 * done afterwards in case the encoder adjusts the mode. */
9069 if (!pipe_config->port_clock)
9070 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9071 * pipe_config->pixel_multiplier;
9072
9073 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9074 if (ret < 0) {
9075 DRM_DEBUG_KMS("CRTC fixup failed\n");
9076 goto fail;
9077 }
9078
9079 if (ret == RETRY) {
9080 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9081 ret = -EINVAL;
9082 goto fail;
9083 }
9084
9085 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9086 retry = false;
9087 goto encoder_retry;
9088 }
9089
9090 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9091 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9092 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9093
9094 return pipe_config;
9095 fail:
9096 kfree(pipe_config);
9097 return ERR_PTR(ret);
9098 }
9099
9100 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9101 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9102 static void
9103 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9104 unsigned *prepare_pipes, unsigned *disable_pipes)
9105 {
9106 struct intel_crtc *intel_crtc;
9107 struct drm_device *dev = crtc->dev;
9108 struct intel_encoder *encoder;
9109 struct intel_connector *connector;
9110 struct drm_crtc *tmp_crtc;
9111
9112 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9113
9114 /* Check which crtcs have changed outputs connected to them, these need
9115 * to be part of the prepare_pipes mask. We don't (yet) support global
9116 * modeset across multiple crtcs, so modeset_pipes will only have one
9117 * bit set at most. */
9118 list_for_each_entry(connector, &dev->mode_config.connector_list,
9119 base.head) {
9120 if (connector->base.encoder == &connector->new_encoder->base)
9121 continue;
9122
9123 if (connector->base.encoder) {
9124 tmp_crtc = connector->base.encoder->crtc;
9125
9126 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9127 }
9128
9129 if (connector->new_encoder)
9130 *prepare_pipes |=
9131 1 << connector->new_encoder->new_crtc->pipe;
9132 }
9133
9134 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9135 base.head) {
9136 if (encoder->base.crtc == &encoder->new_crtc->base)
9137 continue;
9138
9139 if (encoder->base.crtc) {
9140 tmp_crtc = encoder->base.crtc;
9141
9142 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9143 }
9144
9145 if (encoder->new_crtc)
9146 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9147 }
9148
9149 /* Check for pipes that will be enabled/disabled ... */
9150 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9151 base.head) {
9152 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9153 continue;
9154
9155 if (!intel_crtc->new_enabled)
9156 *disable_pipes |= 1 << intel_crtc->pipe;
9157 else
9158 *prepare_pipes |= 1 << intel_crtc->pipe;
9159 }
9160
9161
9162 /* set_mode is also used to update properties on life display pipes. */
9163 intel_crtc = to_intel_crtc(crtc);
9164 if (intel_crtc->new_enabled)
9165 *prepare_pipes |= 1 << intel_crtc->pipe;
9166
9167 /*
9168 * For simplicity do a full modeset on any pipe where the output routing
9169 * changed. We could be more clever, but that would require us to be
9170 * more careful with calling the relevant encoder->mode_set functions.
9171 */
9172 if (*prepare_pipes)
9173 *modeset_pipes = *prepare_pipes;
9174
9175 /* ... and mask these out. */
9176 *modeset_pipes &= ~(*disable_pipes);
9177 *prepare_pipes &= ~(*disable_pipes);
9178
9179 /*
9180 * HACK: We don't (yet) fully support global modesets. intel_set_config
9181 * obies this rule, but the modeset restore mode of
9182 * intel_modeset_setup_hw_state does not.
9183 */
9184 *modeset_pipes &= 1 << intel_crtc->pipe;
9185 *prepare_pipes &= 1 << intel_crtc->pipe;
9186
9187 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9188 *modeset_pipes, *prepare_pipes, *disable_pipes);
9189 }
9190
9191 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9192 {
9193 struct drm_encoder *encoder;
9194 struct drm_device *dev = crtc->dev;
9195
9196 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9197 if (encoder->crtc == crtc)
9198 return true;
9199
9200 return false;
9201 }
9202
9203 static void
9204 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9205 {
9206 struct intel_encoder *intel_encoder;
9207 struct intel_crtc *intel_crtc;
9208 struct drm_connector *connector;
9209
9210 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9211 base.head) {
9212 if (!intel_encoder->base.crtc)
9213 continue;
9214
9215 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9216
9217 if (prepare_pipes & (1 << intel_crtc->pipe))
9218 intel_encoder->connectors_active = false;
9219 }
9220
9221 intel_modeset_commit_output_state(dev);
9222
9223 /* Double check state. */
9224 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9225 base.head) {
9226 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9227 WARN_ON(intel_crtc->new_config &&
9228 intel_crtc->new_config != &intel_crtc->config);
9229 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9230 }
9231
9232 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9233 if (!connector->encoder || !connector->encoder->crtc)
9234 continue;
9235
9236 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9237
9238 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9239 struct drm_property *dpms_property =
9240 dev->mode_config.dpms_property;
9241
9242 connector->dpms = DRM_MODE_DPMS_ON;
9243 drm_object_property_set_value(&connector->base,
9244 dpms_property,
9245 DRM_MODE_DPMS_ON);
9246
9247 intel_encoder = to_intel_encoder(connector->encoder);
9248 intel_encoder->connectors_active = true;
9249 }
9250 }
9251
9252 }
9253
9254 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9255 {
9256 int diff;
9257
9258 if (clock1 == clock2)
9259 return true;
9260
9261 if (!clock1 || !clock2)
9262 return false;
9263
9264 diff = abs(clock1 - clock2);
9265
9266 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9267 return true;
9268
9269 return false;
9270 }
9271
9272 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9273 list_for_each_entry((intel_crtc), \
9274 &(dev)->mode_config.crtc_list, \
9275 base.head) \
9276 if (mask & (1 <<(intel_crtc)->pipe))
9277
9278 static bool
9279 intel_pipe_config_compare(struct drm_device *dev,
9280 struct intel_crtc_config *current_config,
9281 struct intel_crtc_config *pipe_config)
9282 {
9283 #define PIPE_CONF_CHECK_X(name) \
9284 if (current_config->name != pipe_config->name) { \
9285 DRM_ERROR("mismatch in " #name " " \
9286 "(expected 0x%08x, found 0x%08x)\n", \
9287 current_config->name, \
9288 pipe_config->name); \
9289 return false; \
9290 }
9291
9292 #define PIPE_CONF_CHECK_I(name) \
9293 if (current_config->name != pipe_config->name) { \
9294 DRM_ERROR("mismatch in " #name " " \
9295 "(expected %i, found %i)\n", \
9296 current_config->name, \
9297 pipe_config->name); \
9298 return false; \
9299 }
9300
9301 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9302 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9303 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9304 "(expected %i, found %i)\n", \
9305 current_config->name & (mask), \
9306 pipe_config->name & (mask)); \
9307 return false; \
9308 }
9309
9310 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9311 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9312 DRM_ERROR("mismatch in " #name " " \
9313 "(expected %i, found %i)\n", \
9314 current_config->name, \
9315 pipe_config->name); \
9316 return false; \
9317 }
9318
9319 #define PIPE_CONF_QUIRK(quirk) \
9320 ((current_config->quirks | pipe_config->quirks) & (quirk))
9321
9322 PIPE_CONF_CHECK_I(cpu_transcoder);
9323
9324 PIPE_CONF_CHECK_I(has_pch_encoder);
9325 PIPE_CONF_CHECK_I(fdi_lanes);
9326 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9327 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9328 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9329 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9330 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9331
9332 PIPE_CONF_CHECK_I(has_dp_encoder);
9333 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9334 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9335 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9336 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9337 PIPE_CONF_CHECK_I(dp_m_n.tu);
9338
9339 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9340 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9341 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9342 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9343 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9344 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9345
9346 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9347 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9348 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9349 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9350 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9351 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9352
9353 PIPE_CONF_CHECK_I(pixel_multiplier);
9354
9355 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9356 DRM_MODE_FLAG_INTERLACE);
9357
9358 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9359 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9360 DRM_MODE_FLAG_PHSYNC);
9361 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9362 DRM_MODE_FLAG_NHSYNC);
9363 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9364 DRM_MODE_FLAG_PVSYNC);
9365 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9366 DRM_MODE_FLAG_NVSYNC);
9367 }
9368
9369 PIPE_CONF_CHECK_I(pipe_src_w);
9370 PIPE_CONF_CHECK_I(pipe_src_h);
9371
9372 PIPE_CONF_CHECK_I(gmch_pfit.control);
9373 /* pfit ratios are autocomputed by the hw on gen4+ */
9374 if (INTEL_INFO(dev)->gen < 4)
9375 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9376 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9377 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9378 if (current_config->pch_pfit.enabled) {
9379 PIPE_CONF_CHECK_I(pch_pfit.pos);
9380 PIPE_CONF_CHECK_I(pch_pfit.size);
9381 }
9382
9383 /* BDW+ don't expose a synchronous way to read the state */
9384 if (IS_HASWELL(dev))
9385 PIPE_CONF_CHECK_I(ips_enabled);
9386
9387 PIPE_CONF_CHECK_I(double_wide);
9388
9389 PIPE_CONF_CHECK_I(shared_dpll);
9390 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9391 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9392 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9393 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9394
9395 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9396 PIPE_CONF_CHECK_I(pipe_bpp);
9397
9398 if (!HAS_DDI(dev)) {
9399 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9400 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9401 }
9402
9403 #undef PIPE_CONF_CHECK_X
9404 #undef PIPE_CONF_CHECK_I
9405 #undef PIPE_CONF_CHECK_FLAGS
9406 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9407 #undef PIPE_CONF_QUIRK
9408
9409 return true;
9410 }
9411
9412 static void
9413 check_connector_state(struct drm_device *dev)
9414 {
9415 struct intel_connector *connector;
9416
9417 list_for_each_entry(connector, &dev->mode_config.connector_list,
9418 base.head) {
9419 /* This also checks the encoder/connector hw state with the
9420 * ->get_hw_state callbacks. */
9421 intel_connector_check_state(connector);
9422
9423 WARN(&connector->new_encoder->base != connector->base.encoder,
9424 "connector's staged encoder doesn't match current encoder\n");
9425 }
9426 }
9427
9428 static void
9429 check_encoder_state(struct drm_device *dev)
9430 {
9431 struct intel_encoder *encoder;
9432 struct intel_connector *connector;
9433
9434 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9435 base.head) {
9436 bool enabled = false;
9437 bool active = false;
9438 enum pipe pipe, tracked_pipe;
9439
9440 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9441 encoder->base.base.id,
9442 drm_get_encoder_name(&encoder->base));
9443
9444 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9445 "encoder's stage crtc doesn't match current crtc\n");
9446 WARN(encoder->connectors_active && !encoder->base.crtc,
9447 "encoder's active_connectors set, but no crtc\n");
9448
9449 list_for_each_entry(connector, &dev->mode_config.connector_list,
9450 base.head) {
9451 if (connector->base.encoder != &encoder->base)
9452 continue;
9453 enabled = true;
9454 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9455 active = true;
9456 }
9457 WARN(!!encoder->base.crtc != enabled,
9458 "encoder's enabled state mismatch "
9459 "(expected %i, found %i)\n",
9460 !!encoder->base.crtc, enabled);
9461 WARN(active && !encoder->base.crtc,
9462 "active encoder with no crtc\n");
9463
9464 WARN(encoder->connectors_active != active,
9465 "encoder's computed active state doesn't match tracked active state "
9466 "(expected %i, found %i)\n", active, encoder->connectors_active);
9467
9468 active = encoder->get_hw_state(encoder, &pipe);
9469 WARN(active != encoder->connectors_active,
9470 "encoder's hw state doesn't match sw tracking "
9471 "(expected %i, found %i)\n",
9472 encoder->connectors_active, active);
9473
9474 if (!encoder->base.crtc)
9475 continue;
9476
9477 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9478 WARN(active && pipe != tracked_pipe,
9479 "active encoder's pipe doesn't match"
9480 "(expected %i, found %i)\n",
9481 tracked_pipe, pipe);
9482
9483 }
9484 }
9485
9486 static void
9487 check_crtc_state(struct drm_device *dev)
9488 {
9489 drm_i915_private_t *dev_priv = dev->dev_private;
9490 struct intel_crtc *crtc;
9491 struct intel_encoder *encoder;
9492 struct intel_crtc_config pipe_config;
9493
9494 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9495 base.head) {
9496 bool enabled = false;
9497 bool active = false;
9498
9499 memset(&pipe_config, 0, sizeof(pipe_config));
9500
9501 DRM_DEBUG_KMS("[CRTC:%d]\n",
9502 crtc->base.base.id);
9503
9504 WARN(crtc->active && !crtc->base.enabled,
9505 "active crtc, but not enabled in sw tracking\n");
9506
9507 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9508 base.head) {
9509 if (encoder->base.crtc != &crtc->base)
9510 continue;
9511 enabled = true;
9512 if (encoder->connectors_active)
9513 active = true;
9514 }
9515
9516 WARN(active != crtc->active,
9517 "crtc's computed active state doesn't match tracked active state "
9518 "(expected %i, found %i)\n", active, crtc->active);
9519 WARN(enabled != crtc->base.enabled,
9520 "crtc's computed enabled state doesn't match tracked enabled state "
9521 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9522
9523 active = dev_priv->display.get_pipe_config(crtc,
9524 &pipe_config);
9525
9526 /* hw state is inconsistent with the pipe A quirk */
9527 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9528 active = crtc->active;
9529
9530 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9531 base.head) {
9532 enum pipe pipe;
9533 if (encoder->base.crtc != &crtc->base)
9534 continue;
9535 if (encoder->get_hw_state(encoder, &pipe))
9536 encoder->get_config(encoder, &pipe_config);
9537 }
9538
9539 WARN(crtc->active != active,
9540 "crtc active state doesn't match with hw state "
9541 "(expected %i, found %i)\n", crtc->active, active);
9542
9543 if (active &&
9544 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9545 WARN(1, "pipe state doesn't match!\n");
9546 intel_dump_pipe_config(crtc, &pipe_config,
9547 "[hw state]");
9548 intel_dump_pipe_config(crtc, &crtc->config,
9549 "[sw state]");
9550 }
9551 }
9552 }
9553
9554 static void
9555 check_shared_dpll_state(struct drm_device *dev)
9556 {
9557 drm_i915_private_t *dev_priv = dev->dev_private;
9558 struct intel_crtc *crtc;
9559 struct intel_dpll_hw_state dpll_hw_state;
9560 int i;
9561
9562 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9563 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9564 int enabled_crtcs = 0, active_crtcs = 0;
9565 bool active;
9566
9567 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9568
9569 DRM_DEBUG_KMS("%s\n", pll->name);
9570
9571 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9572
9573 WARN(pll->active > pll->refcount,
9574 "more active pll users than references: %i vs %i\n",
9575 pll->active, pll->refcount);
9576 WARN(pll->active && !pll->on,
9577 "pll in active use but not on in sw tracking\n");
9578 WARN(pll->on && !pll->active,
9579 "pll in on but not on in use in sw tracking\n");
9580 WARN(pll->on != active,
9581 "pll on state mismatch (expected %i, found %i)\n",
9582 pll->on, active);
9583
9584 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9585 base.head) {
9586 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9587 enabled_crtcs++;
9588 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9589 active_crtcs++;
9590 }
9591 WARN(pll->active != active_crtcs,
9592 "pll active crtcs mismatch (expected %i, found %i)\n",
9593 pll->active, active_crtcs);
9594 WARN(pll->refcount != enabled_crtcs,
9595 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9596 pll->refcount, enabled_crtcs);
9597
9598 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9599 sizeof(dpll_hw_state)),
9600 "pll hw state mismatch\n");
9601 }
9602 }
9603
9604 void
9605 intel_modeset_check_state(struct drm_device *dev)
9606 {
9607 check_connector_state(dev);
9608 check_encoder_state(dev);
9609 check_crtc_state(dev);
9610 check_shared_dpll_state(dev);
9611 }
9612
9613 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9614 int dotclock)
9615 {
9616 /*
9617 * FDI already provided one idea for the dotclock.
9618 * Yell if the encoder disagrees.
9619 */
9620 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9621 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9622 pipe_config->adjusted_mode.crtc_clock, dotclock);
9623 }
9624
9625 static int __intel_set_mode(struct drm_crtc *crtc,
9626 struct drm_display_mode *mode,
9627 int x, int y, struct drm_framebuffer *fb)
9628 {
9629 struct drm_device *dev = crtc->dev;
9630 drm_i915_private_t *dev_priv = dev->dev_private;
9631 struct drm_display_mode *saved_mode;
9632 struct intel_crtc_config *pipe_config = NULL;
9633 struct intel_crtc *intel_crtc;
9634 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9635 int ret = 0;
9636
9637 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9638 if (!saved_mode)
9639 return -ENOMEM;
9640
9641 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9642 &prepare_pipes, &disable_pipes);
9643
9644 *saved_mode = crtc->mode;
9645
9646 /* Hack: Because we don't (yet) support global modeset on multiple
9647 * crtcs, we don't keep track of the new mode for more than one crtc.
9648 * Hence simply check whether any bit is set in modeset_pipes in all the
9649 * pieces of code that are not yet converted to deal with mutliple crtcs
9650 * changing their mode at the same time. */
9651 if (modeset_pipes) {
9652 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9653 if (IS_ERR(pipe_config)) {
9654 ret = PTR_ERR(pipe_config);
9655 pipe_config = NULL;
9656
9657 goto out;
9658 }
9659 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9660 "[modeset]");
9661 to_intel_crtc(crtc)->new_config = pipe_config;
9662 }
9663
9664 /*
9665 * See if the config requires any additional preparation, e.g.
9666 * to adjust global state with pipes off. We need to do this
9667 * here so we can get the modeset_pipe updated config for the new
9668 * mode set on this crtc. For other crtcs we need to use the
9669 * adjusted_mode bits in the crtc directly.
9670 */
9671 if (IS_VALLEYVIEW(dev)) {
9672 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9673
9674 /* may have added more to prepare_pipes than we should */
9675 prepare_pipes &= ~disable_pipes;
9676 }
9677
9678 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9679 intel_crtc_disable(&intel_crtc->base);
9680
9681 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9682 if (intel_crtc->base.enabled)
9683 dev_priv->display.crtc_disable(&intel_crtc->base);
9684 }
9685
9686 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9687 * to set it here already despite that we pass it down the callchain.
9688 */
9689 if (modeset_pipes) {
9690 crtc->mode = *mode;
9691 /* mode_set/enable/disable functions rely on a correct pipe
9692 * config. */
9693 to_intel_crtc(crtc)->config = *pipe_config;
9694 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9695
9696 /*
9697 * Calculate and store various constants which
9698 * are later needed by vblank and swap-completion
9699 * timestamping. They are derived from true hwmode.
9700 */
9701 drm_calc_timestamping_constants(crtc,
9702 &pipe_config->adjusted_mode);
9703 }
9704
9705 /* Only after disabling all output pipelines that will be changed can we
9706 * update the the output configuration. */
9707 intel_modeset_update_state(dev, prepare_pipes);
9708
9709 if (dev_priv->display.modeset_global_resources)
9710 dev_priv->display.modeset_global_resources(dev);
9711
9712 /* Set up the DPLL and any encoders state that needs to adjust or depend
9713 * on the DPLL.
9714 */
9715 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9716 ret = intel_crtc_mode_set(&intel_crtc->base,
9717 x, y, fb);
9718 if (ret)
9719 goto done;
9720 }
9721
9722 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9723 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9724 dev_priv->display.crtc_enable(&intel_crtc->base);
9725
9726 /* FIXME: add subpixel order */
9727 done:
9728 if (ret && crtc->enabled)
9729 crtc->mode = *saved_mode;
9730
9731 out:
9732 kfree(pipe_config);
9733 kfree(saved_mode);
9734 return ret;
9735 }
9736
9737 static int intel_set_mode(struct drm_crtc *crtc,
9738 struct drm_display_mode *mode,
9739 int x, int y, struct drm_framebuffer *fb)
9740 {
9741 int ret;
9742
9743 ret = __intel_set_mode(crtc, mode, x, y, fb);
9744
9745 if (ret == 0)
9746 intel_modeset_check_state(crtc->dev);
9747
9748 return ret;
9749 }
9750
9751 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9752 {
9753 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9754 }
9755
9756 #undef for_each_intel_crtc_masked
9757
9758 static void intel_set_config_free(struct intel_set_config *config)
9759 {
9760 if (!config)
9761 return;
9762
9763 kfree(config->save_connector_encoders);
9764 kfree(config->save_encoder_crtcs);
9765 kfree(config->save_crtc_enabled);
9766 kfree(config);
9767 }
9768
9769 static int intel_set_config_save_state(struct drm_device *dev,
9770 struct intel_set_config *config)
9771 {
9772 struct drm_crtc *crtc;
9773 struct drm_encoder *encoder;
9774 struct drm_connector *connector;
9775 int count;
9776
9777 config->save_crtc_enabled =
9778 kcalloc(dev->mode_config.num_crtc,
9779 sizeof(bool), GFP_KERNEL);
9780 if (!config->save_crtc_enabled)
9781 return -ENOMEM;
9782
9783 config->save_encoder_crtcs =
9784 kcalloc(dev->mode_config.num_encoder,
9785 sizeof(struct drm_crtc *), GFP_KERNEL);
9786 if (!config->save_encoder_crtcs)
9787 return -ENOMEM;
9788
9789 config->save_connector_encoders =
9790 kcalloc(dev->mode_config.num_connector,
9791 sizeof(struct drm_encoder *), GFP_KERNEL);
9792 if (!config->save_connector_encoders)
9793 return -ENOMEM;
9794
9795 /* Copy data. Note that driver private data is not affected.
9796 * Should anything bad happen only the expected state is
9797 * restored, not the drivers personal bookkeeping.
9798 */
9799 count = 0;
9800 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9801 config->save_crtc_enabled[count++] = crtc->enabled;
9802 }
9803
9804 count = 0;
9805 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9806 config->save_encoder_crtcs[count++] = encoder->crtc;
9807 }
9808
9809 count = 0;
9810 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9811 config->save_connector_encoders[count++] = connector->encoder;
9812 }
9813
9814 return 0;
9815 }
9816
9817 static void intel_set_config_restore_state(struct drm_device *dev,
9818 struct intel_set_config *config)
9819 {
9820 struct intel_crtc *crtc;
9821 struct intel_encoder *encoder;
9822 struct intel_connector *connector;
9823 int count;
9824
9825 count = 0;
9826 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9827 crtc->new_enabled = config->save_crtc_enabled[count++];
9828
9829 if (crtc->new_enabled)
9830 crtc->new_config = &crtc->config;
9831 else
9832 crtc->new_config = NULL;
9833 }
9834
9835 count = 0;
9836 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9837 encoder->new_crtc =
9838 to_intel_crtc(config->save_encoder_crtcs[count++]);
9839 }
9840
9841 count = 0;
9842 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9843 connector->new_encoder =
9844 to_intel_encoder(config->save_connector_encoders[count++]);
9845 }
9846 }
9847
9848 static bool
9849 is_crtc_connector_off(struct drm_mode_set *set)
9850 {
9851 int i;
9852
9853 if (set->num_connectors == 0)
9854 return false;
9855
9856 if (WARN_ON(set->connectors == NULL))
9857 return false;
9858
9859 for (i = 0; i < set->num_connectors; i++)
9860 if (set->connectors[i]->encoder &&
9861 set->connectors[i]->encoder->crtc == set->crtc &&
9862 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9863 return true;
9864
9865 return false;
9866 }
9867
9868 static void
9869 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9870 struct intel_set_config *config)
9871 {
9872
9873 /* We should be able to check here if the fb has the same properties
9874 * and then just flip_or_move it */
9875 if (is_crtc_connector_off(set)) {
9876 config->mode_changed = true;
9877 } else if (set->crtc->fb != set->fb) {
9878 /* If we have no fb then treat it as a full mode set */
9879 if (set->crtc->fb == NULL) {
9880 struct intel_crtc *intel_crtc =
9881 to_intel_crtc(set->crtc);
9882
9883 if (intel_crtc->active && i915_fastboot) {
9884 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9885 config->fb_changed = true;
9886 } else {
9887 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9888 config->mode_changed = true;
9889 }
9890 } else if (set->fb == NULL) {
9891 config->mode_changed = true;
9892 } else if (set->fb->pixel_format !=
9893 set->crtc->fb->pixel_format) {
9894 config->mode_changed = true;
9895 } else {
9896 config->fb_changed = true;
9897 }
9898 }
9899
9900 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9901 config->fb_changed = true;
9902
9903 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9904 DRM_DEBUG_KMS("modes are different, full mode set\n");
9905 drm_mode_debug_printmodeline(&set->crtc->mode);
9906 drm_mode_debug_printmodeline(set->mode);
9907 config->mode_changed = true;
9908 }
9909
9910 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9911 set->crtc->base.id, config->mode_changed, config->fb_changed);
9912 }
9913
9914 static int
9915 intel_modeset_stage_output_state(struct drm_device *dev,
9916 struct drm_mode_set *set,
9917 struct intel_set_config *config)
9918 {
9919 struct intel_connector *connector;
9920 struct intel_encoder *encoder;
9921 struct intel_crtc *crtc;
9922 int ro;
9923
9924 /* The upper layers ensure that we either disable a crtc or have a list
9925 * of connectors. For paranoia, double-check this. */
9926 WARN_ON(!set->fb && (set->num_connectors != 0));
9927 WARN_ON(set->fb && (set->num_connectors == 0));
9928
9929 list_for_each_entry(connector, &dev->mode_config.connector_list,
9930 base.head) {
9931 /* Otherwise traverse passed in connector list and get encoders
9932 * for them. */
9933 for (ro = 0; ro < set->num_connectors; ro++) {
9934 if (set->connectors[ro] == &connector->base) {
9935 connector->new_encoder = connector->encoder;
9936 break;
9937 }
9938 }
9939
9940 /* If we disable the crtc, disable all its connectors. Also, if
9941 * the connector is on the changing crtc but not on the new
9942 * connector list, disable it. */
9943 if ((!set->fb || ro == set->num_connectors) &&
9944 connector->base.encoder &&
9945 connector->base.encoder->crtc == set->crtc) {
9946 connector->new_encoder = NULL;
9947
9948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9949 connector->base.base.id,
9950 drm_get_connector_name(&connector->base));
9951 }
9952
9953
9954 if (&connector->new_encoder->base != connector->base.encoder) {
9955 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9956 config->mode_changed = true;
9957 }
9958 }
9959 /* connector->new_encoder is now updated for all connectors. */
9960
9961 /* Update crtc of enabled connectors. */
9962 list_for_each_entry(connector, &dev->mode_config.connector_list,
9963 base.head) {
9964 struct drm_crtc *new_crtc;
9965
9966 if (!connector->new_encoder)
9967 continue;
9968
9969 new_crtc = connector->new_encoder->base.crtc;
9970
9971 for (ro = 0; ro < set->num_connectors; ro++) {
9972 if (set->connectors[ro] == &connector->base)
9973 new_crtc = set->crtc;
9974 }
9975
9976 /* Make sure the new CRTC will work with the encoder */
9977 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9978 new_crtc)) {
9979 return -EINVAL;
9980 }
9981 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9982
9983 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9984 connector->base.base.id,
9985 drm_get_connector_name(&connector->base),
9986 new_crtc->base.id);
9987 }
9988
9989 /* Check for any encoders that needs to be disabled. */
9990 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9991 base.head) {
9992 int num_connectors = 0;
9993 list_for_each_entry(connector,
9994 &dev->mode_config.connector_list,
9995 base.head) {
9996 if (connector->new_encoder == encoder) {
9997 WARN_ON(!connector->new_encoder->new_crtc);
9998 num_connectors++;
9999 }
10000 }
10001
10002 if (num_connectors == 0)
10003 encoder->new_crtc = NULL;
10004 else if (num_connectors > 1)
10005 return -EINVAL;
10006
10007 /* Only now check for crtc changes so we don't miss encoders
10008 * that will be disabled. */
10009 if (&encoder->new_crtc->base != encoder->base.crtc) {
10010 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10011 config->mode_changed = true;
10012 }
10013 }
10014 /* Now we've also updated encoder->new_crtc for all encoders. */
10015
10016 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10017 base.head) {
10018 crtc->new_enabled = false;
10019
10020 list_for_each_entry(encoder,
10021 &dev->mode_config.encoder_list,
10022 base.head) {
10023 if (encoder->new_crtc == crtc) {
10024 crtc->new_enabled = true;
10025 break;
10026 }
10027 }
10028
10029 if (crtc->new_enabled != crtc->base.enabled) {
10030 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10031 crtc->new_enabled ? "en" : "dis");
10032 config->mode_changed = true;
10033 }
10034
10035 if (crtc->new_enabled)
10036 crtc->new_config = &crtc->config;
10037 else
10038 crtc->new_config = NULL;
10039 }
10040
10041 return 0;
10042 }
10043
10044 static void disable_crtc_nofb(struct intel_crtc *crtc)
10045 {
10046 struct drm_device *dev = crtc->base.dev;
10047 struct intel_encoder *encoder;
10048 struct intel_connector *connector;
10049
10050 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10051 pipe_name(crtc->pipe));
10052
10053 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10054 if (connector->new_encoder &&
10055 connector->new_encoder->new_crtc == crtc)
10056 connector->new_encoder = NULL;
10057 }
10058
10059 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10060 if (encoder->new_crtc == crtc)
10061 encoder->new_crtc = NULL;
10062 }
10063
10064 crtc->new_enabled = false;
10065 crtc->new_config = NULL;
10066 }
10067
10068 static int intel_crtc_set_config(struct drm_mode_set *set)
10069 {
10070 struct drm_device *dev;
10071 struct drm_mode_set save_set;
10072 struct intel_set_config *config;
10073 int ret;
10074
10075 BUG_ON(!set);
10076 BUG_ON(!set->crtc);
10077 BUG_ON(!set->crtc->helper_private);
10078
10079 /* Enforce sane interface api - has been abused by the fb helper. */
10080 BUG_ON(!set->mode && set->fb);
10081 BUG_ON(set->fb && set->num_connectors == 0);
10082
10083 if (set->fb) {
10084 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10085 set->crtc->base.id, set->fb->base.id,
10086 (int)set->num_connectors, set->x, set->y);
10087 } else {
10088 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10089 }
10090
10091 dev = set->crtc->dev;
10092
10093 ret = -ENOMEM;
10094 config = kzalloc(sizeof(*config), GFP_KERNEL);
10095 if (!config)
10096 goto out_config;
10097
10098 ret = intel_set_config_save_state(dev, config);
10099 if (ret)
10100 goto out_config;
10101
10102 save_set.crtc = set->crtc;
10103 save_set.mode = &set->crtc->mode;
10104 save_set.x = set->crtc->x;
10105 save_set.y = set->crtc->y;
10106 save_set.fb = set->crtc->fb;
10107
10108 /* Compute whether we need a full modeset, only an fb base update or no
10109 * change at all. In the future we might also check whether only the
10110 * mode changed, e.g. for LVDS where we only change the panel fitter in
10111 * such cases. */
10112 intel_set_config_compute_mode_changes(set, config);
10113
10114 ret = intel_modeset_stage_output_state(dev, set, config);
10115 if (ret)
10116 goto fail;
10117
10118 if (config->mode_changed) {
10119 ret = intel_set_mode(set->crtc, set->mode,
10120 set->x, set->y, set->fb);
10121 } else if (config->fb_changed) {
10122 intel_crtc_wait_for_pending_flips(set->crtc);
10123
10124 ret = intel_pipe_set_base(set->crtc,
10125 set->x, set->y, set->fb);
10126 /*
10127 * In the fastboot case this may be our only check of the
10128 * state after boot. It would be better to only do it on
10129 * the first update, but we don't have a nice way of doing that
10130 * (and really, set_config isn't used much for high freq page
10131 * flipping, so increasing its cost here shouldn't be a big
10132 * deal).
10133 */
10134 if (i915_fastboot && ret == 0)
10135 intel_modeset_check_state(set->crtc->dev);
10136 }
10137
10138 if (ret) {
10139 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10140 set->crtc->base.id, ret);
10141 fail:
10142 intel_set_config_restore_state(dev, config);
10143
10144 /*
10145 * HACK: if the pipe was on, but we didn't have a framebuffer,
10146 * force the pipe off to avoid oopsing in the modeset code
10147 * due to fb==NULL. This should only happen during boot since
10148 * we don't yet reconstruct the FB from the hardware state.
10149 */
10150 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10151 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10152
10153 /* Try to restore the config */
10154 if (config->mode_changed &&
10155 intel_set_mode(save_set.crtc, save_set.mode,
10156 save_set.x, save_set.y, save_set.fb))
10157 DRM_ERROR("failed to restore config after modeset failure\n");
10158 }
10159
10160 out_config:
10161 intel_set_config_free(config);
10162 return ret;
10163 }
10164
10165 static const struct drm_crtc_funcs intel_crtc_funcs = {
10166 .cursor_set = intel_crtc_cursor_set,
10167 .cursor_move = intel_crtc_cursor_move,
10168 .gamma_set = intel_crtc_gamma_set,
10169 .set_config = intel_crtc_set_config,
10170 .destroy = intel_crtc_destroy,
10171 .page_flip = intel_crtc_page_flip,
10172 };
10173
10174 static void intel_cpu_pll_init(struct drm_device *dev)
10175 {
10176 if (HAS_DDI(dev))
10177 intel_ddi_pll_init(dev);
10178 }
10179
10180 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10181 struct intel_shared_dpll *pll,
10182 struct intel_dpll_hw_state *hw_state)
10183 {
10184 uint32_t val;
10185
10186 val = I915_READ(PCH_DPLL(pll->id));
10187 hw_state->dpll = val;
10188 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10189 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10190
10191 return val & DPLL_VCO_ENABLE;
10192 }
10193
10194 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10195 struct intel_shared_dpll *pll)
10196 {
10197 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10198 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10199 }
10200
10201 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10202 struct intel_shared_dpll *pll)
10203 {
10204 /* PCH refclock must be enabled first */
10205 ibx_assert_pch_refclk_enabled(dev_priv);
10206
10207 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10208
10209 /* Wait for the clocks to stabilize. */
10210 POSTING_READ(PCH_DPLL(pll->id));
10211 udelay(150);
10212
10213 /* The pixel multiplier can only be updated once the
10214 * DPLL is enabled and the clocks are stable.
10215 *
10216 * So write it again.
10217 */
10218 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10219 POSTING_READ(PCH_DPLL(pll->id));
10220 udelay(200);
10221 }
10222
10223 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10224 struct intel_shared_dpll *pll)
10225 {
10226 struct drm_device *dev = dev_priv->dev;
10227 struct intel_crtc *crtc;
10228
10229 /* Make sure no transcoder isn't still depending on us. */
10230 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10231 if (intel_crtc_to_shared_dpll(crtc) == pll)
10232 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10233 }
10234
10235 I915_WRITE(PCH_DPLL(pll->id), 0);
10236 POSTING_READ(PCH_DPLL(pll->id));
10237 udelay(200);
10238 }
10239
10240 static char *ibx_pch_dpll_names[] = {
10241 "PCH DPLL A",
10242 "PCH DPLL B",
10243 };
10244
10245 static void ibx_pch_dpll_init(struct drm_device *dev)
10246 {
10247 struct drm_i915_private *dev_priv = dev->dev_private;
10248 int i;
10249
10250 dev_priv->num_shared_dpll = 2;
10251
10252 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10253 dev_priv->shared_dplls[i].id = i;
10254 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10255 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10256 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10257 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10258 dev_priv->shared_dplls[i].get_hw_state =
10259 ibx_pch_dpll_get_hw_state;
10260 }
10261 }
10262
10263 static void intel_shared_dpll_init(struct drm_device *dev)
10264 {
10265 struct drm_i915_private *dev_priv = dev->dev_private;
10266
10267 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10268 ibx_pch_dpll_init(dev);
10269 else
10270 dev_priv->num_shared_dpll = 0;
10271
10272 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10273 }
10274
10275 static void intel_crtc_init(struct drm_device *dev, int pipe)
10276 {
10277 drm_i915_private_t *dev_priv = dev->dev_private;
10278 struct intel_crtc *intel_crtc;
10279 int i;
10280
10281 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10282 if (intel_crtc == NULL)
10283 return;
10284
10285 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10286
10287 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10288 for (i = 0; i < 256; i++) {
10289 intel_crtc->lut_r[i] = i;
10290 intel_crtc->lut_g[i] = i;
10291 intel_crtc->lut_b[i] = i;
10292 }
10293
10294 /*
10295 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10296 * is hooked to plane B. Hence we want plane A feeding pipe B.
10297 */
10298 intel_crtc->pipe = pipe;
10299 intel_crtc->plane = pipe;
10300 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10301 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10302 intel_crtc->plane = !pipe;
10303 }
10304
10305 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10306 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10307 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10308 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10309
10310 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10311 }
10312
10313 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10314 {
10315 struct drm_encoder *encoder = connector->base.encoder;
10316
10317 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10318
10319 if (!encoder)
10320 return INVALID_PIPE;
10321
10322 return to_intel_crtc(encoder->crtc)->pipe;
10323 }
10324
10325 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10326 struct drm_file *file)
10327 {
10328 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10329 struct drm_mode_object *drmmode_obj;
10330 struct intel_crtc *crtc;
10331
10332 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10333 return -ENODEV;
10334
10335 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10336 DRM_MODE_OBJECT_CRTC);
10337
10338 if (!drmmode_obj) {
10339 DRM_ERROR("no such CRTC id\n");
10340 return -ENOENT;
10341 }
10342
10343 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10344 pipe_from_crtc_id->pipe = crtc->pipe;
10345
10346 return 0;
10347 }
10348
10349 static int intel_encoder_clones(struct intel_encoder *encoder)
10350 {
10351 struct drm_device *dev = encoder->base.dev;
10352 struct intel_encoder *source_encoder;
10353 int index_mask = 0;
10354 int entry = 0;
10355
10356 list_for_each_entry(source_encoder,
10357 &dev->mode_config.encoder_list, base.head) {
10358
10359 if (encoder == source_encoder)
10360 index_mask |= (1 << entry);
10361
10362 /* Intel hw has only one MUX where enocoders could be cloned. */
10363 if (encoder->cloneable && source_encoder->cloneable)
10364 index_mask |= (1 << entry);
10365
10366 entry++;
10367 }
10368
10369 return index_mask;
10370 }
10371
10372 static bool has_edp_a(struct drm_device *dev)
10373 {
10374 struct drm_i915_private *dev_priv = dev->dev_private;
10375
10376 if (!IS_MOBILE(dev))
10377 return false;
10378
10379 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10380 return false;
10381
10382 if (IS_GEN5(dev) &&
10383 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10384 return false;
10385
10386 return true;
10387 }
10388
10389 const char *intel_output_name(int output)
10390 {
10391 static const char *names[] = {
10392 [INTEL_OUTPUT_UNUSED] = "Unused",
10393 [INTEL_OUTPUT_ANALOG] = "Analog",
10394 [INTEL_OUTPUT_DVO] = "DVO",
10395 [INTEL_OUTPUT_SDVO] = "SDVO",
10396 [INTEL_OUTPUT_LVDS] = "LVDS",
10397 [INTEL_OUTPUT_TVOUT] = "TV",
10398 [INTEL_OUTPUT_HDMI] = "HDMI",
10399 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10400 [INTEL_OUTPUT_EDP] = "eDP",
10401 [INTEL_OUTPUT_DSI] = "DSI",
10402 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10403 };
10404
10405 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10406 return "Invalid";
10407
10408 return names[output];
10409 }
10410
10411 static void intel_setup_outputs(struct drm_device *dev)
10412 {
10413 struct drm_i915_private *dev_priv = dev->dev_private;
10414 struct intel_encoder *encoder;
10415 bool dpd_is_edp = false;
10416
10417 intel_lvds_init(dev);
10418
10419 if (!IS_ULT(dev))
10420 intel_crt_init(dev);
10421
10422 if (HAS_DDI(dev)) {
10423 int found;
10424
10425 /* Haswell uses DDI functions to detect digital outputs */
10426 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10427 /* DDI A only supports eDP */
10428 if (found)
10429 intel_ddi_init(dev, PORT_A);
10430
10431 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10432 * register */
10433 found = I915_READ(SFUSE_STRAP);
10434
10435 if (found & SFUSE_STRAP_DDIB_DETECTED)
10436 intel_ddi_init(dev, PORT_B);
10437 if (found & SFUSE_STRAP_DDIC_DETECTED)
10438 intel_ddi_init(dev, PORT_C);
10439 if (found & SFUSE_STRAP_DDID_DETECTED)
10440 intel_ddi_init(dev, PORT_D);
10441 } else if (HAS_PCH_SPLIT(dev)) {
10442 int found;
10443 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10444
10445 if (has_edp_a(dev))
10446 intel_dp_init(dev, DP_A, PORT_A);
10447
10448 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10449 /* PCH SDVOB multiplex with HDMIB */
10450 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10451 if (!found)
10452 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10453 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10454 intel_dp_init(dev, PCH_DP_B, PORT_B);
10455 }
10456
10457 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10458 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10459
10460 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10461 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10462
10463 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10464 intel_dp_init(dev, PCH_DP_C, PORT_C);
10465
10466 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10467 intel_dp_init(dev, PCH_DP_D, PORT_D);
10468 } else if (IS_VALLEYVIEW(dev)) {
10469 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10470 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10471 PORT_B);
10472 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10473 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10474 }
10475
10476 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10477 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10478 PORT_C);
10479 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10480 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10481 }
10482
10483 intel_dsi_init(dev);
10484 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10485 bool found = false;
10486
10487 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10488 DRM_DEBUG_KMS("probing SDVOB\n");
10489 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10490 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10491 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10492 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10493 }
10494
10495 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10496 intel_dp_init(dev, DP_B, PORT_B);
10497 }
10498
10499 /* Before G4X SDVOC doesn't have its own detect register */
10500
10501 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10502 DRM_DEBUG_KMS("probing SDVOC\n");
10503 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10504 }
10505
10506 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10507
10508 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10509 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10510 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10511 }
10512 if (SUPPORTS_INTEGRATED_DP(dev))
10513 intel_dp_init(dev, DP_C, PORT_C);
10514 }
10515
10516 if (SUPPORTS_INTEGRATED_DP(dev) &&
10517 (I915_READ(DP_D) & DP_DETECTED))
10518 intel_dp_init(dev, DP_D, PORT_D);
10519 } else if (IS_GEN2(dev))
10520 intel_dvo_init(dev);
10521
10522 if (SUPPORTS_TV(dev))
10523 intel_tv_init(dev);
10524
10525 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10526 encoder->base.possible_crtcs = encoder->crtc_mask;
10527 encoder->base.possible_clones =
10528 intel_encoder_clones(encoder);
10529 }
10530
10531 intel_init_pch_refclk(dev);
10532
10533 drm_helper_move_panel_connectors_to_head(dev);
10534 }
10535
10536 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10537 {
10538 drm_framebuffer_cleanup(&fb->base);
10539 WARN_ON(!fb->obj->framebuffer_references--);
10540 drm_gem_object_unreference_unlocked(&fb->obj->base);
10541 }
10542
10543 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10544 {
10545 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10546
10547 intel_framebuffer_fini(intel_fb);
10548 kfree(intel_fb);
10549 }
10550
10551 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10552 struct drm_file *file,
10553 unsigned int *handle)
10554 {
10555 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10556 struct drm_i915_gem_object *obj = intel_fb->obj;
10557
10558 return drm_gem_handle_create(file, &obj->base, handle);
10559 }
10560
10561 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10562 .destroy = intel_user_framebuffer_destroy,
10563 .create_handle = intel_user_framebuffer_create_handle,
10564 };
10565
10566 int intel_framebuffer_init(struct drm_device *dev,
10567 struct intel_framebuffer *intel_fb,
10568 struct drm_mode_fb_cmd2 *mode_cmd,
10569 struct drm_i915_gem_object *obj)
10570 {
10571 int aligned_height, tile_height;
10572 int pitch_limit;
10573 int ret;
10574
10575 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10576
10577 if (obj->tiling_mode == I915_TILING_Y) {
10578 DRM_DEBUG("hardware does not support tiling Y\n");
10579 return -EINVAL;
10580 }
10581
10582 if (mode_cmd->pitches[0] & 63) {
10583 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10584 mode_cmd->pitches[0]);
10585 return -EINVAL;
10586 }
10587
10588 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10589 pitch_limit = 32*1024;
10590 } else if (INTEL_INFO(dev)->gen >= 4) {
10591 if (obj->tiling_mode)
10592 pitch_limit = 16*1024;
10593 else
10594 pitch_limit = 32*1024;
10595 } else if (INTEL_INFO(dev)->gen >= 3) {
10596 if (obj->tiling_mode)
10597 pitch_limit = 8*1024;
10598 else
10599 pitch_limit = 16*1024;
10600 } else
10601 /* XXX DSPC is limited to 4k tiled */
10602 pitch_limit = 8*1024;
10603
10604 if (mode_cmd->pitches[0] > pitch_limit) {
10605 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10606 obj->tiling_mode ? "tiled" : "linear",
10607 mode_cmd->pitches[0], pitch_limit);
10608 return -EINVAL;
10609 }
10610
10611 if (obj->tiling_mode != I915_TILING_NONE &&
10612 mode_cmd->pitches[0] != obj->stride) {
10613 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10614 mode_cmd->pitches[0], obj->stride);
10615 return -EINVAL;
10616 }
10617
10618 /* Reject formats not supported by any plane early. */
10619 switch (mode_cmd->pixel_format) {
10620 case DRM_FORMAT_C8:
10621 case DRM_FORMAT_RGB565:
10622 case DRM_FORMAT_XRGB8888:
10623 case DRM_FORMAT_ARGB8888:
10624 break;
10625 case DRM_FORMAT_XRGB1555:
10626 case DRM_FORMAT_ARGB1555:
10627 if (INTEL_INFO(dev)->gen > 3) {
10628 DRM_DEBUG("unsupported pixel format: %s\n",
10629 drm_get_format_name(mode_cmd->pixel_format));
10630 return -EINVAL;
10631 }
10632 break;
10633 case DRM_FORMAT_XBGR8888:
10634 case DRM_FORMAT_ABGR8888:
10635 case DRM_FORMAT_XRGB2101010:
10636 case DRM_FORMAT_ARGB2101010:
10637 case DRM_FORMAT_XBGR2101010:
10638 case DRM_FORMAT_ABGR2101010:
10639 if (INTEL_INFO(dev)->gen < 4) {
10640 DRM_DEBUG("unsupported pixel format: %s\n",
10641 drm_get_format_name(mode_cmd->pixel_format));
10642 return -EINVAL;
10643 }
10644 break;
10645 case DRM_FORMAT_YUYV:
10646 case DRM_FORMAT_UYVY:
10647 case DRM_FORMAT_YVYU:
10648 case DRM_FORMAT_VYUY:
10649 if (INTEL_INFO(dev)->gen < 5) {
10650 DRM_DEBUG("unsupported pixel format: %s\n",
10651 drm_get_format_name(mode_cmd->pixel_format));
10652 return -EINVAL;
10653 }
10654 break;
10655 default:
10656 DRM_DEBUG("unsupported pixel format: %s\n",
10657 drm_get_format_name(mode_cmd->pixel_format));
10658 return -EINVAL;
10659 }
10660
10661 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10662 if (mode_cmd->offsets[0] != 0)
10663 return -EINVAL;
10664
10665 tile_height = IS_GEN2(dev) ? 16 : 8;
10666 aligned_height = ALIGN(mode_cmd->height,
10667 obj->tiling_mode ? tile_height : 1);
10668 /* FIXME drm helper for size checks (especially planar formats)? */
10669 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10670 return -EINVAL;
10671
10672 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10673 intel_fb->obj = obj;
10674 intel_fb->obj->framebuffer_references++;
10675
10676 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10677 if (ret) {
10678 DRM_ERROR("framebuffer init failed %d\n", ret);
10679 return ret;
10680 }
10681
10682 return 0;
10683 }
10684
10685 static struct drm_framebuffer *
10686 intel_user_framebuffer_create(struct drm_device *dev,
10687 struct drm_file *filp,
10688 struct drm_mode_fb_cmd2 *mode_cmd)
10689 {
10690 struct drm_i915_gem_object *obj;
10691
10692 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10693 mode_cmd->handles[0]));
10694 if (&obj->base == NULL)
10695 return ERR_PTR(-ENOENT);
10696
10697 return intel_framebuffer_create(dev, mode_cmd, obj);
10698 }
10699
10700 #ifndef CONFIG_DRM_I915_FBDEV
10701 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10702 {
10703 }
10704 #endif
10705
10706 static const struct drm_mode_config_funcs intel_mode_funcs = {
10707 .fb_create = intel_user_framebuffer_create,
10708 .output_poll_changed = intel_fbdev_output_poll_changed,
10709 };
10710
10711 /* Set up chip specific display functions */
10712 static void intel_init_display(struct drm_device *dev)
10713 {
10714 struct drm_i915_private *dev_priv = dev->dev_private;
10715
10716 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10717 dev_priv->display.find_dpll = g4x_find_best_dpll;
10718 else if (IS_VALLEYVIEW(dev))
10719 dev_priv->display.find_dpll = vlv_find_best_dpll;
10720 else if (IS_PINEVIEW(dev))
10721 dev_priv->display.find_dpll = pnv_find_best_dpll;
10722 else
10723 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10724
10725 if (HAS_DDI(dev)) {
10726 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10727 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10728 dev_priv->display.crtc_enable = haswell_crtc_enable;
10729 dev_priv->display.crtc_disable = haswell_crtc_disable;
10730 dev_priv->display.off = haswell_crtc_off;
10731 dev_priv->display.update_plane = ironlake_update_plane;
10732 } else if (HAS_PCH_SPLIT(dev)) {
10733 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10734 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10735 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10736 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10737 dev_priv->display.off = ironlake_crtc_off;
10738 dev_priv->display.update_plane = ironlake_update_plane;
10739 } else if (IS_VALLEYVIEW(dev)) {
10740 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10741 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10742 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10743 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10744 dev_priv->display.off = i9xx_crtc_off;
10745 dev_priv->display.update_plane = i9xx_update_plane;
10746 } else {
10747 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10748 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10749 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10750 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10751 dev_priv->display.off = i9xx_crtc_off;
10752 dev_priv->display.update_plane = i9xx_update_plane;
10753 }
10754
10755 /* Returns the core display clock speed */
10756 if (IS_VALLEYVIEW(dev))
10757 dev_priv->display.get_display_clock_speed =
10758 valleyview_get_display_clock_speed;
10759 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10760 dev_priv->display.get_display_clock_speed =
10761 i945_get_display_clock_speed;
10762 else if (IS_I915G(dev))
10763 dev_priv->display.get_display_clock_speed =
10764 i915_get_display_clock_speed;
10765 else if (IS_I945GM(dev) || IS_845G(dev))
10766 dev_priv->display.get_display_clock_speed =
10767 i9xx_misc_get_display_clock_speed;
10768 else if (IS_PINEVIEW(dev))
10769 dev_priv->display.get_display_clock_speed =
10770 pnv_get_display_clock_speed;
10771 else if (IS_I915GM(dev))
10772 dev_priv->display.get_display_clock_speed =
10773 i915gm_get_display_clock_speed;
10774 else if (IS_I865G(dev))
10775 dev_priv->display.get_display_clock_speed =
10776 i865_get_display_clock_speed;
10777 else if (IS_I85X(dev))
10778 dev_priv->display.get_display_clock_speed =
10779 i855_get_display_clock_speed;
10780 else /* 852, 830 */
10781 dev_priv->display.get_display_clock_speed =
10782 i830_get_display_clock_speed;
10783
10784 if (HAS_PCH_SPLIT(dev)) {
10785 if (IS_GEN5(dev)) {
10786 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10787 dev_priv->display.write_eld = ironlake_write_eld;
10788 } else if (IS_GEN6(dev)) {
10789 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10790 dev_priv->display.write_eld = ironlake_write_eld;
10791 } else if (IS_IVYBRIDGE(dev)) {
10792 /* FIXME: detect B0+ stepping and use auto training */
10793 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10794 dev_priv->display.write_eld = ironlake_write_eld;
10795 dev_priv->display.modeset_global_resources =
10796 ivb_modeset_global_resources;
10797 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10798 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10799 dev_priv->display.write_eld = haswell_write_eld;
10800 dev_priv->display.modeset_global_resources =
10801 haswell_modeset_global_resources;
10802 }
10803 } else if (IS_G4X(dev)) {
10804 dev_priv->display.write_eld = g4x_write_eld;
10805 } else if (IS_VALLEYVIEW(dev)) {
10806 dev_priv->display.modeset_global_resources =
10807 valleyview_modeset_global_resources;
10808 dev_priv->display.write_eld = ironlake_write_eld;
10809 }
10810
10811 /* Default just returns -ENODEV to indicate unsupported */
10812 dev_priv->display.queue_flip = intel_default_queue_flip;
10813
10814 switch (INTEL_INFO(dev)->gen) {
10815 case 2:
10816 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10817 break;
10818
10819 case 3:
10820 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10821 break;
10822
10823 case 4:
10824 case 5:
10825 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10826 break;
10827
10828 case 6:
10829 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10830 break;
10831 case 7:
10832 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10833 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10834 break;
10835 }
10836
10837 intel_panel_init_backlight_funcs(dev);
10838 }
10839
10840 /*
10841 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10842 * resume, or other times. This quirk makes sure that's the case for
10843 * affected systems.
10844 */
10845 static void quirk_pipea_force(struct drm_device *dev)
10846 {
10847 struct drm_i915_private *dev_priv = dev->dev_private;
10848
10849 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10850 DRM_INFO("applying pipe a force quirk\n");
10851 }
10852
10853 /*
10854 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10855 */
10856 static void quirk_ssc_force_disable(struct drm_device *dev)
10857 {
10858 struct drm_i915_private *dev_priv = dev->dev_private;
10859 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10860 DRM_INFO("applying lvds SSC disable quirk\n");
10861 }
10862
10863 /*
10864 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10865 * brightness value
10866 */
10867 static void quirk_invert_brightness(struct drm_device *dev)
10868 {
10869 struct drm_i915_private *dev_priv = dev->dev_private;
10870 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10871 DRM_INFO("applying inverted panel brightness quirk\n");
10872 }
10873
10874 struct intel_quirk {
10875 int device;
10876 int subsystem_vendor;
10877 int subsystem_device;
10878 void (*hook)(struct drm_device *dev);
10879 };
10880
10881 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10882 struct intel_dmi_quirk {
10883 void (*hook)(struct drm_device *dev);
10884 const struct dmi_system_id (*dmi_id_list)[];
10885 };
10886
10887 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10888 {
10889 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10890 return 1;
10891 }
10892
10893 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10894 {
10895 .dmi_id_list = &(const struct dmi_system_id[]) {
10896 {
10897 .callback = intel_dmi_reverse_brightness,
10898 .ident = "NCR Corporation",
10899 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10900 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10901 },
10902 },
10903 { } /* terminating entry */
10904 },
10905 .hook = quirk_invert_brightness,
10906 },
10907 };
10908
10909 static struct intel_quirk intel_quirks[] = {
10910 /* HP Mini needs pipe A force quirk (LP: #322104) */
10911 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10912
10913 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10914 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10915
10916 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10917 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10918
10919 /* 830 needs to leave pipe A & dpll A up */
10920 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10921
10922 /* Lenovo U160 cannot use SSC on LVDS */
10923 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10924
10925 /* Sony Vaio Y cannot use SSC on LVDS */
10926 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10927
10928 /* Acer Aspire 5734Z must invert backlight brightness */
10929 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10930
10931 /* Acer/eMachines G725 */
10932 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10933
10934 /* Acer/eMachines e725 */
10935 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10936
10937 /* Acer/Packard Bell NCL20 */
10938 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10939
10940 /* Acer Aspire 4736Z */
10941 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10942 };
10943
10944 static void intel_init_quirks(struct drm_device *dev)
10945 {
10946 struct pci_dev *d = dev->pdev;
10947 int i;
10948
10949 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10950 struct intel_quirk *q = &intel_quirks[i];
10951
10952 if (d->device == q->device &&
10953 (d->subsystem_vendor == q->subsystem_vendor ||
10954 q->subsystem_vendor == PCI_ANY_ID) &&
10955 (d->subsystem_device == q->subsystem_device ||
10956 q->subsystem_device == PCI_ANY_ID))
10957 q->hook(dev);
10958 }
10959 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10960 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10961 intel_dmi_quirks[i].hook(dev);
10962 }
10963 }
10964
10965 /* Disable the VGA plane that we never use */
10966 static void i915_disable_vga(struct drm_device *dev)
10967 {
10968 struct drm_i915_private *dev_priv = dev->dev_private;
10969 u8 sr1;
10970 u32 vga_reg = i915_vgacntrl_reg(dev);
10971
10972 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10973 outb(SR01, VGA_SR_INDEX);
10974 sr1 = inb(VGA_SR_DATA);
10975 outb(sr1 | 1<<5, VGA_SR_DATA);
10976 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10977 udelay(300);
10978
10979 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10980 POSTING_READ(vga_reg);
10981 }
10982
10983 void intel_modeset_init_hw(struct drm_device *dev)
10984 {
10985 intel_prepare_ddi(dev);
10986
10987 intel_init_clock_gating(dev);
10988
10989 intel_reset_dpio(dev);
10990
10991 mutex_lock(&dev->struct_mutex);
10992 intel_enable_gt_powersave(dev);
10993 mutex_unlock(&dev->struct_mutex);
10994 }
10995
10996 void intel_modeset_suspend_hw(struct drm_device *dev)
10997 {
10998 intel_suspend_hw(dev);
10999 }
11000
11001 void intel_modeset_init(struct drm_device *dev)
11002 {
11003 struct drm_i915_private *dev_priv = dev->dev_private;
11004 int i, j, ret;
11005
11006 drm_mode_config_init(dev);
11007
11008 dev->mode_config.min_width = 0;
11009 dev->mode_config.min_height = 0;
11010
11011 dev->mode_config.preferred_depth = 24;
11012 dev->mode_config.prefer_shadow = 1;
11013
11014 dev->mode_config.funcs = &intel_mode_funcs;
11015
11016 intel_init_quirks(dev);
11017
11018 intel_init_pm(dev);
11019
11020 if (INTEL_INFO(dev)->num_pipes == 0)
11021 return;
11022
11023 intel_init_display(dev);
11024
11025 if (IS_GEN2(dev)) {
11026 dev->mode_config.max_width = 2048;
11027 dev->mode_config.max_height = 2048;
11028 } else if (IS_GEN3(dev)) {
11029 dev->mode_config.max_width = 4096;
11030 dev->mode_config.max_height = 4096;
11031 } else {
11032 dev->mode_config.max_width = 8192;
11033 dev->mode_config.max_height = 8192;
11034 }
11035 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11036
11037 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11038 INTEL_INFO(dev)->num_pipes,
11039 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11040
11041 for_each_pipe(i) {
11042 intel_crtc_init(dev, i);
11043 for (j = 0; j < dev_priv->num_plane; j++) {
11044 ret = intel_plane_init(dev, i, j);
11045 if (ret)
11046 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11047 pipe_name(i), sprite_name(i, j), ret);
11048 }
11049 }
11050
11051 intel_init_dpio(dev);
11052 intel_reset_dpio(dev);
11053
11054 intel_cpu_pll_init(dev);
11055 intel_shared_dpll_init(dev);
11056
11057 /* Just disable it once at startup */
11058 i915_disable_vga(dev);
11059 intel_setup_outputs(dev);
11060
11061 /* Just in case the BIOS is doing something questionable. */
11062 intel_disable_fbc(dev);
11063 }
11064
11065 static void
11066 intel_connector_break_all_links(struct intel_connector *connector)
11067 {
11068 connector->base.dpms = DRM_MODE_DPMS_OFF;
11069 connector->base.encoder = NULL;
11070 connector->encoder->connectors_active = false;
11071 connector->encoder->base.crtc = NULL;
11072 }
11073
11074 static void intel_enable_pipe_a(struct drm_device *dev)
11075 {
11076 struct intel_connector *connector;
11077 struct drm_connector *crt = NULL;
11078 struct intel_load_detect_pipe load_detect_temp;
11079
11080 /* We can't just switch on the pipe A, we need to set things up with a
11081 * proper mode and output configuration. As a gross hack, enable pipe A
11082 * by enabling the load detect pipe once. */
11083 list_for_each_entry(connector,
11084 &dev->mode_config.connector_list,
11085 base.head) {
11086 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11087 crt = &connector->base;
11088 break;
11089 }
11090 }
11091
11092 if (!crt)
11093 return;
11094
11095 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11096 intel_release_load_detect_pipe(crt, &load_detect_temp);
11097
11098
11099 }
11100
11101 static bool
11102 intel_check_plane_mapping(struct intel_crtc *crtc)
11103 {
11104 struct drm_device *dev = crtc->base.dev;
11105 struct drm_i915_private *dev_priv = dev->dev_private;
11106 u32 reg, val;
11107
11108 if (INTEL_INFO(dev)->num_pipes == 1)
11109 return true;
11110
11111 reg = DSPCNTR(!crtc->plane);
11112 val = I915_READ(reg);
11113
11114 if ((val & DISPLAY_PLANE_ENABLE) &&
11115 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11116 return false;
11117
11118 return true;
11119 }
11120
11121 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11122 {
11123 struct drm_device *dev = crtc->base.dev;
11124 struct drm_i915_private *dev_priv = dev->dev_private;
11125 u32 reg;
11126
11127 /* Clear any frame start delays used for debugging left by the BIOS */
11128 reg = PIPECONF(crtc->config.cpu_transcoder);
11129 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11130
11131 /* We need to sanitize the plane -> pipe mapping first because this will
11132 * disable the crtc (and hence change the state) if it is wrong. Note
11133 * that gen4+ has a fixed plane -> pipe mapping. */
11134 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11135 struct intel_connector *connector;
11136 bool plane;
11137
11138 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11139 crtc->base.base.id);
11140
11141 /* Pipe has the wrong plane attached and the plane is active.
11142 * Temporarily change the plane mapping and disable everything
11143 * ... */
11144 plane = crtc->plane;
11145 crtc->plane = !plane;
11146 dev_priv->display.crtc_disable(&crtc->base);
11147 crtc->plane = plane;
11148
11149 /* ... and break all links. */
11150 list_for_each_entry(connector, &dev->mode_config.connector_list,
11151 base.head) {
11152 if (connector->encoder->base.crtc != &crtc->base)
11153 continue;
11154
11155 intel_connector_break_all_links(connector);
11156 }
11157
11158 WARN_ON(crtc->active);
11159 crtc->base.enabled = false;
11160 }
11161
11162 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11163 crtc->pipe == PIPE_A && !crtc->active) {
11164 /* BIOS forgot to enable pipe A, this mostly happens after
11165 * resume. Force-enable the pipe to fix this, the update_dpms
11166 * call below we restore the pipe to the right state, but leave
11167 * the required bits on. */
11168 intel_enable_pipe_a(dev);
11169 }
11170
11171 /* Adjust the state of the output pipe according to whether we
11172 * have active connectors/encoders. */
11173 intel_crtc_update_dpms(&crtc->base);
11174
11175 if (crtc->active != crtc->base.enabled) {
11176 struct intel_encoder *encoder;
11177
11178 /* This can happen either due to bugs in the get_hw_state
11179 * functions or because the pipe is force-enabled due to the
11180 * pipe A quirk. */
11181 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11182 crtc->base.base.id,
11183 crtc->base.enabled ? "enabled" : "disabled",
11184 crtc->active ? "enabled" : "disabled");
11185
11186 crtc->base.enabled = crtc->active;
11187
11188 /* Because we only establish the connector -> encoder ->
11189 * crtc links if something is active, this means the
11190 * crtc is now deactivated. Break the links. connector
11191 * -> encoder links are only establish when things are
11192 * actually up, hence no need to break them. */
11193 WARN_ON(crtc->active);
11194
11195 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11196 WARN_ON(encoder->connectors_active);
11197 encoder->base.crtc = NULL;
11198 }
11199 }
11200 }
11201
11202 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11203 {
11204 struct intel_connector *connector;
11205 struct drm_device *dev = encoder->base.dev;
11206
11207 /* We need to check both for a crtc link (meaning that the
11208 * encoder is active and trying to read from a pipe) and the
11209 * pipe itself being active. */
11210 bool has_active_crtc = encoder->base.crtc &&
11211 to_intel_crtc(encoder->base.crtc)->active;
11212
11213 if (encoder->connectors_active && !has_active_crtc) {
11214 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11215 encoder->base.base.id,
11216 drm_get_encoder_name(&encoder->base));
11217
11218 /* Connector is active, but has no active pipe. This is
11219 * fallout from our resume register restoring. Disable
11220 * the encoder manually again. */
11221 if (encoder->base.crtc) {
11222 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11223 encoder->base.base.id,
11224 drm_get_encoder_name(&encoder->base));
11225 encoder->disable(encoder);
11226 }
11227
11228 /* Inconsistent output/port/pipe state happens presumably due to
11229 * a bug in one of the get_hw_state functions. Or someplace else
11230 * in our code, like the register restore mess on resume. Clamp
11231 * things to off as a safer default. */
11232 list_for_each_entry(connector,
11233 &dev->mode_config.connector_list,
11234 base.head) {
11235 if (connector->encoder != encoder)
11236 continue;
11237
11238 intel_connector_break_all_links(connector);
11239 }
11240 }
11241 /* Enabled encoders without active connectors will be fixed in
11242 * the crtc fixup. */
11243 }
11244
11245 void i915_redisable_vga(struct drm_device *dev)
11246 {
11247 struct drm_i915_private *dev_priv = dev->dev_private;
11248 u32 vga_reg = i915_vgacntrl_reg(dev);
11249
11250 /* This function can be called both from intel_modeset_setup_hw_state or
11251 * at a very early point in our resume sequence, where the power well
11252 * structures are not yet restored. Since this function is at a very
11253 * paranoid "someone might have enabled VGA while we were not looking"
11254 * level, just check if the power well is enabled instead of trying to
11255 * follow the "don't touch the power well if we don't need it" policy
11256 * the rest of the driver uses. */
11257 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11258 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11259 return;
11260
11261 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11262 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11263 i915_disable_vga(dev);
11264 }
11265 }
11266
11267 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11268 {
11269 struct drm_i915_private *dev_priv = dev->dev_private;
11270 enum pipe pipe;
11271 struct intel_crtc *crtc;
11272 struct intel_encoder *encoder;
11273 struct intel_connector *connector;
11274 int i;
11275
11276 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11277 base.head) {
11278 memset(&crtc->config, 0, sizeof(crtc->config));
11279
11280 crtc->active = dev_priv->display.get_pipe_config(crtc,
11281 &crtc->config);
11282
11283 crtc->base.enabled = crtc->active;
11284 crtc->primary_enabled = crtc->active;
11285
11286 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11287 crtc->base.base.id,
11288 crtc->active ? "enabled" : "disabled");
11289 }
11290
11291 /* FIXME: Smash this into the new shared dpll infrastructure. */
11292 if (HAS_DDI(dev))
11293 intel_ddi_setup_hw_pll_state(dev);
11294
11295 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11296 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11297
11298 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11299 pll->active = 0;
11300 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11301 base.head) {
11302 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11303 pll->active++;
11304 }
11305 pll->refcount = pll->active;
11306
11307 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11308 pll->name, pll->refcount, pll->on);
11309 }
11310
11311 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11312 base.head) {
11313 pipe = 0;
11314
11315 if (encoder->get_hw_state(encoder, &pipe)) {
11316 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11317 encoder->base.crtc = &crtc->base;
11318 encoder->get_config(encoder, &crtc->config);
11319 } else {
11320 encoder->base.crtc = NULL;
11321 }
11322
11323 encoder->connectors_active = false;
11324 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11325 encoder->base.base.id,
11326 drm_get_encoder_name(&encoder->base),
11327 encoder->base.crtc ? "enabled" : "disabled",
11328 pipe_name(pipe));
11329 }
11330
11331 list_for_each_entry(connector, &dev->mode_config.connector_list,
11332 base.head) {
11333 if (connector->get_hw_state(connector)) {
11334 connector->base.dpms = DRM_MODE_DPMS_ON;
11335 connector->encoder->connectors_active = true;
11336 connector->base.encoder = &connector->encoder->base;
11337 } else {
11338 connector->base.dpms = DRM_MODE_DPMS_OFF;
11339 connector->base.encoder = NULL;
11340 }
11341 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11342 connector->base.base.id,
11343 drm_get_connector_name(&connector->base),
11344 connector->base.encoder ? "enabled" : "disabled");
11345 }
11346 }
11347
11348 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11349 * and i915 state tracking structures. */
11350 void intel_modeset_setup_hw_state(struct drm_device *dev,
11351 bool force_restore)
11352 {
11353 struct drm_i915_private *dev_priv = dev->dev_private;
11354 enum pipe pipe;
11355 struct intel_crtc *crtc;
11356 struct intel_encoder *encoder;
11357 int i;
11358
11359 intel_modeset_readout_hw_state(dev);
11360
11361 /*
11362 * Now that we have the config, copy it to each CRTC struct
11363 * Note that this could go away if we move to using crtc_config
11364 * checking everywhere.
11365 */
11366 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11367 base.head) {
11368 if (crtc->active && i915_fastboot) {
11369 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11370
11371 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11372 crtc->base.base.id);
11373 drm_mode_debug_printmodeline(&crtc->base.mode);
11374 }
11375 }
11376
11377 /* HW state is read out, now we need to sanitize this mess. */
11378 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11379 base.head) {
11380 intel_sanitize_encoder(encoder);
11381 }
11382
11383 for_each_pipe(pipe) {
11384 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11385 intel_sanitize_crtc(crtc);
11386 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11387 }
11388
11389 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11390 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11391
11392 if (!pll->on || pll->active)
11393 continue;
11394
11395 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11396
11397 pll->disable(dev_priv, pll);
11398 pll->on = false;
11399 }
11400
11401 if (HAS_PCH_SPLIT(dev))
11402 ilk_wm_get_hw_state(dev);
11403
11404 if (force_restore) {
11405 i915_redisable_vga(dev);
11406
11407 /*
11408 * We need to use raw interfaces for restoring state to avoid
11409 * checking (bogus) intermediate states.
11410 */
11411 for_each_pipe(pipe) {
11412 struct drm_crtc *crtc =
11413 dev_priv->pipe_to_crtc_mapping[pipe];
11414
11415 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11416 crtc->fb);
11417 }
11418 } else {
11419 intel_modeset_update_staged_output_state(dev);
11420 }
11421
11422 intel_modeset_check_state(dev);
11423 }
11424
11425 void intel_modeset_gem_init(struct drm_device *dev)
11426 {
11427 intel_modeset_init_hw(dev);
11428
11429 intel_setup_overlay(dev);
11430
11431 mutex_lock(&dev->mode_config.mutex);
11432 drm_mode_config_reset(dev);
11433 intel_modeset_setup_hw_state(dev, false);
11434 mutex_unlock(&dev->mode_config.mutex);
11435 }
11436
11437 void intel_modeset_cleanup(struct drm_device *dev)
11438 {
11439 struct drm_i915_private *dev_priv = dev->dev_private;
11440 struct drm_crtc *crtc;
11441 struct drm_connector *connector;
11442
11443 /*
11444 * Interrupts and polling as the first thing to avoid creating havoc.
11445 * Too much stuff here (turning of rps, connectors, ...) would
11446 * experience fancy races otherwise.
11447 */
11448 drm_irq_uninstall(dev);
11449 cancel_work_sync(&dev_priv->hotplug_work);
11450 /*
11451 * Due to the hpd irq storm handling the hotplug work can re-arm the
11452 * poll handlers. Hence disable polling after hpd handling is shut down.
11453 */
11454 drm_kms_helper_poll_fini(dev);
11455
11456 mutex_lock(&dev->struct_mutex);
11457
11458 intel_unregister_dsm_handler();
11459
11460 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11461 /* Skip inactive CRTCs */
11462 if (!crtc->fb)
11463 continue;
11464
11465 intel_increase_pllclock(crtc);
11466 }
11467
11468 intel_disable_fbc(dev);
11469
11470 intel_disable_gt_powersave(dev);
11471
11472 ironlake_teardown_rc6(dev);
11473
11474 mutex_unlock(&dev->struct_mutex);
11475
11476 /* flush any delayed tasks or pending work */
11477 flush_scheduled_work();
11478
11479 /* destroy the backlight and sysfs files before encoders/connectors */
11480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11481 intel_panel_destroy_backlight(connector);
11482 drm_sysfs_connector_remove(connector);
11483 }
11484
11485 drm_mode_config_cleanup(dev);
11486
11487 intel_cleanup_overlay(dev);
11488 }
11489
11490 /*
11491 * Return which encoder is currently attached for connector.
11492 */
11493 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11494 {
11495 return &intel_attached_encoder(connector)->base;
11496 }
11497
11498 void intel_connector_attach_encoder(struct intel_connector *connector,
11499 struct intel_encoder *encoder)
11500 {
11501 connector->encoder = encoder;
11502 drm_mode_connector_attach_encoder(&connector->base,
11503 &encoder->base);
11504 }
11505
11506 /*
11507 * set vga decode state - true == enable VGA decode
11508 */
11509 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11510 {
11511 struct drm_i915_private *dev_priv = dev->dev_private;
11512 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11513 u16 gmch_ctrl;
11514
11515 pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
11516 if (state)
11517 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11518 else
11519 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11520 pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
11521 return 0;
11522 }
11523
11524 struct intel_display_error_state {
11525
11526 u32 power_well_driver;
11527
11528 int num_transcoders;
11529
11530 struct intel_cursor_error_state {
11531 u32 control;
11532 u32 position;
11533 u32 base;
11534 u32 size;
11535 } cursor[I915_MAX_PIPES];
11536
11537 struct intel_pipe_error_state {
11538 bool power_domain_on;
11539 u32 source;
11540 } pipe[I915_MAX_PIPES];
11541
11542 struct intel_plane_error_state {
11543 u32 control;
11544 u32 stride;
11545 u32 size;
11546 u32 pos;
11547 u32 addr;
11548 u32 surface;
11549 u32 tile_offset;
11550 } plane[I915_MAX_PIPES];
11551
11552 struct intel_transcoder_error_state {
11553 bool power_domain_on;
11554 enum transcoder cpu_transcoder;
11555
11556 u32 conf;
11557
11558 u32 htotal;
11559 u32 hblank;
11560 u32 hsync;
11561 u32 vtotal;
11562 u32 vblank;
11563 u32 vsync;
11564 } transcoder[4];
11565 };
11566
11567 struct intel_display_error_state *
11568 intel_display_capture_error_state(struct drm_device *dev)
11569 {
11570 drm_i915_private_t *dev_priv = dev->dev_private;
11571 struct intel_display_error_state *error;
11572 int transcoders[] = {
11573 TRANSCODER_A,
11574 TRANSCODER_B,
11575 TRANSCODER_C,
11576 TRANSCODER_EDP,
11577 };
11578 int i;
11579
11580 if (INTEL_INFO(dev)->num_pipes == 0)
11581 return NULL;
11582
11583 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11584 if (error == NULL)
11585 return NULL;
11586
11587 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11588 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11589
11590 for_each_pipe(i) {
11591 error->pipe[i].power_domain_on =
11592 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11593 if (!error->pipe[i].power_domain_on)
11594 continue;
11595
11596 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11597 error->cursor[i].control = I915_READ(CURCNTR(i));
11598 error->cursor[i].position = I915_READ(CURPOS(i));
11599 error->cursor[i].base = I915_READ(CURBASE(i));
11600 } else {
11601 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11602 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11603 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11604 }
11605
11606 error->plane[i].control = I915_READ(DSPCNTR(i));
11607 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11608 if (INTEL_INFO(dev)->gen <= 3) {
11609 error->plane[i].size = I915_READ(DSPSIZE(i));
11610 error->plane[i].pos = I915_READ(DSPPOS(i));
11611 }
11612 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11613 error->plane[i].addr = I915_READ(DSPADDR(i));
11614 if (INTEL_INFO(dev)->gen >= 4) {
11615 error->plane[i].surface = I915_READ(DSPSURF(i));
11616 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11617 }
11618
11619 error->pipe[i].source = I915_READ(PIPESRC(i));
11620 }
11621
11622 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11623 if (HAS_DDI(dev_priv->dev))
11624 error->num_transcoders++; /* Account for eDP. */
11625
11626 for (i = 0; i < error->num_transcoders; i++) {
11627 enum transcoder cpu_transcoder = transcoders[i];
11628
11629 error->transcoder[i].power_domain_on =
11630 intel_display_power_enabled_sw(dev,
11631 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11632 if (!error->transcoder[i].power_domain_on)
11633 continue;
11634
11635 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11636
11637 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11638 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11639 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11640 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11641 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11642 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11643 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11644 }
11645
11646 return error;
11647 }
11648
11649 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11650
11651 void
11652 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11653 struct drm_device *dev,
11654 struct intel_display_error_state *error)
11655 {
11656 int i;
11657
11658 if (!error)
11659 return;
11660
11661 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11662 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11663 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11664 error->power_well_driver);
11665 for_each_pipe(i) {
11666 err_printf(m, "Pipe [%d]:\n", i);
11667 err_printf(m, " Power: %s\n",
11668 error->pipe[i].power_domain_on ? "on" : "off");
11669 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11670
11671 err_printf(m, "Plane [%d]:\n", i);
11672 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11673 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11674 if (INTEL_INFO(dev)->gen <= 3) {
11675 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11676 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11677 }
11678 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11679 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11680 if (INTEL_INFO(dev)->gen >= 4) {
11681 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11682 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11683 }
11684
11685 err_printf(m, "Cursor [%d]:\n", i);
11686 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11687 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11688 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11689 }
11690
11691 for (i = 0; i < error->num_transcoders; i++) {
11692 err_printf(m, "CPU transcoder: %c\n",
11693 transcoder_name(error->transcoder[i].cpu_transcoder));
11694 err_printf(m, " Power: %s\n",
11695 error->transcoder[i].power_domain_on ? "on" : "off");
11696 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11697 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11698 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11699 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11700 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11701 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11702 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11703 }
11704 }
Linux kernel - Deliverables
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