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drm/i915: set watermarks for third pipe on IVB
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41
42 #include "drm_crtc_helper.h"
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
90
91 static bool
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
94 static bool
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
97
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
100 {
101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
106 }
107
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
120 };
121
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
134 };
135
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
148 };
149
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
162 };
163
164
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
177 },
178 .find_pll = intel_g4x_find_best_PLL,
179 };
180
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
193 };
194
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
206 },
207 .find_pll = intel_g4x_find_best_PLL,
208 };
209
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
221 },
222 .find_pll = intel_g4x_find_best_PLL,
223 };
224
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
237 };
238
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
253 };
254
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
267 };
268
269 /* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
286 };
287
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
314 };
315
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
343 };
344
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
357 };
358
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
361 {
362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 const intel_limit_t *limit;
365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
370 if (refclk == 100000)
371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
375 if (refclk == 100000)
376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
383 else
384 limit = &intel_limits_ironlake_dac;
385
386 return limit;
387 }
388
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 {
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
399 limit = &intel_limits_g4x_dual_channel_lvds;
400 else
401 /* LVDS with dual channel */
402 limit = &intel_limits_g4x_single_channel_lvds;
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits_g4x_hdmi;
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits_g4x_sdvo;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409 limit = &intel_limits_g4x_display_port;
410 } else /* The option is for other outputs */
411 limit = &intel_limits_i9xx_sdvo;
412
413 return limit;
414 }
415
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 {
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
421 if (HAS_PCH_SPLIT(dev))
422 limit = intel_ironlake_limit(crtc, refclk);
423 else if (IS_G4X(dev)) {
424 limit = intel_g4x_limit(crtc);
425 } else if (IS_PINEVIEW(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_pineview_lvds;
428 else
429 limit = &intel_limits_pineview_sdvo;
430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437 limit = &intel_limits_i8xx_lvds;
438 else
439 limit = &intel_limits_i8xx_dvo;
440 }
441 return limit;
442 }
443
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
446 {
447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451 }
452
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 {
455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
457 return;
458 }
459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463 }
464
465 /**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 {
470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
479 }
480
481 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
482 /**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
490 {
491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
492 INTELPllInvalid("p1 out of range\n");
493 if (clock->p < limit->p.min || limit->p.max < clock->p)
494 INTELPllInvalid("p out of range\n");
495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
496 INTELPllInvalid("m2 out of range\n");
497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
498 INTELPllInvalid("m1 out of range\n");
499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500 INTELPllInvalid("m1 <= m2\n");
501 if (clock->m < limit->m.min || limit->m.max < clock->m)
502 INTELPllInvalid("m out of range\n");
503 if (clock->n < limit->n.min || limit->n.max < clock->n)
504 INTELPllInvalid("n out of range\n");
505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506 INTELPllInvalid("vco out of range\n");
507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511 INTELPllInvalid("dot out of range\n");
512
513 return true;
514 }
515
516 static bool
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
520 {
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
524 int err = target;
525
526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527 (I915_READ(LVDS)) != 0) {
528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
546 memset(best_clock, 0, sizeof(*best_clock));
547
548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
559 int this_err;
560
561 intel_clock(dev, refclk, &clock);
562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577 }
578
579 static bool
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582 {
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 int lvds_reg;
594
595 if (HAS_PCH_SPLIT(dev))
596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
613 /* based on hardware requirement, prefer smaller n to precision */
614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615 /* based on hardware requirement, prefere larger m1,m2 */
616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
624 intel_clock(dev, refclk, &clock);
625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
627 continue;
628
629 this_err = abs(clock.dot - target);
630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
640 return found;
641 }
642
643 static bool
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
646 {
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
649
650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666 }
667
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 static bool
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672 {
673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
693 }
694
695 /**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 {
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int pipestat_reg = PIPESTAT(pipe);
707
708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
724 /* Wait for vblank interrupt bit to set */
725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
728 DRM_DEBUG_KMS("vblank wait timed out\n");
729 }
730
731 /*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
746 *
747 */
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 {
750 struct drm_i915_private *dev_priv = dev->dev_private;
751
752 if (INTEL_INFO(dev)->gen >= 4) {
753 int reg = PIPECONF(pipe);
754
755 /* Wait for the Pipe State to go off */
756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
761 int reg = PIPEDSL(pipe);
762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
766 last_line = I915_READ(reg) & DSL_LINEMASK;
767 mdelay(5);
768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
773 }
774
775 static const char *state_string(bool enabled)
776 {
777 return enabled ? "on" : "off";
778 }
779
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783 {
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794 }
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
798 /* For ILK+ */
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801 {
802 int reg;
803 u32 val;
804 bool cur_state;
805
806 if (HAS_PCH_CPT(dev_priv->dev)) {
807 u32 pch_dpll;
808
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
814
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
817 }
818
819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
825 }
826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
831 {
832 int reg;
833 u32 val;
834 bool cur_state;
835
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
842 }
843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
848 {
849 int reg;
850 u32 val;
851 bool cur_state;
852
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
859 }
860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865 {
866 int reg;
867 u32 val;
868
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
871 return;
872
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876 }
877
878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879 enum pipe pipe)
880 {
881 int reg;
882 u32 val;
883
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887 }
888
889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891 {
892 int pp_reg, lvds_reg;
893 u32 val;
894 enum pipe panel_pipe = PIPE_A;
895 bool locked = true;
896
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
899 lvds_reg = PCH_LVDS;
900 } else {
901 pp_reg = PP_CONTROL;
902 lvds_reg = LVDS;
903 }
904
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908 locked = false;
909
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911 panel_pipe = PIPE_B;
912
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
915 pipe_name(pipe));
916 }
917
918 static void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
920 {
921 int reg;
922 u32 val;
923 bool cur_state;
924
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
930 pipe_name(pipe), state_string(state), state_string(cur_state));
931 }
932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
934
935 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
936 enum plane plane)
937 {
938 int reg;
939 u32 val;
940
941 reg = DSPCNTR(plane);
942 val = I915_READ(reg);
943 WARN(!(val & DISPLAY_PLANE_ENABLE),
944 "plane %c assertion failure, should be active but is disabled\n",
945 plane_name(plane));
946 }
947
948 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950 {
951 int reg, i;
952 u32 val;
953 int cur_pipe;
954
955 /* Planes are fixed to pipes on ILK+ */
956 if (HAS_PCH_SPLIT(dev_priv->dev))
957 return;
958
959 /* Need to check both planes against the pipe */
960 for (i = 0; i < 2; i++) {
961 reg = DSPCNTR(i);
962 val = I915_READ(reg);
963 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964 DISPPLANE_SEL_PIPE_SHIFT;
965 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
966 "plane %c assertion failure, should be off on pipe %c but is still active\n",
967 plane_name(i), pipe_name(pipe));
968 }
969 }
970
971 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
972 {
973 u32 val;
974 bool enabled;
975
976 val = I915_READ(PCH_DREF_CONTROL);
977 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978 DREF_SUPERSPREAD_SOURCE_MASK));
979 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980 }
981
982 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe)
984 {
985 int reg;
986 u32 val;
987 bool enabled;
988
989 reg = TRANSCONF(pipe);
990 val = I915_READ(reg);
991 enabled = !!(val & TRANS_ENABLE);
992 WARN(enabled,
993 "transcoder assertion failed, should be off on pipe %c but is still active\n",
994 pipe_name(pipe));
995 }
996
997 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998 enum pipe pipe, u32 port_sel, u32 val)
999 {
1000 if ((val & DP_PORT_EN) == 0)
1001 return false;
1002
1003 if (HAS_PCH_CPT(dev_priv->dev)) {
1004 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007 return false;
1008 } else {
1009 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010 return false;
1011 }
1012 return true;
1013 }
1014
1015 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 val)
1017 {
1018 if ((val & PORT_ENABLE) == 0)
1019 return false;
1020
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023 return false;
1024 } else {
1025 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026 return false;
1027 }
1028 return true;
1029 }
1030
1031 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe, u32 val)
1033 {
1034 if ((val & LVDS_PORT_EN) == 0)
1035 return false;
1036
1037 if (HAS_PCH_CPT(dev_priv->dev)) {
1038 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039 return false;
1040 } else {
1041 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042 return false;
1043 }
1044 return true;
1045 }
1046
1047 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, u32 val)
1049 {
1050 if ((val & ADPA_DAC_ENABLE) == 0)
1051 return false;
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054 return false;
1055 } else {
1056 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057 return false;
1058 }
1059 return true;
1060 }
1061
1062 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1063 enum pipe pipe, int reg, u32 port_sel)
1064 {
1065 u32 val = I915_READ(reg);
1066 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1067 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1068 reg, pipe_name(pipe));
1069 }
1070
1071 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, int reg)
1073 {
1074 u32 val = I915_READ(reg);
1075 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1076 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1077 reg, pipe_name(pipe));
1078 }
1079
1080 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe)
1082 {
1083 int reg;
1084 u32 val;
1085
1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1089
1090 reg = PCH_ADPA;
1091 val = I915_READ(reg);
1092 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1093 "PCH VGA enabled on transcoder %c, should be disabled\n",
1094 pipe_name(pipe));
1095
1096 reg = PCH_LVDS;
1097 val = I915_READ(reg);
1098 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1099 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1100 pipe_name(pipe));
1101
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105 }
1106
1107 /**
1108 * intel_enable_pll - enable a PLL
1109 * @dev_priv: i915 private structure
1110 * @pipe: pipe PLL to enable
1111 *
1112 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1113 * make sure the PLL reg is writable first though, since the panel write
1114 * protect mechanism may be enabled.
1115 *
1116 * Note! This is for pre-ILK only.
1117 */
1118 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119 {
1120 int reg;
1121 u32 val;
1122
1123 /* No really, not for ILK+ */
1124 BUG_ON(dev_priv->info->gen >= 5);
1125
1126 /* PLL is protected by panel, make sure we can write it */
1127 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128 assert_panel_unlocked(dev_priv, pipe);
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 val |= DPLL_VCO_ENABLE;
1133
1134 /* We do this three times for luck */
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(150); /* wait for warmup */
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(150); /* wait for warmup */
1141 I915_WRITE(reg, val);
1142 POSTING_READ(reg);
1143 udelay(150); /* wait for warmup */
1144 }
1145
1146 /**
1147 * intel_disable_pll - disable a PLL
1148 * @dev_priv: i915 private structure
1149 * @pipe: pipe PLL to disable
1150 *
1151 * Disable the PLL for @pipe, making sure the pipe is off first.
1152 *
1153 * Note! This is for pre-ILK only.
1154 */
1155 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157 int reg;
1158 u32 val;
1159
1160 /* Don't disable pipe A or pipe A PLLs if needed */
1161 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162 return;
1163
1164 /* Make sure the pipe isn't still relying on us */
1165 assert_pipe_disabled(dev_priv, pipe);
1166
1167 reg = DPLL(pipe);
1168 val = I915_READ(reg);
1169 val &= ~DPLL_VCO_ENABLE;
1170 I915_WRITE(reg, val);
1171 POSTING_READ(reg);
1172 }
1173
1174 /**
1175 * intel_enable_pch_pll - enable PCH PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to enable
1178 *
1179 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180 * drives the transcoder clock.
1181 */
1182 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183 enum pipe pipe)
1184 {
1185 int reg;
1186 u32 val;
1187
1188 if (pipe > 1)
1189 return;
1190
1191 /* PCH only available on ILK+ */
1192 BUG_ON(dev_priv->info->gen < 5);
1193
1194 /* PCH refclock must be enabled first */
1195 assert_pch_refclk_enabled(dev_priv);
1196
1197 reg = PCH_DPLL(pipe);
1198 val = I915_READ(reg);
1199 val |= DPLL_VCO_ENABLE;
1200 I915_WRITE(reg, val);
1201 POSTING_READ(reg);
1202 udelay(200);
1203 }
1204
1205 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207 {
1208 int reg;
1209 u32 val;
1210
1211 if (pipe > 1)
1212 return;
1213
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure transcoder isn't still depending on us */
1218 assert_transcoder_disabled(dev_priv, pipe);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226 }
1227
1228 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230 {
1231 int reg;
1232 u32 val;
1233
1234 /* PCH only available on ILK+ */
1235 BUG_ON(dev_priv->info->gen < 5);
1236
1237 /* Make sure PCH DPLL is enabled */
1238 assert_pch_pll_enabled(dev_priv, pipe);
1239
1240 /* FDI must be feeding us bits for PCH ports */
1241 assert_fdi_tx_enabled(dev_priv, pipe);
1242 assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244 reg = TRANSCONF(pipe);
1245 val = I915_READ(reg);
1246
1247 if (HAS_PCH_IBX(dev_priv->dev)) {
1248 /*
1249 * make the BPC in transcoder be consistent with
1250 * that in pipeconf reg.
1251 */
1252 val &= ~PIPE_BPC_MASK;
1253 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254 }
1255 I915_WRITE(reg, val | TRANS_ENABLE);
1256 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258 }
1259
1260 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262 {
1263 int reg;
1264 u32 val;
1265
1266 /* FDI relies on the transcoder */
1267 assert_fdi_tx_disabled(dev_priv, pipe);
1268 assert_fdi_rx_disabled(dev_priv, pipe);
1269
1270 /* Ports must be off as well */
1271 assert_pch_ports_disabled(dev_priv, pipe);
1272
1273 reg = TRANSCONF(pipe);
1274 val = I915_READ(reg);
1275 val &= ~TRANS_ENABLE;
1276 I915_WRITE(reg, val);
1277 /* wait for PCH transcoder off, transcoder state */
1278 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279 DRM_ERROR("failed to disable transcoder\n");
1280 }
1281
1282 /**
1283 * intel_enable_pipe - enable a pipe, asserting requirements
1284 * @dev_priv: i915 private structure
1285 * @pipe: pipe to enable
1286 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1287 *
1288 * Enable @pipe, making sure that various hardware specific requirements
1289 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290 *
1291 * @pipe should be %PIPE_A or %PIPE_B.
1292 *
1293 * Will wait until the pipe is actually running (i.e. first vblank) before
1294 * returning.
1295 */
1296 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297 bool pch_port)
1298 {
1299 int reg;
1300 u32 val;
1301
1302 /*
1303 * A pipe without a PLL won't actually be able to drive bits from
1304 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1305 * need the check.
1306 */
1307 if (!HAS_PCH_SPLIT(dev_priv->dev))
1308 assert_pll_enabled(dev_priv, pipe);
1309 else {
1310 if (pch_port) {
1311 /* if driving the PCH, we need FDI enabled */
1312 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314 }
1315 /* FIXME: assert CPU port conditions for SNB+ */
1316 }
1317
1318 reg = PIPECONF(pipe);
1319 val = I915_READ(reg);
1320 if (val & PIPECONF_ENABLE)
1321 return;
1322
1323 I915_WRITE(reg, val | PIPECONF_ENABLE);
1324 intel_wait_for_vblank(dev_priv->dev, pipe);
1325 }
1326
1327 /**
1328 * intel_disable_pipe - disable a pipe, asserting requirements
1329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to disable
1331 *
1332 * Disable @pipe, making sure that various hardware specific requirements
1333 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334 *
1335 * @pipe should be %PIPE_A or %PIPE_B.
1336 *
1337 * Will wait until the pipe has shut down before returning.
1338 */
1339 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341 {
1342 int reg;
1343 u32 val;
1344
1345 /*
1346 * Make sure planes won't keep trying to pump pixels to us,
1347 * or we might hang the display.
1348 */
1349 assert_planes_disabled(dev_priv, pipe);
1350
1351 /* Don't disable pipe A or pipe A PLLs if needed */
1352 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353 return;
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
1357 if ((val & PIPECONF_ENABLE) == 0)
1358 return;
1359
1360 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1361 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362 }
1363
1364 /*
1365 * Plane regs are double buffered, going from enabled->disabled needs a
1366 * trigger in order to latch. The display address reg provides this.
1367 */
1368 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369 enum plane plane)
1370 {
1371 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373 }
1374
1375 /**
1376 * intel_enable_plane - enable a display plane on a given pipe
1377 * @dev_priv: i915 private structure
1378 * @plane: plane to enable
1379 * @pipe: pipe being fed
1380 *
1381 * Enable @plane on @pipe, making sure that @pipe is running first.
1382 */
1383 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384 enum plane plane, enum pipe pipe)
1385 {
1386 int reg;
1387 u32 val;
1388
1389 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390 assert_pipe_enabled(dev_priv, pipe);
1391
1392 reg = DSPCNTR(plane);
1393 val = I915_READ(reg);
1394 if (val & DISPLAY_PLANE_ENABLE)
1395 return;
1396
1397 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1398 intel_flush_display_plane(dev_priv, plane);
1399 intel_wait_for_vblank(dev_priv->dev, pipe);
1400 }
1401
1402 /**
1403 * intel_disable_plane - disable a display plane
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to disable
1406 * @pipe: pipe consuming the data
1407 *
1408 * Disable @plane; should be an independent operation.
1409 */
1410 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1412 {
1413 int reg;
1414 u32 val;
1415
1416 reg = DSPCNTR(plane);
1417 val = I915_READ(reg);
1418 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419 return;
1420
1421 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1422 intel_flush_display_plane(dev_priv, plane);
1423 intel_wait_for_vblank(dev_priv->dev, pipe);
1424 }
1425
1426 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1427 enum pipe pipe, int reg, u32 port_sel)
1428 {
1429 u32 val = I915_READ(reg);
1430 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1431 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1432 I915_WRITE(reg, val & ~DP_PORT_EN);
1433 }
1434 }
1435
1436 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg)
1438 {
1439 u32 val = I915_READ(reg);
1440 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1441 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442 reg, pipe);
1443 I915_WRITE(reg, val & ~PORT_ENABLE);
1444 }
1445 }
1446
1447 /* Disable any ports connected to this transcoder */
1448 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450 {
1451 u32 reg, val;
1452
1453 val = I915_READ(PCH_PP_CONTROL);
1454 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
1456 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1459
1460 reg = PCH_ADPA;
1461 val = I915_READ(reg);
1462 if (adpa_pipe_enabled(dev_priv, val, pipe))
1463 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465 reg = PCH_LVDS;
1466 val = I915_READ(reg);
1467 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1469 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470 POSTING_READ(reg);
1471 udelay(100);
1472 }
1473
1474 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476 disable_pch_hdmi(dev_priv, pipe, HDMID);
1477 }
1478
1479 static void i8xx_disable_fbc(struct drm_device *dev)
1480 {
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 fbc_ctl;
1483
1484 /* Disable compression */
1485 fbc_ctl = I915_READ(FBC_CONTROL);
1486 if ((fbc_ctl & FBC_CTL_EN) == 0)
1487 return;
1488
1489 fbc_ctl &= ~FBC_CTL_EN;
1490 I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492 /* Wait for compressing bit to clear */
1493 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494 DRM_DEBUG_KMS("FBC idle timed out\n");
1495 return;
1496 }
1497
1498 DRM_DEBUG_KMS("disabled FBC\n");
1499 }
1500
1501 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502 {
1503 struct drm_device *dev = crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_framebuffer *fb = crtc->fb;
1506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1507 struct drm_i915_gem_object *obj = intel_fb->obj;
1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1509 int cfb_pitch;
1510 int plane, i;
1511 u32 fbc_ctl, fbc_ctl2;
1512
1513 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514 if (fb->pitch < cfb_pitch)
1515 cfb_pitch = fb->pitch;
1516
1517 /* FBC_CTL wants 64B units */
1518 cfb_pitch = (cfb_pitch / 64) - 1;
1519 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1520
1521 /* Clear old tags */
1522 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525 /* Set it up... */
1526 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527 fbc_ctl2 |= plane;
1528 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531 /* enable it... */
1532 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1533 if (IS_I945GM(dev))
1534 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1535 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1536 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1537 fbc_ctl |= obj->fence_reg;
1538 I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
1540 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541 cfb_pitch, crtc->y, intel_crtc->plane);
1542 }
1543
1544 static bool i8xx_fbc_enabled(struct drm_device *dev)
1545 {
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549 }
1550
1551 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557 struct drm_i915_gem_object *obj = intel_fb->obj;
1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1560 unsigned long stall_watermark = 200;
1561 u32 dpfc_ctl;
1562
1563 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1564 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1565 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1566
1567 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572 /* enable it... */
1573 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
1575 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1576 }
1577
1578 static void g4x_disable_fbc(struct drm_device *dev)
1579 {
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 u32 dpfc_ctl;
1582
1583 /* Disable compression */
1584 dpfc_ctl = I915_READ(DPFC_CONTROL);
1585 if (dpfc_ctl & DPFC_CTL_EN) {
1586 dpfc_ctl &= ~DPFC_CTL_EN;
1587 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1588
1589 DRM_DEBUG_KMS("disabled FBC\n");
1590 }
1591 }
1592
1593 static bool g4x_fbc_enabled(struct drm_device *dev)
1594 {
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598 }
1599
1600 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601 {
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 u32 blt_ecoskpd;
1604
1605 /* Make sure blitter notifies FBC of writes */
1606 gen6_gt_force_wake_get(dev_priv);
1607 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609 GEN6_BLITTER_LOCK_SHIFT;
1610 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614 GEN6_BLITTER_LOCK_SHIFT);
1615 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1617 gen6_gt_force_wake_put(dev_priv);
1618 }
1619
1620 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621 {
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_framebuffer *fb = crtc->fb;
1625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1626 struct drm_i915_gem_object *obj = intel_fb->obj;
1627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1629 unsigned long stall_watermark = 200;
1630 u32 dpfc_ctl;
1631
1632 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1633 dpfc_ctl &= DPFC_RESERVED;
1634 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1635 /* Set persistent mode for front-buffer rendering, ala X. */
1636 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1637 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1638 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1639
1640 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1644 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1645 /* enable it... */
1646 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1647
1648 if (IS_GEN6(dev)) {
1649 I915_WRITE(SNB_DPFC_CTL_SA,
1650 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1651 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1652 sandybridge_blit_fbc_update(dev);
1653 }
1654
1655 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656 }
1657
1658 static void ironlake_disable_fbc(struct drm_device *dev)
1659 {
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 u32 dpfc_ctl;
1662
1663 /* Disable compression */
1664 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1665 if (dpfc_ctl & DPFC_CTL_EN) {
1666 dpfc_ctl &= ~DPFC_CTL_EN;
1667 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1668
1669 DRM_DEBUG_KMS("disabled FBC\n");
1670 }
1671 }
1672
1673 static bool ironlake_fbc_enabled(struct drm_device *dev)
1674 {
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678 }
1679
1680 bool intel_fbc_enabled(struct drm_device *dev)
1681 {
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.fbc_enabled)
1685 return false;
1686
1687 return dev_priv->display.fbc_enabled(dev);
1688 }
1689
1690 static void intel_fbc_work_fn(struct work_struct *__work)
1691 {
1692 struct intel_fbc_work *work =
1693 container_of(to_delayed_work(__work),
1694 struct intel_fbc_work, work);
1695 struct drm_device *dev = work->crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698 mutex_lock(&dev->struct_mutex);
1699 if (work == dev_priv->fbc_work) {
1700 /* Double check that we haven't switched fb without cancelling
1701 * the prior work.
1702 */
1703 if (work->crtc->fb == work->fb) {
1704 dev_priv->display.enable_fbc(work->crtc,
1705 work->interval);
1706
1707 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708 dev_priv->cfb_fb = work->crtc->fb->base.id;
1709 dev_priv->cfb_y = work->crtc->y;
1710 }
1711
1712 dev_priv->fbc_work = NULL;
1713 }
1714 mutex_unlock(&dev->struct_mutex);
1715
1716 kfree(work);
1717 }
1718
1719 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720 {
1721 if (dev_priv->fbc_work == NULL)
1722 return;
1723
1724 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726 /* Synchronisation is provided by struct_mutex and checking of
1727 * dev_priv->fbc_work, so we can perform the cancellation
1728 * entirely asynchronously.
1729 */
1730 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731 /* tasklet was killed before being run, clean up */
1732 kfree(dev_priv->fbc_work);
1733
1734 /* Mark the work as no longer wanted so that if it does
1735 * wake-up (because the work was already running and waiting
1736 * for our mutex), it will discover that is no longer
1737 * necessary to run.
1738 */
1739 dev_priv->fbc_work = NULL;
1740 }
1741
1742 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1743 {
1744 struct intel_fbc_work *work;
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 if (!dev_priv->display.enable_fbc)
1749 return;
1750
1751 intel_cancel_fbc_work(dev_priv);
1752
1753 work = kzalloc(sizeof *work, GFP_KERNEL);
1754 if (work == NULL) {
1755 dev_priv->display.enable_fbc(crtc, interval);
1756 return;
1757 }
1758
1759 work->crtc = crtc;
1760 work->fb = crtc->fb;
1761 work->interval = interval;
1762 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764 dev_priv->fbc_work = work;
1765
1766 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768 /* Delay the actual enabling to let pageflipping cease and the
1769 * display to settle before starting the compression. Note that
1770 * this delay also serves a second purpose: it allows for a
1771 * vblank to pass after disabling the FBC before we attempt
1772 * to modify the control registers.
1773 *
1774 * A more complicated solution would involve tracking vblanks
1775 * following the termination of the page-flipping sequence
1776 * and indeed performing the enable as a co-routine and not
1777 * waiting synchronously upon the vblank.
1778 */
1779 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1780 }
1781
1782 void intel_disable_fbc(struct drm_device *dev)
1783 {
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785
1786 intel_cancel_fbc_work(dev_priv);
1787
1788 if (!dev_priv->display.disable_fbc)
1789 return;
1790
1791 dev_priv->display.disable_fbc(dev);
1792 dev_priv->cfb_plane = -1;
1793 }
1794
1795 /**
1796 * intel_update_fbc - enable/disable FBC as needed
1797 * @dev: the drm_device
1798 *
1799 * Set up the framebuffer compression hardware at mode set time. We
1800 * enable it if possible:
1801 * - plane A only (on pre-965)
1802 * - no pixel mulitply/line duplication
1803 * - no alpha buffer discard
1804 * - no dual wide
1805 * - framebuffer <= 2048 in width, 1536 in height
1806 *
1807 * We can't assume that any compression will take place (worst case),
1808 * so the compressed buffer has to be the same size as the uncompressed
1809 * one. It also must reside (along with the line length buffer) in
1810 * stolen memory.
1811 *
1812 * We need to enable/disable FBC on a global basis.
1813 */
1814 static void intel_update_fbc(struct drm_device *dev)
1815 {
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 struct drm_crtc *crtc = NULL, *tmp_crtc;
1818 struct intel_crtc *intel_crtc;
1819 struct drm_framebuffer *fb;
1820 struct intel_framebuffer *intel_fb;
1821 struct drm_i915_gem_object *obj;
1822 int enable_fbc;
1823
1824 DRM_DEBUG_KMS("\n");
1825
1826 if (!i915_powersave)
1827 return;
1828
1829 if (!I915_HAS_FBC(dev))
1830 return;
1831
1832 /*
1833 * If FBC is already on, we just have to verify that we can
1834 * keep it that way...
1835 * Need to disable if:
1836 * - more than one pipe is active
1837 * - changing FBC params (stride, fence, mode)
1838 * - new fb is too large to fit in compressed buffer
1839 * - going to an unsupported config (interlace, pixel multiply, etc.)
1840 */
1841 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1842 if (tmp_crtc->enabled && tmp_crtc->fb) {
1843 if (crtc) {
1844 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846 goto out_disable;
1847 }
1848 crtc = tmp_crtc;
1849 }
1850 }
1851
1852 if (!crtc || crtc->fb == NULL) {
1853 DRM_DEBUG_KMS("no output, disabling\n");
1854 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1855 goto out_disable;
1856 }
1857
1858 intel_crtc = to_intel_crtc(crtc);
1859 fb = crtc->fb;
1860 intel_fb = to_intel_framebuffer(fb);
1861 obj = intel_fb->obj;
1862
1863 enable_fbc = i915_enable_fbc;
1864 if (enable_fbc < 0) {
1865 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866 enable_fbc = 1;
1867 if (INTEL_INFO(dev)->gen <= 5)
1868 enable_fbc = 0;
1869 }
1870 if (!enable_fbc) {
1871 DRM_DEBUG_KMS("fbc disabled per module param\n");
1872 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873 goto out_disable;
1874 }
1875 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1876 DRM_DEBUG_KMS("framebuffer too large, disabling "
1877 "compression\n");
1878 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1879 goto out_disable;
1880 }
1881 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1883 DRM_DEBUG_KMS("mode incompatible with compression, "
1884 "disabling\n");
1885 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1886 goto out_disable;
1887 }
1888 if ((crtc->mode.hdisplay > 2048) ||
1889 (crtc->mode.vdisplay > 1536)) {
1890 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1892 goto out_disable;
1893 }
1894 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1895 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1896 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1897 goto out_disable;
1898 }
1899
1900 /* The use of a CPU fence is mandatory in order to detect writes
1901 * by the CPU to the scanout and trigger updates to the FBC.
1902 */
1903 if (obj->tiling_mode != I915_TILING_X ||
1904 obj->fence_reg == I915_FENCE_REG_NONE) {
1905 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1906 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1907 goto out_disable;
1908 }
1909
1910 /* If the kernel debugger is active, always disable compression */
1911 if (in_dbg_master())
1912 goto out_disable;
1913
1914 /* If the scanout has not changed, don't modify the FBC settings.
1915 * Note that we make the fundamental assumption that the fb->obj
1916 * cannot be unpinned (and have its GTT offset and fence revoked)
1917 * without first being decoupled from the scanout and FBC disabled.
1918 */
1919 if (dev_priv->cfb_plane == intel_crtc->plane &&
1920 dev_priv->cfb_fb == fb->base.id &&
1921 dev_priv->cfb_y == crtc->y)
1922 return;
1923
1924 if (intel_fbc_enabled(dev)) {
1925 /* We update FBC along two paths, after changing fb/crtc
1926 * configuration (modeswitching) and after page-flipping
1927 * finishes. For the latter, we know that not only did
1928 * we disable the FBC at the start of the page-flip
1929 * sequence, but also more than one vblank has passed.
1930 *
1931 * For the former case of modeswitching, it is possible
1932 * to switch between two FBC valid configurations
1933 * instantaneously so we do need to disable the FBC
1934 * before we can modify its control registers. We also
1935 * have to wait for the next vblank for that to take
1936 * effect. However, since we delay enabling FBC we can
1937 * assume that a vblank has passed since disabling and
1938 * that we can safely alter the registers in the deferred
1939 * callback.
1940 *
1941 * In the scenario that we go from a valid to invalid
1942 * and then back to valid FBC configuration we have
1943 * no strict enforcement that a vblank occurred since
1944 * disabling the FBC. However, along all current pipe
1945 * disabling paths we do need to wait for a vblank at
1946 * some point. And we wait before enabling FBC anyway.
1947 */
1948 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949 intel_disable_fbc(dev);
1950 }
1951
1952 intel_enable_fbc(crtc, 500);
1953 return;
1954
1955 out_disable:
1956 /* Multiple disables should be harmless */
1957 if (intel_fbc_enabled(dev)) {
1958 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1959 intel_disable_fbc(dev);
1960 }
1961 }
1962
1963 int
1964 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1965 struct drm_i915_gem_object *obj,
1966 struct intel_ring_buffer *pipelined)
1967 {
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1969 u32 alignment;
1970 int ret;
1971
1972 switch (obj->tiling_mode) {
1973 case I915_TILING_NONE:
1974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
1976 else if (INTEL_INFO(dev)->gen >= 4)
1977 alignment = 4 * 1024;
1978 else
1979 alignment = 64 * 1024;
1980 break;
1981 case I915_TILING_X:
1982 /* pin() will align the object as required by fence */
1983 alignment = 0;
1984 break;
1985 case I915_TILING_Y:
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988 return -EINVAL;
1989 default:
1990 BUG();
1991 }
1992
1993 dev_priv->mm.interruptible = false;
1994 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1995 if (ret)
1996 goto err_interruptible;
1997
1998 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999 * fence, whereas 965+ only requires a fence if using
2000 * framebuffer compression. For simplicity, we always install
2001 * a fence as the cost is not that onerous.
2002 */
2003 if (obj->tiling_mode != I915_TILING_NONE) {
2004 ret = i915_gem_object_get_fence(obj, pipelined);
2005 if (ret)
2006 goto err_unpin;
2007 }
2008
2009 dev_priv->mm.interruptible = true;
2010 return 0;
2011
2012 err_unpin:
2013 i915_gem_object_unpin(obj);
2014 err_interruptible:
2015 dev_priv->mm.interruptible = true;
2016 return ret;
2017 }
2018
2019 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020 int x, int y)
2021 {
2022 struct drm_device *dev = crtc->dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025 struct intel_framebuffer *intel_fb;
2026 struct drm_i915_gem_object *obj;
2027 int plane = intel_crtc->plane;
2028 unsigned long Start, Offset;
2029 u32 dspcntr;
2030 u32 reg;
2031
2032 switch (plane) {
2033 case 0:
2034 case 1:
2035 break;
2036 default:
2037 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2043
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->bits_per_pixel) {
2049 case 8:
2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
2052 case 16:
2053 if (fb->depth == 15)
2054 dspcntr |= DISPPLANE_15_16BPP;
2055 else
2056 dspcntr |= DISPPLANE_16BPP;
2057 break;
2058 case 24:
2059 case 32:
2060 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061 break;
2062 default:
2063 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2064 return -EINVAL;
2065 }
2066 if (INTEL_INFO(dev)->gen >= 4) {
2067 if (obj->tiling_mode != I915_TILING_NONE)
2068 dspcntr |= DISPPLANE_TILED;
2069 else
2070 dspcntr &= ~DISPPLANE_TILED;
2071 }
2072
2073 I915_WRITE(reg, dspcntr);
2074
2075 Start = obj->gtt_offset;
2076 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 Start, Offset, x, y, fb->pitch);
2080 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2081 if (INTEL_INFO(dev)->gen >= 4) {
2082 I915_WRITE(DSPSURF(plane), Start);
2083 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084 I915_WRITE(DSPADDR(plane), Offset);
2085 } else
2086 I915_WRITE(DSPADDR(plane), Start + Offset);
2087 POSTING_READ(reg);
2088
2089 return 0;
2090 }
2091
2092 static int ironlake_update_plane(struct drm_crtc *crtc,
2093 struct drm_framebuffer *fb, int x, int y)
2094 {
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098 struct intel_framebuffer *intel_fb;
2099 struct drm_i915_gem_object *obj;
2100 int plane = intel_crtc->plane;
2101 unsigned long Start, Offset;
2102 u32 dspcntr;
2103 u32 reg;
2104
2105 switch (plane) {
2106 case 0:
2107 case 1:
2108 case 2:
2109 break;
2110 default:
2111 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112 return -EINVAL;
2113 }
2114
2115 intel_fb = to_intel_framebuffer(fb);
2116 obj = intel_fb->obj;
2117
2118 reg = DSPCNTR(plane);
2119 dspcntr = I915_READ(reg);
2120 /* Mask out pixel format bits in case we change it */
2121 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122 switch (fb->bits_per_pixel) {
2123 case 8:
2124 dspcntr |= DISPPLANE_8BPP;
2125 break;
2126 case 16:
2127 if (fb->depth != 16)
2128 return -EINVAL;
2129
2130 dspcntr |= DISPPLANE_16BPP;
2131 break;
2132 case 24:
2133 case 32:
2134 if (fb->depth == 24)
2135 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136 else if (fb->depth == 30)
2137 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138 else
2139 return -EINVAL;
2140 break;
2141 default:
2142 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143 return -EINVAL;
2144 }
2145
2146 if (obj->tiling_mode != I915_TILING_NONE)
2147 dspcntr |= DISPPLANE_TILED;
2148 else
2149 dspcntr &= ~DISPPLANE_TILED;
2150
2151 /* must disable */
2152 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154 I915_WRITE(reg, dspcntr);
2155
2156 Start = obj->gtt_offset;
2157 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 Start, Offset, x, y, fb->pitch);
2161 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2165 POSTING_READ(reg);
2166
2167 return 0;
2168 }
2169
2170 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 static int
2172 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173 int x, int y, enum mode_set_atomic state)
2174 {
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 int ret;
2178
2179 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180 if (ret)
2181 return ret;
2182
2183 intel_update_fbc(dev);
2184 intel_increase_pllclock(crtc);
2185
2186 return 0;
2187 }
2188
2189 static int
2190 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191 struct drm_framebuffer *old_fb)
2192 {
2193 struct drm_device *dev = crtc->dev;
2194 struct drm_i915_master_private *master_priv;
2195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2196 int ret;
2197
2198 /* no fb bound */
2199 if (!crtc->fb) {
2200 DRM_ERROR("No FB bound\n");
2201 return 0;
2202 }
2203
2204 switch (intel_crtc->plane) {
2205 case 0:
2206 case 1:
2207 break;
2208 case 2:
2209 if (IS_IVYBRIDGE(dev))
2210 break;
2211 /* fall through otherwise */
2212 default:
2213 DRM_ERROR("no plane for crtc\n");
2214 return -EINVAL;
2215 }
2216
2217 mutex_lock(&dev->struct_mutex);
2218 ret = intel_pin_and_fence_fb_obj(dev,
2219 to_intel_framebuffer(crtc->fb)->obj,
2220 NULL);
2221 if (ret != 0) {
2222 mutex_unlock(&dev->struct_mutex);
2223 DRM_ERROR("pin & fence failed\n");
2224 return ret;
2225 }
2226
2227 if (old_fb) {
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2230
2231 wait_event(dev_priv->pending_flip_queue,
2232 atomic_read(&dev_priv->mm.wedged) ||
2233 atomic_read(&obj->pending_flip) == 0);
2234
2235 /* Big Hammer, we also need to ensure that any pending
2236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237 * current scanout is retired before unpinning the old
2238 * framebuffer.
2239 *
2240 * This should only fail upon a hung GPU, in which case we
2241 * can safely continue.
2242 */
2243 ret = i915_gem_object_finish_gpu(obj);
2244 (void) ret;
2245 }
2246
2247 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248 LEAVE_ATOMIC_MODE_SET);
2249 if (ret) {
2250 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2251 mutex_unlock(&dev->struct_mutex);
2252 DRM_ERROR("failed to update base address\n");
2253 return ret;
2254 }
2255
2256 if (old_fb) {
2257 intel_wait_for_vblank(dev, intel_crtc->pipe);
2258 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2259 }
2260
2261 mutex_unlock(&dev->struct_mutex);
2262
2263 if (!dev->primary->master)
2264 return 0;
2265
2266 master_priv = dev->primary->master->driver_priv;
2267 if (!master_priv->sarea_priv)
2268 return 0;
2269
2270 if (intel_crtc->pipe) {
2271 master_priv->sarea_priv->pipeB_x = x;
2272 master_priv->sarea_priv->pipeB_y = y;
2273 } else {
2274 master_priv->sarea_priv->pipeA_x = x;
2275 master_priv->sarea_priv->pipeA_y = y;
2276 }
2277
2278 return 0;
2279 }
2280
2281 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2282 {
2283 struct drm_device *dev = crtc->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 u32 dpa_ctl;
2286
2287 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2288 dpa_ctl = I915_READ(DP_A);
2289 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291 if (clock < 200000) {
2292 u32 temp;
2293 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294 /* workaround for 160Mhz:
2295 1) program 0x4600c bits 15:0 = 0x8124
2296 2) program 0x46010 bit 0 = 1
2297 3) program 0x46034 bit 24 = 1
2298 4) program 0x64000 bit 14 = 1
2299 */
2300 temp = I915_READ(0x4600c);
2301 temp &= 0xffff0000;
2302 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304 temp = I915_READ(0x46010);
2305 I915_WRITE(0x46010, temp | 1);
2306
2307 temp = I915_READ(0x46034);
2308 I915_WRITE(0x46034, temp | (1 << 24));
2309 } else {
2310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311 }
2312 I915_WRITE(DP_A, dpa_ctl);
2313
2314 POSTING_READ(DP_A);
2315 udelay(500);
2316 }
2317
2318 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319 {
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 u32 reg, temp;
2325
2326 /* enable normal train */
2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
2329 if (IS_IVYBRIDGE(dev)) {
2330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2335 }
2336 I915_WRITE(reg, temp);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343 } else {
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2346 }
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349 /* wait one idle pattern time */
2350 POSTING_READ(reg);
2351 udelay(1000);
2352
2353 /* IVB wants error correction enabled */
2354 if (IS_IVYBRIDGE(dev))
2355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356 FDI_FE_ERRC_ENABLE);
2357 }
2358
2359 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360 {
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364 flags |= FDI_PHASE_SYNC_OVR(pipe);
2365 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366 flags |= FDI_PHASE_SYNC_EN(pipe);
2367 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368 POSTING_READ(SOUTH_CHICKEN1);
2369 }
2370
2371 /* The FDI link training functions for ILK/Ibexpeak. */
2372 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373 {
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 int pipe = intel_crtc->pipe;
2378 int plane = intel_crtc->plane;
2379 u32 reg, temp, tries;
2380
2381 /* FDI needs bits from pipe & plane first */
2382 assert_pipe_enabled(dev_priv, pipe);
2383 assert_plane_enabled(dev_priv, plane);
2384
2385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386 for train result */
2387 reg = FDI_RX_IMR(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_RX_SYMBOL_LOCK;
2390 temp &= ~FDI_RX_BIT_LOCK;
2391 I915_WRITE(reg, temp);
2392 I915_READ(reg);
2393 udelay(150);
2394
2395 /* enable CPU FDI TX and PCH FDI RX */
2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
2398 temp &= ~(7 << 19);
2399 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_PATTERN_1;
2402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2403
2404 reg = FDI_RX_CTL(pipe);
2405 temp = I915_READ(reg);
2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_PATTERN_1;
2408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410 POSTING_READ(reg);
2411 udelay(150);
2412
2413 /* Ironlake workaround, enable clock pointer after FDI enable*/
2414 if (HAS_PCH_IBX(dev)) {
2415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417 FDI_RX_PHASE_SYNC_POINTER_EN);
2418 }
2419
2420 reg = FDI_RX_IIR(pipe);
2421 for (tries = 0; tries < 5; tries++) {
2422 temp = I915_READ(reg);
2423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425 if ((temp & FDI_RX_BIT_LOCK)) {
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
2427 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2428 break;
2429 }
2430 }
2431 if (tries == 5)
2432 DRM_ERROR("FDI train 1 fail!\n");
2433
2434 /* Train 2 */
2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_2;
2439 I915_WRITE(reg, temp);
2440
2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_2;
2445 I915_WRITE(reg, temp);
2446
2447 POSTING_READ(reg);
2448 udelay(150);
2449
2450 reg = FDI_RX_IIR(pipe);
2451 for (tries = 0; tries < 5; tries++) {
2452 temp = I915_READ(reg);
2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if (temp & FDI_RX_SYMBOL_LOCK) {
2456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2457 DRM_DEBUG_KMS("FDI train 2 done.\n");
2458 break;
2459 }
2460 }
2461 if (tries == 5)
2462 DRM_ERROR("FDI train 2 fail!\n");
2463
2464 DRM_DEBUG_KMS("FDI train done\n");
2465
2466 }
2467
2468 static const int snb_b_fdi_train_param[] = {
2469 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473 };
2474
2475 /* The FDI link training functions for SNB/Cougarpoint. */
2476 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477 {
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
2482 u32 reg, temp, i;
2483
2484 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485 for train result */
2486 reg = FDI_RX_IMR(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_RX_SYMBOL_LOCK;
2489 temp &= ~FDI_RX_BIT_LOCK;
2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
2493 udelay(150);
2494
2495 /* enable CPU FDI TX and PCH FDI RX */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2506
2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
2509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 }
2516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518 POSTING_READ(reg);
2519 udelay(150);
2520
2521 if (HAS_PCH_CPT(dev))
2522 cpt_phase_pointer_enable(dev, pipe);
2523
2524 for (i = 0; i < 4; i++) {
2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
2527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= snb_b_fdi_train_param[i];
2529 I915_WRITE(reg, temp);
2530
2531 POSTING_READ(reg);
2532 udelay(500);
2533
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_BIT_LOCK) {
2539 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2540 DRM_DEBUG_KMS("FDI train 1 done.\n");
2541 break;
2542 }
2543 }
2544 if (i == 4)
2545 DRM_ERROR("FDI train 1 fail!\n");
2546
2547 /* Train 2 */
2548 reg = FDI_TX_CTL(pipe);
2549 temp = I915_READ(reg);
2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 if (IS_GEN6(dev)) {
2553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554 /* SNB-B */
2555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556 }
2557 I915_WRITE(reg, temp);
2558
2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
2561 if (HAS_PCH_CPT(dev)) {
2562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564 } else {
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567 }
2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
2571 udelay(150);
2572
2573 for (i = 0; i < 4; i++) {
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577 temp |= snb_b_fdi_train_param[i];
2578 I915_WRITE(reg, temp);
2579
2580 POSTING_READ(reg);
2581 udelay(500);
2582
2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587 if (temp & FDI_RX_SYMBOL_LOCK) {
2588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2589 DRM_DEBUG_KMS("FDI train 2 done.\n");
2590 break;
2591 }
2592 }
2593 if (i == 4)
2594 DRM_ERROR("FDI train 2 fail!\n");
2595
2596 DRM_DEBUG_KMS("FDI train done.\n");
2597 }
2598
2599 /* Manual link training for Ivy Bridge A0 parts */
2600 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601 {
2602 struct drm_device *dev = crtc->dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605 int pipe = intel_crtc->pipe;
2606 u32 reg, temp, i;
2607
2608 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 for train result */
2610 reg = FDI_RX_IMR(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_RX_SYMBOL_LOCK;
2613 temp &= ~FDI_RX_BIT_LOCK;
2614 I915_WRITE(reg, temp);
2615
2616 POSTING_READ(reg);
2617 udelay(150);
2618
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~(7 << 19);
2623 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628 temp |= FDI_COMPOSITE_SYNC;
2629 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_AUTO;
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636 temp |= FDI_COMPOSITE_SYNC;
2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
2642 if (HAS_PCH_CPT(dev))
2643 cpt_phase_pointer_enable(dev, pipe);
2644
2645 for (i = 0; i < 4; i++) {
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(500);
2654
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659 if (temp & FDI_RX_BIT_LOCK ||
2660 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662 DRM_DEBUG_KMS("FDI train 1 done.\n");
2663 break;
2664 }
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676 I915_WRITE(reg, temp);
2677
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
2687 for (i = 0; i < 4; i++) {
2688 reg = FDI_TX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691 temp |= snb_b_fdi_train_param[i];
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(500);
2696
2697 reg = FDI_RX_IIR(pipe);
2698 temp = I915_READ(reg);
2699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701 if (temp & FDI_RX_SYMBOL_LOCK) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 2 fail!\n");
2709
2710 DRM_DEBUG_KMS("FDI train done.\n");
2711 }
2712
2713 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2714 {
2715 struct drm_device *dev = crtc->dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718 int pipe = intel_crtc->pipe;
2719 u32 reg, temp;
2720
2721 /* Write the TU size bits so error detection works */
2722 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2724
2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~((0x7 << 19) | (0x7 << 16));
2729 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2730 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
2734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
2737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
2741 udelay(200);
2742
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749 POSTING_READ(reg);
2750 udelay(100);
2751 }
2752 }
2753
2754 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755 {
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763 POSTING_READ(SOUTH_CHICKEN1);
2764 }
2765 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766 {
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* disable CPU FDI tx and PCH FDI rx */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777 POSTING_READ(reg);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(0x7 << 16);
2782 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785 POSTING_READ(reg);
2786 udelay(100);
2787
2788 /* Ironlake workaround, disable clock pointer after downing FDI */
2789 if (HAS_PCH_IBX(dev)) {
2790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2791 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792 I915_READ(FDI_RX_CHICKEN(pipe) &
2793 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2794 } else if (HAS_PCH_CPT(dev)) {
2795 cpt_phase_pointer_disable(dev, pipe);
2796 }
2797
2798 /* still set train pattern 1 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE;
2802 temp |= FDI_LINK_TRAIN_PATTERN_1;
2803 I915_WRITE(reg, temp);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 if (HAS_PCH_CPT(dev)) {
2808 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810 } else {
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 }
2814 /* BPC in FDI rx is consistent with that in PIPECONF */
2815 temp &= ~(0x07 << 16);
2816 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817 I915_WRITE(reg, temp);
2818
2819 POSTING_READ(reg);
2820 udelay(100);
2821 }
2822
2823 /*
2824 * When we disable a pipe, we need to clear any pending scanline wait events
2825 * to avoid hanging the ring, which we assume we are waiting on.
2826 */
2827 static void intel_clear_scanline_wait(struct drm_device *dev)
2828 {
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 struct intel_ring_buffer *ring;
2831 u32 tmp;
2832
2833 if (IS_GEN2(dev))
2834 /* Can't break the hang on i8xx */
2835 return;
2836
2837 ring = LP_RING(dev_priv);
2838 tmp = I915_READ_CTL(ring);
2839 if (tmp & RING_WAIT)
2840 I915_WRITE_CTL(ring, tmp);
2841 }
2842
2843 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844 {
2845 struct drm_i915_gem_object *obj;
2846 struct drm_i915_private *dev_priv;
2847
2848 if (crtc->fb == NULL)
2849 return;
2850
2851 obj = to_intel_framebuffer(crtc->fb)->obj;
2852 dev_priv = crtc->dev->dev_private;
2853 wait_event(dev_priv->pending_flip_queue,
2854 atomic_read(&obj->pending_flip) == 0);
2855 }
2856
2857 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858 {
2859 struct drm_device *dev = crtc->dev;
2860 struct drm_mode_config *mode_config = &dev->mode_config;
2861 struct intel_encoder *encoder;
2862
2863 /*
2864 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865 * must be driven by its own crtc; no sharing is possible.
2866 */
2867 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868 if (encoder->base.crtc != crtc)
2869 continue;
2870
2871 switch (encoder->type) {
2872 case INTEL_OUTPUT_EDP:
2873 if (!intel_encoder_is_pch_edp(&encoder->base))
2874 return false;
2875 continue;
2876 }
2877 }
2878
2879 return true;
2880 }
2881
2882 /*
2883 * Enable PCH resources required for PCH ports:
2884 * - PCH PLLs
2885 * - FDI training & RX/TX
2886 * - update transcoder timings
2887 * - DP transcoding bits
2888 * - transcoder
2889 */
2890 static void ironlake_pch_enable(struct drm_crtc *crtc)
2891 {
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2896 u32 reg, temp, transc_sel;
2897
2898 /* For PCH output, training FDI link */
2899 dev_priv->display.fdi_link_train(crtc);
2900
2901 intel_enable_pch_pll(dev_priv, pipe);
2902
2903 if (HAS_PCH_CPT(dev)) {
2904 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2905 TRANSC_DPLLB_SEL;
2906
2907 /* Be sure PCH DPLL SEL is set */
2908 temp = I915_READ(PCH_DPLL_SEL);
2909 if (pipe == 0) {
2910 temp &= ~(TRANSA_DPLLB_SEL);
2911 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2912 } else if (pipe == 1) {
2913 temp &= ~(TRANSB_DPLLB_SEL);
2914 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2915 } else if (pipe == 2) {
2916 temp &= ~(TRANSC_DPLLB_SEL);
2917 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2918 }
2919 I915_WRITE(PCH_DPLL_SEL, temp);
2920 }
2921
2922 /* set transcoder timing, panel must allow it */
2923 assert_panel_unlocked(dev_priv, pipe);
2924 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2925 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2926 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2927
2928 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2929 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2930 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2931
2932 intel_fdi_normal_train(crtc);
2933
2934 /* For PCH DP, enable TRANS_DP_CTL */
2935 if (HAS_PCH_CPT(dev) &&
2936 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2937 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2938 reg = TRANS_DP_CTL(pipe);
2939 temp = I915_READ(reg);
2940 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2941 TRANS_DP_SYNC_MASK |
2942 TRANS_DP_BPC_MASK);
2943 temp |= (TRANS_DP_OUTPUT_ENABLE |
2944 TRANS_DP_ENH_FRAMING);
2945 temp |= bpc << 9; /* same format but at 11:9 */
2946
2947 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2948 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2949 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2950 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2951
2952 switch (intel_trans_dp_port_sel(crtc)) {
2953 case PCH_DP_B:
2954 temp |= TRANS_DP_PORT_SEL_B;
2955 break;
2956 case PCH_DP_C:
2957 temp |= TRANS_DP_PORT_SEL_C;
2958 break;
2959 case PCH_DP_D:
2960 temp |= TRANS_DP_PORT_SEL_D;
2961 break;
2962 default:
2963 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2964 temp |= TRANS_DP_PORT_SEL_B;
2965 break;
2966 }
2967
2968 I915_WRITE(reg, temp);
2969 }
2970
2971 intel_enable_transcoder(dev_priv, pipe);
2972 }
2973
2974 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2975 {
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2978 u32 temp;
2979
2980 temp = I915_READ(dslreg);
2981 udelay(500);
2982 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2983 /* Without this, mode sets may fail silently on FDI */
2984 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2985 udelay(250);
2986 I915_WRITE(tc2reg, 0);
2987 if (wait_for(I915_READ(dslreg) != temp, 5))
2988 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2989 }
2990 }
2991
2992 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2993 {
2994 struct drm_device *dev = crtc->dev;
2995 struct drm_i915_private *dev_priv = dev->dev_private;
2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2997 int pipe = intel_crtc->pipe;
2998 int plane = intel_crtc->plane;
2999 u32 temp;
3000 bool is_pch_port;
3001
3002 if (intel_crtc->active)
3003 return;
3004
3005 intel_crtc->active = true;
3006 intel_update_watermarks(dev);
3007
3008 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3009 temp = I915_READ(PCH_LVDS);
3010 if ((temp & LVDS_PORT_EN) == 0)
3011 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3012 }
3013
3014 is_pch_port = intel_crtc_driving_pch(crtc);
3015
3016 if (is_pch_port)
3017 ironlake_fdi_pll_enable(crtc);
3018 else
3019 ironlake_fdi_disable(crtc);
3020
3021 /* Enable panel fitting for LVDS */
3022 if (dev_priv->pch_pf_size &&
3023 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3024 /* Force use of hard-coded filter coefficients
3025 * as some pre-programmed values are broken,
3026 * e.g. x201.
3027 */
3028 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3029 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3030 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3031 }
3032
3033 /*
3034 * On ILK+ LUT must be loaded before the pipe is running but with
3035 * clocks enabled
3036 */
3037 intel_crtc_load_lut(crtc);
3038
3039 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3040 intel_enable_plane(dev_priv, plane, pipe);
3041
3042 if (is_pch_port)
3043 ironlake_pch_enable(crtc);
3044
3045 mutex_lock(&dev->struct_mutex);
3046 intel_update_fbc(dev);
3047 mutex_unlock(&dev->struct_mutex);
3048
3049 intel_crtc_update_cursor(crtc, true);
3050 }
3051
3052 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3053 {
3054 struct drm_device *dev = crtc->dev;
3055 struct drm_i915_private *dev_priv = dev->dev_private;
3056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057 int pipe = intel_crtc->pipe;
3058 int plane = intel_crtc->plane;
3059 u32 reg, temp;
3060
3061 if (!intel_crtc->active)
3062 return;
3063
3064 intel_crtc_wait_for_pending_flips(crtc);
3065 drm_vblank_off(dev, pipe);
3066 intel_crtc_update_cursor(crtc, false);
3067
3068 intel_disable_plane(dev_priv, plane, pipe);
3069
3070 if (dev_priv->cfb_plane == plane)
3071 intel_disable_fbc(dev);
3072
3073 intel_disable_pipe(dev_priv, pipe);
3074
3075 /* Disable PF */
3076 I915_WRITE(PF_CTL(pipe), 0);
3077 I915_WRITE(PF_WIN_SZ(pipe), 0);
3078
3079 ironlake_fdi_disable(crtc);
3080
3081 /* This is a horrible layering violation; we should be doing this in
3082 * the connector/encoder ->prepare instead, but we don't always have
3083 * enough information there about the config to know whether it will
3084 * actually be necessary or just cause undesired flicker.
3085 */
3086 intel_disable_pch_ports(dev_priv, pipe);
3087
3088 intel_disable_transcoder(dev_priv, pipe);
3089
3090 if (HAS_PCH_CPT(dev)) {
3091 /* disable TRANS_DP_CTL */
3092 reg = TRANS_DP_CTL(pipe);
3093 temp = I915_READ(reg);
3094 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3095 temp |= TRANS_DP_PORT_SEL_NONE;
3096 I915_WRITE(reg, temp);
3097
3098 /* disable DPLL_SEL */
3099 temp = I915_READ(PCH_DPLL_SEL);
3100 switch (pipe) {
3101 case 0:
3102 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3103 break;
3104 case 1:
3105 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3106 break;
3107 case 2:
3108 /* C shares PLL A or B */
3109 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3110 break;
3111 default:
3112 BUG(); /* wtf */
3113 }
3114 I915_WRITE(PCH_DPLL_SEL, temp);
3115 }
3116
3117 /* disable PCH DPLL */
3118 if (!intel_crtc->no_pll)
3119 intel_disable_pch_pll(dev_priv, pipe);
3120
3121 /* Switch from PCDclk to Rawclk */
3122 reg = FDI_RX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3125
3126 /* Disable CPU FDI TX PLL */
3127 reg = FDI_TX_CTL(pipe);
3128 temp = I915_READ(reg);
3129 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3130
3131 POSTING_READ(reg);
3132 udelay(100);
3133
3134 reg = FDI_RX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3137
3138 /* Wait for the clocks to turn off. */
3139 POSTING_READ(reg);
3140 udelay(100);
3141
3142 intel_crtc->active = false;
3143 intel_update_watermarks(dev);
3144
3145 mutex_lock(&dev->struct_mutex);
3146 intel_update_fbc(dev);
3147 intel_clear_scanline_wait(dev);
3148 mutex_unlock(&dev->struct_mutex);
3149 }
3150
3151 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3152 {
3153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154 int pipe = intel_crtc->pipe;
3155 int plane = intel_crtc->plane;
3156
3157 /* XXX: When our outputs are all unaware of DPMS modes other than off
3158 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3159 */
3160 switch (mode) {
3161 case DRM_MODE_DPMS_ON:
3162 case DRM_MODE_DPMS_STANDBY:
3163 case DRM_MODE_DPMS_SUSPEND:
3164 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3165 ironlake_crtc_enable(crtc);
3166 break;
3167
3168 case DRM_MODE_DPMS_OFF:
3169 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3170 ironlake_crtc_disable(crtc);
3171 break;
3172 }
3173 }
3174
3175 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3176 {
3177 if (!enable && intel_crtc->overlay) {
3178 struct drm_device *dev = intel_crtc->base.dev;
3179 struct drm_i915_private *dev_priv = dev->dev_private;
3180
3181 mutex_lock(&dev->struct_mutex);
3182 dev_priv->mm.interruptible = false;
3183 (void) intel_overlay_switch_off(intel_crtc->overlay);
3184 dev_priv->mm.interruptible = true;
3185 mutex_unlock(&dev->struct_mutex);
3186 }
3187
3188 /* Let userspace switch the overlay on again. In most cases userspace
3189 * has to recompute where to put it anyway.
3190 */
3191 }
3192
3193 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3194 {
3195 struct drm_device *dev = crtc->dev;
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3198 int pipe = intel_crtc->pipe;
3199 int plane = intel_crtc->plane;
3200
3201 if (intel_crtc->active)
3202 return;
3203
3204 intel_crtc->active = true;
3205 intel_update_watermarks(dev);
3206
3207 intel_enable_pll(dev_priv, pipe);
3208 intel_enable_pipe(dev_priv, pipe, false);
3209 intel_enable_plane(dev_priv, plane, pipe);
3210
3211 intel_crtc_load_lut(crtc);
3212 intel_update_fbc(dev);
3213
3214 /* Give the overlay scaler a chance to enable if it's on this pipe */
3215 intel_crtc_dpms_overlay(intel_crtc, true);
3216 intel_crtc_update_cursor(crtc, true);
3217 }
3218
3219 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3220 {
3221 struct drm_device *dev = crtc->dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224 int pipe = intel_crtc->pipe;
3225 int plane = intel_crtc->plane;
3226
3227 if (!intel_crtc->active)
3228 return;
3229
3230 /* Give the overlay scaler a chance to disable if it's on this pipe */
3231 intel_crtc_wait_for_pending_flips(crtc);
3232 drm_vblank_off(dev, pipe);
3233 intel_crtc_dpms_overlay(intel_crtc, false);
3234 intel_crtc_update_cursor(crtc, false);
3235
3236 if (dev_priv->cfb_plane == plane)
3237 intel_disable_fbc(dev);
3238
3239 intel_disable_plane(dev_priv, plane, pipe);
3240 intel_disable_pipe(dev_priv, pipe);
3241 intel_disable_pll(dev_priv, pipe);
3242
3243 intel_crtc->active = false;
3244 intel_update_fbc(dev);
3245 intel_update_watermarks(dev);
3246 intel_clear_scanline_wait(dev);
3247 }
3248
3249 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3250 {
3251 /* XXX: When our outputs are all unaware of DPMS modes other than off
3252 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3253 */
3254 switch (mode) {
3255 case DRM_MODE_DPMS_ON:
3256 case DRM_MODE_DPMS_STANDBY:
3257 case DRM_MODE_DPMS_SUSPEND:
3258 i9xx_crtc_enable(crtc);
3259 break;
3260 case DRM_MODE_DPMS_OFF:
3261 i9xx_crtc_disable(crtc);
3262 break;
3263 }
3264 }
3265
3266 /**
3267 * Sets the power management mode of the pipe and plane.
3268 */
3269 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3270 {
3271 struct drm_device *dev = crtc->dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273 struct drm_i915_master_private *master_priv;
3274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275 int pipe = intel_crtc->pipe;
3276 bool enabled;
3277
3278 if (intel_crtc->dpms_mode == mode)
3279 return;
3280
3281 intel_crtc->dpms_mode = mode;
3282
3283 dev_priv->display.dpms(crtc, mode);
3284
3285 if (!dev->primary->master)
3286 return;
3287
3288 master_priv = dev->primary->master->driver_priv;
3289 if (!master_priv->sarea_priv)
3290 return;
3291
3292 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3293
3294 switch (pipe) {
3295 case 0:
3296 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3297 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3298 break;
3299 case 1:
3300 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3301 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3302 break;
3303 default:
3304 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3305 break;
3306 }
3307 }
3308
3309 static void intel_crtc_disable(struct drm_crtc *crtc)
3310 {
3311 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3312 struct drm_device *dev = crtc->dev;
3313
3314 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3315
3316 if (crtc->fb) {
3317 mutex_lock(&dev->struct_mutex);
3318 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3319 mutex_unlock(&dev->struct_mutex);
3320 }
3321 }
3322
3323 /* Prepare for a mode set.
3324 *
3325 * Note we could be a lot smarter here. We need to figure out which outputs
3326 * will be enabled, which disabled (in short, how the config will changes)
3327 * and perform the minimum necessary steps to accomplish that, e.g. updating
3328 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3329 * panel fitting is in the proper state, etc.
3330 */
3331 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3332 {
3333 i9xx_crtc_disable(crtc);
3334 }
3335
3336 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3337 {
3338 i9xx_crtc_enable(crtc);
3339 }
3340
3341 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3342 {
3343 ironlake_crtc_disable(crtc);
3344 }
3345
3346 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3347 {
3348 ironlake_crtc_enable(crtc);
3349 }
3350
3351 void intel_encoder_prepare(struct drm_encoder *encoder)
3352 {
3353 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3354 /* lvds has its own version of prepare see intel_lvds_prepare */
3355 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3356 }
3357
3358 void intel_encoder_commit(struct drm_encoder *encoder)
3359 {
3360 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3361 struct drm_device *dev = encoder->dev;
3362 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3363 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3364
3365 /* lvds has its own version of commit see intel_lvds_commit */
3366 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3367
3368 if (HAS_PCH_CPT(dev))
3369 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3370 }
3371
3372 void intel_encoder_destroy(struct drm_encoder *encoder)
3373 {
3374 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3375
3376 drm_encoder_cleanup(encoder);
3377 kfree(intel_encoder);
3378 }
3379
3380 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3381 struct drm_display_mode *mode,
3382 struct drm_display_mode *adjusted_mode)
3383 {
3384 struct drm_device *dev = crtc->dev;
3385
3386 if (HAS_PCH_SPLIT(dev)) {
3387 /* FDI link clock is fixed at 2.7G */
3388 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3389 return false;
3390 }
3391
3392 /* XXX some encoders set the crtcinfo, others don't.
3393 * Obviously we need some form of conflict resolution here...
3394 */
3395 if (adjusted_mode->crtc_htotal == 0)
3396 drm_mode_set_crtcinfo(adjusted_mode, 0);
3397
3398 return true;
3399 }
3400
3401 static int i945_get_display_clock_speed(struct drm_device *dev)
3402 {
3403 return 400000;
3404 }
3405
3406 static int i915_get_display_clock_speed(struct drm_device *dev)
3407 {
3408 return 333000;
3409 }
3410
3411 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3412 {
3413 return 200000;
3414 }
3415
3416 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3417 {
3418 u16 gcfgc = 0;
3419
3420 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3421
3422 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3423 return 133000;
3424 else {
3425 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3426 case GC_DISPLAY_CLOCK_333_MHZ:
3427 return 333000;
3428 default:
3429 case GC_DISPLAY_CLOCK_190_200_MHZ:
3430 return 190000;
3431 }
3432 }
3433 }
3434
3435 static int i865_get_display_clock_speed(struct drm_device *dev)
3436 {
3437 return 266000;
3438 }
3439
3440 static int i855_get_display_clock_speed(struct drm_device *dev)
3441 {
3442 u16 hpllcc = 0;
3443 /* Assume that the hardware is in the high speed state. This
3444 * should be the default.
3445 */
3446 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3447 case GC_CLOCK_133_200:
3448 case GC_CLOCK_100_200:
3449 return 200000;
3450 case GC_CLOCK_166_250:
3451 return 250000;
3452 case GC_CLOCK_100_133:
3453 return 133000;
3454 }
3455
3456 /* Shouldn't happen */
3457 return 0;
3458 }
3459
3460 static int i830_get_display_clock_speed(struct drm_device *dev)
3461 {
3462 return 133000;
3463 }
3464
3465 struct fdi_m_n {
3466 u32 tu;
3467 u32 gmch_m;
3468 u32 gmch_n;
3469 u32 link_m;
3470 u32 link_n;
3471 };
3472
3473 static void
3474 fdi_reduce_ratio(u32 *num, u32 *den)
3475 {
3476 while (*num > 0xffffff || *den > 0xffffff) {
3477 *num >>= 1;
3478 *den >>= 1;
3479 }
3480 }
3481
3482 static void
3483 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3484 int link_clock, struct fdi_m_n *m_n)
3485 {
3486 m_n->tu = 64; /* default size */
3487
3488 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3489 m_n->gmch_m = bits_per_pixel * pixel_clock;
3490 m_n->gmch_n = link_clock * nlanes * 8;
3491 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3492
3493 m_n->link_m = pixel_clock;
3494 m_n->link_n = link_clock;
3495 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3496 }
3497
3498
3499 struct intel_watermark_params {
3500 unsigned long fifo_size;
3501 unsigned long max_wm;
3502 unsigned long default_wm;
3503 unsigned long guard_size;
3504 unsigned long cacheline_size;
3505 };
3506
3507 /* Pineview has different values for various configs */
3508 static const struct intel_watermark_params pineview_display_wm = {
3509 PINEVIEW_DISPLAY_FIFO,
3510 PINEVIEW_MAX_WM,
3511 PINEVIEW_DFT_WM,
3512 PINEVIEW_GUARD_WM,
3513 PINEVIEW_FIFO_LINE_SIZE
3514 };
3515 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3516 PINEVIEW_DISPLAY_FIFO,
3517 PINEVIEW_MAX_WM,
3518 PINEVIEW_DFT_HPLLOFF_WM,
3519 PINEVIEW_GUARD_WM,
3520 PINEVIEW_FIFO_LINE_SIZE
3521 };
3522 static const struct intel_watermark_params pineview_cursor_wm = {
3523 PINEVIEW_CURSOR_FIFO,
3524 PINEVIEW_CURSOR_MAX_WM,
3525 PINEVIEW_CURSOR_DFT_WM,
3526 PINEVIEW_CURSOR_GUARD_WM,
3527 PINEVIEW_FIFO_LINE_SIZE,
3528 };
3529 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3530 PINEVIEW_CURSOR_FIFO,
3531 PINEVIEW_CURSOR_MAX_WM,
3532 PINEVIEW_CURSOR_DFT_WM,
3533 PINEVIEW_CURSOR_GUARD_WM,
3534 PINEVIEW_FIFO_LINE_SIZE
3535 };
3536 static const struct intel_watermark_params g4x_wm_info = {
3537 G4X_FIFO_SIZE,
3538 G4X_MAX_WM,
3539 G4X_MAX_WM,
3540 2,
3541 G4X_FIFO_LINE_SIZE,
3542 };
3543 static const struct intel_watermark_params g4x_cursor_wm_info = {
3544 I965_CURSOR_FIFO,
3545 I965_CURSOR_MAX_WM,
3546 I965_CURSOR_DFT_WM,
3547 2,
3548 G4X_FIFO_LINE_SIZE,
3549 };
3550 static const struct intel_watermark_params i965_cursor_wm_info = {
3551 I965_CURSOR_FIFO,
3552 I965_CURSOR_MAX_WM,
3553 I965_CURSOR_DFT_WM,
3554 2,
3555 I915_FIFO_LINE_SIZE,
3556 };
3557 static const struct intel_watermark_params i945_wm_info = {
3558 I945_FIFO_SIZE,
3559 I915_MAX_WM,
3560 1,
3561 2,
3562 I915_FIFO_LINE_SIZE
3563 };
3564 static const struct intel_watermark_params i915_wm_info = {
3565 I915_FIFO_SIZE,
3566 I915_MAX_WM,
3567 1,
3568 2,
3569 I915_FIFO_LINE_SIZE
3570 };
3571 static const struct intel_watermark_params i855_wm_info = {
3572 I855GM_FIFO_SIZE,
3573 I915_MAX_WM,
3574 1,
3575 2,
3576 I830_FIFO_LINE_SIZE
3577 };
3578 static const struct intel_watermark_params i830_wm_info = {
3579 I830_FIFO_SIZE,
3580 I915_MAX_WM,
3581 1,
3582 2,
3583 I830_FIFO_LINE_SIZE
3584 };
3585
3586 static const struct intel_watermark_params ironlake_display_wm_info = {
3587 ILK_DISPLAY_FIFO,
3588 ILK_DISPLAY_MAXWM,
3589 ILK_DISPLAY_DFTWM,
3590 2,
3591 ILK_FIFO_LINE_SIZE
3592 };
3593 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3594 ILK_CURSOR_FIFO,
3595 ILK_CURSOR_MAXWM,
3596 ILK_CURSOR_DFTWM,
3597 2,
3598 ILK_FIFO_LINE_SIZE
3599 };
3600 static const struct intel_watermark_params ironlake_display_srwm_info = {
3601 ILK_DISPLAY_SR_FIFO,
3602 ILK_DISPLAY_MAX_SRWM,
3603 ILK_DISPLAY_DFT_SRWM,
3604 2,
3605 ILK_FIFO_LINE_SIZE
3606 };
3607 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3608 ILK_CURSOR_SR_FIFO,
3609 ILK_CURSOR_MAX_SRWM,
3610 ILK_CURSOR_DFT_SRWM,
3611 2,
3612 ILK_FIFO_LINE_SIZE
3613 };
3614
3615 static const struct intel_watermark_params sandybridge_display_wm_info = {
3616 SNB_DISPLAY_FIFO,
3617 SNB_DISPLAY_MAXWM,
3618 SNB_DISPLAY_DFTWM,
3619 2,
3620 SNB_FIFO_LINE_SIZE
3621 };
3622 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3623 SNB_CURSOR_FIFO,
3624 SNB_CURSOR_MAXWM,
3625 SNB_CURSOR_DFTWM,
3626 2,
3627 SNB_FIFO_LINE_SIZE
3628 };
3629 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3630 SNB_DISPLAY_SR_FIFO,
3631 SNB_DISPLAY_MAX_SRWM,
3632 SNB_DISPLAY_DFT_SRWM,
3633 2,
3634 SNB_FIFO_LINE_SIZE
3635 };
3636 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3637 SNB_CURSOR_SR_FIFO,
3638 SNB_CURSOR_MAX_SRWM,
3639 SNB_CURSOR_DFT_SRWM,
3640 2,
3641 SNB_FIFO_LINE_SIZE
3642 };
3643
3644
3645 /**
3646 * intel_calculate_wm - calculate watermark level
3647 * @clock_in_khz: pixel clock
3648 * @wm: chip FIFO params
3649 * @pixel_size: display pixel size
3650 * @latency_ns: memory latency for the platform
3651 *
3652 * Calculate the watermark level (the level at which the display plane will
3653 * start fetching from memory again). Each chip has a different display
3654 * FIFO size and allocation, so the caller needs to figure that out and pass
3655 * in the correct intel_watermark_params structure.
3656 *
3657 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3658 * on the pixel size. When it reaches the watermark level, it'll start
3659 * fetching FIFO line sized based chunks from memory until the FIFO fills
3660 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3661 * will occur, and a display engine hang could result.
3662 */
3663 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3664 const struct intel_watermark_params *wm,
3665 int fifo_size,
3666 int pixel_size,
3667 unsigned long latency_ns)
3668 {
3669 long entries_required, wm_size;
3670
3671 /*
3672 * Note: we need to make sure we don't overflow for various clock &
3673 * latency values.
3674 * clocks go from a few thousand to several hundred thousand.
3675 * latency is usually a few thousand
3676 */
3677 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3678 1000;
3679 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3680
3681 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3682
3683 wm_size = fifo_size - (entries_required + wm->guard_size);
3684
3685 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3686
3687 /* Don't promote wm_size to unsigned... */
3688 if (wm_size > (long)wm->max_wm)
3689 wm_size = wm->max_wm;
3690 if (wm_size <= 0)
3691 wm_size = wm->default_wm;
3692 return wm_size;
3693 }
3694
3695 struct cxsr_latency {
3696 int is_desktop;
3697 int is_ddr3;
3698 unsigned long fsb_freq;
3699 unsigned long mem_freq;
3700 unsigned long display_sr;
3701 unsigned long display_hpll_disable;
3702 unsigned long cursor_sr;
3703 unsigned long cursor_hpll_disable;
3704 };
3705
3706 static const struct cxsr_latency cxsr_latency_table[] = {
3707 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3708 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3709 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3710 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3711 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3712
3713 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3714 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3715 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3716 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3717 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3718
3719 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3720 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3721 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3722 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3723 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3724
3725 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3726 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3727 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3728 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3729 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3730
3731 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3732 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3733 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3734 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3735 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3736
3737 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3738 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3739 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3740 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3741 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3742 };
3743
3744 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3745 int is_ddr3,
3746 int fsb,
3747 int mem)
3748 {
3749 const struct cxsr_latency *latency;
3750 int i;
3751
3752 if (fsb == 0 || mem == 0)
3753 return NULL;
3754
3755 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3756 latency = &cxsr_latency_table[i];
3757 if (is_desktop == latency->is_desktop &&
3758 is_ddr3 == latency->is_ddr3 &&
3759 fsb == latency->fsb_freq && mem == latency->mem_freq)
3760 return latency;
3761 }
3762
3763 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3764
3765 return NULL;
3766 }
3767
3768 static void pineview_disable_cxsr(struct drm_device *dev)
3769 {
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771
3772 /* deactivate cxsr */
3773 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3774 }
3775
3776 /*
3777 * Latency for FIFO fetches is dependent on several factors:
3778 * - memory configuration (speed, channels)
3779 * - chipset
3780 * - current MCH state
3781 * It can be fairly high in some situations, so here we assume a fairly
3782 * pessimal value. It's a tradeoff between extra memory fetches (if we
3783 * set this value too high, the FIFO will fetch frequently to stay full)
3784 * and power consumption (set it too low to save power and we might see
3785 * FIFO underruns and display "flicker").
3786 *
3787 * A value of 5us seems to be a good balance; safe for very low end
3788 * platforms but not overly aggressive on lower latency configs.
3789 */
3790 static const int latency_ns = 5000;
3791
3792 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3793 {
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 uint32_t dsparb = I915_READ(DSPARB);
3796 int size;
3797
3798 size = dsparb & 0x7f;
3799 if (plane)
3800 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3801
3802 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3803 plane ? "B" : "A", size);
3804
3805 return size;
3806 }
3807
3808 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3809 {
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 uint32_t dsparb = I915_READ(DSPARB);
3812 int size;
3813
3814 size = dsparb & 0x1ff;
3815 if (plane)
3816 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3817 size >>= 1; /* Convert to cachelines */
3818
3819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3820 plane ? "B" : "A", size);
3821
3822 return size;
3823 }
3824
3825 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3826 {
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 uint32_t dsparb = I915_READ(DSPARB);
3829 int size;
3830
3831 size = dsparb & 0x7f;
3832 size >>= 2; /* Convert to cachelines */
3833
3834 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3835 plane ? "B" : "A",
3836 size);
3837
3838 return size;
3839 }
3840
3841 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3842 {
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 uint32_t dsparb = I915_READ(DSPARB);
3845 int size;
3846
3847 size = dsparb & 0x7f;
3848 size >>= 1; /* Convert to cachelines */
3849
3850 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3851 plane ? "B" : "A", size);
3852
3853 return size;
3854 }
3855
3856 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3857 {
3858 struct drm_crtc *crtc, *enabled = NULL;
3859
3860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3861 if (crtc->enabled && crtc->fb) {
3862 if (enabled)
3863 return NULL;
3864 enabled = crtc;
3865 }
3866 }
3867
3868 return enabled;
3869 }
3870
3871 static void pineview_update_wm(struct drm_device *dev)
3872 {
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct drm_crtc *crtc;
3875 const struct cxsr_latency *latency;
3876 u32 reg;
3877 unsigned long wm;
3878
3879 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3880 dev_priv->fsb_freq, dev_priv->mem_freq);
3881 if (!latency) {
3882 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3883 pineview_disable_cxsr(dev);
3884 return;
3885 }
3886
3887 crtc = single_enabled_crtc(dev);
3888 if (crtc) {
3889 int clock = crtc->mode.clock;
3890 int pixel_size = crtc->fb->bits_per_pixel / 8;
3891
3892 /* Display SR */
3893 wm = intel_calculate_wm(clock, &pineview_display_wm,
3894 pineview_display_wm.fifo_size,
3895 pixel_size, latency->display_sr);
3896 reg = I915_READ(DSPFW1);
3897 reg &= ~DSPFW_SR_MASK;
3898 reg |= wm << DSPFW_SR_SHIFT;
3899 I915_WRITE(DSPFW1, reg);
3900 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3901
3902 /* cursor SR */
3903 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3904 pineview_display_wm.fifo_size,
3905 pixel_size, latency->cursor_sr);
3906 reg = I915_READ(DSPFW3);
3907 reg &= ~DSPFW_CURSOR_SR_MASK;
3908 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3909 I915_WRITE(DSPFW3, reg);
3910
3911 /* Display HPLL off SR */
3912 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3913 pineview_display_hplloff_wm.fifo_size,
3914 pixel_size, latency->display_hpll_disable);
3915 reg = I915_READ(DSPFW3);
3916 reg &= ~DSPFW_HPLL_SR_MASK;
3917 reg |= wm & DSPFW_HPLL_SR_MASK;
3918 I915_WRITE(DSPFW3, reg);
3919
3920 /* cursor HPLL off SR */
3921 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3922 pineview_display_hplloff_wm.fifo_size,
3923 pixel_size, latency->cursor_hpll_disable);
3924 reg = I915_READ(DSPFW3);
3925 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3926 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3927 I915_WRITE(DSPFW3, reg);
3928 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3929
3930 /* activate cxsr */
3931 I915_WRITE(DSPFW3,
3932 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3933 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3934 } else {
3935 pineview_disable_cxsr(dev);
3936 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3937 }
3938 }
3939
3940 static bool g4x_compute_wm0(struct drm_device *dev,
3941 int plane,
3942 const struct intel_watermark_params *display,
3943 int display_latency_ns,
3944 const struct intel_watermark_params *cursor,
3945 int cursor_latency_ns,
3946 int *plane_wm,
3947 int *cursor_wm)
3948 {
3949 struct drm_crtc *crtc;
3950 int htotal, hdisplay, clock, pixel_size;
3951 int line_time_us, line_count;
3952 int entries, tlb_miss;
3953
3954 crtc = intel_get_crtc_for_plane(dev, plane);
3955 if (crtc->fb == NULL || !crtc->enabled) {
3956 *cursor_wm = cursor->guard_size;
3957 *plane_wm = display->guard_size;
3958 return false;
3959 }
3960
3961 htotal = crtc->mode.htotal;
3962 hdisplay = crtc->mode.hdisplay;
3963 clock = crtc->mode.clock;
3964 pixel_size = crtc->fb->bits_per_pixel / 8;
3965
3966 /* Use the small buffer method to calculate plane watermark */
3967 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3968 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3969 if (tlb_miss > 0)
3970 entries += tlb_miss;
3971 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3972 *plane_wm = entries + display->guard_size;
3973 if (*plane_wm > (int)display->max_wm)
3974 *plane_wm = display->max_wm;
3975
3976 /* Use the large buffer method to calculate cursor watermark */
3977 line_time_us = ((htotal * 1000) / clock);
3978 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3979 entries = line_count * 64 * pixel_size;
3980 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3981 if (tlb_miss > 0)
3982 entries += tlb_miss;
3983 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3984 *cursor_wm = entries + cursor->guard_size;
3985 if (*cursor_wm > (int)cursor->max_wm)
3986 *cursor_wm = (int)cursor->max_wm;
3987
3988 return true;
3989 }
3990
3991 /*
3992 * Check the wm result.
3993 *
3994 * If any calculated watermark values is larger than the maximum value that
3995 * can be programmed into the associated watermark register, that watermark
3996 * must be disabled.
3997 */
3998 static bool g4x_check_srwm(struct drm_device *dev,
3999 int display_wm, int cursor_wm,
4000 const struct intel_watermark_params *display,
4001 const struct intel_watermark_params *cursor)
4002 {
4003 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4004 display_wm, cursor_wm);
4005
4006 if (display_wm > display->max_wm) {
4007 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4008 display_wm, display->max_wm);
4009 return false;
4010 }
4011
4012 if (cursor_wm > cursor->max_wm) {
4013 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4014 cursor_wm, cursor->max_wm);
4015 return false;
4016 }
4017
4018 if (!(display_wm || cursor_wm)) {
4019 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4020 return false;
4021 }
4022
4023 return true;
4024 }
4025
4026 static bool g4x_compute_srwm(struct drm_device *dev,
4027 int plane,
4028 int latency_ns,
4029 const struct intel_watermark_params *display,
4030 const struct intel_watermark_params *cursor,
4031 int *display_wm, int *cursor_wm)
4032 {
4033 struct drm_crtc *crtc;
4034 int hdisplay, htotal, pixel_size, clock;
4035 unsigned long line_time_us;
4036 int line_count, line_size;
4037 int small, large;
4038 int entries;
4039
4040 if (!latency_ns) {
4041 *display_wm = *cursor_wm = 0;
4042 return false;
4043 }
4044
4045 crtc = intel_get_crtc_for_plane(dev, plane);
4046 hdisplay = crtc->mode.hdisplay;
4047 htotal = crtc->mode.htotal;
4048 clock = crtc->mode.clock;
4049 pixel_size = crtc->fb->bits_per_pixel / 8;
4050
4051 line_time_us = (htotal * 1000) / clock;
4052 line_count = (latency_ns / line_time_us + 1000) / 1000;
4053 line_size = hdisplay * pixel_size;
4054
4055 /* Use the minimum of the small and large buffer method for primary */
4056 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4057 large = line_count * line_size;
4058
4059 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4060 *display_wm = entries + display->guard_size;
4061
4062 /* calculate the self-refresh watermark for display cursor */
4063 entries = line_count * pixel_size * 64;
4064 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4065 *cursor_wm = entries + cursor->guard_size;
4066
4067 return g4x_check_srwm(dev,
4068 *display_wm, *cursor_wm,
4069 display, cursor);
4070 }
4071
4072 #define single_plane_enabled(mask) is_power_of_2(mask)
4073
4074 static void g4x_update_wm(struct drm_device *dev)
4075 {
4076 static const int sr_latency_ns = 12000;
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4079 int plane_sr, cursor_sr;
4080 unsigned int enabled = 0;
4081
4082 if (g4x_compute_wm0(dev, 0,
4083 &g4x_wm_info, latency_ns,
4084 &g4x_cursor_wm_info, latency_ns,
4085 &planea_wm, &cursora_wm))
4086 enabled |= 1;
4087
4088 if (g4x_compute_wm0(dev, 1,
4089 &g4x_wm_info, latency_ns,
4090 &g4x_cursor_wm_info, latency_ns,
4091 &planeb_wm, &cursorb_wm))
4092 enabled |= 2;
4093
4094 plane_sr = cursor_sr = 0;
4095 if (single_plane_enabled(enabled) &&
4096 g4x_compute_srwm(dev, ffs(enabled) - 1,
4097 sr_latency_ns,
4098 &g4x_wm_info,
4099 &g4x_cursor_wm_info,
4100 &plane_sr, &cursor_sr))
4101 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4102 else
4103 I915_WRITE(FW_BLC_SELF,
4104 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4105
4106 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4107 planea_wm, cursora_wm,
4108 planeb_wm, cursorb_wm,
4109 plane_sr, cursor_sr);
4110
4111 I915_WRITE(DSPFW1,
4112 (plane_sr << DSPFW_SR_SHIFT) |
4113 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4114 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4115 planea_wm);
4116 I915_WRITE(DSPFW2,
4117 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4118 (cursora_wm << DSPFW_CURSORA_SHIFT));
4119 /* HPLL off in SR has some issues on G4x... disable it */
4120 I915_WRITE(DSPFW3,
4121 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4122 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4123 }
4124
4125 static void i965_update_wm(struct drm_device *dev)
4126 {
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct drm_crtc *crtc;
4129 int srwm = 1;
4130 int cursor_sr = 16;
4131
4132 /* Calc sr entries for one plane configs */
4133 crtc = single_enabled_crtc(dev);
4134 if (crtc) {
4135 /* self-refresh has much higher latency */
4136 static const int sr_latency_ns = 12000;
4137 int clock = crtc->mode.clock;
4138 int htotal = crtc->mode.htotal;
4139 int hdisplay = crtc->mode.hdisplay;
4140 int pixel_size = crtc->fb->bits_per_pixel / 8;
4141 unsigned long line_time_us;
4142 int entries;
4143
4144 line_time_us = ((htotal * 1000) / clock);
4145
4146 /* Use ns/us then divide to preserve precision */
4147 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4148 pixel_size * hdisplay;
4149 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4150 srwm = I965_FIFO_SIZE - entries;
4151 if (srwm < 0)
4152 srwm = 1;
4153 srwm &= 0x1ff;
4154 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4155 entries, srwm);
4156
4157 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4158 pixel_size * 64;
4159 entries = DIV_ROUND_UP(entries,
4160 i965_cursor_wm_info.cacheline_size);
4161 cursor_sr = i965_cursor_wm_info.fifo_size -
4162 (entries + i965_cursor_wm_info.guard_size);
4163
4164 if (cursor_sr > i965_cursor_wm_info.max_wm)
4165 cursor_sr = i965_cursor_wm_info.max_wm;
4166
4167 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4168 "cursor %d\n", srwm, cursor_sr);
4169
4170 if (IS_CRESTLINE(dev))
4171 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4172 } else {
4173 /* Turn off self refresh if both pipes are enabled */
4174 if (IS_CRESTLINE(dev))
4175 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4176 & ~FW_BLC_SELF_EN);
4177 }
4178
4179 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4180 srwm);
4181
4182 /* 965 has limitations... */
4183 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4184 (8 << 16) | (8 << 8) | (8 << 0));
4185 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4186 /* update cursor SR watermark */
4187 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4188 }
4189
4190 static void i9xx_update_wm(struct drm_device *dev)
4191 {
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193 const struct intel_watermark_params *wm_info;
4194 uint32_t fwater_lo;
4195 uint32_t fwater_hi;
4196 int cwm, srwm = 1;
4197 int fifo_size;
4198 int planea_wm, planeb_wm;
4199 struct drm_crtc *crtc, *enabled = NULL;
4200
4201 if (IS_I945GM(dev))
4202 wm_info = &i945_wm_info;
4203 else if (!IS_GEN2(dev))
4204 wm_info = &i915_wm_info;
4205 else
4206 wm_info = &i855_wm_info;
4207
4208 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4209 crtc = intel_get_crtc_for_plane(dev, 0);
4210 if (crtc->enabled && crtc->fb) {
4211 planea_wm = intel_calculate_wm(crtc->mode.clock,
4212 wm_info, fifo_size,
4213 crtc->fb->bits_per_pixel / 8,
4214 latency_ns);
4215 enabled = crtc;
4216 } else
4217 planea_wm = fifo_size - wm_info->guard_size;
4218
4219 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4220 crtc = intel_get_crtc_for_plane(dev, 1);
4221 if (crtc->enabled && crtc->fb) {
4222 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4223 wm_info, fifo_size,
4224 crtc->fb->bits_per_pixel / 8,
4225 latency_ns);
4226 if (enabled == NULL)
4227 enabled = crtc;
4228 else
4229 enabled = NULL;
4230 } else
4231 planeb_wm = fifo_size - wm_info->guard_size;
4232
4233 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4234
4235 /*
4236 * Overlay gets an aggressive default since video jitter is bad.
4237 */
4238 cwm = 2;
4239
4240 /* Play safe and disable self-refresh before adjusting watermarks. */
4241 if (IS_I945G(dev) || IS_I945GM(dev))
4242 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4243 else if (IS_I915GM(dev))
4244 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4245
4246 /* Calc sr entries for one plane configs */
4247 if (HAS_FW_BLC(dev) && enabled) {
4248 /* self-refresh has much higher latency */
4249 static const int sr_latency_ns = 6000;
4250 int clock = enabled->mode.clock;
4251 int htotal = enabled->mode.htotal;
4252 int hdisplay = enabled->mode.hdisplay;
4253 int pixel_size = enabled->fb->bits_per_pixel / 8;
4254 unsigned long line_time_us;
4255 int entries;
4256
4257 line_time_us = (htotal * 1000) / clock;
4258
4259 /* Use ns/us then divide to preserve precision */
4260 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4261 pixel_size * hdisplay;
4262 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4263 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4264 srwm = wm_info->fifo_size - entries;
4265 if (srwm < 0)
4266 srwm = 1;
4267
4268 if (IS_I945G(dev) || IS_I945GM(dev))
4269 I915_WRITE(FW_BLC_SELF,
4270 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4271 else if (IS_I915GM(dev))
4272 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4273 }
4274
4275 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4276 planea_wm, planeb_wm, cwm, srwm);
4277
4278 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4279 fwater_hi = (cwm & 0x1f);
4280
4281 /* Set request length to 8 cachelines per fetch */
4282 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4283 fwater_hi = fwater_hi | (1 << 8);
4284
4285 I915_WRITE(FW_BLC, fwater_lo);
4286 I915_WRITE(FW_BLC2, fwater_hi);
4287
4288 if (HAS_FW_BLC(dev)) {
4289 if (enabled) {
4290 if (IS_I945G(dev) || IS_I945GM(dev))
4291 I915_WRITE(FW_BLC_SELF,
4292 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4293 else if (IS_I915GM(dev))
4294 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4295 DRM_DEBUG_KMS("memory self refresh enabled\n");
4296 } else
4297 DRM_DEBUG_KMS("memory self refresh disabled\n");
4298 }
4299 }
4300
4301 static void i830_update_wm(struct drm_device *dev)
4302 {
4303 struct drm_i915_private *dev_priv = dev->dev_private;
4304 struct drm_crtc *crtc;
4305 uint32_t fwater_lo;
4306 int planea_wm;
4307
4308 crtc = single_enabled_crtc(dev);
4309 if (crtc == NULL)
4310 return;
4311
4312 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4313 dev_priv->display.get_fifo_size(dev, 0),
4314 crtc->fb->bits_per_pixel / 8,
4315 latency_ns);
4316 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4317 fwater_lo |= (3<<8) | planea_wm;
4318
4319 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4320
4321 I915_WRITE(FW_BLC, fwater_lo);
4322 }
4323
4324 #define ILK_LP0_PLANE_LATENCY 700
4325 #define ILK_LP0_CURSOR_LATENCY 1300
4326
4327 /*
4328 * Check the wm result.
4329 *
4330 * If any calculated watermark values is larger than the maximum value that
4331 * can be programmed into the associated watermark register, that watermark
4332 * must be disabled.
4333 */
4334 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4335 int fbc_wm, int display_wm, int cursor_wm,
4336 const struct intel_watermark_params *display,
4337 const struct intel_watermark_params *cursor)
4338 {
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340
4341 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4342 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4343
4344 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4345 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4346 fbc_wm, SNB_FBC_MAX_SRWM, level);
4347
4348 /* fbc has it's own way to disable FBC WM */
4349 I915_WRITE(DISP_ARB_CTL,
4350 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4351 return false;
4352 }
4353
4354 if (display_wm > display->max_wm) {
4355 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4356 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4357 return false;
4358 }
4359
4360 if (cursor_wm > cursor->max_wm) {
4361 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4362 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4363 return false;
4364 }
4365
4366 if (!(fbc_wm || display_wm || cursor_wm)) {
4367 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4368 return false;
4369 }
4370
4371 return true;
4372 }
4373
4374 /*
4375 * Compute watermark values of WM[1-3],
4376 */
4377 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4378 int latency_ns,
4379 const struct intel_watermark_params *display,
4380 const struct intel_watermark_params *cursor,
4381 int *fbc_wm, int *display_wm, int *cursor_wm)
4382 {
4383 struct drm_crtc *crtc;
4384 unsigned long line_time_us;
4385 int hdisplay, htotal, pixel_size, clock;
4386 int line_count, line_size;
4387 int small, large;
4388 int entries;
4389
4390 if (!latency_ns) {
4391 *fbc_wm = *display_wm = *cursor_wm = 0;
4392 return false;
4393 }
4394
4395 crtc = intel_get_crtc_for_plane(dev, plane);
4396 hdisplay = crtc->mode.hdisplay;
4397 htotal = crtc->mode.htotal;
4398 clock = crtc->mode.clock;
4399 pixel_size = crtc->fb->bits_per_pixel / 8;
4400
4401 line_time_us = (htotal * 1000) / clock;
4402 line_count = (latency_ns / line_time_us + 1000) / 1000;
4403 line_size = hdisplay * pixel_size;
4404
4405 /* Use the minimum of the small and large buffer method for primary */
4406 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4407 large = line_count * line_size;
4408
4409 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4410 *display_wm = entries + display->guard_size;
4411
4412 /*
4413 * Spec says:
4414 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4415 */
4416 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4417
4418 /* calculate the self-refresh watermark for display cursor */
4419 entries = line_count * pixel_size * 64;
4420 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4421 *cursor_wm = entries + cursor->guard_size;
4422
4423 return ironlake_check_srwm(dev, level,
4424 *fbc_wm, *display_wm, *cursor_wm,
4425 display, cursor);
4426 }
4427
4428 static void ironlake_update_wm(struct drm_device *dev)
4429 {
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431 int fbc_wm, plane_wm, cursor_wm;
4432 unsigned int enabled;
4433
4434 enabled = 0;
4435 if (g4x_compute_wm0(dev, 0,
4436 &ironlake_display_wm_info,
4437 ILK_LP0_PLANE_LATENCY,
4438 &ironlake_cursor_wm_info,
4439 ILK_LP0_CURSOR_LATENCY,
4440 &plane_wm, &cursor_wm)) {
4441 I915_WRITE(WM0_PIPEA_ILK,
4442 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4443 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4444 " plane %d, " "cursor: %d\n",
4445 plane_wm, cursor_wm);
4446 enabled |= 1;
4447 }
4448
4449 if (g4x_compute_wm0(dev, 1,
4450 &ironlake_display_wm_info,
4451 ILK_LP0_PLANE_LATENCY,
4452 &ironlake_cursor_wm_info,
4453 ILK_LP0_CURSOR_LATENCY,
4454 &plane_wm, &cursor_wm)) {
4455 I915_WRITE(WM0_PIPEB_ILK,
4456 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4457 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4458 " plane %d, cursor: %d\n",
4459 plane_wm, cursor_wm);
4460 enabled |= 2;
4461 }
4462
4463 /*
4464 * Calculate and update the self-refresh watermark only when one
4465 * display plane is used.
4466 */
4467 I915_WRITE(WM3_LP_ILK, 0);
4468 I915_WRITE(WM2_LP_ILK, 0);
4469 I915_WRITE(WM1_LP_ILK, 0);
4470
4471 if (!single_plane_enabled(enabled))
4472 return;
4473 enabled = ffs(enabled) - 1;
4474
4475 /* WM1 */
4476 if (!ironlake_compute_srwm(dev, 1, enabled,
4477 ILK_READ_WM1_LATENCY() * 500,
4478 &ironlake_display_srwm_info,
4479 &ironlake_cursor_srwm_info,
4480 &fbc_wm, &plane_wm, &cursor_wm))
4481 return;
4482
4483 I915_WRITE(WM1_LP_ILK,
4484 WM1_LP_SR_EN |
4485 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4486 (fbc_wm << WM1_LP_FBC_SHIFT) |
4487 (plane_wm << WM1_LP_SR_SHIFT) |
4488 cursor_wm);
4489
4490 /* WM2 */
4491 if (!ironlake_compute_srwm(dev, 2, enabled,
4492 ILK_READ_WM2_LATENCY() * 500,
4493 &ironlake_display_srwm_info,
4494 &ironlake_cursor_srwm_info,
4495 &fbc_wm, &plane_wm, &cursor_wm))
4496 return;
4497
4498 I915_WRITE(WM2_LP_ILK,
4499 WM2_LP_EN |
4500 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4501 (fbc_wm << WM1_LP_FBC_SHIFT) |
4502 (plane_wm << WM1_LP_SR_SHIFT) |
4503 cursor_wm);
4504
4505 /*
4506 * WM3 is unsupported on ILK, probably because we don't have latency
4507 * data for that power state
4508 */
4509 }
4510
4511 static void sandybridge_update_wm(struct drm_device *dev)
4512 {
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4515 int fbc_wm, plane_wm, cursor_wm;
4516 unsigned int enabled;
4517
4518 enabled = 0;
4519 if (g4x_compute_wm0(dev, 0,
4520 &sandybridge_display_wm_info, latency,
4521 &sandybridge_cursor_wm_info, latency,
4522 &plane_wm, &cursor_wm)) {
4523 I915_WRITE(WM0_PIPEA_ILK,
4524 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4525 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4526 " plane %d, " "cursor: %d\n",
4527 plane_wm, cursor_wm);
4528 enabled |= 1;
4529 }
4530
4531 if (g4x_compute_wm0(dev, 1,
4532 &sandybridge_display_wm_info, latency,
4533 &sandybridge_cursor_wm_info, latency,
4534 &plane_wm, &cursor_wm)) {
4535 I915_WRITE(WM0_PIPEB_ILK,
4536 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4537 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4538 " plane %d, cursor: %d\n",
4539 plane_wm, cursor_wm);
4540 enabled |= 2;
4541 }
4542
4543 /* IVB has 3 pipes */
4544 if (IS_IVYBRIDGE(dev) &&
4545 g4x_compute_wm0(dev, 2,
4546 &sandybridge_display_wm_info, latency,
4547 &sandybridge_cursor_wm_info, latency,
4548 &plane_wm, &cursor_wm)) {
4549 I915_WRITE(WM0_PIPEC_IVB,
4550 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4551 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4552 " plane %d, cursor: %d\n",
4553 plane_wm, cursor_wm);
4554 enabled |= 3;
4555 }
4556
4557 /*
4558 * Calculate and update the self-refresh watermark only when one
4559 * display plane is used.
4560 *
4561 * SNB support 3 levels of watermark.
4562 *
4563 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4564 * and disabled in the descending order
4565 *
4566 */
4567 I915_WRITE(WM3_LP_ILK, 0);
4568 I915_WRITE(WM2_LP_ILK, 0);
4569 I915_WRITE(WM1_LP_ILK, 0);
4570
4571 if (!single_plane_enabled(enabled))
4572 return;
4573 enabled = ffs(enabled) - 1;
4574
4575 /* WM1 */
4576 if (!ironlake_compute_srwm(dev, 1, enabled,
4577 SNB_READ_WM1_LATENCY() * 500,
4578 &sandybridge_display_srwm_info,
4579 &sandybridge_cursor_srwm_info,
4580 &fbc_wm, &plane_wm, &cursor_wm))
4581 return;
4582
4583 I915_WRITE(WM1_LP_ILK,
4584 WM1_LP_SR_EN |
4585 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4586 (fbc_wm << WM1_LP_FBC_SHIFT) |
4587 (plane_wm << WM1_LP_SR_SHIFT) |
4588 cursor_wm);
4589
4590 /* WM2 */
4591 if (!ironlake_compute_srwm(dev, 2, enabled,
4592 SNB_READ_WM2_LATENCY() * 500,
4593 &sandybridge_display_srwm_info,
4594 &sandybridge_cursor_srwm_info,
4595 &fbc_wm, &plane_wm, &cursor_wm))
4596 return;
4597
4598 I915_WRITE(WM2_LP_ILK,
4599 WM2_LP_EN |
4600 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4601 (fbc_wm << WM1_LP_FBC_SHIFT) |
4602 (plane_wm << WM1_LP_SR_SHIFT) |
4603 cursor_wm);
4604
4605 /* WM3 */
4606 if (!ironlake_compute_srwm(dev, 3, enabled,
4607 SNB_READ_WM3_LATENCY() * 500,
4608 &sandybridge_display_srwm_info,
4609 &sandybridge_cursor_srwm_info,
4610 &fbc_wm, &plane_wm, &cursor_wm))
4611 return;
4612
4613 I915_WRITE(WM3_LP_ILK,
4614 WM3_LP_EN |
4615 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4616 (fbc_wm << WM1_LP_FBC_SHIFT) |
4617 (plane_wm << WM1_LP_SR_SHIFT) |
4618 cursor_wm);
4619 }
4620
4621 /**
4622 * intel_update_watermarks - update FIFO watermark values based on current modes
4623 *
4624 * Calculate watermark values for the various WM regs based on current mode
4625 * and plane configuration.
4626 *
4627 * There are several cases to deal with here:
4628 * - normal (i.e. non-self-refresh)
4629 * - self-refresh (SR) mode
4630 * - lines are large relative to FIFO size (buffer can hold up to 2)
4631 * - lines are small relative to FIFO size (buffer can hold more than 2
4632 * lines), so need to account for TLB latency
4633 *
4634 * The normal calculation is:
4635 * watermark = dotclock * bytes per pixel * latency
4636 * where latency is platform & configuration dependent (we assume pessimal
4637 * values here).
4638 *
4639 * The SR calculation is:
4640 * watermark = (trunc(latency/line time)+1) * surface width *
4641 * bytes per pixel
4642 * where
4643 * line time = htotal / dotclock
4644 * surface width = hdisplay for normal plane and 64 for cursor
4645 * and latency is assumed to be high, as above.
4646 *
4647 * The final value programmed to the register should always be rounded up,
4648 * and include an extra 2 entries to account for clock crossings.
4649 *
4650 * We don't use the sprite, so we can ignore that. And on Crestline we have
4651 * to set the non-SR watermarks to 8.
4652 */
4653 static void intel_update_watermarks(struct drm_device *dev)
4654 {
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656
4657 if (dev_priv->display.update_wm)
4658 dev_priv->display.update_wm(dev);
4659 }
4660
4661 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4662 {
4663 if (i915_panel_use_ssc >= 0)
4664 return i915_panel_use_ssc != 0;
4665 return dev_priv->lvds_use_ssc
4666 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4667 }
4668
4669 /**
4670 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4671 * @crtc: CRTC structure
4672 *
4673 * A pipe may be connected to one or more outputs. Based on the depth of the
4674 * attached framebuffer, choose a good color depth to use on the pipe.
4675 *
4676 * If possible, match the pipe depth to the fb depth. In some cases, this
4677 * isn't ideal, because the connected output supports a lesser or restricted
4678 * set of depths. Resolve that here:
4679 * LVDS typically supports only 6bpc, so clamp down in that case
4680 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4681 * Displays may support a restricted set as well, check EDID and clamp as
4682 * appropriate.
4683 *
4684 * RETURNS:
4685 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4686 * true if they don't match).
4687 */
4688 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4689 unsigned int *pipe_bpp)
4690 {
4691 struct drm_device *dev = crtc->dev;
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693 struct drm_encoder *encoder;
4694 struct drm_connector *connector;
4695 unsigned int display_bpc = UINT_MAX, bpc;
4696
4697 /* Walk the encoders & connectors on this crtc, get min bpc */
4698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4699 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4700
4701 if (encoder->crtc != crtc)
4702 continue;
4703
4704 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4705 unsigned int lvds_bpc;
4706
4707 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4708 LVDS_A3_POWER_UP)
4709 lvds_bpc = 8;
4710 else
4711 lvds_bpc = 6;
4712
4713 if (lvds_bpc < display_bpc) {
4714 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4715 display_bpc = lvds_bpc;
4716 }
4717 continue;
4718 }
4719
4720 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4721 /* Use VBT settings if we have an eDP panel */
4722 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4723
4724 if (edp_bpc < display_bpc) {
4725 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4726 display_bpc = edp_bpc;
4727 }
4728 continue;
4729 }
4730
4731 /* Not one of the known troublemakers, check the EDID */
4732 list_for_each_entry(connector, &dev->mode_config.connector_list,
4733 head) {
4734 if (connector->encoder != encoder)
4735 continue;
4736
4737 /* Don't use an invalid EDID bpc value */
4738 if (connector->display_info.bpc &&
4739 connector->display_info.bpc < display_bpc) {
4740 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4741 display_bpc = connector->display_info.bpc;
4742 }
4743 }
4744
4745 /*
4746 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4747 * through, clamp it down. (Note: >12bpc will be caught below.)
4748 */
4749 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4750 if (display_bpc > 8 && display_bpc < 12) {
4751 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4752 display_bpc = 12;
4753 } else {
4754 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4755 display_bpc = 8;
4756 }
4757 }
4758 }
4759
4760 /*
4761 * We could just drive the pipe at the highest bpc all the time and
4762 * enable dithering as needed, but that costs bandwidth. So choose
4763 * the minimum value that expresses the full color range of the fb but
4764 * also stays within the max display bpc discovered above.
4765 */
4766
4767 switch (crtc->fb->depth) {
4768 case 8:
4769 bpc = 8; /* since we go through a colormap */
4770 break;
4771 case 15:
4772 case 16:
4773 bpc = 6; /* min is 18bpp */
4774 break;
4775 case 24:
4776 bpc = 8;
4777 break;
4778 case 30:
4779 bpc = 10;
4780 break;
4781 case 48:
4782 bpc = 12;
4783 break;
4784 default:
4785 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4786 bpc = min((unsigned int)8, display_bpc);
4787 break;
4788 }
4789
4790 display_bpc = min(display_bpc, bpc);
4791
4792 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4793 bpc, display_bpc);
4794
4795 *pipe_bpp = display_bpc * 3;
4796
4797 return display_bpc != bpc;
4798 }
4799
4800 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4801 struct drm_display_mode *mode,
4802 struct drm_display_mode *adjusted_mode,
4803 int x, int y,
4804 struct drm_framebuffer *old_fb)
4805 {
4806 struct drm_device *dev = crtc->dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 int pipe = intel_crtc->pipe;
4810 int plane = intel_crtc->plane;
4811 int refclk, num_connectors = 0;
4812 intel_clock_t clock, reduced_clock;
4813 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4814 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4815 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4816 struct drm_mode_config *mode_config = &dev->mode_config;
4817 struct intel_encoder *encoder;
4818 const intel_limit_t *limit;
4819 int ret;
4820 u32 temp;
4821 u32 lvds_sync = 0;
4822
4823 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4824 if (encoder->base.crtc != crtc)
4825 continue;
4826
4827 switch (encoder->type) {
4828 case INTEL_OUTPUT_LVDS:
4829 is_lvds = true;
4830 break;
4831 case INTEL_OUTPUT_SDVO:
4832 case INTEL_OUTPUT_HDMI:
4833 is_sdvo = true;
4834 if (encoder->needs_tv_clock)
4835 is_tv = true;
4836 break;
4837 case INTEL_OUTPUT_DVO:
4838 is_dvo = true;
4839 break;
4840 case INTEL_OUTPUT_TVOUT:
4841 is_tv = true;
4842 break;
4843 case INTEL_OUTPUT_ANALOG:
4844 is_crt = true;
4845 break;
4846 case INTEL_OUTPUT_DISPLAYPORT:
4847 is_dp = true;
4848 break;
4849 }
4850
4851 num_connectors++;
4852 }
4853
4854 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4855 refclk = dev_priv->lvds_ssc_freq * 1000;
4856 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4857 refclk / 1000);
4858 } else if (!IS_GEN2(dev)) {
4859 refclk = 96000;
4860 } else {
4861 refclk = 48000;
4862 }
4863
4864 /*
4865 * Returns a set of divisors for the desired target clock with the given
4866 * refclk, or FALSE. The returned values represent the clock equation:
4867 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4868 */
4869 limit = intel_limit(crtc, refclk);
4870 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4871 if (!ok) {
4872 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4873 return -EINVAL;
4874 }
4875
4876 /* Ensure that the cursor is valid for the new mode before changing... */
4877 intel_crtc_update_cursor(crtc, true);
4878
4879 if (is_lvds && dev_priv->lvds_downclock_avail) {
4880 has_reduced_clock = limit->find_pll(limit, crtc,
4881 dev_priv->lvds_downclock,
4882 refclk,
4883 &reduced_clock);
4884 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4885 /*
4886 * If the different P is found, it means that we can't
4887 * switch the display clock by using the FP0/FP1.
4888 * In such case we will disable the LVDS downclock
4889 * feature.
4890 */
4891 DRM_DEBUG_KMS("Different P is found for "
4892 "LVDS clock/downclock\n");
4893 has_reduced_clock = 0;
4894 }
4895 }
4896 /* SDVO TV has fixed PLL values depend on its clock range,
4897 this mirrors vbios setting. */
4898 if (is_sdvo && is_tv) {
4899 if (adjusted_mode->clock >= 100000
4900 && adjusted_mode->clock < 140500) {
4901 clock.p1 = 2;
4902 clock.p2 = 10;
4903 clock.n = 3;
4904 clock.m1 = 16;
4905 clock.m2 = 8;
4906 } else if (adjusted_mode->clock >= 140500
4907 && adjusted_mode->clock <= 200000) {
4908 clock.p1 = 1;
4909 clock.p2 = 10;
4910 clock.n = 6;
4911 clock.m1 = 12;
4912 clock.m2 = 8;
4913 }
4914 }
4915
4916 if (IS_PINEVIEW(dev)) {
4917 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4918 if (has_reduced_clock)
4919 fp2 = (1 << reduced_clock.n) << 16 |
4920 reduced_clock.m1 << 8 | reduced_clock.m2;
4921 } else {
4922 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4923 if (has_reduced_clock)
4924 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4925 reduced_clock.m2;
4926 }
4927
4928 dpll = DPLL_VGA_MODE_DIS;
4929
4930 if (!IS_GEN2(dev)) {
4931 if (is_lvds)
4932 dpll |= DPLLB_MODE_LVDS;
4933 else
4934 dpll |= DPLLB_MODE_DAC_SERIAL;
4935 if (is_sdvo) {
4936 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4937 if (pixel_multiplier > 1) {
4938 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4939 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4940 }
4941 dpll |= DPLL_DVO_HIGH_SPEED;
4942 }
4943 if (is_dp)
4944 dpll |= DPLL_DVO_HIGH_SPEED;
4945
4946 /* compute bitmask from p1 value */
4947 if (IS_PINEVIEW(dev))
4948 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4949 else {
4950 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4951 if (IS_G4X(dev) && has_reduced_clock)
4952 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4953 }
4954 switch (clock.p2) {
4955 case 5:
4956 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4957 break;
4958 case 7:
4959 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4960 break;
4961 case 10:
4962 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4963 break;
4964 case 14:
4965 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4966 break;
4967 }
4968 if (INTEL_INFO(dev)->gen >= 4)
4969 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4970 } else {
4971 if (is_lvds) {
4972 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4973 } else {
4974 if (clock.p1 == 2)
4975 dpll |= PLL_P1_DIVIDE_BY_TWO;
4976 else
4977 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4978 if (clock.p2 == 4)
4979 dpll |= PLL_P2_DIVIDE_BY_4;
4980 }
4981 }
4982
4983 if (is_sdvo && is_tv)
4984 dpll |= PLL_REF_INPUT_TVCLKINBC;
4985 else if (is_tv)
4986 /* XXX: just matching BIOS for now */
4987 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4988 dpll |= 3;
4989 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4990 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4991 else
4992 dpll |= PLL_REF_INPUT_DREFCLK;
4993
4994 /* setup pipeconf */
4995 pipeconf = I915_READ(PIPECONF(pipe));
4996
4997 /* Set up the display plane register */
4998 dspcntr = DISPPLANE_GAMMA_ENABLE;
4999
5000 /* Ironlake's plane is forced to pipe, bit 24 is to
5001 enable color space conversion */
5002 if (pipe == 0)
5003 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5004 else
5005 dspcntr |= DISPPLANE_SEL_PIPE_B;
5006
5007 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5008 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5009 * core speed.
5010 *
5011 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5012 * pipe == 0 check?
5013 */
5014 if (mode->clock >
5015 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5016 pipeconf |= PIPECONF_DOUBLE_WIDE;
5017 else
5018 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5019 }
5020
5021 dpll |= DPLL_VCO_ENABLE;
5022
5023 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5024 drm_mode_debug_printmodeline(mode);
5025
5026 I915_WRITE(FP0(pipe), fp);
5027 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5028
5029 POSTING_READ(DPLL(pipe));
5030 udelay(150);
5031
5032 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5033 * This is an exception to the general rule that mode_set doesn't turn
5034 * things on.
5035 */
5036 if (is_lvds) {
5037 temp = I915_READ(LVDS);
5038 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5039 if (pipe == 1) {
5040 temp |= LVDS_PIPEB_SELECT;
5041 } else {
5042 temp &= ~LVDS_PIPEB_SELECT;
5043 }
5044 /* set the corresponsding LVDS_BORDER bit */
5045 temp |= dev_priv->lvds_border_bits;
5046 /* Set the B0-B3 data pairs corresponding to whether we're going to
5047 * set the DPLLs for dual-channel mode or not.
5048 */
5049 if (clock.p2 == 7)
5050 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5051 else
5052 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5053
5054 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5055 * appropriately here, but we need to look more thoroughly into how
5056 * panels behave in the two modes.
5057 */
5058 /* set the dithering flag on LVDS as needed */
5059 if (INTEL_INFO(dev)->gen >= 4) {
5060 if (dev_priv->lvds_dither)
5061 temp |= LVDS_ENABLE_DITHER;
5062 else
5063 temp &= ~LVDS_ENABLE_DITHER;
5064 }
5065 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5066 lvds_sync |= LVDS_HSYNC_POLARITY;
5067 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5068 lvds_sync |= LVDS_VSYNC_POLARITY;
5069 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5070 != lvds_sync) {
5071 char flags[2] = "-+";
5072 DRM_INFO("Changing LVDS panel from "
5073 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5074 flags[!(temp & LVDS_HSYNC_POLARITY)],
5075 flags[!(temp & LVDS_VSYNC_POLARITY)],
5076 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5077 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5078 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5079 temp |= lvds_sync;
5080 }
5081 I915_WRITE(LVDS, temp);
5082 }
5083
5084 if (is_dp) {
5085 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5086 }
5087
5088 I915_WRITE(DPLL(pipe), dpll);
5089
5090 /* Wait for the clocks to stabilize. */
5091 POSTING_READ(DPLL(pipe));
5092 udelay(150);
5093
5094 if (INTEL_INFO(dev)->gen >= 4) {
5095 temp = 0;
5096 if (is_sdvo) {
5097 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5098 if (temp > 1)
5099 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5100 else
5101 temp = 0;
5102 }
5103 I915_WRITE(DPLL_MD(pipe), temp);
5104 } else {
5105 /* The pixel multiplier can only be updated once the
5106 * DPLL is enabled and the clocks are stable.
5107 *
5108 * So write it again.
5109 */
5110 I915_WRITE(DPLL(pipe), dpll);
5111 }
5112
5113 intel_crtc->lowfreq_avail = false;
5114 if (is_lvds && has_reduced_clock && i915_powersave) {
5115 I915_WRITE(FP1(pipe), fp2);
5116 intel_crtc->lowfreq_avail = true;
5117 if (HAS_PIPE_CXSR(dev)) {
5118 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5119 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5120 }
5121 } else {
5122 I915_WRITE(FP1(pipe), fp);
5123 if (HAS_PIPE_CXSR(dev)) {
5124 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5125 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5126 }
5127 }
5128
5129 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5130 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5131 /* the chip adds 2 halflines automatically */
5132 adjusted_mode->crtc_vdisplay -= 1;
5133 adjusted_mode->crtc_vtotal -= 1;
5134 adjusted_mode->crtc_vblank_start -= 1;
5135 adjusted_mode->crtc_vblank_end -= 1;
5136 adjusted_mode->crtc_vsync_end -= 1;
5137 adjusted_mode->crtc_vsync_start -= 1;
5138 } else
5139 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5140
5141 I915_WRITE(HTOTAL(pipe),
5142 (adjusted_mode->crtc_hdisplay - 1) |
5143 ((adjusted_mode->crtc_htotal - 1) << 16));
5144 I915_WRITE(HBLANK(pipe),
5145 (adjusted_mode->crtc_hblank_start - 1) |
5146 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5147 I915_WRITE(HSYNC(pipe),
5148 (adjusted_mode->crtc_hsync_start - 1) |
5149 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5150
5151 I915_WRITE(VTOTAL(pipe),
5152 (adjusted_mode->crtc_vdisplay - 1) |
5153 ((adjusted_mode->crtc_vtotal - 1) << 16));
5154 I915_WRITE(VBLANK(pipe),
5155 (adjusted_mode->crtc_vblank_start - 1) |
5156 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5157 I915_WRITE(VSYNC(pipe),
5158 (adjusted_mode->crtc_vsync_start - 1) |
5159 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5160
5161 /* pipesrc and dspsize control the size that is scaled from,
5162 * which should always be the user's requested size.
5163 */
5164 I915_WRITE(DSPSIZE(plane),
5165 ((mode->vdisplay - 1) << 16) |
5166 (mode->hdisplay - 1));
5167 I915_WRITE(DSPPOS(plane), 0);
5168 I915_WRITE(PIPESRC(pipe),
5169 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5170
5171 I915_WRITE(PIPECONF(pipe), pipeconf);
5172 POSTING_READ(PIPECONF(pipe));
5173 intel_enable_pipe(dev_priv, pipe, false);
5174
5175 intel_wait_for_vblank(dev, pipe);
5176
5177 I915_WRITE(DSPCNTR(plane), dspcntr);
5178 POSTING_READ(DSPCNTR(plane));
5179 intel_enable_plane(dev_priv, plane, pipe);
5180
5181 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5182
5183 intel_update_watermarks(dev);
5184
5185 return ret;
5186 }
5187
5188 /*
5189 * Initialize reference clocks when the driver loads
5190 */
5191 void ironlake_init_pch_refclk(struct drm_device *dev)
5192 {
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194 struct drm_mode_config *mode_config = &dev->mode_config;
5195 struct intel_encoder *encoder;
5196 u32 temp;
5197 bool has_lvds = false;
5198 bool has_cpu_edp = false;
5199 bool has_pch_edp = false;
5200 bool has_panel = false;
5201 bool has_ck505 = false;
5202 bool can_ssc = false;
5203
5204 /* We need to take the global config into account */
5205 list_for_each_entry(encoder, &mode_config->encoder_list,
5206 base.head) {
5207 switch (encoder->type) {
5208 case INTEL_OUTPUT_LVDS:
5209 has_panel = true;
5210 has_lvds = true;
5211 break;
5212 case INTEL_OUTPUT_EDP:
5213 has_panel = true;
5214 if (intel_encoder_is_pch_edp(&encoder->base))
5215 has_pch_edp = true;
5216 else
5217 has_cpu_edp = true;
5218 break;
5219 }
5220 }
5221
5222 if (HAS_PCH_IBX(dev)) {
5223 has_ck505 = dev_priv->display_clock_mode;
5224 can_ssc = has_ck505;
5225 } else {
5226 has_ck505 = false;
5227 can_ssc = true;
5228 }
5229
5230 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5231 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5232 has_ck505);
5233
5234 /* Ironlake: try to setup display ref clock before DPLL
5235 * enabling. This is only under driver's control after
5236 * PCH B stepping, previous chipset stepping should be
5237 * ignoring this setting.
5238 */
5239 temp = I915_READ(PCH_DREF_CONTROL);
5240 /* Always enable nonspread source */
5241 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5242
5243 if (has_ck505)
5244 temp |= DREF_NONSPREAD_CK505_ENABLE;
5245 else
5246 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5247
5248 if (has_panel) {
5249 temp &= ~DREF_SSC_SOURCE_MASK;
5250 temp |= DREF_SSC_SOURCE_ENABLE;
5251
5252 /* SSC must be turned on before enabling the CPU output */
5253 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5254 DRM_DEBUG_KMS("Using SSC on panel\n");
5255 temp |= DREF_SSC1_ENABLE;
5256 }
5257
5258 /* Get SSC going before enabling the outputs */
5259 I915_WRITE(PCH_DREF_CONTROL, temp);
5260 POSTING_READ(PCH_DREF_CONTROL);
5261 udelay(200);
5262
5263 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5264
5265 /* Enable CPU source on CPU attached eDP */
5266 if (has_cpu_edp) {
5267 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5268 DRM_DEBUG_KMS("Using SSC on eDP\n");
5269 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5270 }
5271 else
5272 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5273 } else
5274 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5275
5276 I915_WRITE(PCH_DREF_CONTROL, temp);
5277 POSTING_READ(PCH_DREF_CONTROL);
5278 udelay(200);
5279 } else {
5280 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5281
5282 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5283
5284 /* Turn off CPU output */
5285 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5286
5287 I915_WRITE(PCH_DREF_CONTROL, temp);
5288 POSTING_READ(PCH_DREF_CONTROL);
5289 udelay(200);
5290
5291 /* Turn off the SSC source */
5292 temp &= ~DREF_SSC_SOURCE_MASK;
5293 temp |= DREF_SSC_SOURCE_DISABLE;
5294
5295 /* Turn off SSC1 */
5296 temp &= ~ DREF_SSC1_ENABLE;
5297
5298 I915_WRITE(PCH_DREF_CONTROL, temp);
5299 POSTING_READ(PCH_DREF_CONTROL);
5300 udelay(200);
5301 }
5302 }
5303
5304 static int ironlake_get_refclk(struct drm_crtc *crtc)
5305 {
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_encoder *encoder;
5309 struct drm_mode_config *mode_config = &dev->mode_config;
5310 struct intel_encoder *edp_encoder = NULL;
5311 int num_connectors = 0;
5312 bool is_lvds = false;
5313
5314 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5315 if (encoder->base.crtc != crtc)
5316 continue;
5317
5318 switch (encoder->type) {
5319 case INTEL_OUTPUT_LVDS:
5320 is_lvds = true;
5321 break;
5322 case INTEL_OUTPUT_EDP:
5323 edp_encoder = encoder;
5324 break;
5325 }
5326 num_connectors++;
5327 }
5328
5329 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5330 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5331 dev_priv->lvds_ssc_freq);
5332 return dev_priv->lvds_ssc_freq * 1000;
5333 }
5334
5335 return 120000;
5336 }
5337
5338 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5339 struct drm_display_mode *mode,
5340 struct drm_display_mode *adjusted_mode,
5341 int x, int y,
5342 struct drm_framebuffer *old_fb)
5343 {
5344 struct drm_device *dev = crtc->dev;
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347 int pipe = intel_crtc->pipe;
5348 int plane = intel_crtc->plane;
5349 int refclk, num_connectors = 0;
5350 intel_clock_t clock, reduced_clock;
5351 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5352 bool ok, has_reduced_clock = false, is_sdvo = false;
5353 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5354 struct intel_encoder *has_edp_encoder = NULL;
5355 struct drm_mode_config *mode_config = &dev->mode_config;
5356 struct intel_encoder *encoder;
5357 const intel_limit_t *limit;
5358 int ret;
5359 struct fdi_m_n m_n = {0};
5360 u32 temp;
5361 u32 lvds_sync = 0;
5362 int target_clock, pixel_multiplier, lane, link_bw, factor;
5363 unsigned int pipe_bpp;
5364 bool dither;
5365
5366 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5367 if (encoder->base.crtc != crtc)
5368 continue;
5369
5370 switch (encoder->type) {
5371 case INTEL_OUTPUT_LVDS:
5372 is_lvds = true;
5373 break;
5374 case INTEL_OUTPUT_SDVO:
5375 case INTEL_OUTPUT_HDMI:
5376 is_sdvo = true;
5377 if (encoder->needs_tv_clock)
5378 is_tv = true;
5379 break;
5380 case INTEL_OUTPUT_TVOUT:
5381 is_tv = true;
5382 break;
5383 case INTEL_OUTPUT_ANALOG:
5384 is_crt = true;
5385 break;
5386 case INTEL_OUTPUT_DISPLAYPORT:
5387 is_dp = true;
5388 break;
5389 case INTEL_OUTPUT_EDP:
5390 has_edp_encoder = encoder;
5391 break;
5392 }
5393
5394 num_connectors++;
5395 }
5396
5397 refclk = ironlake_get_refclk(crtc);
5398
5399 /*
5400 * Returns a set of divisors for the desired target clock with the given
5401 * refclk, or FALSE. The returned values represent the clock equation:
5402 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5403 */
5404 limit = intel_limit(crtc, refclk);
5405 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5406 if (!ok) {
5407 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5408 return -EINVAL;
5409 }
5410
5411 /* Ensure that the cursor is valid for the new mode before changing... */
5412 intel_crtc_update_cursor(crtc, true);
5413
5414 if (is_lvds && dev_priv->lvds_downclock_avail) {
5415 has_reduced_clock = limit->find_pll(limit, crtc,
5416 dev_priv->lvds_downclock,
5417 refclk,
5418 &reduced_clock);
5419 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5420 /*
5421 * If the different P is found, it means that we can't
5422 * switch the display clock by using the FP0/FP1.
5423 * In such case we will disable the LVDS downclock
5424 * feature.
5425 */
5426 DRM_DEBUG_KMS("Different P is found for "
5427 "LVDS clock/downclock\n");
5428 has_reduced_clock = 0;
5429 }
5430 }
5431 /* SDVO TV has fixed PLL values depend on its clock range,
5432 this mirrors vbios setting. */
5433 if (is_sdvo && is_tv) {
5434 if (adjusted_mode->clock >= 100000
5435 && adjusted_mode->clock < 140500) {
5436 clock.p1 = 2;
5437 clock.p2 = 10;
5438 clock.n = 3;
5439 clock.m1 = 16;
5440 clock.m2 = 8;
5441 } else if (adjusted_mode->clock >= 140500
5442 && adjusted_mode->clock <= 200000) {
5443 clock.p1 = 1;
5444 clock.p2 = 10;
5445 clock.n = 6;
5446 clock.m1 = 12;
5447 clock.m2 = 8;
5448 }
5449 }
5450
5451 /* FDI link */
5452 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5453 lane = 0;
5454 /* CPU eDP doesn't require FDI link, so just set DP M/N
5455 according to current link config */
5456 if (has_edp_encoder &&
5457 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5458 target_clock = mode->clock;
5459 intel_edp_link_config(has_edp_encoder,
5460 &lane, &link_bw);
5461 } else {
5462 /* [e]DP over FDI requires target mode clock
5463 instead of link clock */
5464 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5465 target_clock = mode->clock;
5466 else
5467 target_clock = adjusted_mode->clock;
5468
5469 /* FDI is a binary signal running at ~2.7GHz, encoding
5470 * each output octet as 10 bits. The actual frequency
5471 * is stored as a divider into a 100MHz clock, and the
5472 * mode pixel clock is stored in units of 1KHz.
5473 * Hence the bw of each lane in terms of the mode signal
5474 * is:
5475 */
5476 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5477 }
5478
5479 /* determine panel color depth */
5480 temp = I915_READ(PIPECONF(pipe));
5481 temp &= ~PIPE_BPC_MASK;
5482 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5483 switch (pipe_bpp) {
5484 case 18:
5485 temp |= PIPE_6BPC;
5486 break;
5487 case 24:
5488 temp |= PIPE_8BPC;
5489 break;
5490 case 30:
5491 temp |= PIPE_10BPC;
5492 break;
5493 case 36:
5494 temp |= PIPE_12BPC;
5495 break;
5496 default:
5497 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5498 pipe_bpp);
5499 temp |= PIPE_8BPC;
5500 pipe_bpp = 24;
5501 break;
5502 }
5503
5504 intel_crtc->bpp = pipe_bpp;
5505 I915_WRITE(PIPECONF(pipe), temp);
5506
5507 if (!lane) {
5508 /*
5509 * Account for spread spectrum to avoid
5510 * oversubscribing the link. Max center spread
5511 * is 2.5%; use 5% for safety's sake.
5512 */
5513 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5514 lane = bps / (link_bw * 8) + 1;
5515 }
5516
5517 intel_crtc->fdi_lanes = lane;
5518
5519 if (pixel_multiplier > 1)
5520 link_bw *= pixel_multiplier;
5521 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5522 &m_n);
5523
5524 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5525 if (has_reduced_clock)
5526 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5527 reduced_clock.m2;
5528
5529 /* Enable autotuning of the PLL clock (if permissible) */
5530 factor = 21;
5531 if (is_lvds) {
5532 if ((intel_panel_use_ssc(dev_priv) &&
5533 dev_priv->lvds_ssc_freq == 100) ||
5534 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5535 factor = 25;
5536 } else if (is_sdvo && is_tv)
5537 factor = 20;
5538
5539 if (clock.m < factor * clock.n)
5540 fp |= FP_CB_TUNE;
5541
5542 dpll = 0;
5543
5544 if (is_lvds)
5545 dpll |= DPLLB_MODE_LVDS;
5546 else
5547 dpll |= DPLLB_MODE_DAC_SERIAL;
5548 if (is_sdvo) {
5549 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5550 if (pixel_multiplier > 1) {
5551 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5552 }
5553 dpll |= DPLL_DVO_HIGH_SPEED;
5554 }
5555 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5556 dpll |= DPLL_DVO_HIGH_SPEED;
5557
5558 /* compute bitmask from p1 value */
5559 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5560 /* also FPA1 */
5561 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5562
5563 switch (clock.p2) {
5564 case 5:
5565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5566 break;
5567 case 7:
5568 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5569 break;
5570 case 10:
5571 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5572 break;
5573 case 14:
5574 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5575 break;
5576 }
5577
5578 if (is_sdvo && is_tv)
5579 dpll |= PLL_REF_INPUT_TVCLKINBC;
5580 else if (is_tv)
5581 /* XXX: just matching BIOS for now */
5582 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5583 dpll |= 3;
5584 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5585 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5586 else
5587 dpll |= PLL_REF_INPUT_DREFCLK;
5588
5589 /* setup pipeconf */
5590 pipeconf = I915_READ(PIPECONF(pipe));
5591
5592 /* Set up the display plane register */
5593 dspcntr = DISPPLANE_GAMMA_ENABLE;
5594
5595 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5596 drm_mode_debug_printmodeline(mode);
5597
5598 /* PCH eDP needs FDI, but CPU eDP does not */
5599 if (!intel_crtc->no_pll) {
5600 if (!has_edp_encoder ||
5601 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5602 I915_WRITE(PCH_FP0(pipe), fp);
5603 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5604
5605 POSTING_READ(PCH_DPLL(pipe));
5606 udelay(150);
5607 }
5608 } else {
5609 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5610 fp == I915_READ(PCH_FP0(0))) {
5611 intel_crtc->use_pll_a = true;
5612 DRM_DEBUG_KMS("using pipe a dpll\n");
5613 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5614 fp == I915_READ(PCH_FP0(1))) {
5615 intel_crtc->use_pll_a = false;
5616 DRM_DEBUG_KMS("using pipe b dpll\n");
5617 } else {
5618 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5619 return -EINVAL;
5620 }
5621 }
5622
5623 /* enable transcoder DPLL */
5624 if (HAS_PCH_CPT(dev)) {
5625 u32 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
5626 TRANSC_DPLLB_SEL;
5627 temp = I915_READ(PCH_DPLL_SEL);
5628 switch (pipe) {
5629 case 0:
5630 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5631 break;
5632 case 1:
5633 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5634 break;
5635 case 2:
5636 temp &= ~(TRANSC_DPLLB_SEL);
5637 temp |= TRANSC_DPLL_ENABLE | transc_sel;
5638 break;
5639 default:
5640 BUG();
5641 }
5642 I915_WRITE(PCH_DPLL_SEL, temp);
5643
5644 POSTING_READ(PCH_DPLL_SEL);
5645 udelay(150);
5646 }
5647
5648 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5649 * This is an exception to the general rule that mode_set doesn't turn
5650 * things on.
5651 */
5652 if (is_lvds) {
5653 temp = I915_READ(PCH_LVDS);
5654 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5655 if (HAS_PCH_CPT(dev))
5656 temp |= PORT_TRANS_SEL_CPT(pipe);
5657 else if (pipe == 1)
5658 temp |= LVDS_PIPEB_SELECT;
5659 else
5660 temp &= ~LVDS_PIPEB_SELECT;
5661
5662 /* set the corresponsding LVDS_BORDER bit */
5663 temp |= dev_priv->lvds_border_bits;
5664 /* Set the B0-B3 data pairs corresponding to whether we're going to
5665 * set the DPLLs for dual-channel mode or not.
5666 */
5667 if (clock.p2 == 7)
5668 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5669 else
5670 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5671
5672 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5673 * appropriately here, but we need to look more thoroughly into how
5674 * panels behave in the two modes.
5675 */
5676 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5677 lvds_sync |= LVDS_HSYNC_POLARITY;
5678 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5679 lvds_sync |= LVDS_VSYNC_POLARITY;
5680 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5681 != lvds_sync) {
5682 char flags[2] = "-+";
5683 DRM_INFO("Changing LVDS panel from "
5684 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5685 flags[!(temp & LVDS_HSYNC_POLARITY)],
5686 flags[!(temp & LVDS_VSYNC_POLARITY)],
5687 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5688 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5689 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5690 temp |= lvds_sync;
5691 }
5692 I915_WRITE(PCH_LVDS, temp);
5693 }
5694
5695 pipeconf &= ~PIPECONF_DITHER_EN;
5696 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5697 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5698 pipeconf |= PIPECONF_DITHER_EN;
5699 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5700 }
5701 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5702 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5703 } else {
5704 /* For non-DP output, clear any trans DP clock recovery setting.*/
5705 I915_WRITE(TRANSDATA_M1(pipe), 0);
5706 I915_WRITE(TRANSDATA_N1(pipe), 0);
5707 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5708 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5709 }
5710
5711 if (!intel_crtc->no_pll &&
5712 (!has_edp_encoder ||
5713 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5714 I915_WRITE(PCH_DPLL(pipe), dpll);
5715
5716 /* Wait for the clocks to stabilize. */
5717 POSTING_READ(PCH_DPLL(pipe));
5718 udelay(150);
5719
5720 /* The pixel multiplier can only be updated once the
5721 * DPLL is enabled and the clocks are stable.
5722 *
5723 * So write it again.
5724 */
5725 I915_WRITE(PCH_DPLL(pipe), dpll);
5726 }
5727
5728 intel_crtc->lowfreq_avail = false;
5729 if (!intel_crtc->no_pll) {
5730 if (is_lvds && has_reduced_clock && i915_powersave) {
5731 I915_WRITE(PCH_FP1(pipe), fp2);
5732 intel_crtc->lowfreq_avail = true;
5733 if (HAS_PIPE_CXSR(dev)) {
5734 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5735 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5736 }
5737 } else {
5738 I915_WRITE(PCH_FP1(pipe), fp);
5739 if (HAS_PIPE_CXSR(dev)) {
5740 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5741 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5742 }
5743 }
5744 }
5745
5746 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5747 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5748 /* the chip adds 2 halflines automatically */
5749 adjusted_mode->crtc_vdisplay -= 1;
5750 adjusted_mode->crtc_vtotal -= 1;
5751 adjusted_mode->crtc_vblank_start -= 1;
5752 adjusted_mode->crtc_vblank_end -= 1;
5753 adjusted_mode->crtc_vsync_end -= 1;
5754 adjusted_mode->crtc_vsync_start -= 1;
5755 } else
5756 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5757
5758 I915_WRITE(HTOTAL(pipe),
5759 (adjusted_mode->crtc_hdisplay - 1) |
5760 ((adjusted_mode->crtc_htotal - 1) << 16));
5761 I915_WRITE(HBLANK(pipe),
5762 (adjusted_mode->crtc_hblank_start - 1) |
5763 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5764 I915_WRITE(HSYNC(pipe),
5765 (adjusted_mode->crtc_hsync_start - 1) |
5766 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5767
5768 I915_WRITE(VTOTAL(pipe),
5769 (adjusted_mode->crtc_vdisplay - 1) |
5770 ((adjusted_mode->crtc_vtotal - 1) << 16));
5771 I915_WRITE(VBLANK(pipe),
5772 (adjusted_mode->crtc_vblank_start - 1) |
5773 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5774 I915_WRITE(VSYNC(pipe),
5775 (adjusted_mode->crtc_vsync_start - 1) |
5776 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5777
5778 /* pipesrc controls the size that is scaled from, which should
5779 * always be the user's requested size.
5780 */
5781 I915_WRITE(PIPESRC(pipe),
5782 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5783
5784 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5785 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5786 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5787 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5788
5789 if (has_edp_encoder &&
5790 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5791 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5792 }
5793
5794 I915_WRITE(PIPECONF(pipe), pipeconf);
5795 POSTING_READ(PIPECONF(pipe));
5796
5797 intel_wait_for_vblank(dev, pipe);
5798
5799 if (IS_GEN5(dev)) {
5800 /* enable address swizzle for tiling buffer */
5801 temp = I915_READ(DISP_ARB_CTL);
5802 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5803 }
5804
5805 I915_WRITE(DSPCNTR(plane), dspcntr);
5806 POSTING_READ(DSPCNTR(plane));
5807
5808 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5809
5810 intel_update_watermarks(dev);
5811
5812 return ret;
5813 }
5814
5815 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5816 struct drm_display_mode *mode,
5817 struct drm_display_mode *adjusted_mode,
5818 int x, int y,
5819 struct drm_framebuffer *old_fb)
5820 {
5821 struct drm_device *dev = crtc->dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5824 int pipe = intel_crtc->pipe;
5825 int ret;
5826
5827 drm_vblank_pre_modeset(dev, pipe);
5828
5829 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5830 x, y, old_fb);
5831
5832 drm_vblank_post_modeset(dev, pipe);
5833
5834 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5835
5836 return ret;
5837 }
5838
5839 static void g4x_write_eld(struct drm_connector *connector,
5840 struct drm_crtc *crtc)
5841 {
5842 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843 uint8_t *eld = connector->eld;
5844 uint32_t eldv;
5845 uint32_t len;
5846 uint32_t i;
5847
5848 i = I915_READ(G4X_AUD_VID_DID);
5849
5850 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5851 eldv = G4X_ELDV_DEVCL_DEVBLC;
5852 else
5853 eldv = G4X_ELDV_DEVCTG;
5854
5855 i = I915_READ(G4X_AUD_CNTL_ST);
5856 i &= ~(eldv | G4X_ELD_ADDR);
5857 len = (i >> 9) & 0x1f; /* ELD buffer size */
5858 I915_WRITE(G4X_AUD_CNTL_ST, i);
5859
5860 if (!eld[0])
5861 return;
5862
5863 len = min_t(uint8_t, eld[2], len);
5864 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5865 for (i = 0; i < len; i++)
5866 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5867
5868 i = I915_READ(G4X_AUD_CNTL_ST);
5869 i |= eldv;
5870 I915_WRITE(G4X_AUD_CNTL_ST, i);
5871 }
5872
5873 static void ironlake_write_eld(struct drm_connector *connector,
5874 struct drm_crtc *crtc)
5875 {
5876 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5877 uint8_t *eld = connector->eld;
5878 uint32_t eldv;
5879 uint32_t i;
5880 int len;
5881 int hdmiw_hdmiedid;
5882 int aud_cntl_st;
5883 int aud_cntrl_st2;
5884
5885 if (IS_IVYBRIDGE(connector->dev)) {
5886 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5887 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5888 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5889 } else {
5890 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5891 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5892 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5893 }
5894
5895 i = to_intel_crtc(crtc)->pipe;
5896 hdmiw_hdmiedid += i * 0x100;
5897 aud_cntl_st += i * 0x100;
5898
5899 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5900
5901 i = I915_READ(aud_cntl_st);
5902 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5903 if (!i) {
5904 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5905 /* operate blindly on all ports */
5906 eldv = GEN5_ELD_VALIDB;
5907 eldv |= GEN5_ELD_VALIDB << 4;
5908 eldv |= GEN5_ELD_VALIDB << 8;
5909 } else {
5910 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5911 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5912 }
5913
5914 i = I915_READ(aud_cntrl_st2);
5915 i &= ~eldv;
5916 I915_WRITE(aud_cntrl_st2, i);
5917
5918 if (!eld[0])
5919 return;
5920
5921 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5922 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5923 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5924 }
5925
5926 i = I915_READ(aud_cntl_st);
5927 i &= ~GEN5_ELD_ADDRESS;
5928 I915_WRITE(aud_cntl_st, i);
5929
5930 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5931 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5932 for (i = 0; i < len; i++)
5933 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5934
5935 i = I915_READ(aud_cntrl_st2);
5936 i |= eldv;
5937 I915_WRITE(aud_cntrl_st2, i);
5938 }
5939
5940 void intel_write_eld(struct drm_encoder *encoder,
5941 struct drm_display_mode *mode)
5942 {
5943 struct drm_crtc *crtc = encoder->crtc;
5944 struct drm_connector *connector;
5945 struct drm_device *dev = encoder->dev;
5946 struct drm_i915_private *dev_priv = dev->dev_private;
5947
5948 connector = drm_select_eld(encoder, mode);
5949 if (!connector)
5950 return;
5951
5952 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5953 connector->base.id,
5954 drm_get_connector_name(connector),
5955 connector->encoder->base.id,
5956 drm_get_encoder_name(connector->encoder));
5957
5958 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5959
5960 if (dev_priv->display.write_eld)
5961 dev_priv->display.write_eld(connector, crtc);
5962 }
5963
5964 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5965 void intel_crtc_load_lut(struct drm_crtc *crtc)
5966 {
5967 struct drm_device *dev = crtc->dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970 int palreg = PALETTE(intel_crtc->pipe);
5971 int i;
5972
5973 /* The clocks have to be on to load the palette. */
5974 if (!crtc->enabled)
5975 return;
5976
5977 /* use legacy palette for Ironlake */
5978 if (HAS_PCH_SPLIT(dev))
5979 palreg = LGC_PALETTE(intel_crtc->pipe);
5980
5981 for (i = 0; i < 256; i++) {
5982 I915_WRITE(palreg + 4 * i,
5983 (intel_crtc->lut_r[i] << 16) |
5984 (intel_crtc->lut_g[i] << 8) |
5985 intel_crtc->lut_b[i]);
5986 }
5987 }
5988
5989 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5990 {
5991 struct drm_device *dev = crtc->dev;
5992 struct drm_i915_private *dev_priv = dev->dev_private;
5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994 bool visible = base != 0;
5995 u32 cntl;
5996
5997 if (intel_crtc->cursor_visible == visible)
5998 return;
5999
6000 cntl = I915_READ(_CURACNTR);
6001 if (visible) {
6002 /* On these chipsets we can only modify the base whilst
6003 * the cursor is disabled.
6004 */
6005 I915_WRITE(_CURABASE, base);
6006
6007 cntl &= ~(CURSOR_FORMAT_MASK);
6008 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6009 cntl |= CURSOR_ENABLE |
6010 CURSOR_GAMMA_ENABLE |
6011 CURSOR_FORMAT_ARGB;
6012 } else
6013 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6014 I915_WRITE(_CURACNTR, cntl);
6015
6016 intel_crtc->cursor_visible = visible;
6017 }
6018
6019 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6020 {
6021 struct drm_device *dev = crtc->dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6024 int pipe = intel_crtc->pipe;
6025 bool visible = base != 0;
6026
6027 if (intel_crtc->cursor_visible != visible) {
6028 uint32_t cntl = I915_READ(CURCNTR(pipe));
6029 if (base) {
6030 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6031 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6032 cntl |= pipe << 28; /* Connect to correct pipe */
6033 } else {
6034 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6035 cntl |= CURSOR_MODE_DISABLE;
6036 }
6037 I915_WRITE(CURCNTR(pipe), cntl);
6038
6039 intel_crtc->cursor_visible = visible;
6040 }
6041 /* and commit changes on next vblank */
6042 I915_WRITE(CURBASE(pipe), base);
6043 }
6044
6045 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6046 {
6047 struct drm_device *dev = crtc->dev;
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6050 int pipe = intel_crtc->pipe;
6051 bool visible = base != 0;
6052
6053 if (intel_crtc->cursor_visible != visible) {
6054 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6055 if (base) {
6056 cntl &= ~CURSOR_MODE;
6057 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6058 } else {
6059 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6060 cntl |= CURSOR_MODE_DISABLE;
6061 }
6062 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6063
6064 intel_crtc->cursor_visible = visible;
6065 }
6066 /* and commit changes on next vblank */
6067 I915_WRITE(CURBASE_IVB(pipe), base);
6068 }
6069
6070 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6071 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6072 bool on)
6073 {
6074 struct drm_device *dev = crtc->dev;
6075 struct drm_i915_private *dev_priv = dev->dev_private;
6076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6077 int pipe = intel_crtc->pipe;
6078 int x = intel_crtc->cursor_x;
6079 int y = intel_crtc->cursor_y;
6080 u32 base, pos;
6081 bool visible;
6082
6083 pos = 0;
6084
6085 if (on && crtc->enabled && crtc->fb) {
6086 base = intel_crtc->cursor_addr;
6087 if (x > (int) crtc->fb->width)
6088 base = 0;
6089
6090 if (y > (int) crtc->fb->height)
6091 base = 0;
6092 } else
6093 base = 0;
6094
6095 if (x < 0) {
6096 if (x + intel_crtc->cursor_width < 0)
6097 base = 0;
6098
6099 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6100 x = -x;
6101 }
6102 pos |= x << CURSOR_X_SHIFT;
6103
6104 if (y < 0) {
6105 if (y + intel_crtc->cursor_height < 0)
6106 base = 0;
6107
6108 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6109 y = -y;
6110 }
6111 pos |= y << CURSOR_Y_SHIFT;
6112
6113 visible = base != 0;
6114 if (!visible && !intel_crtc->cursor_visible)
6115 return;
6116
6117 if (IS_IVYBRIDGE(dev)) {
6118 I915_WRITE(CURPOS_IVB(pipe), pos);
6119 ivb_update_cursor(crtc, base);
6120 } else {
6121 I915_WRITE(CURPOS(pipe), pos);
6122 if (IS_845G(dev) || IS_I865G(dev))
6123 i845_update_cursor(crtc, base);
6124 else
6125 i9xx_update_cursor(crtc, base);
6126 }
6127
6128 if (visible)
6129 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6130 }
6131
6132 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6133 struct drm_file *file,
6134 uint32_t handle,
6135 uint32_t width, uint32_t height)
6136 {
6137 struct drm_device *dev = crtc->dev;
6138 struct drm_i915_private *dev_priv = dev->dev_private;
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140 struct drm_i915_gem_object *obj;
6141 uint32_t addr;
6142 int ret;
6143
6144 DRM_DEBUG_KMS("\n");
6145
6146 /* if we want to turn off the cursor ignore width and height */
6147 if (!handle) {
6148 DRM_DEBUG_KMS("cursor off\n");
6149 addr = 0;
6150 obj = NULL;
6151 mutex_lock(&dev->struct_mutex);
6152 goto finish;
6153 }
6154
6155 /* Currently we only support 64x64 cursors */
6156 if (width != 64 || height != 64) {
6157 DRM_ERROR("we currently only support 64x64 cursors\n");
6158 return -EINVAL;
6159 }
6160
6161 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6162 if (&obj->base == NULL)
6163 return -ENOENT;
6164
6165 if (obj->base.size < width * height * 4) {
6166 DRM_ERROR("buffer is to small\n");
6167 ret = -ENOMEM;
6168 goto fail;
6169 }
6170
6171 /* we only need to pin inside GTT if cursor is non-phy */
6172 mutex_lock(&dev->struct_mutex);
6173 if (!dev_priv->info->cursor_needs_physical) {
6174 if (obj->tiling_mode) {
6175 DRM_ERROR("cursor cannot be tiled\n");
6176 ret = -EINVAL;
6177 goto fail_locked;
6178 }
6179
6180 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6181 if (ret) {
6182 DRM_ERROR("failed to move cursor bo into the GTT\n");
6183 goto fail_locked;
6184 }
6185
6186 ret = i915_gem_object_put_fence(obj);
6187 if (ret) {
6188 DRM_ERROR("failed to release fence for cursor");
6189 goto fail_unpin;
6190 }
6191
6192 addr = obj->gtt_offset;
6193 } else {
6194 int align = IS_I830(dev) ? 16 * 1024 : 256;
6195 ret = i915_gem_attach_phys_object(dev, obj,
6196 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6197 align);
6198 if (ret) {
6199 DRM_ERROR("failed to attach phys object\n");
6200 goto fail_locked;
6201 }
6202 addr = obj->phys_obj->handle->busaddr;
6203 }
6204
6205 if (IS_GEN2(dev))
6206 I915_WRITE(CURSIZE, (height << 12) | width);
6207
6208 finish:
6209 if (intel_crtc->cursor_bo) {
6210 if (dev_priv->info->cursor_needs_physical) {
6211 if (intel_crtc->cursor_bo != obj)
6212 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6213 } else
6214 i915_gem_object_unpin(intel_crtc->cursor_bo);
6215 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6216 }
6217
6218 mutex_unlock(&dev->struct_mutex);
6219
6220 intel_crtc->cursor_addr = addr;
6221 intel_crtc->cursor_bo = obj;
6222 intel_crtc->cursor_width = width;
6223 intel_crtc->cursor_height = height;
6224
6225 intel_crtc_update_cursor(crtc, true);
6226
6227 return 0;
6228 fail_unpin:
6229 i915_gem_object_unpin(obj);
6230 fail_locked:
6231 mutex_unlock(&dev->struct_mutex);
6232 fail:
6233 drm_gem_object_unreference_unlocked(&obj->base);
6234 return ret;
6235 }
6236
6237 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6238 {
6239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240
6241 intel_crtc->cursor_x = x;
6242 intel_crtc->cursor_y = y;
6243
6244 intel_crtc_update_cursor(crtc, true);
6245
6246 return 0;
6247 }
6248
6249 /** Sets the color ramps on behalf of RandR */
6250 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6251 u16 blue, int regno)
6252 {
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254
6255 intel_crtc->lut_r[regno] = red >> 8;
6256 intel_crtc->lut_g[regno] = green >> 8;
6257 intel_crtc->lut_b[regno] = blue >> 8;
6258 }
6259
6260 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6261 u16 *blue, int regno)
6262 {
6263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264
6265 *red = intel_crtc->lut_r[regno] << 8;
6266 *green = intel_crtc->lut_g[regno] << 8;
6267 *blue = intel_crtc->lut_b[regno] << 8;
6268 }
6269
6270 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6271 u16 *blue, uint32_t start, uint32_t size)
6272 {
6273 int end = (start + size > 256) ? 256 : start + size, i;
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6275
6276 for (i = start; i < end; i++) {
6277 intel_crtc->lut_r[i] = red[i] >> 8;
6278 intel_crtc->lut_g[i] = green[i] >> 8;
6279 intel_crtc->lut_b[i] = blue[i] >> 8;
6280 }
6281
6282 intel_crtc_load_lut(crtc);
6283 }
6284
6285 /**
6286 * Get a pipe with a simple mode set on it for doing load-based monitor
6287 * detection.
6288 *
6289 * It will be up to the load-detect code to adjust the pipe as appropriate for
6290 * its requirements. The pipe will be connected to no other encoders.
6291 *
6292 * Currently this code will only succeed if there is a pipe with no encoders
6293 * configured for it. In the future, it could choose to temporarily disable
6294 * some outputs to free up a pipe for its use.
6295 *
6296 * \return crtc, or NULL if no pipes are available.
6297 */
6298
6299 /* VESA 640x480x72Hz mode to set on the pipe */
6300 static struct drm_display_mode load_detect_mode = {
6301 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6302 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6303 };
6304
6305 static struct drm_framebuffer *
6306 intel_framebuffer_create(struct drm_device *dev,
6307 struct drm_mode_fb_cmd *mode_cmd,
6308 struct drm_i915_gem_object *obj)
6309 {
6310 struct intel_framebuffer *intel_fb;
6311 int ret;
6312
6313 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6314 if (!intel_fb) {
6315 drm_gem_object_unreference_unlocked(&obj->base);
6316 return ERR_PTR(-ENOMEM);
6317 }
6318
6319 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6320 if (ret) {
6321 drm_gem_object_unreference_unlocked(&obj->base);
6322 kfree(intel_fb);
6323 return ERR_PTR(ret);
6324 }
6325
6326 return &intel_fb->base;
6327 }
6328
6329 static u32
6330 intel_framebuffer_pitch_for_width(int width, int bpp)
6331 {
6332 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6333 return ALIGN(pitch, 64);
6334 }
6335
6336 static u32
6337 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6338 {
6339 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6340 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6341 }
6342
6343 static struct drm_framebuffer *
6344 intel_framebuffer_create_for_mode(struct drm_device *dev,
6345 struct drm_display_mode *mode,
6346 int depth, int bpp)
6347 {
6348 struct drm_i915_gem_object *obj;
6349 struct drm_mode_fb_cmd mode_cmd;
6350
6351 obj = i915_gem_alloc_object(dev,
6352 intel_framebuffer_size_for_mode(mode, bpp));
6353 if (obj == NULL)
6354 return ERR_PTR(-ENOMEM);
6355
6356 mode_cmd.width = mode->hdisplay;
6357 mode_cmd.height = mode->vdisplay;
6358 mode_cmd.depth = depth;
6359 mode_cmd.bpp = bpp;
6360 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6361
6362 return intel_framebuffer_create(dev, &mode_cmd, obj);
6363 }
6364
6365 static struct drm_framebuffer *
6366 mode_fits_in_fbdev(struct drm_device *dev,
6367 struct drm_display_mode *mode)
6368 {
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct drm_i915_gem_object *obj;
6371 struct drm_framebuffer *fb;
6372
6373 if (dev_priv->fbdev == NULL)
6374 return NULL;
6375
6376 obj = dev_priv->fbdev->ifb.obj;
6377 if (obj == NULL)
6378 return NULL;
6379
6380 fb = &dev_priv->fbdev->ifb.base;
6381 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6382 fb->bits_per_pixel))
6383 return NULL;
6384
6385 if (obj->base.size < mode->vdisplay * fb->pitch)
6386 return NULL;
6387
6388 return fb;
6389 }
6390
6391 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6392 struct drm_connector *connector,
6393 struct drm_display_mode *mode,
6394 struct intel_load_detect_pipe *old)
6395 {
6396 struct intel_crtc *intel_crtc;
6397 struct drm_crtc *possible_crtc;
6398 struct drm_encoder *encoder = &intel_encoder->base;
6399 struct drm_crtc *crtc = NULL;
6400 struct drm_device *dev = encoder->dev;
6401 struct drm_framebuffer *old_fb;
6402 int i = -1;
6403
6404 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6405 connector->base.id, drm_get_connector_name(connector),
6406 encoder->base.id, drm_get_encoder_name(encoder));
6407
6408 /*
6409 * Algorithm gets a little messy:
6410 *
6411 * - if the connector already has an assigned crtc, use it (but make
6412 * sure it's on first)
6413 *
6414 * - try to find the first unused crtc that can drive this connector,
6415 * and use that if we find one
6416 */
6417
6418 /* See if we already have a CRTC for this connector */
6419 if (encoder->crtc) {
6420 crtc = encoder->crtc;
6421
6422 intel_crtc = to_intel_crtc(crtc);
6423 old->dpms_mode = intel_crtc->dpms_mode;
6424 old->load_detect_temp = false;
6425
6426 /* Make sure the crtc and connector are running */
6427 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6428 struct drm_encoder_helper_funcs *encoder_funcs;
6429 struct drm_crtc_helper_funcs *crtc_funcs;
6430
6431 crtc_funcs = crtc->helper_private;
6432 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6433
6434 encoder_funcs = encoder->helper_private;
6435 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6436 }
6437
6438 return true;
6439 }
6440
6441 /* Find an unused one (if possible) */
6442 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6443 i++;
6444 if (!(encoder->possible_crtcs & (1 << i)))
6445 continue;
6446 if (!possible_crtc->enabled) {
6447 crtc = possible_crtc;
6448 break;
6449 }
6450 }
6451
6452 /*
6453 * If we didn't find an unused CRTC, don't use any.
6454 */
6455 if (!crtc) {
6456 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6457 return false;
6458 }
6459
6460 encoder->crtc = crtc;
6461 connector->encoder = encoder;
6462
6463 intel_crtc = to_intel_crtc(crtc);
6464 old->dpms_mode = intel_crtc->dpms_mode;
6465 old->load_detect_temp = true;
6466 old->release_fb = NULL;
6467
6468 if (!mode)
6469 mode = &load_detect_mode;
6470
6471 old_fb = crtc->fb;
6472
6473 /* We need a framebuffer large enough to accommodate all accesses
6474 * that the plane may generate whilst we perform load detection.
6475 * We can not rely on the fbcon either being present (we get called
6476 * during its initialisation to detect all boot displays, or it may
6477 * not even exist) or that it is large enough to satisfy the
6478 * requested mode.
6479 */
6480 crtc->fb = mode_fits_in_fbdev(dev, mode);
6481 if (crtc->fb == NULL) {
6482 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6483 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6484 old->release_fb = crtc->fb;
6485 } else
6486 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6487 if (IS_ERR(crtc->fb)) {
6488 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6489 crtc->fb = old_fb;
6490 return false;
6491 }
6492
6493 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6494 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6495 if (old->release_fb)
6496 old->release_fb->funcs->destroy(old->release_fb);
6497 crtc->fb = old_fb;
6498 return false;
6499 }
6500
6501 /* let the connector get through one full cycle before testing */
6502 intel_wait_for_vblank(dev, intel_crtc->pipe);
6503
6504 return true;
6505 }
6506
6507 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6508 struct drm_connector *connector,
6509 struct intel_load_detect_pipe *old)
6510 {
6511 struct drm_encoder *encoder = &intel_encoder->base;
6512 struct drm_device *dev = encoder->dev;
6513 struct drm_crtc *crtc = encoder->crtc;
6514 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6515 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6516
6517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6518 connector->base.id, drm_get_connector_name(connector),
6519 encoder->base.id, drm_get_encoder_name(encoder));
6520
6521 if (old->load_detect_temp) {
6522 connector->encoder = NULL;
6523 drm_helper_disable_unused_functions(dev);
6524
6525 if (old->release_fb)
6526 old->release_fb->funcs->destroy(old->release_fb);
6527
6528 return;
6529 }
6530
6531 /* Switch crtc and encoder back off if necessary */
6532 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6533 encoder_funcs->dpms(encoder, old->dpms_mode);
6534 crtc_funcs->dpms(crtc, old->dpms_mode);
6535 }
6536 }
6537
6538 /* Returns the clock of the currently programmed mode of the given pipe. */
6539 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6540 {
6541 struct drm_i915_private *dev_priv = dev->dev_private;
6542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6543 int pipe = intel_crtc->pipe;
6544 u32 dpll = I915_READ(DPLL(pipe));
6545 u32 fp;
6546 intel_clock_t clock;
6547
6548 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6549 fp = I915_READ(FP0(pipe));
6550 else
6551 fp = I915_READ(FP1(pipe));
6552
6553 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6554 if (IS_PINEVIEW(dev)) {
6555 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6556 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6557 } else {
6558 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6559 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6560 }
6561
6562 if (!IS_GEN2(dev)) {
6563 if (IS_PINEVIEW(dev))
6564 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6565 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6566 else
6567 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6568 DPLL_FPA01_P1_POST_DIV_SHIFT);
6569
6570 switch (dpll & DPLL_MODE_MASK) {
6571 case DPLLB_MODE_DAC_SERIAL:
6572 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6573 5 : 10;
6574 break;
6575 case DPLLB_MODE_LVDS:
6576 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6577 7 : 14;
6578 break;
6579 default:
6580 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6581 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6582 return 0;
6583 }
6584
6585 /* XXX: Handle the 100Mhz refclk */
6586 intel_clock(dev, 96000, &clock);
6587 } else {
6588 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6589
6590 if (is_lvds) {
6591 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6592 DPLL_FPA01_P1_POST_DIV_SHIFT);
6593 clock.p2 = 14;
6594
6595 if ((dpll & PLL_REF_INPUT_MASK) ==
6596 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6597 /* XXX: might not be 66MHz */
6598 intel_clock(dev, 66000, &clock);
6599 } else
6600 intel_clock(dev, 48000, &clock);
6601 } else {
6602 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6603 clock.p1 = 2;
6604 else {
6605 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6606 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6607 }
6608 if (dpll & PLL_P2_DIVIDE_BY_4)
6609 clock.p2 = 4;
6610 else
6611 clock.p2 = 2;
6612
6613 intel_clock(dev, 48000, &clock);
6614 }
6615 }
6616
6617 /* XXX: It would be nice to validate the clocks, but we can't reuse
6618 * i830PllIsValid() because it relies on the xf86_config connector
6619 * configuration being accurate, which it isn't necessarily.
6620 */
6621
6622 return clock.dot;
6623 }
6624
6625 /** Returns the currently programmed mode of the given pipe. */
6626 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6627 struct drm_crtc *crtc)
6628 {
6629 struct drm_i915_private *dev_priv = dev->dev_private;
6630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6631 int pipe = intel_crtc->pipe;
6632 struct drm_display_mode *mode;
6633 int htot = I915_READ(HTOTAL(pipe));
6634 int hsync = I915_READ(HSYNC(pipe));
6635 int vtot = I915_READ(VTOTAL(pipe));
6636 int vsync = I915_READ(VSYNC(pipe));
6637
6638 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6639 if (!mode)
6640 return NULL;
6641
6642 mode->clock = intel_crtc_clock_get(dev, crtc);
6643 mode->hdisplay = (htot & 0xffff) + 1;
6644 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6645 mode->hsync_start = (hsync & 0xffff) + 1;
6646 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6647 mode->vdisplay = (vtot & 0xffff) + 1;
6648 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6649 mode->vsync_start = (vsync & 0xffff) + 1;
6650 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6651
6652 drm_mode_set_name(mode);
6653 drm_mode_set_crtcinfo(mode, 0);
6654
6655 return mode;
6656 }
6657
6658 #define GPU_IDLE_TIMEOUT 500 /* ms */
6659
6660 /* When this timer fires, we've been idle for awhile */
6661 static void intel_gpu_idle_timer(unsigned long arg)
6662 {
6663 struct drm_device *dev = (struct drm_device *)arg;
6664 drm_i915_private_t *dev_priv = dev->dev_private;
6665
6666 if (!list_empty(&dev_priv->mm.active_list)) {
6667 /* Still processing requests, so just re-arm the timer. */
6668 mod_timer(&dev_priv->idle_timer, jiffies +
6669 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6670 return;
6671 }
6672
6673 dev_priv->busy = false;
6674 queue_work(dev_priv->wq, &dev_priv->idle_work);
6675 }
6676
6677 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6678
6679 static void intel_crtc_idle_timer(unsigned long arg)
6680 {
6681 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6682 struct drm_crtc *crtc = &intel_crtc->base;
6683 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6684 struct intel_framebuffer *intel_fb;
6685
6686 intel_fb = to_intel_framebuffer(crtc->fb);
6687 if (intel_fb && intel_fb->obj->active) {
6688 /* The framebuffer is still being accessed by the GPU. */
6689 mod_timer(&intel_crtc->idle_timer, jiffies +
6690 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6691 return;
6692 }
6693
6694 intel_crtc->busy = false;
6695 queue_work(dev_priv->wq, &dev_priv->idle_work);
6696 }
6697
6698 static void intel_increase_pllclock(struct drm_crtc *crtc)
6699 {
6700 struct drm_device *dev = crtc->dev;
6701 drm_i915_private_t *dev_priv = dev->dev_private;
6702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6703 int pipe = intel_crtc->pipe;
6704 int dpll_reg = DPLL(pipe);
6705 int dpll;
6706
6707 if (HAS_PCH_SPLIT(dev))
6708 return;
6709
6710 if (!dev_priv->lvds_downclock_avail)
6711 return;
6712
6713 dpll = I915_READ(dpll_reg);
6714 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6715 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6716
6717 /* Unlock panel regs */
6718 I915_WRITE(PP_CONTROL,
6719 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6720
6721 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6722 I915_WRITE(dpll_reg, dpll);
6723 intel_wait_for_vblank(dev, pipe);
6724
6725 dpll = I915_READ(dpll_reg);
6726 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6727 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6728
6729 /* ...and lock them again */
6730 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6731 }
6732
6733 /* Schedule downclock */
6734 mod_timer(&intel_crtc->idle_timer, jiffies +
6735 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6736 }
6737
6738 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6739 {
6740 struct drm_device *dev = crtc->dev;
6741 drm_i915_private_t *dev_priv = dev->dev_private;
6742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6743 int pipe = intel_crtc->pipe;
6744 int dpll_reg = DPLL(pipe);
6745 int dpll = I915_READ(dpll_reg);
6746
6747 if (HAS_PCH_SPLIT(dev))
6748 return;
6749
6750 if (!dev_priv->lvds_downclock_avail)
6751 return;
6752
6753 /*
6754 * Since this is called by a timer, we should never get here in
6755 * the manual case.
6756 */
6757 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6758 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6759
6760 /* Unlock panel regs */
6761 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6762 PANEL_UNLOCK_REGS);
6763
6764 dpll |= DISPLAY_RATE_SELECT_FPA1;
6765 I915_WRITE(dpll_reg, dpll);
6766 intel_wait_for_vblank(dev, pipe);
6767 dpll = I915_READ(dpll_reg);
6768 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6769 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6770
6771 /* ...and lock them again */
6772 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6773 }
6774
6775 }
6776
6777 /**
6778 * intel_idle_update - adjust clocks for idleness
6779 * @work: work struct
6780 *
6781 * Either the GPU or display (or both) went idle. Check the busy status
6782 * here and adjust the CRTC and GPU clocks as necessary.
6783 */
6784 static void intel_idle_update(struct work_struct *work)
6785 {
6786 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6787 idle_work);
6788 struct drm_device *dev = dev_priv->dev;
6789 struct drm_crtc *crtc;
6790 struct intel_crtc *intel_crtc;
6791
6792 if (!i915_powersave)
6793 return;
6794
6795 mutex_lock(&dev->struct_mutex);
6796
6797 i915_update_gfx_val(dev_priv);
6798
6799 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6800 /* Skip inactive CRTCs */
6801 if (!crtc->fb)
6802 continue;
6803
6804 intel_crtc = to_intel_crtc(crtc);
6805 if (!intel_crtc->busy)
6806 intel_decrease_pllclock(crtc);
6807 }
6808
6809
6810 mutex_unlock(&dev->struct_mutex);
6811 }
6812
6813 /**
6814 * intel_mark_busy - mark the GPU and possibly the display busy
6815 * @dev: drm device
6816 * @obj: object we're operating on
6817 *
6818 * Callers can use this function to indicate that the GPU is busy processing
6819 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6820 * buffer), we'll also mark the display as busy, so we know to increase its
6821 * clock frequency.
6822 */
6823 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6824 {
6825 drm_i915_private_t *dev_priv = dev->dev_private;
6826 struct drm_crtc *crtc = NULL;
6827 struct intel_framebuffer *intel_fb;
6828 struct intel_crtc *intel_crtc;
6829
6830 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6831 return;
6832
6833 if (!dev_priv->busy)
6834 dev_priv->busy = true;
6835 else
6836 mod_timer(&dev_priv->idle_timer, jiffies +
6837 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6838
6839 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6840 if (!crtc->fb)
6841 continue;
6842
6843 intel_crtc = to_intel_crtc(crtc);
6844 intel_fb = to_intel_framebuffer(crtc->fb);
6845 if (intel_fb->obj == obj) {
6846 if (!intel_crtc->busy) {
6847 /* Non-busy -> busy, upclock */
6848 intel_increase_pllclock(crtc);
6849 intel_crtc->busy = true;
6850 } else {
6851 /* Busy -> busy, put off timer */
6852 mod_timer(&intel_crtc->idle_timer, jiffies +
6853 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6854 }
6855 }
6856 }
6857 }
6858
6859 static void intel_crtc_destroy(struct drm_crtc *crtc)
6860 {
6861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6862 struct drm_device *dev = crtc->dev;
6863 struct intel_unpin_work *work;
6864 unsigned long flags;
6865
6866 spin_lock_irqsave(&dev->event_lock, flags);
6867 work = intel_crtc->unpin_work;
6868 intel_crtc->unpin_work = NULL;
6869 spin_unlock_irqrestore(&dev->event_lock, flags);
6870
6871 if (work) {
6872 cancel_work_sync(&work->work);
6873 kfree(work);
6874 }
6875
6876 drm_crtc_cleanup(crtc);
6877
6878 kfree(intel_crtc);
6879 }
6880
6881 static void intel_unpin_work_fn(struct work_struct *__work)
6882 {
6883 struct intel_unpin_work *work =
6884 container_of(__work, struct intel_unpin_work, work);
6885
6886 mutex_lock(&work->dev->struct_mutex);
6887 i915_gem_object_unpin(work->old_fb_obj);
6888 drm_gem_object_unreference(&work->pending_flip_obj->base);
6889 drm_gem_object_unreference(&work->old_fb_obj->base);
6890
6891 intel_update_fbc(work->dev);
6892 mutex_unlock(&work->dev->struct_mutex);
6893 kfree(work);
6894 }
6895
6896 static void do_intel_finish_page_flip(struct drm_device *dev,
6897 struct drm_crtc *crtc)
6898 {
6899 drm_i915_private_t *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 struct intel_unpin_work *work;
6902 struct drm_i915_gem_object *obj;
6903 struct drm_pending_vblank_event *e;
6904 struct timeval tnow, tvbl;
6905 unsigned long flags;
6906
6907 /* Ignore early vblank irqs */
6908 if (intel_crtc == NULL)
6909 return;
6910
6911 do_gettimeofday(&tnow);
6912
6913 spin_lock_irqsave(&dev->event_lock, flags);
6914 work = intel_crtc->unpin_work;
6915 if (work == NULL || !work->pending) {
6916 spin_unlock_irqrestore(&dev->event_lock, flags);
6917 return;
6918 }
6919
6920 intel_crtc->unpin_work = NULL;
6921
6922 if (work->event) {
6923 e = work->event;
6924 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6925
6926 /* Called before vblank count and timestamps have
6927 * been updated for the vblank interval of flip
6928 * completion? Need to increment vblank count and
6929 * add one videorefresh duration to returned timestamp
6930 * to account for this. We assume this happened if we
6931 * get called over 0.9 frame durations after the last
6932 * timestamped vblank.
6933 *
6934 * This calculation can not be used with vrefresh rates
6935 * below 5Hz (10Hz to be on the safe side) without
6936 * promoting to 64 integers.
6937 */
6938 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6939 9 * crtc->framedur_ns) {
6940 e->event.sequence++;
6941 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6942 crtc->framedur_ns);
6943 }
6944
6945 e->event.tv_sec = tvbl.tv_sec;
6946 e->event.tv_usec = tvbl.tv_usec;
6947
6948 list_add_tail(&e->base.link,
6949 &e->base.file_priv->event_list);
6950 wake_up_interruptible(&e->base.file_priv->event_wait);
6951 }
6952
6953 drm_vblank_put(dev, intel_crtc->pipe);
6954
6955 spin_unlock_irqrestore(&dev->event_lock, flags);
6956
6957 obj = work->old_fb_obj;
6958
6959 atomic_clear_mask(1 << intel_crtc->plane,
6960 &obj->pending_flip.counter);
6961 if (atomic_read(&obj->pending_flip) == 0)
6962 wake_up(&dev_priv->pending_flip_queue);
6963
6964 schedule_work(&work->work);
6965
6966 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6967 }
6968
6969 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6970 {
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6973
6974 do_intel_finish_page_flip(dev, crtc);
6975 }
6976
6977 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6978 {
6979 drm_i915_private_t *dev_priv = dev->dev_private;
6980 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6981
6982 do_intel_finish_page_flip(dev, crtc);
6983 }
6984
6985 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6986 {
6987 drm_i915_private_t *dev_priv = dev->dev_private;
6988 struct intel_crtc *intel_crtc =
6989 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6990 unsigned long flags;
6991
6992 spin_lock_irqsave(&dev->event_lock, flags);
6993 if (intel_crtc->unpin_work) {
6994 if ((++intel_crtc->unpin_work->pending) > 1)
6995 DRM_ERROR("Prepared flip multiple times\n");
6996 } else {
6997 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6998 }
6999 spin_unlock_irqrestore(&dev->event_lock, flags);
7000 }
7001
7002 static int intel_gen2_queue_flip(struct drm_device *dev,
7003 struct drm_crtc *crtc,
7004 struct drm_framebuffer *fb,
7005 struct drm_i915_gem_object *obj)
7006 {
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7009 unsigned long offset;
7010 u32 flip_mask;
7011 int ret;
7012
7013 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7014 if (ret)
7015 goto out;
7016
7017 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7018 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7019
7020 ret = BEGIN_LP_RING(6);
7021 if (ret)
7022 goto out;
7023
7024 /* Can't queue multiple flips, so wait for the previous
7025 * one to finish before executing the next.
7026 */
7027 if (intel_crtc->plane)
7028 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7029 else
7030 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7031 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7032 OUT_RING(MI_NOOP);
7033 OUT_RING(MI_DISPLAY_FLIP |
7034 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7035 OUT_RING(fb->pitch);
7036 OUT_RING(obj->gtt_offset + offset);
7037 OUT_RING(MI_NOOP);
7038 ADVANCE_LP_RING();
7039 out:
7040 return ret;
7041 }
7042
7043 static int intel_gen3_queue_flip(struct drm_device *dev,
7044 struct drm_crtc *crtc,
7045 struct drm_framebuffer *fb,
7046 struct drm_i915_gem_object *obj)
7047 {
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050 unsigned long offset;
7051 u32 flip_mask;
7052 int ret;
7053
7054 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7055 if (ret)
7056 goto out;
7057
7058 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7059 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7060
7061 ret = BEGIN_LP_RING(6);
7062 if (ret)
7063 goto out;
7064
7065 if (intel_crtc->plane)
7066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7067 else
7068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7069 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7070 OUT_RING(MI_NOOP);
7071 OUT_RING(MI_DISPLAY_FLIP_I915 |
7072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7073 OUT_RING(fb->pitch);
7074 OUT_RING(obj->gtt_offset + offset);
7075 OUT_RING(MI_NOOP);
7076
7077 ADVANCE_LP_RING();
7078 out:
7079 return ret;
7080 }
7081
7082 static int intel_gen4_queue_flip(struct drm_device *dev,
7083 struct drm_crtc *crtc,
7084 struct drm_framebuffer *fb,
7085 struct drm_i915_gem_object *obj)
7086 {
7087 struct drm_i915_private *dev_priv = dev->dev_private;
7088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089 uint32_t pf, pipesrc;
7090 int ret;
7091
7092 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7093 if (ret)
7094 goto out;
7095
7096 ret = BEGIN_LP_RING(4);
7097 if (ret)
7098 goto out;
7099
7100 /* i965+ uses the linear or tiled offsets from the
7101 * Display Registers (which do not change across a page-flip)
7102 * so we need only reprogram the base address.
7103 */
7104 OUT_RING(MI_DISPLAY_FLIP |
7105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7106 OUT_RING(fb->pitch);
7107 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7108
7109 /* XXX Enabling the panel-fitter across page-flip is so far
7110 * untested on non-native modes, so ignore it for now.
7111 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7112 */
7113 pf = 0;
7114 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7115 OUT_RING(pf | pipesrc);
7116 ADVANCE_LP_RING();
7117 out:
7118 return ret;
7119 }
7120
7121 static int intel_gen6_queue_flip(struct drm_device *dev,
7122 struct drm_crtc *crtc,
7123 struct drm_framebuffer *fb,
7124 struct drm_i915_gem_object *obj)
7125 {
7126 struct drm_i915_private *dev_priv = dev->dev_private;
7127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128 uint32_t pf, pipesrc;
7129 int ret;
7130
7131 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7132 if (ret)
7133 goto out;
7134
7135 ret = BEGIN_LP_RING(4);
7136 if (ret)
7137 goto out;
7138
7139 OUT_RING(MI_DISPLAY_FLIP |
7140 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7141 OUT_RING(fb->pitch | obj->tiling_mode);
7142 OUT_RING(obj->gtt_offset);
7143
7144 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7145 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7146 OUT_RING(pf | pipesrc);
7147 ADVANCE_LP_RING();
7148 out:
7149 return ret;
7150 }
7151
7152 /*
7153 * On gen7 we currently use the blit ring because (in early silicon at least)
7154 * the render ring doesn't give us interrpts for page flip completion, which
7155 * means clients will hang after the first flip is queued. Fortunately the
7156 * blit ring generates interrupts properly, so use it instead.
7157 */
7158 static int intel_gen7_queue_flip(struct drm_device *dev,
7159 struct drm_crtc *crtc,
7160 struct drm_framebuffer *fb,
7161 struct drm_i915_gem_object *obj)
7162 {
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7166 int ret;
7167
7168 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7169 if (ret)
7170 goto out;
7171
7172 ret = intel_ring_begin(ring, 4);
7173 if (ret)
7174 goto out;
7175
7176 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7177 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7178 intel_ring_emit(ring, (obj->gtt_offset));
7179 intel_ring_emit(ring, (MI_NOOP));
7180 intel_ring_advance(ring);
7181 out:
7182 return ret;
7183 }
7184
7185 static int intel_default_queue_flip(struct drm_device *dev,
7186 struct drm_crtc *crtc,
7187 struct drm_framebuffer *fb,
7188 struct drm_i915_gem_object *obj)
7189 {
7190 return -ENODEV;
7191 }
7192
7193 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7194 struct drm_framebuffer *fb,
7195 struct drm_pending_vblank_event *event)
7196 {
7197 struct drm_device *dev = crtc->dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 struct intel_framebuffer *intel_fb;
7200 struct drm_i915_gem_object *obj;
7201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7202 struct intel_unpin_work *work;
7203 unsigned long flags;
7204 int ret;
7205
7206 work = kzalloc(sizeof *work, GFP_KERNEL);
7207 if (work == NULL)
7208 return -ENOMEM;
7209
7210 work->event = event;
7211 work->dev = crtc->dev;
7212 intel_fb = to_intel_framebuffer(crtc->fb);
7213 work->old_fb_obj = intel_fb->obj;
7214 INIT_WORK(&work->work, intel_unpin_work_fn);
7215
7216 /* We borrow the event spin lock for protecting unpin_work */
7217 spin_lock_irqsave(&dev->event_lock, flags);
7218 if (intel_crtc->unpin_work) {
7219 spin_unlock_irqrestore(&dev->event_lock, flags);
7220 kfree(work);
7221
7222 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7223 return -EBUSY;
7224 }
7225 intel_crtc->unpin_work = work;
7226 spin_unlock_irqrestore(&dev->event_lock, flags);
7227
7228 intel_fb = to_intel_framebuffer(fb);
7229 obj = intel_fb->obj;
7230
7231 mutex_lock(&dev->struct_mutex);
7232
7233 /* Reference the objects for the scheduled work. */
7234 drm_gem_object_reference(&work->old_fb_obj->base);
7235 drm_gem_object_reference(&obj->base);
7236
7237 crtc->fb = fb;
7238
7239 ret = drm_vblank_get(dev, intel_crtc->pipe);
7240 if (ret)
7241 goto cleanup_objs;
7242
7243 work->pending_flip_obj = obj;
7244
7245 work->enable_stall_check = true;
7246
7247 /* Block clients from rendering to the new back buffer until
7248 * the flip occurs and the object is no longer visible.
7249 */
7250 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7251
7252 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7253 if (ret)
7254 goto cleanup_pending;
7255
7256 intel_disable_fbc(dev);
7257 mutex_unlock(&dev->struct_mutex);
7258
7259 trace_i915_flip_request(intel_crtc->plane, obj);
7260
7261 return 0;
7262
7263 cleanup_pending:
7264 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7265 cleanup_objs:
7266 drm_gem_object_unreference(&work->old_fb_obj->base);
7267 drm_gem_object_unreference(&obj->base);
7268 mutex_unlock(&dev->struct_mutex);
7269
7270 spin_lock_irqsave(&dev->event_lock, flags);
7271 intel_crtc->unpin_work = NULL;
7272 spin_unlock_irqrestore(&dev->event_lock, flags);
7273
7274 kfree(work);
7275
7276 return ret;
7277 }
7278
7279 static void intel_sanitize_modesetting(struct drm_device *dev,
7280 int pipe, int plane)
7281 {
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 u32 reg, val;
7284
7285 if (HAS_PCH_SPLIT(dev))
7286 return;
7287
7288 /* Who knows what state these registers were left in by the BIOS or
7289 * grub?
7290 *
7291 * If we leave the registers in a conflicting state (e.g. with the
7292 * display plane reading from the other pipe than the one we intend
7293 * to use) then when we attempt to teardown the active mode, we will
7294 * not disable the pipes and planes in the correct order -- leaving
7295 * a plane reading from a disabled pipe and possibly leading to
7296 * undefined behaviour.
7297 */
7298
7299 reg = DSPCNTR(plane);
7300 val = I915_READ(reg);
7301
7302 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7303 return;
7304 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7305 return;
7306
7307 /* This display plane is active and attached to the other CPU pipe. */
7308 pipe = !pipe;
7309
7310 /* Disable the plane and wait for it to stop reading from the pipe. */
7311 intel_disable_plane(dev_priv, plane, pipe);
7312 intel_disable_pipe(dev_priv, pipe);
7313 }
7314
7315 static void intel_crtc_reset(struct drm_crtc *crtc)
7316 {
7317 struct drm_device *dev = crtc->dev;
7318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7319
7320 /* Reset flags back to the 'unknown' status so that they
7321 * will be correctly set on the initial modeset.
7322 */
7323 intel_crtc->dpms_mode = -1;
7324
7325 /* We need to fix up any BIOS configuration that conflicts with
7326 * our expectations.
7327 */
7328 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7329 }
7330
7331 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7332 .dpms = intel_crtc_dpms,
7333 .mode_fixup = intel_crtc_mode_fixup,
7334 .mode_set = intel_crtc_mode_set,
7335 .mode_set_base = intel_pipe_set_base,
7336 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7337 .load_lut = intel_crtc_load_lut,
7338 .disable = intel_crtc_disable,
7339 };
7340
7341 static const struct drm_crtc_funcs intel_crtc_funcs = {
7342 .reset = intel_crtc_reset,
7343 .cursor_set = intel_crtc_cursor_set,
7344 .cursor_move = intel_crtc_cursor_move,
7345 .gamma_set = intel_crtc_gamma_set,
7346 .set_config = drm_crtc_helper_set_config,
7347 .destroy = intel_crtc_destroy,
7348 .page_flip = intel_crtc_page_flip,
7349 };
7350
7351 static void intel_crtc_init(struct drm_device *dev, int pipe)
7352 {
7353 drm_i915_private_t *dev_priv = dev->dev_private;
7354 struct intel_crtc *intel_crtc;
7355 int i;
7356
7357 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7358 if (intel_crtc == NULL)
7359 return;
7360
7361 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7362
7363 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7364 for (i = 0; i < 256; i++) {
7365 intel_crtc->lut_r[i] = i;
7366 intel_crtc->lut_g[i] = i;
7367 intel_crtc->lut_b[i] = i;
7368 }
7369
7370 /* Swap pipes & planes for FBC on pre-965 */
7371 intel_crtc->pipe = pipe;
7372 intel_crtc->plane = pipe;
7373 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7374 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7375 intel_crtc->plane = !pipe;
7376 }
7377
7378 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7379 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7380 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7381 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7382
7383 intel_crtc_reset(&intel_crtc->base);
7384 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7385 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7386
7387 if (HAS_PCH_SPLIT(dev)) {
7388 if (pipe == 2 && IS_IVYBRIDGE(dev))
7389 intel_crtc->no_pll = true;
7390 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7391 intel_helper_funcs.commit = ironlake_crtc_commit;
7392 } else {
7393 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7394 intel_helper_funcs.commit = i9xx_crtc_commit;
7395 }
7396
7397 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7398
7399 intel_crtc->busy = false;
7400
7401 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7402 (unsigned long)intel_crtc);
7403 }
7404
7405 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7406 struct drm_file *file)
7407 {
7408 drm_i915_private_t *dev_priv = dev->dev_private;
7409 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7410 struct drm_mode_object *drmmode_obj;
7411 struct intel_crtc *crtc;
7412
7413 if (!dev_priv) {
7414 DRM_ERROR("called with no initialization\n");
7415 return -EINVAL;
7416 }
7417
7418 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7419 DRM_MODE_OBJECT_CRTC);
7420
7421 if (!drmmode_obj) {
7422 DRM_ERROR("no such CRTC id\n");
7423 return -EINVAL;
7424 }
7425
7426 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7427 pipe_from_crtc_id->pipe = crtc->pipe;
7428
7429 return 0;
7430 }
7431
7432 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7433 {
7434 struct intel_encoder *encoder;
7435 int index_mask = 0;
7436 int entry = 0;
7437
7438 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7439 if (type_mask & encoder->clone_mask)
7440 index_mask |= (1 << entry);
7441 entry++;
7442 }
7443
7444 return index_mask;
7445 }
7446
7447 static bool has_edp_a(struct drm_device *dev)
7448 {
7449 struct drm_i915_private *dev_priv = dev->dev_private;
7450
7451 if (!IS_MOBILE(dev))
7452 return false;
7453
7454 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7455 return false;
7456
7457 if (IS_GEN5(dev) &&
7458 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7459 return false;
7460
7461 return true;
7462 }
7463
7464 static void intel_setup_outputs(struct drm_device *dev)
7465 {
7466 struct drm_i915_private *dev_priv = dev->dev_private;
7467 struct intel_encoder *encoder;
7468 bool dpd_is_edp = false;
7469 bool has_lvds = false;
7470
7471 if (IS_MOBILE(dev) && !IS_I830(dev))
7472 has_lvds = intel_lvds_init(dev);
7473 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7474 /* disable the panel fitter on everything but LVDS */
7475 I915_WRITE(PFIT_CONTROL, 0);
7476 }
7477
7478 if (HAS_PCH_SPLIT(dev)) {
7479 dpd_is_edp = intel_dpd_is_edp(dev);
7480
7481 if (has_edp_a(dev))
7482 intel_dp_init(dev, DP_A);
7483
7484 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7485 intel_dp_init(dev, PCH_DP_D);
7486 }
7487
7488 intel_crt_init(dev);
7489
7490 if (HAS_PCH_SPLIT(dev)) {
7491 int found;
7492
7493 if (I915_READ(HDMIB) & PORT_DETECTED) {
7494 /* PCH SDVOB multiplex with HDMIB */
7495 found = intel_sdvo_init(dev, PCH_SDVOB);
7496 if (!found)
7497 intel_hdmi_init(dev, HDMIB);
7498 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7499 intel_dp_init(dev, PCH_DP_B);
7500 }
7501
7502 if (I915_READ(HDMIC) & PORT_DETECTED)
7503 intel_hdmi_init(dev, HDMIC);
7504
7505 if (I915_READ(HDMID) & PORT_DETECTED)
7506 intel_hdmi_init(dev, HDMID);
7507
7508 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7509 intel_dp_init(dev, PCH_DP_C);
7510
7511 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7512 intel_dp_init(dev, PCH_DP_D);
7513
7514 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7515 bool found = false;
7516
7517 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7518 DRM_DEBUG_KMS("probing SDVOB\n");
7519 found = intel_sdvo_init(dev, SDVOB);
7520 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7521 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7522 intel_hdmi_init(dev, SDVOB);
7523 }
7524
7525 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7526 DRM_DEBUG_KMS("probing DP_B\n");
7527 intel_dp_init(dev, DP_B);
7528 }
7529 }
7530
7531 /* Before G4X SDVOC doesn't have its own detect register */
7532
7533 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7534 DRM_DEBUG_KMS("probing SDVOC\n");
7535 found = intel_sdvo_init(dev, SDVOC);
7536 }
7537
7538 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7539
7540 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7541 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7542 intel_hdmi_init(dev, SDVOC);
7543 }
7544 if (SUPPORTS_INTEGRATED_DP(dev)) {
7545 DRM_DEBUG_KMS("probing DP_C\n");
7546 intel_dp_init(dev, DP_C);
7547 }
7548 }
7549
7550 if (SUPPORTS_INTEGRATED_DP(dev) &&
7551 (I915_READ(DP_D) & DP_DETECTED)) {
7552 DRM_DEBUG_KMS("probing DP_D\n");
7553 intel_dp_init(dev, DP_D);
7554 }
7555 } else if (IS_GEN2(dev))
7556 intel_dvo_init(dev);
7557
7558 if (SUPPORTS_TV(dev))
7559 intel_tv_init(dev);
7560
7561 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7562 encoder->base.possible_crtcs = encoder->crtc_mask;
7563 encoder->base.possible_clones =
7564 intel_encoder_clones(dev, encoder->clone_mask);
7565 }
7566
7567 /* disable all the possible outputs/crtcs before entering KMS mode */
7568 drm_helper_disable_unused_functions(dev);
7569
7570 if (HAS_PCH_SPLIT(dev))
7571 ironlake_init_pch_refclk(dev);
7572 }
7573
7574 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7575 {
7576 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7577
7578 drm_framebuffer_cleanup(fb);
7579 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7580
7581 kfree(intel_fb);
7582 }
7583
7584 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7585 struct drm_file *file,
7586 unsigned int *handle)
7587 {
7588 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7589 struct drm_i915_gem_object *obj = intel_fb->obj;
7590
7591 return drm_gem_handle_create(file, &obj->base, handle);
7592 }
7593
7594 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7595 .destroy = intel_user_framebuffer_destroy,
7596 .create_handle = intel_user_framebuffer_create_handle,
7597 };
7598
7599 int intel_framebuffer_init(struct drm_device *dev,
7600 struct intel_framebuffer *intel_fb,
7601 struct drm_mode_fb_cmd *mode_cmd,
7602 struct drm_i915_gem_object *obj)
7603 {
7604 int ret;
7605
7606 if (obj->tiling_mode == I915_TILING_Y)
7607 return -EINVAL;
7608
7609 if (mode_cmd->pitch & 63)
7610 return -EINVAL;
7611
7612 switch (mode_cmd->bpp) {
7613 case 8:
7614 case 16:
7615 /* Only pre-ILK can handle 5:5:5 */
7616 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7617 return -EINVAL;
7618 break;
7619
7620 case 24:
7621 case 32:
7622 break;
7623 default:
7624 return -EINVAL;
7625 }
7626
7627 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7628 if (ret) {
7629 DRM_ERROR("framebuffer init failed %d\n", ret);
7630 return ret;
7631 }
7632
7633 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7634 intel_fb->obj = obj;
7635 return 0;
7636 }
7637
7638 static struct drm_framebuffer *
7639 intel_user_framebuffer_create(struct drm_device *dev,
7640 struct drm_file *filp,
7641 struct drm_mode_fb_cmd *mode_cmd)
7642 {
7643 struct drm_i915_gem_object *obj;
7644
7645 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7646 if (&obj->base == NULL)
7647 return ERR_PTR(-ENOENT);
7648
7649 return intel_framebuffer_create(dev, mode_cmd, obj);
7650 }
7651
7652 static const struct drm_mode_config_funcs intel_mode_funcs = {
7653 .fb_create = intel_user_framebuffer_create,
7654 .output_poll_changed = intel_fb_output_poll_changed,
7655 };
7656
7657 static struct drm_i915_gem_object *
7658 intel_alloc_context_page(struct drm_device *dev)
7659 {
7660 struct drm_i915_gem_object *ctx;
7661 int ret;
7662
7663 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7664
7665 ctx = i915_gem_alloc_object(dev, 4096);
7666 if (!ctx) {
7667 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7668 return NULL;
7669 }
7670
7671 ret = i915_gem_object_pin(ctx, 4096, true);
7672 if (ret) {
7673 DRM_ERROR("failed to pin power context: %d\n", ret);
7674 goto err_unref;
7675 }
7676
7677 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7678 if (ret) {
7679 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7680 goto err_unpin;
7681 }
7682
7683 return ctx;
7684
7685 err_unpin:
7686 i915_gem_object_unpin(ctx);
7687 err_unref:
7688 drm_gem_object_unreference(&ctx->base);
7689 mutex_unlock(&dev->struct_mutex);
7690 return NULL;
7691 }
7692
7693 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7694 {
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 u16 rgvswctl;
7697
7698 rgvswctl = I915_READ16(MEMSWCTL);
7699 if (rgvswctl & MEMCTL_CMD_STS) {
7700 DRM_DEBUG("gpu busy, RCS change rejected\n");
7701 return false; /* still busy with another command */
7702 }
7703
7704 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7705 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7706 I915_WRITE16(MEMSWCTL, rgvswctl);
7707 POSTING_READ16(MEMSWCTL);
7708
7709 rgvswctl |= MEMCTL_CMD_STS;
7710 I915_WRITE16(MEMSWCTL, rgvswctl);
7711
7712 return true;
7713 }
7714
7715 void ironlake_enable_drps(struct drm_device *dev)
7716 {
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7718 u32 rgvmodectl = I915_READ(MEMMODECTL);
7719 u8 fmax, fmin, fstart, vstart;
7720
7721 /* Enable temp reporting */
7722 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7723 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7724
7725 /* 100ms RC evaluation intervals */
7726 I915_WRITE(RCUPEI, 100000);
7727 I915_WRITE(RCDNEI, 100000);
7728
7729 /* Set max/min thresholds to 90ms and 80ms respectively */
7730 I915_WRITE(RCBMAXAVG, 90000);
7731 I915_WRITE(RCBMINAVG, 80000);
7732
7733 I915_WRITE(MEMIHYST, 1);
7734
7735 /* Set up min, max, and cur for interrupt handling */
7736 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7737 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7738 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7739 MEMMODE_FSTART_SHIFT;
7740
7741 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7742 PXVFREQ_PX_SHIFT;
7743
7744 dev_priv->fmax = fmax; /* IPS callback will increase this */
7745 dev_priv->fstart = fstart;
7746
7747 dev_priv->max_delay = fstart;
7748 dev_priv->min_delay = fmin;
7749 dev_priv->cur_delay = fstart;
7750
7751 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7752 fmax, fmin, fstart);
7753
7754 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7755
7756 /*
7757 * Interrupts will be enabled in ironlake_irq_postinstall
7758 */
7759
7760 I915_WRITE(VIDSTART, vstart);
7761 POSTING_READ(VIDSTART);
7762
7763 rgvmodectl |= MEMMODE_SWMODE_EN;
7764 I915_WRITE(MEMMODECTL, rgvmodectl);
7765
7766 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7767 DRM_ERROR("stuck trying to change perf mode\n");
7768 msleep(1);
7769
7770 ironlake_set_drps(dev, fstart);
7771
7772 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7773 I915_READ(0x112e0);
7774 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7775 dev_priv->last_count2 = I915_READ(0x112f4);
7776 getrawmonotonic(&dev_priv->last_time2);
7777 }
7778
7779 void ironlake_disable_drps(struct drm_device *dev)
7780 {
7781 struct drm_i915_private *dev_priv = dev->dev_private;
7782 u16 rgvswctl = I915_READ16(MEMSWCTL);
7783
7784 /* Ack interrupts, disable EFC interrupt */
7785 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7786 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7787 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7788 I915_WRITE(DEIIR, DE_PCU_EVENT);
7789 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7790
7791 /* Go back to the starting frequency */
7792 ironlake_set_drps(dev, dev_priv->fstart);
7793 msleep(1);
7794 rgvswctl |= MEMCTL_CMD_STS;
7795 I915_WRITE(MEMSWCTL, rgvswctl);
7796 msleep(1);
7797
7798 }
7799
7800 void gen6_set_rps(struct drm_device *dev, u8 val)
7801 {
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 u32 swreq;
7804
7805 swreq = (val & 0x3ff) << 25;
7806 I915_WRITE(GEN6_RPNSWREQ, swreq);
7807 }
7808
7809 void gen6_disable_rps(struct drm_device *dev)
7810 {
7811 struct drm_i915_private *dev_priv = dev->dev_private;
7812
7813 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7814 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7815 I915_WRITE(GEN6_PMIER, 0);
7816 /* Complete PM interrupt masking here doesn't race with the rps work
7817 * item again unmasking PM interrupts because that is using a different
7818 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7819 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7820
7821 spin_lock_irq(&dev_priv->rps_lock);
7822 dev_priv->pm_iir = 0;
7823 spin_unlock_irq(&dev_priv->rps_lock);
7824
7825 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7826 }
7827
7828 static unsigned long intel_pxfreq(u32 vidfreq)
7829 {
7830 unsigned long freq;
7831 int div = (vidfreq & 0x3f0000) >> 16;
7832 int post = (vidfreq & 0x3000) >> 12;
7833 int pre = (vidfreq & 0x7);
7834
7835 if (!pre)
7836 return 0;
7837
7838 freq = ((div * 133333) / ((1<<post) * pre));
7839
7840 return freq;
7841 }
7842
7843 void intel_init_emon(struct drm_device *dev)
7844 {
7845 struct drm_i915_private *dev_priv = dev->dev_private;
7846 u32 lcfuse;
7847 u8 pxw[16];
7848 int i;
7849
7850 /* Disable to program */
7851 I915_WRITE(ECR, 0);
7852 POSTING_READ(ECR);
7853
7854 /* Program energy weights for various events */
7855 I915_WRITE(SDEW, 0x15040d00);
7856 I915_WRITE(CSIEW0, 0x007f0000);
7857 I915_WRITE(CSIEW1, 0x1e220004);
7858 I915_WRITE(CSIEW2, 0x04000004);
7859
7860 for (i = 0; i < 5; i++)
7861 I915_WRITE(PEW + (i * 4), 0);
7862 for (i = 0; i < 3; i++)
7863 I915_WRITE(DEW + (i * 4), 0);
7864
7865 /* Program P-state weights to account for frequency power adjustment */
7866 for (i = 0; i < 16; i++) {
7867 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7868 unsigned long freq = intel_pxfreq(pxvidfreq);
7869 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7870 PXVFREQ_PX_SHIFT;
7871 unsigned long val;
7872
7873 val = vid * vid;
7874 val *= (freq / 1000);
7875 val *= 255;
7876 val /= (127*127*900);
7877 if (val > 0xff)
7878 DRM_ERROR("bad pxval: %ld\n", val);
7879 pxw[i] = val;
7880 }
7881 /* Render standby states get 0 weight */
7882 pxw[14] = 0;
7883 pxw[15] = 0;
7884
7885 for (i = 0; i < 4; i++) {
7886 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7887 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7888 I915_WRITE(PXW + (i * 4), val);
7889 }
7890
7891 /* Adjust magic regs to magic values (more experimental results) */
7892 I915_WRITE(OGW0, 0);
7893 I915_WRITE(OGW1, 0);
7894 I915_WRITE(EG0, 0x00007f00);
7895 I915_WRITE(EG1, 0x0000000e);
7896 I915_WRITE(EG2, 0x000e0000);
7897 I915_WRITE(EG3, 0x68000300);
7898 I915_WRITE(EG4, 0x42000000);
7899 I915_WRITE(EG5, 0x00140031);
7900 I915_WRITE(EG6, 0);
7901 I915_WRITE(EG7, 0);
7902
7903 for (i = 0; i < 8; i++)
7904 I915_WRITE(PXWL + (i * 4), 0);
7905
7906 /* Enable PMON + select events */
7907 I915_WRITE(ECR, 0x80000019);
7908
7909 lcfuse = I915_READ(LCFUSE02);
7910
7911 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7912 }
7913
7914 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7915 {
7916 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7917 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7918 u32 pcu_mbox, rc6_mask = 0;
7919 int cur_freq, min_freq, max_freq;
7920 int i;
7921
7922 /* Here begins a magic sequence of register writes to enable
7923 * auto-downclocking.
7924 *
7925 * Perhaps there might be some value in exposing these to
7926 * userspace...
7927 */
7928 I915_WRITE(GEN6_RC_STATE, 0);
7929 mutex_lock(&dev_priv->dev->struct_mutex);
7930 gen6_gt_force_wake_get(dev_priv);
7931
7932 /* disable the counters and set deterministic thresholds */
7933 I915_WRITE(GEN6_RC_CONTROL, 0);
7934
7935 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7936 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7937 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7938 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7939 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7940
7941 for (i = 0; i < I915_NUM_RINGS; i++)
7942 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7943
7944 I915_WRITE(GEN6_RC_SLEEP, 0);
7945 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7946 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7947 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7948 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7949
7950 if (i915_enable_rc6)
7951 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7952 GEN6_RC_CTL_RC6_ENABLE;
7953
7954 I915_WRITE(GEN6_RC_CONTROL,
7955 rc6_mask |
7956 GEN6_RC_CTL_EI_MODE(1) |
7957 GEN6_RC_CTL_HW_ENABLE);
7958
7959 I915_WRITE(GEN6_RPNSWREQ,
7960 GEN6_FREQUENCY(10) |
7961 GEN6_OFFSET(0) |
7962 GEN6_AGGRESSIVE_TURBO);
7963 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7964 GEN6_FREQUENCY(12));
7965
7966 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7967 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7968 18 << 24 |
7969 6 << 16);
7970 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7971 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7972 I915_WRITE(GEN6_RP_UP_EI, 100000);
7973 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7974 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7975 I915_WRITE(GEN6_RP_CONTROL,
7976 GEN6_RP_MEDIA_TURBO |
7977 GEN6_RP_USE_NORMAL_FREQ |
7978 GEN6_RP_MEDIA_IS_GFX |
7979 GEN6_RP_ENABLE |
7980 GEN6_RP_UP_BUSY_AVG |
7981 GEN6_RP_DOWN_IDLE_CONT);
7982
7983 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7984 500))
7985 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7986
7987 I915_WRITE(GEN6_PCODE_DATA, 0);
7988 I915_WRITE(GEN6_PCODE_MAILBOX,
7989 GEN6_PCODE_READY |
7990 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7991 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7992 500))
7993 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7994
7995 min_freq = (rp_state_cap & 0xff0000) >> 16;
7996 max_freq = rp_state_cap & 0xff;
7997 cur_freq = (gt_perf_status & 0xff00) >> 8;
7998
7999 /* Check for overclock support */
8000 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8001 500))
8002 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8003 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8004 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8005 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8006 500))
8007 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8008 if (pcu_mbox & (1<<31)) { /* OC supported */
8009 max_freq = pcu_mbox & 0xff;
8010 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8011 }
8012
8013 /* In units of 100MHz */
8014 dev_priv->max_delay = max_freq;
8015 dev_priv->min_delay = min_freq;
8016 dev_priv->cur_delay = cur_freq;
8017
8018 /* requires MSI enabled */
8019 I915_WRITE(GEN6_PMIER,
8020 GEN6_PM_MBOX_EVENT |
8021 GEN6_PM_THERMAL_EVENT |
8022 GEN6_PM_RP_DOWN_TIMEOUT |
8023 GEN6_PM_RP_UP_THRESHOLD |
8024 GEN6_PM_RP_DOWN_THRESHOLD |
8025 GEN6_PM_RP_UP_EI_EXPIRED |
8026 GEN6_PM_RP_DOWN_EI_EXPIRED);
8027 spin_lock_irq(&dev_priv->rps_lock);
8028 WARN_ON(dev_priv->pm_iir != 0);
8029 I915_WRITE(GEN6_PMIMR, 0);
8030 spin_unlock_irq(&dev_priv->rps_lock);
8031 /* enable all PM interrupts */
8032 I915_WRITE(GEN6_PMINTRMSK, 0);
8033
8034 gen6_gt_force_wake_put(dev_priv);
8035 mutex_unlock(&dev_priv->dev->struct_mutex);
8036 }
8037
8038 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8039 {
8040 int min_freq = 15;
8041 int gpu_freq, ia_freq, max_ia_freq;
8042 int scaling_factor = 180;
8043
8044 max_ia_freq = cpufreq_quick_get_max(0);
8045 /*
8046 * Default to measured freq if none found, PCU will ensure we don't go
8047 * over
8048 */
8049 if (!max_ia_freq)
8050 max_ia_freq = tsc_khz;
8051
8052 /* Convert from kHz to MHz */
8053 max_ia_freq /= 1000;
8054
8055 mutex_lock(&dev_priv->dev->struct_mutex);
8056
8057 /*
8058 * For each potential GPU frequency, load a ring frequency we'd like
8059 * to use for memory access. We do this by specifying the IA frequency
8060 * the PCU should use as a reference to determine the ring frequency.
8061 */
8062 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8063 gpu_freq--) {
8064 int diff = dev_priv->max_delay - gpu_freq;
8065
8066 /*
8067 * For GPU frequencies less than 750MHz, just use the lowest
8068 * ring freq.
8069 */
8070 if (gpu_freq < min_freq)
8071 ia_freq = 800;
8072 else
8073 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8074 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8075
8076 I915_WRITE(GEN6_PCODE_DATA,
8077 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8078 gpu_freq);
8079 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8080 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8081 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8082 GEN6_PCODE_READY) == 0, 10)) {
8083 DRM_ERROR("pcode write of freq table timed out\n");
8084 continue;
8085 }
8086 }
8087
8088 mutex_unlock(&dev_priv->dev->struct_mutex);
8089 }
8090
8091 static void ironlake_init_clock_gating(struct drm_device *dev)
8092 {
8093 struct drm_i915_private *dev_priv = dev->dev_private;
8094 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8095
8096 /* Required for FBC */
8097 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8098 DPFCRUNIT_CLOCK_GATE_DISABLE |
8099 DPFDUNIT_CLOCK_GATE_DISABLE;
8100 /* Required for CxSR */
8101 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8102
8103 I915_WRITE(PCH_3DCGDIS0,
8104 MARIUNIT_CLOCK_GATE_DISABLE |
8105 SVSMUNIT_CLOCK_GATE_DISABLE);
8106 I915_WRITE(PCH_3DCGDIS1,
8107 VFMUNIT_CLOCK_GATE_DISABLE);
8108
8109 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8110
8111 /*
8112 * According to the spec the following bits should be set in
8113 * order to enable memory self-refresh
8114 * The bit 22/21 of 0x42004
8115 * The bit 5 of 0x42020
8116 * The bit 15 of 0x45000
8117 */
8118 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8119 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8120 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8121 I915_WRITE(ILK_DSPCLK_GATE,
8122 (I915_READ(ILK_DSPCLK_GATE) |
8123 ILK_DPARB_CLK_GATE));
8124 I915_WRITE(DISP_ARB_CTL,
8125 (I915_READ(DISP_ARB_CTL) |
8126 DISP_FBC_WM_DIS));
8127 I915_WRITE(WM3_LP_ILK, 0);
8128 I915_WRITE(WM2_LP_ILK, 0);
8129 I915_WRITE(WM1_LP_ILK, 0);
8130
8131 /*
8132 * Based on the document from hardware guys the following bits
8133 * should be set unconditionally in order to enable FBC.
8134 * The bit 22 of 0x42000
8135 * The bit 22 of 0x42004
8136 * The bit 7,8,9 of 0x42020.
8137 */
8138 if (IS_IRONLAKE_M(dev)) {
8139 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8140 I915_READ(ILK_DISPLAY_CHICKEN1) |
8141 ILK_FBCQ_DIS);
8142 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8143 I915_READ(ILK_DISPLAY_CHICKEN2) |
8144 ILK_DPARB_GATE);
8145 I915_WRITE(ILK_DSPCLK_GATE,
8146 I915_READ(ILK_DSPCLK_GATE) |
8147 ILK_DPFC_DIS1 |
8148 ILK_DPFC_DIS2 |
8149 ILK_CLK_FBC);
8150 }
8151
8152 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8153 I915_READ(ILK_DISPLAY_CHICKEN2) |
8154 ILK_ELPIN_409_SELECT);
8155 I915_WRITE(_3D_CHICKEN2,
8156 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8157 _3D_CHICKEN2_WM_READ_PIPELINED);
8158 }
8159
8160 static void gen6_init_clock_gating(struct drm_device *dev)
8161 {
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 int pipe;
8164 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8165
8166 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8167
8168 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8169 I915_READ(ILK_DISPLAY_CHICKEN2) |
8170 ILK_ELPIN_409_SELECT);
8171
8172 I915_WRITE(WM3_LP_ILK, 0);
8173 I915_WRITE(WM2_LP_ILK, 0);
8174 I915_WRITE(WM1_LP_ILK, 0);
8175
8176 /*
8177 * According to the spec the following bits should be
8178 * set in order to enable memory self-refresh and fbc:
8179 * The bit21 and bit22 of 0x42000
8180 * The bit21 and bit22 of 0x42004
8181 * The bit5 and bit7 of 0x42020
8182 * The bit14 of 0x70180
8183 * The bit14 of 0x71180
8184 */
8185 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8186 I915_READ(ILK_DISPLAY_CHICKEN1) |
8187 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8188 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8189 I915_READ(ILK_DISPLAY_CHICKEN2) |
8190 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8191 I915_WRITE(ILK_DSPCLK_GATE,
8192 I915_READ(ILK_DSPCLK_GATE) |
8193 ILK_DPARB_CLK_GATE |
8194 ILK_DPFD_CLK_GATE);
8195
8196 for_each_pipe(pipe) {
8197 I915_WRITE(DSPCNTR(pipe),
8198 I915_READ(DSPCNTR(pipe)) |
8199 DISPPLANE_TRICKLE_FEED_DISABLE);
8200 intel_flush_display_plane(dev_priv, pipe);
8201 }
8202 }
8203
8204 static void ivybridge_init_clock_gating(struct drm_device *dev)
8205 {
8206 struct drm_i915_private *dev_priv = dev->dev_private;
8207 int pipe;
8208 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8209
8210 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8211
8212 I915_WRITE(WM3_LP_ILK, 0);
8213 I915_WRITE(WM2_LP_ILK, 0);
8214 I915_WRITE(WM1_LP_ILK, 0);
8215
8216 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8217
8218 for_each_pipe(pipe) {
8219 I915_WRITE(DSPCNTR(pipe),
8220 I915_READ(DSPCNTR(pipe)) |
8221 DISPPLANE_TRICKLE_FEED_DISABLE);
8222 intel_flush_display_plane(dev_priv, pipe);
8223 }
8224 }
8225
8226 static void g4x_init_clock_gating(struct drm_device *dev)
8227 {
8228 struct drm_i915_private *dev_priv = dev->dev_private;
8229 uint32_t dspclk_gate;
8230
8231 I915_WRITE(RENCLK_GATE_D1, 0);
8232 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8233 GS_UNIT_CLOCK_GATE_DISABLE |
8234 CL_UNIT_CLOCK_GATE_DISABLE);
8235 I915_WRITE(RAMCLK_GATE_D, 0);
8236 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8237 OVRUNIT_CLOCK_GATE_DISABLE |
8238 OVCUNIT_CLOCK_GATE_DISABLE;
8239 if (IS_GM45(dev))
8240 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8241 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8242 }
8243
8244 static void crestline_init_clock_gating(struct drm_device *dev)
8245 {
8246 struct drm_i915_private *dev_priv = dev->dev_private;
8247
8248 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8249 I915_WRITE(RENCLK_GATE_D2, 0);
8250 I915_WRITE(DSPCLK_GATE_D, 0);
8251 I915_WRITE(RAMCLK_GATE_D, 0);
8252 I915_WRITE16(DEUC, 0);
8253 }
8254
8255 static void broadwater_init_clock_gating(struct drm_device *dev)
8256 {
8257 struct drm_i915_private *dev_priv = dev->dev_private;
8258
8259 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8260 I965_RCC_CLOCK_GATE_DISABLE |
8261 I965_RCPB_CLOCK_GATE_DISABLE |
8262 I965_ISC_CLOCK_GATE_DISABLE |
8263 I965_FBC_CLOCK_GATE_DISABLE);
8264 I915_WRITE(RENCLK_GATE_D2, 0);
8265 }
8266
8267 static void gen3_init_clock_gating(struct drm_device *dev)
8268 {
8269 struct drm_i915_private *dev_priv = dev->dev_private;
8270 u32 dstate = I915_READ(D_STATE);
8271
8272 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8273 DSTATE_DOT_CLOCK_GATING;
8274 I915_WRITE(D_STATE, dstate);
8275 }
8276
8277 static void i85x_init_clock_gating(struct drm_device *dev)
8278 {
8279 struct drm_i915_private *dev_priv = dev->dev_private;
8280
8281 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8282 }
8283
8284 static void i830_init_clock_gating(struct drm_device *dev)
8285 {
8286 struct drm_i915_private *dev_priv = dev->dev_private;
8287
8288 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8289 }
8290
8291 static void ibx_init_clock_gating(struct drm_device *dev)
8292 {
8293 struct drm_i915_private *dev_priv = dev->dev_private;
8294
8295 /*
8296 * On Ibex Peak and Cougar Point, we need to disable clock
8297 * gating for the panel power sequencer or it will fail to
8298 * start up when no ports are active.
8299 */
8300 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8301 }
8302
8303 static void cpt_init_clock_gating(struct drm_device *dev)
8304 {
8305 struct drm_i915_private *dev_priv = dev->dev_private;
8306 int pipe;
8307
8308 /*
8309 * On Ibex Peak and Cougar Point, we need to disable clock
8310 * gating for the panel power sequencer or it will fail to
8311 * start up when no ports are active.
8312 */
8313 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8314 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8315 DPLS_EDP_PPS_FIX_DIS);
8316 /* Without this, mode sets may fail silently on FDI */
8317 for_each_pipe(pipe)
8318 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8319 }
8320
8321 static void ironlake_teardown_rc6(struct drm_device *dev)
8322 {
8323 struct drm_i915_private *dev_priv = dev->dev_private;
8324
8325 if (dev_priv->renderctx) {
8326 i915_gem_object_unpin(dev_priv->renderctx);
8327 drm_gem_object_unreference(&dev_priv->renderctx->base);
8328 dev_priv->renderctx = NULL;
8329 }
8330
8331 if (dev_priv->pwrctx) {
8332 i915_gem_object_unpin(dev_priv->pwrctx);
8333 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8334 dev_priv->pwrctx = NULL;
8335 }
8336 }
8337
8338 static void ironlake_disable_rc6(struct drm_device *dev)
8339 {
8340 struct drm_i915_private *dev_priv = dev->dev_private;
8341
8342 if (I915_READ(PWRCTXA)) {
8343 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8344 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8345 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8346 50);
8347
8348 I915_WRITE(PWRCTXA, 0);
8349 POSTING_READ(PWRCTXA);
8350
8351 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8352 POSTING_READ(RSTDBYCTL);
8353 }
8354
8355 ironlake_teardown_rc6(dev);
8356 }
8357
8358 static int ironlake_setup_rc6(struct drm_device *dev)
8359 {
8360 struct drm_i915_private *dev_priv = dev->dev_private;
8361
8362 if (dev_priv->renderctx == NULL)
8363 dev_priv->renderctx = intel_alloc_context_page(dev);
8364 if (!dev_priv->renderctx)
8365 return -ENOMEM;
8366
8367 if (dev_priv->pwrctx == NULL)
8368 dev_priv->pwrctx = intel_alloc_context_page(dev);
8369 if (!dev_priv->pwrctx) {
8370 ironlake_teardown_rc6(dev);
8371 return -ENOMEM;
8372 }
8373
8374 return 0;
8375 }
8376
8377 void ironlake_enable_rc6(struct drm_device *dev)
8378 {
8379 struct drm_i915_private *dev_priv = dev->dev_private;
8380 int ret;
8381
8382 /* rc6 disabled by default due to repeated reports of hanging during
8383 * boot and resume.
8384 */
8385 if (!i915_enable_rc6)
8386 return;
8387
8388 mutex_lock(&dev->struct_mutex);
8389 ret = ironlake_setup_rc6(dev);
8390 if (ret) {
8391 mutex_unlock(&dev->struct_mutex);
8392 return;
8393 }
8394
8395 /*
8396 * GPU can automatically power down the render unit if given a page
8397 * to save state.
8398 */
8399 ret = BEGIN_LP_RING(6);
8400 if (ret) {
8401 ironlake_teardown_rc6(dev);
8402 mutex_unlock(&dev->struct_mutex);
8403 return;
8404 }
8405
8406 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8407 OUT_RING(MI_SET_CONTEXT);
8408 OUT_RING(dev_priv->renderctx->gtt_offset |
8409 MI_MM_SPACE_GTT |
8410 MI_SAVE_EXT_STATE_EN |
8411 MI_RESTORE_EXT_STATE_EN |
8412 MI_RESTORE_INHIBIT);
8413 OUT_RING(MI_SUSPEND_FLUSH);
8414 OUT_RING(MI_NOOP);
8415 OUT_RING(MI_FLUSH);
8416 ADVANCE_LP_RING();
8417
8418 /*
8419 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8420 * does an implicit flush, combined with MI_FLUSH above, it should be
8421 * safe to assume that renderctx is valid
8422 */
8423 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8424 if (ret) {
8425 DRM_ERROR("failed to enable ironlake power power savings\n");
8426 ironlake_teardown_rc6(dev);
8427 mutex_unlock(&dev->struct_mutex);
8428 return;
8429 }
8430
8431 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8432 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8433 mutex_unlock(&dev->struct_mutex);
8434 }
8435
8436 void intel_init_clock_gating(struct drm_device *dev)
8437 {
8438 struct drm_i915_private *dev_priv = dev->dev_private;
8439
8440 dev_priv->display.init_clock_gating(dev);
8441
8442 if (dev_priv->display.init_pch_clock_gating)
8443 dev_priv->display.init_pch_clock_gating(dev);
8444 }
8445
8446 /* Set up chip specific display functions */
8447 static void intel_init_display(struct drm_device *dev)
8448 {
8449 struct drm_i915_private *dev_priv = dev->dev_private;
8450
8451 /* We always want a DPMS function */
8452 if (HAS_PCH_SPLIT(dev)) {
8453 dev_priv->display.dpms = ironlake_crtc_dpms;
8454 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8455 dev_priv->display.update_plane = ironlake_update_plane;
8456 } else {
8457 dev_priv->display.dpms = i9xx_crtc_dpms;
8458 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8459 dev_priv->display.update_plane = i9xx_update_plane;
8460 }
8461
8462 if (I915_HAS_FBC(dev)) {
8463 if (HAS_PCH_SPLIT(dev)) {
8464 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8465 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8466 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8467 } else if (IS_GM45(dev)) {
8468 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8469 dev_priv->display.enable_fbc = g4x_enable_fbc;
8470 dev_priv->display.disable_fbc = g4x_disable_fbc;
8471 } else if (IS_CRESTLINE(dev)) {
8472 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8473 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8474 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8475 }
8476 /* 855GM needs testing */
8477 }
8478
8479 /* Returns the core display clock speed */
8480 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8481 dev_priv->display.get_display_clock_speed =
8482 i945_get_display_clock_speed;
8483 else if (IS_I915G(dev))
8484 dev_priv->display.get_display_clock_speed =
8485 i915_get_display_clock_speed;
8486 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8487 dev_priv->display.get_display_clock_speed =
8488 i9xx_misc_get_display_clock_speed;
8489 else if (IS_I915GM(dev))
8490 dev_priv->display.get_display_clock_speed =
8491 i915gm_get_display_clock_speed;
8492 else if (IS_I865G(dev))
8493 dev_priv->display.get_display_clock_speed =
8494 i865_get_display_clock_speed;
8495 else if (IS_I85X(dev))
8496 dev_priv->display.get_display_clock_speed =
8497 i855_get_display_clock_speed;
8498 else /* 852, 830 */
8499 dev_priv->display.get_display_clock_speed =
8500 i830_get_display_clock_speed;
8501
8502 /* For FIFO watermark updates */
8503 if (HAS_PCH_SPLIT(dev)) {
8504 if (HAS_PCH_IBX(dev))
8505 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8506 else if (HAS_PCH_CPT(dev))
8507 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8508
8509 if (IS_GEN5(dev)) {
8510 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8511 dev_priv->display.update_wm = ironlake_update_wm;
8512 else {
8513 DRM_DEBUG_KMS("Failed to get proper latency. "
8514 "Disable CxSR\n");
8515 dev_priv->display.update_wm = NULL;
8516 }
8517 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8518 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8519 dev_priv->display.write_eld = ironlake_write_eld;
8520 } else if (IS_GEN6(dev)) {
8521 if (SNB_READ_WM0_LATENCY()) {
8522 dev_priv->display.update_wm = sandybridge_update_wm;
8523 } else {
8524 DRM_DEBUG_KMS("Failed to read display plane latency. "
8525 "Disable CxSR\n");
8526 dev_priv->display.update_wm = NULL;
8527 }
8528 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8529 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8530 dev_priv->display.write_eld = ironlake_write_eld;
8531 } else if (IS_IVYBRIDGE(dev)) {
8532 /* FIXME: detect B0+ stepping and use auto training */
8533 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8534 if (SNB_READ_WM0_LATENCY()) {
8535 dev_priv->display.update_wm = sandybridge_update_wm;
8536 } else {
8537 DRM_DEBUG_KMS("Failed to read display plane latency. "
8538 "Disable CxSR\n");
8539 dev_priv->display.update_wm = NULL;
8540 }
8541 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8542 dev_priv->display.write_eld = ironlake_write_eld;
8543 } else
8544 dev_priv->display.update_wm = NULL;
8545 } else if (IS_PINEVIEW(dev)) {
8546 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8547 dev_priv->is_ddr3,
8548 dev_priv->fsb_freq,
8549 dev_priv->mem_freq)) {
8550 DRM_INFO("failed to find known CxSR latency "
8551 "(found ddr%s fsb freq %d, mem freq %d), "
8552 "disabling CxSR\n",
8553 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8554 dev_priv->fsb_freq, dev_priv->mem_freq);
8555 /* Disable CxSR and never update its watermark again */
8556 pineview_disable_cxsr(dev);
8557 dev_priv->display.update_wm = NULL;
8558 } else
8559 dev_priv->display.update_wm = pineview_update_wm;
8560 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8561 } else if (IS_G4X(dev)) {
8562 dev_priv->display.write_eld = g4x_write_eld;
8563 dev_priv->display.update_wm = g4x_update_wm;
8564 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8565 } else if (IS_GEN4(dev)) {
8566 dev_priv->display.update_wm = i965_update_wm;
8567 if (IS_CRESTLINE(dev))
8568 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8569 else if (IS_BROADWATER(dev))
8570 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8571 } else if (IS_GEN3(dev)) {
8572 dev_priv->display.update_wm = i9xx_update_wm;
8573 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8574 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8575 } else if (IS_I865G(dev)) {
8576 dev_priv->display.update_wm = i830_update_wm;
8577 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8578 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8579 } else if (IS_I85X(dev)) {
8580 dev_priv->display.update_wm = i9xx_update_wm;
8581 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8582 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8583 } else {
8584 dev_priv->display.update_wm = i830_update_wm;
8585 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8586 if (IS_845G(dev))
8587 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8588 else
8589 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8590 }
8591
8592 /* Default just returns -ENODEV to indicate unsupported */
8593 dev_priv->display.queue_flip = intel_default_queue_flip;
8594
8595 switch (INTEL_INFO(dev)->gen) {
8596 case 2:
8597 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8598 break;
8599
8600 case 3:
8601 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8602 break;
8603
8604 case 4:
8605 case 5:
8606 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8607 break;
8608
8609 case 6:
8610 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8611 break;
8612 case 7:
8613 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8614 break;
8615 }
8616 }
8617
8618 /*
8619 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8620 * resume, or other times. This quirk makes sure that's the case for
8621 * affected systems.
8622 */
8623 static void quirk_pipea_force(struct drm_device *dev)
8624 {
8625 struct drm_i915_private *dev_priv = dev->dev_private;
8626
8627 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8628 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8629 }
8630
8631 /*
8632 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8633 */
8634 static void quirk_ssc_force_disable(struct drm_device *dev)
8635 {
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8638 }
8639
8640 struct intel_quirk {
8641 int device;
8642 int subsystem_vendor;
8643 int subsystem_device;
8644 void (*hook)(struct drm_device *dev);
8645 };
8646
8647 struct intel_quirk intel_quirks[] = {
8648 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8649 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8650 /* HP Mini needs pipe A force quirk (LP: #322104) */
8651 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8652
8653 /* Thinkpad R31 needs pipe A force quirk */
8654 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8655 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8656 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8657
8658 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8659 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8660 /* ThinkPad X40 needs pipe A force quirk */
8661
8662 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8663 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8664
8665 /* 855 & before need to leave pipe A & dpll A up */
8666 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8667 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8668
8669 /* Lenovo U160 cannot use SSC on LVDS */
8670 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8671
8672 /* Sony Vaio Y cannot use SSC on LVDS */
8673 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8674 };
8675
8676 static void intel_init_quirks(struct drm_device *dev)
8677 {
8678 struct pci_dev *d = dev->pdev;
8679 int i;
8680
8681 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8682 struct intel_quirk *q = &intel_quirks[i];
8683
8684 if (d->device == q->device &&
8685 (d->subsystem_vendor == q->subsystem_vendor ||
8686 q->subsystem_vendor == PCI_ANY_ID) &&
8687 (d->subsystem_device == q->subsystem_device ||
8688 q->subsystem_device == PCI_ANY_ID))
8689 q->hook(dev);
8690 }
8691 }
8692
8693 /* Disable the VGA plane that we never use */
8694 static void i915_disable_vga(struct drm_device *dev)
8695 {
8696 struct drm_i915_private *dev_priv = dev->dev_private;
8697 u8 sr1;
8698 u32 vga_reg;
8699
8700 if (HAS_PCH_SPLIT(dev))
8701 vga_reg = CPU_VGACNTRL;
8702 else
8703 vga_reg = VGACNTRL;
8704
8705 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8706 outb(1, VGA_SR_INDEX);
8707 sr1 = inb(VGA_SR_DATA);
8708 outb(sr1 | 1<<5, VGA_SR_DATA);
8709 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8710 udelay(300);
8711
8712 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8713 POSTING_READ(vga_reg);
8714 }
8715
8716 void intel_modeset_init(struct drm_device *dev)
8717 {
8718 struct drm_i915_private *dev_priv = dev->dev_private;
8719 int i;
8720
8721 drm_mode_config_init(dev);
8722
8723 dev->mode_config.min_width = 0;
8724 dev->mode_config.min_height = 0;
8725
8726 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8727
8728 intel_init_quirks(dev);
8729
8730 intel_init_display(dev);
8731
8732 if (IS_GEN2(dev)) {
8733 dev->mode_config.max_width = 2048;
8734 dev->mode_config.max_height = 2048;
8735 } else if (IS_GEN3(dev)) {
8736 dev->mode_config.max_width = 4096;
8737 dev->mode_config.max_height = 4096;
8738 } else {
8739 dev->mode_config.max_width = 8192;
8740 dev->mode_config.max_height = 8192;
8741 }
8742 dev->mode_config.fb_base = dev->agp->base;
8743
8744 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8745 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8746
8747 for (i = 0; i < dev_priv->num_pipe; i++) {
8748 intel_crtc_init(dev, i);
8749 }
8750
8751 /* Just disable it once at startup */
8752 i915_disable_vga(dev);
8753 intel_setup_outputs(dev);
8754
8755 intel_init_clock_gating(dev);
8756
8757 if (IS_IRONLAKE_M(dev)) {
8758 ironlake_enable_drps(dev);
8759 intel_init_emon(dev);
8760 }
8761
8762 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8763 gen6_enable_rps(dev_priv);
8764 gen6_update_ring_freq(dev_priv);
8765 }
8766
8767 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8768 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8769 (unsigned long)dev);
8770 }
8771
8772 void intel_modeset_gem_init(struct drm_device *dev)
8773 {
8774 if (IS_IRONLAKE_M(dev))
8775 ironlake_enable_rc6(dev);
8776
8777 intel_setup_overlay(dev);
8778 }
8779
8780 void intel_modeset_cleanup(struct drm_device *dev)
8781 {
8782 struct drm_i915_private *dev_priv = dev->dev_private;
8783 struct drm_crtc *crtc;
8784 struct intel_crtc *intel_crtc;
8785
8786 drm_kms_helper_poll_fini(dev);
8787 mutex_lock(&dev->struct_mutex);
8788
8789 intel_unregister_dsm_handler();
8790
8791
8792 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8793 /* Skip inactive CRTCs */
8794 if (!crtc->fb)
8795 continue;
8796
8797 intel_crtc = to_intel_crtc(crtc);
8798 intel_increase_pllclock(crtc);
8799 }
8800
8801 intel_disable_fbc(dev);
8802
8803 if (IS_IRONLAKE_M(dev))
8804 ironlake_disable_drps(dev);
8805 if (IS_GEN6(dev) || IS_GEN7(dev))
8806 gen6_disable_rps(dev);
8807
8808 if (IS_IRONLAKE_M(dev))
8809 ironlake_disable_rc6(dev);
8810
8811 mutex_unlock(&dev->struct_mutex);
8812
8813 /* Disable the irq before mode object teardown, for the irq might
8814 * enqueue unpin/hotplug work. */
8815 drm_irq_uninstall(dev);
8816 cancel_work_sync(&dev_priv->hotplug_work);
8817 cancel_work_sync(&dev_priv->rps_work);
8818
8819 /* flush any delayed tasks or pending work */
8820 flush_scheduled_work();
8821
8822 /* Shut off idle work before the crtcs get freed. */
8823 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8824 intel_crtc = to_intel_crtc(crtc);
8825 del_timer_sync(&intel_crtc->idle_timer);
8826 }
8827 del_timer_sync(&dev_priv->idle_timer);
8828 cancel_work_sync(&dev_priv->idle_work);
8829
8830 drm_mode_config_cleanup(dev);
8831 }
8832
8833 /*
8834 * Return which encoder is currently attached for connector.
8835 */
8836 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8837 {
8838 return &intel_attached_encoder(connector)->base;
8839 }
8840
8841 void intel_connector_attach_encoder(struct intel_connector *connector,
8842 struct intel_encoder *encoder)
8843 {
8844 connector->encoder = encoder;
8845 drm_mode_connector_attach_encoder(&connector->base,
8846 &encoder->base);
8847 }
8848
8849 /*
8850 * set vga decode state - true == enable VGA decode
8851 */
8852 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8853 {
8854 struct drm_i915_private *dev_priv = dev->dev_private;
8855 u16 gmch_ctrl;
8856
8857 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8858 if (state)
8859 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8860 else
8861 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8862 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8863 return 0;
8864 }
8865
8866 #ifdef CONFIG_DEBUG_FS
8867 #include <linux/seq_file.h>
8868
8869 struct intel_display_error_state {
8870 struct intel_cursor_error_state {
8871 u32 control;
8872 u32 position;
8873 u32 base;
8874 u32 size;
8875 } cursor[2];
8876
8877 struct intel_pipe_error_state {
8878 u32 conf;
8879 u32 source;
8880
8881 u32 htotal;
8882 u32 hblank;
8883 u32 hsync;
8884 u32 vtotal;
8885 u32 vblank;
8886 u32 vsync;
8887 } pipe[2];
8888
8889 struct intel_plane_error_state {
8890 u32 control;
8891 u32 stride;
8892 u32 size;
8893 u32 pos;
8894 u32 addr;
8895 u32 surface;
8896 u32 tile_offset;
8897 } plane[2];
8898 };
8899
8900 struct intel_display_error_state *
8901 intel_display_capture_error_state(struct drm_device *dev)
8902 {
8903 drm_i915_private_t *dev_priv = dev->dev_private;
8904 struct intel_display_error_state *error;
8905 int i;
8906
8907 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8908 if (error == NULL)
8909 return NULL;
8910
8911 for (i = 0; i < 2; i++) {
8912 error->cursor[i].control = I915_READ(CURCNTR(i));
8913 error->cursor[i].position = I915_READ(CURPOS(i));
8914 error->cursor[i].base = I915_READ(CURBASE(i));
8915
8916 error->plane[i].control = I915_READ(DSPCNTR(i));
8917 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8918 error->plane[i].size = I915_READ(DSPSIZE(i));
8919 error->plane[i].pos = I915_READ(DSPPOS(i));
8920 error->plane[i].addr = I915_READ(DSPADDR(i));
8921 if (INTEL_INFO(dev)->gen >= 4) {
8922 error->plane[i].surface = I915_READ(DSPSURF(i));
8923 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8924 }
8925
8926 error->pipe[i].conf = I915_READ(PIPECONF(i));
8927 error->pipe[i].source = I915_READ(PIPESRC(i));
8928 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8929 error->pipe[i].hblank = I915_READ(HBLANK(i));
8930 error->pipe[i].hsync = I915_READ(HSYNC(i));
8931 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8932 error->pipe[i].vblank = I915_READ(VBLANK(i));
8933 error->pipe[i].vsync = I915_READ(VSYNC(i));
8934 }
8935
8936 return error;
8937 }
8938
8939 void
8940 intel_display_print_error_state(struct seq_file *m,
8941 struct drm_device *dev,
8942 struct intel_display_error_state *error)
8943 {
8944 int i;
8945
8946 for (i = 0; i < 2; i++) {
8947 seq_printf(m, "Pipe [%d]:\n", i);
8948 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8949 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8950 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8951 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8952 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8953 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8954 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8955 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8956
8957 seq_printf(m, "Plane [%d]:\n", i);
8958 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8959 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8960 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8961 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8962 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8963 if (INTEL_INFO(dev)->gen >= 4) {
8964 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8965 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8966 }
8967
8968 seq_printf(m, "Cursor [%d]:\n", i);
8969 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8970 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8971 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8972 }
8973 }
8974 #endif
Linux kernel - Deliverables
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