2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
51 DRM_FORMAT_XRGB8888, \
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2
[] = {
56 COMMON_PRIMARY_FORMATS
,
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4
[] = {
63 COMMON_PRIMARY_FORMATS
, \
66 DRM_FORMAT_XRGB2101010
,
67 DRM_FORMAT_ARGB2101010
,
68 DRM_FORMAT_XBGR2101010
,
69 DRM_FORMAT_ABGR2101010
,
73 static const uint32_t intel_cursor_formats
[] = {
77 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
79 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
80 struct intel_crtc_state
*pipe_config
);
81 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
82 struct intel_crtc_state
*pipe_config
);
84 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
85 int x
, int y
, struct drm_framebuffer
*old_fb
);
86 static int intel_framebuffer_init(struct drm_device
*dev
,
87 struct intel_framebuffer
*ifb
,
88 struct drm_mode_fb_cmd2
*mode_cmd
,
89 struct drm_i915_gem_object
*obj
);
90 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
91 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
93 struct intel_link_m_n
*m_n
,
94 struct intel_link_m_n
*m2_n2
);
95 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
96 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
97 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
98 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
99 const struct intel_crtc_state
*pipe_config
);
100 static void chv_prepare_pll(struct intel_crtc
*crtc
,
101 const struct intel_crtc_state
*pipe_config
);
102 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
103 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6480000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
416 struct drm_device
*dev
= crtc
->base
.dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
420 if (encoder
->type
== type
)
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
434 struct drm_device
*dev
= crtc
->base
.dev
;
435 struct intel_encoder
*encoder
;
437 for_each_intel_encoder(dev
, encoder
)
438 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
444 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
447 struct drm_device
*dev
= crtc
->base
.dev
;
448 const intel_limit_t
*limit
;
450 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
451 if (intel_is_dual_link_lvds(dev
)) {
452 if (refclk
== 100000)
453 limit
= &intel_limits_ironlake_dual_lvds_100m
;
455 limit
= &intel_limits_ironlake_dual_lvds
;
457 if (refclk
== 100000)
458 limit
= &intel_limits_ironlake_single_lvds_100m
;
460 limit
= &intel_limits_ironlake_single_lvds
;
463 limit
= &intel_limits_ironlake_dac
;
468 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
470 struct drm_device
*dev
= crtc
->base
.dev
;
471 const intel_limit_t
*limit
;
473 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
474 if (intel_is_dual_link_lvds(dev
))
475 limit
= &intel_limits_g4x_dual_channel_lvds
;
477 limit
= &intel_limits_g4x_single_channel_lvds
;
478 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
479 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
480 limit
= &intel_limits_g4x_hdmi
;
481 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
482 limit
= &intel_limits_g4x_sdvo
;
483 } else /* The option is for other outputs */
484 limit
= &intel_limits_i9xx_sdvo
;
489 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
491 struct drm_device
*dev
= crtc
->base
.dev
;
492 const intel_limit_t
*limit
;
494 if (HAS_PCH_SPLIT(dev
))
495 limit
= intel_ironlake_limit(crtc
, refclk
);
496 else if (IS_G4X(dev
)) {
497 limit
= intel_g4x_limit(crtc
);
498 } else if (IS_PINEVIEW(dev
)) {
499 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
500 limit
= &intel_limits_pineview_lvds
;
502 limit
= &intel_limits_pineview_sdvo
;
503 } else if (IS_CHERRYVIEW(dev
)) {
504 limit
= &intel_limits_chv
;
505 } else if (IS_VALLEYVIEW(dev
)) {
506 limit
= &intel_limits_vlv
;
507 } else if (!IS_GEN2(dev
)) {
508 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
509 limit
= &intel_limits_i9xx_lvds
;
511 limit
= &intel_limits_i9xx_sdvo
;
513 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
514 limit
= &intel_limits_i8xx_lvds
;
515 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
516 limit
= &intel_limits_i8xx_dvo
;
518 limit
= &intel_limits_i8xx_dac
;
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
526 clock
->m
= clock
->m2
+ 2;
527 clock
->p
= clock
->p1
* clock
->p2
;
528 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
530 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
531 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
534 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
536 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
539 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
541 clock
->m
= i9xx_dpll_compute_m(clock
);
542 clock
->p
= clock
->p1
* clock
->p2
;
543 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
545 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
546 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
549 static void chv_clock(int refclk
, intel_clock_t
*clock
)
551 clock
->m
= clock
->m1
* clock
->m2
;
552 clock
->p
= clock
->p1
* clock
->p2
;
553 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
555 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
557 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
566 static bool intel_PLL_is_valid(struct drm_device
*dev
,
567 const intel_limit_t
*limit
,
568 const intel_clock_t
*clock
)
570 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
571 INTELPllInvalid("n out of range\n");
572 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
577 INTELPllInvalid("m1 out of range\n");
579 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
580 if (clock
->m1
<= clock
->m2
)
581 INTELPllInvalid("m1 <= m2\n");
583 if (!IS_VALLEYVIEW(dev
)) {
584 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
585 INTELPllInvalid("p out of range\n");
586 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
587 INTELPllInvalid("m out of range\n");
590 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
595 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
596 INTELPllInvalid("dot out of range\n");
602 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
603 int target
, int refclk
, intel_clock_t
*match_clock
,
604 intel_clock_t
*best_clock
)
606 struct drm_device
*dev
= crtc
->base
.dev
;
610 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
616 if (intel_is_dual_link_lvds(dev
))
617 clock
.p2
= limit
->p2
.p2_fast
;
619 clock
.p2
= limit
->p2
.p2_slow
;
621 if (target
< limit
->p2
.dot_limit
)
622 clock
.p2
= limit
->p2
.p2_slow
;
624 clock
.p2
= limit
->p2
.p2_fast
;
627 memset(best_clock
, 0, sizeof(*best_clock
));
629 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
631 for (clock
.m2
= limit
->m2
.min
;
632 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
633 if (clock
.m2
>= clock
.m1
)
635 for (clock
.n
= limit
->n
.min
;
636 clock
.n
<= limit
->n
.max
; clock
.n
++) {
637 for (clock
.p1
= limit
->p1
.min
;
638 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
641 i9xx_clock(refclk
, &clock
);
642 if (!intel_PLL_is_valid(dev
, limit
,
646 clock
.p
!= match_clock
->p
)
649 this_err
= abs(clock
.dot
- target
);
650 if (this_err
< err
) {
659 return (err
!= target
);
663 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
664 int target
, int refclk
, intel_clock_t
*match_clock
,
665 intel_clock_t
*best_clock
)
667 struct drm_device
*dev
= crtc
->base
.dev
;
671 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
677 if (intel_is_dual_link_lvds(dev
))
678 clock
.p2
= limit
->p2
.p2_fast
;
680 clock
.p2
= limit
->p2
.p2_slow
;
682 if (target
< limit
->p2
.dot_limit
)
683 clock
.p2
= limit
->p2
.p2_slow
;
685 clock
.p2
= limit
->p2
.p2_fast
;
688 memset(best_clock
, 0, sizeof(*best_clock
));
690 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
692 for (clock
.m2
= limit
->m2
.min
;
693 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
694 for (clock
.n
= limit
->n
.min
;
695 clock
.n
<= limit
->n
.max
; clock
.n
++) {
696 for (clock
.p1
= limit
->p1
.min
;
697 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
700 pineview_clock(refclk
, &clock
);
701 if (!intel_PLL_is_valid(dev
, limit
,
705 clock
.p
!= match_clock
->p
)
708 this_err
= abs(clock
.dot
- target
);
709 if (this_err
< err
) {
718 return (err
!= target
);
722 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
723 int target
, int refclk
, intel_clock_t
*match_clock
,
724 intel_clock_t
*best_clock
)
726 struct drm_device
*dev
= crtc
->base
.dev
;
730 /* approximately equals target * 0.00585 */
731 int err_most
= (target
>> 8) + (target
>> 9);
734 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
735 if (intel_is_dual_link_lvds(dev
))
736 clock
.p2
= limit
->p2
.p2_fast
;
738 clock
.p2
= limit
->p2
.p2_slow
;
740 if (target
< limit
->p2
.dot_limit
)
741 clock
.p2
= limit
->p2
.p2_slow
;
743 clock
.p2
= limit
->p2
.p2_fast
;
746 memset(best_clock
, 0, sizeof(*best_clock
));
747 max_n
= limit
->n
.max
;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock
.m1
= limit
->m1
.max
;
752 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
753 for (clock
.m2
= limit
->m2
.max
;
754 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
755 for (clock
.p1
= limit
->p1
.max
;
756 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
759 i9xx_clock(refclk
, &clock
);
760 if (!intel_PLL_is_valid(dev
, limit
,
764 this_err
= abs(clock
.dot
- target
);
765 if (this_err
< err_most
) {
779 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
780 int target
, int refclk
, intel_clock_t
*match_clock
,
781 intel_clock_t
*best_clock
)
783 struct drm_device
*dev
= crtc
->base
.dev
;
785 unsigned int bestppm
= 1000000;
786 /* min update 19.2 MHz */
787 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
790 target
*= 5; /* fast clock */
792 memset(best_clock
, 0, sizeof(*best_clock
));
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
796 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
797 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
798 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
799 clock
.p
= clock
.p1
* clock
.p2
;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
802 unsigned int ppm
, diff
;
804 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
807 vlv_clock(refclk
, &clock
);
809 if (!intel_PLL_is_valid(dev
, limit
,
813 diff
= abs(clock
.dot
- target
);
814 ppm
= div_u64(1000000ULL * diff
, target
);
816 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
822 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
836 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
837 int target
, int refclk
, intel_clock_t
*match_clock
,
838 intel_clock_t
*best_clock
)
840 struct drm_device
*dev
= crtc
->base
.dev
;
845 memset(best_clock
, 0, sizeof(*best_clock
));
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
852 clock
.n
= 1, clock
.m1
= 2;
853 target
*= 5; /* fast clock */
855 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
856 for (clock
.p2
= limit
->p2
.p2_fast
;
857 clock
.p2
>= limit
->p2
.p2_slow
;
858 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
860 clock
.p
= clock
.p1
* clock
.p2
;
862 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
863 clock
.n
) << 22, refclk
* clock
.m1
);
865 if (m2
> INT_MAX
/clock
.m1
)
870 chv_clock(refclk
, &clock
);
872 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
875 /* based on hardware requirement, prefer bigger p
877 if (clock
.p
> best_clock
->p
) {
887 bool intel_crtc_active(struct drm_crtc
*crtc
)
889 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
900 return intel_crtc
->active
&& crtc
->primary
->fb
&&
901 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
904 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
907 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
908 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
910 return intel_crtc
->config
->cpu_transcoder
;
913 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
916 u32 reg
= PIPEDSL(pipe
);
921 line_mask
= DSL_LINEMASK_GEN2
;
923 line_mask
= DSL_LINEMASK_GEN3
;
925 line1
= I915_READ(reg
) & line_mask
;
927 line2
= I915_READ(reg
) & line_mask
;
929 return line1
== line2
;
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
941 * wait for the pipe register state bit to turn off
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
948 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
950 struct drm_device
*dev
= crtc
->base
.dev
;
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
953 enum pipe pipe
= crtc
->pipe
;
955 if (INTEL_INFO(dev
)->gen
>= 4) {
956 int reg
= PIPECONF(cpu_transcoder
);
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
961 WARN(1, "pipe_off wait timed out\n");
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
965 WARN(1, "pipe_off wait timed out\n");
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
974 * Returns true if @port is connected, false otherwise.
976 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
977 struct intel_digital_port
*port
)
981 if (HAS_PCH_IBX(dev_priv
->dev
)) {
982 switch (port
->port
) {
984 bit
= SDE_PORTB_HOTPLUG
;
987 bit
= SDE_PORTC_HOTPLUG
;
990 bit
= SDE_PORTD_HOTPLUG
;
996 switch (port
->port
) {
998 bit
= SDE_PORTB_HOTPLUG_CPT
;
1001 bit
= SDE_PORTC_HOTPLUG_CPT
;
1004 bit
= SDE_PORTD_HOTPLUG_CPT
;
1011 return I915_READ(SDEISR
) & bit
;
1014 static const char *state_string(bool enabled
)
1016 return enabled
? "on" : "off";
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private
*dev_priv
,
1021 enum pipe pipe
, bool state
)
1028 val
= I915_READ(reg
);
1029 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1030 I915_STATE_WARN(cur_state
!= state
,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state
), state_string(cur_state
));
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1041 mutex_lock(&dev_priv
->dpio_lock
);
1042 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1043 mutex_unlock(&dev_priv
->dpio_lock
);
1045 cur_state
= val
& DSI_PLL_VCO_EN
;
1046 I915_STATE_WARN(cur_state
!= state
,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state
), state_string(cur_state
));
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1053 struct intel_shared_dpll
*
1054 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1056 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1058 if (crtc
->config
->shared_dpll
< 0)
1061 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1065 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1066 struct intel_shared_dpll
*pll
,
1070 struct intel_dpll_hw_state hw_state
;
1073 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1076 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1077 I915_STATE_WARN(cur_state
!= state
,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll
->name
, state_string(state
), state_string(cur_state
));
1082 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1083 enum pipe pipe
, bool state
)
1088 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1091 if (HAS_DDI(dev_priv
->dev
)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1094 val
= I915_READ(reg
);
1095 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1097 reg
= FDI_TX_CTL(pipe
);
1098 val
= I915_READ(reg
);
1099 cur_state
= !!(val
& FDI_TX_ENABLE
);
1101 I915_STATE_WARN(cur_state
!= state
,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state
), state_string(cur_state
));
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1108 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1109 enum pipe pipe
, bool state
)
1115 reg
= FDI_RX_CTL(pipe
);
1116 val
= I915_READ(reg
);
1117 cur_state
= !!(val
& FDI_RX_ENABLE
);
1118 I915_STATE_WARN(cur_state
!= state
,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state
), state_string(cur_state
));
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv
->dev
))
1139 reg
= FDI_TX_CTL(pipe
);
1140 val
= I915_READ(reg
);
1141 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1144 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1154 I915_STATE_WARN(cur_state
!= state
,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1159 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1162 struct drm_device
*dev
= dev_priv
->dev
;
1165 enum pipe panel_pipe
= PIPE_A
;
1168 if (WARN_ON(HAS_DDI(dev
)))
1171 if (HAS_PCH_SPLIT(dev
)) {
1174 pp_reg
= PCH_PP_CONTROL
;
1175 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1177 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1178 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1179 panel_pipe
= PIPE_B
;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev
)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1186 pp_reg
= PP_CONTROL
;
1187 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1188 panel_pipe
= PIPE_B
;
1191 val
= I915_READ(pp_reg
);
1192 if (!(val
& PANEL_POWER_ON
) ||
1193 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1196 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1197 "panel assertion failure, pipe %c regs locked\n",
1201 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1202 enum pipe pipe
, bool state
)
1204 struct drm_device
*dev
= dev_priv
->dev
;
1207 if (IS_845G(dev
) || IS_I865G(dev
))
1208 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1210 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1212 I915_STATE_WARN(cur_state
!= state
,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1219 void assert_pipe(struct drm_i915_private
*dev_priv
,
1220 enum pipe pipe
, bool state
)
1225 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1230 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1233 if (!intel_display_power_is_enabled(dev_priv
,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1237 reg
= PIPECONF(cpu_transcoder
);
1238 val
= I915_READ(reg
);
1239 cur_state
= !!(val
& PIPECONF_ENABLE
);
1242 I915_STATE_WARN(cur_state
!= state
,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1247 static void assert_plane(struct drm_i915_private
*dev_priv
,
1248 enum plane plane
, bool state
)
1254 reg
= DSPCNTR(plane
);
1255 val
= I915_READ(reg
);
1256 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1257 I915_STATE_WARN(cur_state
!= state
,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane
), state_string(state
), state_string(cur_state
));
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1265 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1268 struct drm_device
*dev
= dev_priv
->dev
;
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev
)->gen
>= 4) {
1275 reg
= DSPCNTR(pipe
);
1276 val
= I915_READ(reg
);
1277 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1278 "plane %c assertion failure, should be disabled but not\n",
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv
, i
) {
1286 val
= I915_READ(reg
);
1287 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1288 DISPPLANE_SEL_PIPE_SHIFT
;
1289 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i
), pipe_name(pipe
));
1295 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1298 struct drm_device
*dev
= dev_priv
->dev
;
1302 if (INTEL_INFO(dev
)->gen
>= 9) {
1303 for_each_sprite(dev_priv
, pipe
, sprite
) {
1304 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1305 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite
, pipe_name(pipe
));
1309 } else if (IS_VALLEYVIEW(dev
)) {
1310 for_each_sprite(dev_priv
, pipe
, sprite
) {
1311 reg
= SPCNTR(pipe
, sprite
);
1312 val
= I915_READ(reg
);
1313 I915_STATE_WARN(val
& SP_ENABLE
,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1317 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1319 val
= I915_READ(reg
);
1320 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe
), pipe_name(pipe
));
1323 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1324 reg
= DVSCNTR(pipe
);
1325 val
= I915_READ(reg
);
1326 I915_STATE_WARN(val
& DVS_ENABLE
,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe
), pipe_name(pipe
));
1332 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1335 drm_crtc_vblank_put(crtc
);
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1345 val
= I915_READ(PCH_DREF_CONTROL
);
1346 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1347 DREF_SUPERSPREAD_SOURCE_MASK
));
1348 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1358 reg
= PCH_TRANSCONF(pipe
);
1359 val
= I915_READ(reg
);
1360 enabled
= !!(val
& TRANS_ENABLE
);
1361 I915_STATE_WARN(enabled
,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1367 enum pipe pipe
, u32 port_sel
, u32 val
)
1369 if ((val
& DP_PORT_EN
) == 0)
1372 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1373 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1374 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1375 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1377 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1378 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1381 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1387 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1388 enum pipe pipe
, u32 val
)
1390 if ((val
& SDVO_ENABLE
) == 0)
1393 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1394 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1396 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1397 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1400 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1406 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1407 enum pipe pipe
, u32 val
)
1409 if ((val
& LVDS_PORT_EN
) == 0)
1412 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1413 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1416 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1422 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1423 enum pipe pipe
, u32 val
)
1425 if ((val
& ADPA_DAC_ENABLE
) == 0)
1427 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1428 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1431 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1437 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1438 enum pipe pipe
, int reg
, u32 port_sel
)
1440 u32 val
= I915_READ(reg
);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg
, pipe_name(pipe
));
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1446 && (val
& DP_PIPEB_SELECT
),
1447 "IBX PCH dp port still using transcoder B\n");
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1451 enum pipe pipe
, int reg
)
1453 u32 val
= I915_READ(reg
);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg
, pipe_name(pipe
));
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1459 && (val
& SDVO_PIPE_B_SELECT
),
1460 "IBX PCH hdmi port still using transcoder B\n");
1463 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1469 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1470 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1471 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1474 val
= I915_READ(reg
);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 val
= I915_READ(reg
);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1486 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1487 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1490 static void intel_init_dpio(struct drm_device
*dev
)
1492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1494 if (!IS_VALLEYVIEW(dev
))
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1502 if (IS_CHERRYVIEW(dev
)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1510 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1511 const struct intel_crtc_state
*pipe_config
)
1513 struct drm_device
*dev
= crtc
->base
.dev
;
1514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1515 int reg
= DPLL(crtc
->pipe
);
1516 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1518 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv
->dev
))
1525 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1527 I915_WRITE(reg
, dpll
);
1531 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1534 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1535 POSTING_READ(DPLL_MD(crtc
->pipe
));
1537 /* We do this three times for luck */
1538 I915_WRITE(reg
, dpll
);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg
, dpll
);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg
, dpll
);
1546 udelay(150); /* wait for warmup */
1549 static void chv_enable_pll(struct intel_crtc
*crtc
,
1550 const struct intel_crtc_state
*pipe_config
)
1552 struct drm_device
*dev
= crtc
->base
.dev
;
1553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1554 int pipe
= crtc
->pipe
;
1555 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1558 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1562 mutex_lock(&dev_priv
->dpio_lock
);
1564 /* Enable back the 10bit clock to display controller */
1565 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1566 tmp
|= DPIO_DCLKP_EN
;
1567 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1583 POSTING_READ(DPLL_MD(pipe
));
1585 mutex_unlock(&dev_priv
->dpio_lock
);
1588 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1590 struct intel_crtc
*crtc
;
1593 for_each_intel_crtc(dev
, crtc
)
1594 count
+= crtc
->active
&&
1595 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1600 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1602 struct drm_device
*dev
= crtc
->base
.dev
;
1603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1604 int reg
= DPLL(crtc
->pipe
);
1605 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1607 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1614 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1624 dpll
|= DPLL_DVO_2X_MODE
;
1625 I915_WRITE(DPLL(!crtc
->pipe
),
1626 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1629 /* Wait for the clocks to stabilize. */
1633 if (INTEL_INFO(dev
)->gen
>= 4) {
1634 I915_WRITE(DPLL_MD(crtc
->pipe
),
1635 crtc
->config
->dpll_hw_state
.dpll_md
);
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1640 * So write it again.
1642 I915_WRITE(reg
, dpll
);
1645 /* We do this three times for luck */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg
, dpll
);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg
, dpll
);
1654 udelay(150); /* wait for warmup */
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 * Note! This is for pre-ILK only.
1666 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1668 struct drm_device
*dev
= crtc
->base
.dev
;
1669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1670 enum pipe pipe
= crtc
->pipe
;
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1674 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1675 intel_num_dvo_pipes(dev
) == 1) {
1676 I915_WRITE(DPLL(PIPE_B
),
1677 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1678 I915_WRITE(DPLL(PIPE_A
),
1679 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1684 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv
, pipe
);
1690 I915_WRITE(DPLL(pipe
), 0);
1691 POSTING_READ(DPLL(pipe
));
1694 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv
, pipe
);
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1706 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1707 I915_WRITE(DPLL(pipe
), val
);
1708 POSTING_READ(DPLL(pipe
));
1712 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1714 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv
, pipe
);
1720 /* Set PLL en = 0 */
1721 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1723 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1724 I915_WRITE(DPLL(pipe
), val
);
1725 POSTING_READ(DPLL(pipe
));
1727 mutex_lock(&dev_priv
->dpio_lock
);
1729 /* Disable 10bit clock to display controller */
1730 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1731 val
&= ~DPIO_DCLKP_EN
;
1732 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1734 /* disable left/right clock distribution */
1735 if (pipe
!= PIPE_B
) {
1736 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1737 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1738 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1740 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1741 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1742 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1745 mutex_unlock(&dev_priv
->dpio_lock
);
1748 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1749 struct intel_digital_port
*dport
)
1754 switch (dport
->port
) {
1756 port_mask
= DPLL_PORTB_READY_MASK
;
1760 port_mask
= DPLL_PORTC_READY_MASK
;
1764 port_mask
= DPLL_PORTD_READY_MASK
;
1765 dpll_reg
= DPIO_PHY_STATUS
;
1771 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport
->port
), I915_READ(dpll_reg
));
1776 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1778 struct drm_device
*dev
= crtc
->base
.dev
;
1779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1780 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1782 if (WARN_ON(pll
== NULL
))
1785 WARN_ON(!pll
->config
.crtc_mask
);
1786 if (pll
->active
== 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1789 assert_shared_dpll_disabled(dev_priv
, pll
);
1791 pll
->mode_set(dev_priv
, pll
);
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1803 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1805 struct drm_device
*dev
= crtc
->base
.dev
;
1806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1807 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1809 if (WARN_ON(pll
== NULL
))
1812 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll
->name
, pll
->active
, pll
->on
,
1817 crtc
->base
.base
.id
);
1819 if (pll
->active
++) {
1821 assert_shared_dpll_enabled(dev_priv
, pll
);
1826 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1828 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1829 pll
->enable(dev_priv
, pll
);
1833 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1835 struct drm_device
*dev
= crtc
->base
.dev
;
1836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1837 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1841 if (WARN_ON(pll
== NULL
))
1844 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll
->name
, pll
->active
, pll
->on
,
1849 crtc
->base
.base
.id
);
1851 if (WARN_ON(pll
->active
== 0)) {
1852 assert_shared_dpll_disabled(dev_priv
, pll
);
1856 assert_shared_dpll_enabled(dev_priv
, pll
);
1861 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1862 pll
->disable(dev_priv
, pll
);
1865 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1871 struct drm_device
*dev
= dev_priv
->dev
;
1872 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1873 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1874 uint32_t reg
, val
, pipeconf_val
;
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev
));
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv
,
1881 intel_crtc_to_shared_dpll(intel_crtc
));
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv
, pipe
);
1885 assert_fdi_rx_enabled(dev_priv
, pipe
);
1887 if (HAS_PCH_CPT(dev
)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg
= TRANS_CHICKEN2(pipe
);
1891 val
= I915_READ(reg
);
1892 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1893 I915_WRITE(reg
, val
);
1896 reg
= PCH_TRANSCONF(pipe
);
1897 val
= I915_READ(reg
);
1898 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1900 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1905 val
&= ~PIPECONF_BPC_MASK
;
1906 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1909 val
&= ~TRANS_INTERLACE_MASK
;
1910 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1911 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1912 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1913 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1915 val
|= TRANS_INTERLACED
;
1917 val
|= TRANS_PROGRESSIVE
;
1919 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1920 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1925 enum transcoder cpu_transcoder
)
1927 u32 val
, pipeconf_val
;
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1934 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1936 /* Workaround: set timing override bit. */
1937 val
= I915_READ(_TRANSA_CHICKEN2
);
1938 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1939 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1942 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1944 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1945 PIPECONF_INTERLACED_ILK
)
1946 val
|= TRANS_INTERLACED
;
1948 val
|= TRANS_PROGRESSIVE
;
1950 I915_WRITE(LPT_TRANSCONF
, val
);
1951 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1958 struct drm_device
*dev
= dev_priv
->dev
;
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv
, pipe
);
1963 assert_fdi_rx_disabled(dev_priv
, pipe
);
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv
, pipe
);
1968 reg
= PCH_TRANSCONF(pipe
);
1969 val
= I915_READ(reg
);
1970 val
&= ~TRANS_ENABLE
;
1971 I915_WRITE(reg
, val
);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1976 if (!HAS_PCH_IBX(dev
)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg
= TRANS_CHICKEN2(pipe
);
1979 val
= I915_READ(reg
);
1980 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1981 I915_WRITE(reg
, val
);
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1989 val
= I915_READ(LPT_TRANSCONF
);
1990 val
&= ~TRANS_ENABLE
;
1991 I915_WRITE(LPT_TRANSCONF
, val
);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1996 /* Workaround: clear timing override bit. */
1997 val
= I915_READ(_TRANSA_CHICKEN2
);
1998 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1999 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2009 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2011 struct drm_device
*dev
= crtc
->base
.dev
;
2012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2013 enum pipe pipe
= crtc
->pipe
;
2014 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2016 enum pipe pch_transcoder
;
2020 assert_planes_disabled(dev_priv
, pipe
);
2021 assert_cursor_disabled(dev_priv
, pipe
);
2022 assert_sprites_disabled(dev_priv
, pipe
);
2024 if (HAS_PCH_LPT(dev_priv
->dev
))
2025 pch_transcoder
= TRANSCODER_A
;
2027 pch_transcoder
= pipe
;
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2034 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2035 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2036 assert_dsi_pll_enabled(dev_priv
);
2038 assert_pll_enabled(dev_priv
, pipe
);
2040 if (crtc
->config
->has_pch_encoder
) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2043 assert_fdi_tx_pll_enabled(dev_priv
,
2044 (enum pipe
) cpu_transcoder
);
2046 /* FIXME: assert CPU port conditions for SNB+ */
2049 reg
= PIPECONF(cpu_transcoder
);
2050 val
= I915_READ(reg
);
2051 if (val
& PIPECONF_ENABLE
) {
2052 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2053 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2057 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2069 * Will wait until the pipe has shut down before returning.
2071 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2073 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2074 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2075 enum pipe pipe
= crtc
->pipe
;
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2083 assert_planes_disabled(dev_priv
, pipe
);
2084 assert_cursor_disabled(dev_priv
, pipe
);
2085 assert_sprites_disabled(dev_priv
, pipe
);
2087 reg
= PIPECONF(cpu_transcoder
);
2088 val
= I915_READ(reg
);
2089 if ((val
& PIPECONF_ENABLE
) == 0)
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2096 if (crtc
->config
->double_wide
)
2097 val
&= ~PIPECONF_DOUBLE_WIDE
;
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2101 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2102 val
&= ~PIPECONF_ENABLE
;
2104 I915_WRITE(reg
, val
);
2105 if ((val
& PIPECONF_ENABLE
) == 0)
2106 intel_wait_for_pipe_off(crtc
);
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2113 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2116 struct drm_device
*dev
= dev_priv
->dev
;
2117 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2119 I915_WRITE(reg
, I915_READ(reg
));
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2130 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2131 struct drm_crtc
*crtc
)
2133 struct drm_device
*dev
= plane
->dev
;
2134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2140 if (intel_crtc
->primary_enabled
)
2143 intel_crtc
->primary_enabled
= true;
2145 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2153 if (IS_BROADWELL(dev
))
2154 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2164 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2165 struct drm_crtc
*crtc
)
2167 struct drm_device
*dev
= plane
->dev
;
2168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2169 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2171 if (WARN_ON(!intel_crtc
->active
))
2174 if (!intel_crtc
->primary_enabled
)
2177 intel_crtc
->primary_enabled
= false;
2179 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2183 static bool need_vtd_wa(struct drm_device
*dev
)
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2193 intel_fb_align_height(struct drm_device
*dev
, int height
,
2194 uint32_t pixel_format
,
2195 uint64_t fb_format_modifier
)
2198 uint32_t bits_per_pixel
;
2200 switch (fb_format_modifier
) {
2201 case DRM_FORMAT_MOD_NONE
:
2204 case I915_FORMAT_MOD_X_TILED
:
2205 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2207 case I915_FORMAT_MOD_Y_TILED
:
2210 case I915_FORMAT_MOD_Yf_TILED
:
2211 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2212 switch (bits_per_pixel
) {
2226 "128-bit pixels are not supported for display!");
2232 MISSING_CASE(fb_format_modifier
);
2237 return ALIGN(height
, tile_height
);
2241 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2242 struct drm_framebuffer
*fb
,
2243 struct intel_engine_cs
*pipelined
)
2245 struct drm_device
*dev
= fb
->dev
;
2246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2247 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2251 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2253 switch (fb
->modifier
[0]) {
2254 case DRM_FORMAT_MOD_NONE
:
2255 if (INTEL_INFO(dev
)->gen
>= 9)
2256 alignment
= 256 * 1024;
2257 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2258 alignment
= 128 * 1024;
2259 else if (INTEL_INFO(dev
)->gen
>= 4)
2260 alignment
= 4 * 1024;
2262 alignment
= 64 * 1024;
2264 case I915_FORMAT_MOD_X_TILED
:
2265 if (INTEL_INFO(dev
)->gen
>= 9)
2266 alignment
= 256 * 1024;
2268 /* pin() will align the object as required by fence */
2272 case I915_FORMAT_MOD_Y_TILED
:
2273 case I915_FORMAT_MOD_Yf_TILED
:
2274 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2275 "Y tiling bo slipped through, driver bug!\n"))
2277 alignment
= 1 * 1024 * 1024;
2280 MISSING_CASE(fb
->modifier
[0]);
2284 /* Note that the w/a also requires 64 PTE of padding following the
2285 * bo. We currently fill all unused PTE with the shadow page and so
2286 * we should always have valid PTE following the scanout preventing
2289 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2290 alignment
= 256 * 1024;
2293 * Global gtt pte registers are special registers which actually forward
2294 * writes to a chunk of system memory. Which means that there is no risk
2295 * that the register values disappear as soon as we call
2296 * intel_runtime_pm_put(), so it is correct to wrap only the
2297 * pin/unpin/fence and not more.
2299 intel_runtime_pm_get(dev_priv
);
2301 dev_priv
->mm
.interruptible
= false;
2302 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2304 goto err_interruptible
;
2306 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307 * fence, whereas 965+ only requires a fence if using
2308 * framebuffer compression. For simplicity, we always install
2309 * a fence as the cost is not that onerous.
2311 ret
= i915_gem_object_get_fence(obj
);
2315 i915_gem_object_pin_fence(obj
);
2317 dev_priv
->mm
.interruptible
= true;
2318 intel_runtime_pm_put(dev_priv
);
2322 i915_gem_object_unpin_from_display_plane(obj
);
2324 dev_priv
->mm
.interruptible
= true;
2325 intel_runtime_pm_put(dev_priv
);
2329 static void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2331 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2333 i915_gem_object_unpin_fence(obj
);
2334 i915_gem_object_unpin_from_display_plane(obj
);
2337 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338 * is assumed to be a power-of-two. */
2339 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2340 unsigned int tiling_mode
,
2344 if (tiling_mode
!= I915_TILING_NONE
) {
2345 unsigned int tile_rows
, tiles
;
2350 tiles
= *x
/ (512/cpp
);
2353 return tile_rows
* pitch
* 8 + tiles
* 4096;
2355 unsigned int offset
;
2357 offset
= *y
* pitch
+ *x
* cpp
;
2359 *x
= (offset
& 4095) / cpp
;
2360 return offset
& -4096;
2364 static int i9xx_format_to_fourcc(int format
)
2367 case DISPPLANE_8BPP
:
2368 return DRM_FORMAT_C8
;
2369 case DISPPLANE_BGRX555
:
2370 return DRM_FORMAT_XRGB1555
;
2371 case DISPPLANE_BGRX565
:
2372 return DRM_FORMAT_RGB565
;
2374 case DISPPLANE_BGRX888
:
2375 return DRM_FORMAT_XRGB8888
;
2376 case DISPPLANE_RGBX888
:
2377 return DRM_FORMAT_XBGR8888
;
2378 case DISPPLANE_BGRX101010
:
2379 return DRM_FORMAT_XRGB2101010
;
2380 case DISPPLANE_RGBX101010
:
2381 return DRM_FORMAT_XBGR2101010
;
2385 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2388 case PLANE_CTL_FORMAT_RGB_565
:
2389 return DRM_FORMAT_RGB565
;
2391 case PLANE_CTL_FORMAT_XRGB_8888
:
2394 return DRM_FORMAT_ABGR8888
;
2396 return DRM_FORMAT_XBGR8888
;
2399 return DRM_FORMAT_ARGB8888
;
2401 return DRM_FORMAT_XRGB8888
;
2403 case PLANE_CTL_FORMAT_XRGB_2101010
:
2405 return DRM_FORMAT_XBGR2101010
;
2407 return DRM_FORMAT_XRGB2101010
;
2412 intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2413 struct intel_initial_plane_config
*plane_config
)
2415 struct drm_device
*dev
= crtc
->base
.dev
;
2416 struct drm_i915_gem_object
*obj
= NULL
;
2417 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2418 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2419 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2420 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2423 size_aligned
-= base_aligned
;
2425 if (plane_config
->size
== 0)
2428 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2435 obj
->tiling_mode
= plane_config
->tiling
;
2436 if (obj
->tiling_mode
== I915_TILING_X
)
2437 obj
->stride
= fb
->pitches
[0];
2439 mode_cmd
.pixel_format
= fb
->pixel_format
;
2440 mode_cmd
.width
= fb
->width
;
2441 mode_cmd
.height
= fb
->height
;
2442 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2443 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2444 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2446 mutex_lock(&dev
->struct_mutex
);
2448 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2450 DRM_DEBUG_KMS("intel fb init failed\n");
2454 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2455 mutex_unlock(&dev
->struct_mutex
);
2457 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2461 drm_gem_object_unreference(&obj
->base
);
2462 mutex_unlock(&dev
->struct_mutex
);
2466 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2468 update_state_fb(struct drm_plane
*plane
)
2470 if (plane
->fb
== plane
->state
->fb
)
2473 if (plane
->state
->fb
)
2474 drm_framebuffer_unreference(plane
->state
->fb
);
2475 plane
->state
->fb
= plane
->fb
;
2476 if (plane
->state
->fb
)
2477 drm_framebuffer_reference(plane
->state
->fb
);
2481 intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2482 struct intel_initial_plane_config
*plane_config
)
2484 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2487 struct intel_crtc
*i
;
2488 struct drm_i915_gem_object
*obj
;
2490 if (!plane_config
->fb
)
2493 if (intel_alloc_plane_obj(intel_crtc
, plane_config
)) {
2494 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2496 primary
->fb
= &plane_config
->fb
->base
;
2497 primary
->state
->crtc
= &intel_crtc
->base
;
2498 update_state_fb(primary
);
2503 kfree(plane_config
->fb
);
2506 * Failed to alloc the obj, check to see if we should share
2507 * an fb with another CRTC instead
2509 for_each_crtc(dev
, c
) {
2510 i
= to_intel_crtc(c
);
2512 if (c
== &intel_crtc
->base
)
2518 obj
= intel_fb_obj(c
->primary
->fb
);
2522 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2523 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2525 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2526 dev_priv
->preserve_bios_swizzle
= true;
2528 drm_framebuffer_reference(c
->primary
->fb
);
2529 primary
->fb
= c
->primary
->fb
;
2530 primary
->state
->crtc
= &intel_crtc
->base
;
2531 update_state_fb(intel_crtc
->base
.primary
);
2532 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2539 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2540 struct drm_framebuffer
*fb
,
2543 struct drm_device
*dev
= crtc
->dev
;
2544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2545 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2546 struct drm_i915_gem_object
*obj
;
2547 int plane
= intel_crtc
->plane
;
2548 unsigned long linear_offset
;
2550 u32 reg
= DSPCNTR(plane
);
2553 if (!intel_crtc
->primary_enabled
) {
2555 if (INTEL_INFO(dev
)->gen
>= 4)
2556 I915_WRITE(DSPSURF(plane
), 0);
2558 I915_WRITE(DSPADDR(plane
), 0);
2563 obj
= intel_fb_obj(fb
);
2564 if (WARN_ON(obj
== NULL
))
2567 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2569 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2571 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2573 if (INTEL_INFO(dev
)->gen
< 4) {
2574 if (intel_crtc
->pipe
== PIPE_B
)
2575 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2577 /* pipesrc and dspsize control the size that is scaled from,
2578 * which should always be the user's requested size.
2580 I915_WRITE(DSPSIZE(plane
),
2581 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2582 (intel_crtc
->config
->pipe_src_w
- 1));
2583 I915_WRITE(DSPPOS(plane
), 0);
2584 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2585 I915_WRITE(PRIMSIZE(plane
),
2586 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2587 (intel_crtc
->config
->pipe_src_w
- 1));
2588 I915_WRITE(PRIMPOS(plane
), 0);
2589 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2592 switch (fb
->pixel_format
) {
2594 dspcntr
|= DISPPLANE_8BPP
;
2596 case DRM_FORMAT_XRGB1555
:
2597 case DRM_FORMAT_ARGB1555
:
2598 dspcntr
|= DISPPLANE_BGRX555
;
2600 case DRM_FORMAT_RGB565
:
2601 dspcntr
|= DISPPLANE_BGRX565
;
2603 case DRM_FORMAT_XRGB8888
:
2604 case DRM_FORMAT_ARGB8888
:
2605 dspcntr
|= DISPPLANE_BGRX888
;
2607 case DRM_FORMAT_XBGR8888
:
2608 case DRM_FORMAT_ABGR8888
:
2609 dspcntr
|= DISPPLANE_RGBX888
;
2611 case DRM_FORMAT_XRGB2101010
:
2612 case DRM_FORMAT_ARGB2101010
:
2613 dspcntr
|= DISPPLANE_BGRX101010
;
2615 case DRM_FORMAT_XBGR2101010
:
2616 case DRM_FORMAT_ABGR2101010
:
2617 dspcntr
|= DISPPLANE_RGBX101010
;
2623 if (INTEL_INFO(dev
)->gen
>= 4 &&
2624 obj
->tiling_mode
!= I915_TILING_NONE
)
2625 dspcntr
|= DISPPLANE_TILED
;
2628 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2630 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2632 if (INTEL_INFO(dev
)->gen
>= 4) {
2633 intel_crtc
->dspaddr_offset
=
2634 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2637 linear_offset
-= intel_crtc
->dspaddr_offset
;
2639 intel_crtc
->dspaddr_offset
= linear_offset
;
2642 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2643 dspcntr
|= DISPPLANE_ROTATE_180
;
2645 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2646 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2648 /* Finding the last pixel of the last line of the display
2649 data and adding to linear_offset*/
2651 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2652 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2655 I915_WRITE(reg
, dspcntr
);
2657 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2658 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2660 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2661 if (INTEL_INFO(dev
)->gen
>= 4) {
2662 I915_WRITE(DSPSURF(plane
),
2663 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2664 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2665 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2667 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2671 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2672 struct drm_framebuffer
*fb
,
2675 struct drm_device
*dev
= crtc
->dev
;
2676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2678 struct drm_i915_gem_object
*obj
;
2679 int plane
= intel_crtc
->plane
;
2680 unsigned long linear_offset
;
2682 u32 reg
= DSPCNTR(plane
);
2685 if (!intel_crtc
->primary_enabled
) {
2687 I915_WRITE(DSPSURF(plane
), 0);
2692 obj
= intel_fb_obj(fb
);
2693 if (WARN_ON(obj
== NULL
))
2696 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2698 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2700 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2702 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2703 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2705 switch (fb
->pixel_format
) {
2707 dspcntr
|= DISPPLANE_8BPP
;
2709 case DRM_FORMAT_RGB565
:
2710 dspcntr
|= DISPPLANE_BGRX565
;
2712 case DRM_FORMAT_XRGB8888
:
2713 case DRM_FORMAT_ARGB8888
:
2714 dspcntr
|= DISPPLANE_BGRX888
;
2716 case DRM_FORMAT_XBGR8888
:
2717 case DRM_FORMAT_ABGR8888
:
2718 dspcntr
|= DISPPLANE_RGBX888
;
2720 case DRM_FORMAT_XRGB2101010
:
2721 case DRM_FORMAT_ARGB2101010
:
2722 dspcntr
|= DISPPLANE_BGRX101010
;
2724 case DRM_FORMAT_XBGR2101010
:
2725 case DRM_FORMAT_ABGR2101010
:
2726 dspcntr
|= DISPPLANE_RGBX101010
;
2732 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2733 dspcntr
|= DISPPLANE_TILED
;
2735 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2736 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2738 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2739 intel_crtc
->dspaddr_offset
=
2740 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2743 linear_offset
-= intel_crtc
->dspaddr_offset
;
2744 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2745 dspcntr
|= DISPPLANE_ROTATE_180
;
2747 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2748 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2749 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2754 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2755 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2759 I915_WRITE(reg
, dspcntr
);
2761 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2762 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2764 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2765 I915_WRITE(DSPSURF(plane
),
2766 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2767 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2768 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2770 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2771 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2776 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2777 uint32_t pixel_format
)
2779 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2782 * The stride is either expressed as a multiple of 64 bytes
2783 * chunks for linear buffers or in number of tiles for tiled
2786 switch (fb_modifier
) {
2787 case DRM_FORMAT_MOD_NONE
:
2789 case I915_FORMAT_MOD_X_TILED
:
2790 if (INTEL_INFO(dev
)->gen
== 2)
2793 case I915_FORMAT_MOD_Y_TILED
:
2794 /* No need to check for old gens and Y tiling since this is
2795 * about the display engine and those will be blocked before
2799 case I915_FORMAT_MOD_Yf_TILED
:
2800 if (bits_per_pixel
== 8)
2805 MISSING_CASE(fb_modifier
);
2810 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2811 struct drm_framebuffer
*fb
,
2814 struct drm_device
*dev
= crtc
->dev
;
2815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2816 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2817 struct drm_i915_gem_object
*obj
;
2818 int pipe
= intel_crtc
->pipe
;
2819 u32 plane_ctl
, stride_div
;
2821 if (!intel_crtc
->primary_enabled
) {
2822 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2823 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2824 POSTING_READ(PLANE_CTL(pipe
, 0));
2828 plane_ctl
= PLANE_CTL_ENABLE
|
2829 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2830 PLANE_CTL_PIPE_CSC_ENABLE
;
2832 switch (fb
->pixel_format
) {
2833 case DRM_FORMAT_RGB565
:
2834 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2836 case DRM_FORMAT_XRGB8888
:
2837 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2839 case DRM_FORMAT_ARGB8888
:
2840 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2841 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2843 case DRM_FORMAT_XBGR8888
:
2844 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2845 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2847 case DRM_FORMAT_ABGR8888
:
2848 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2849 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2850 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2852 case DRM_FORMAT_XRGB2101010
:
2853 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2855 case DRM_FORMAT_XBGR2101010
:
2856 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2857 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2863 switch (fb
->modifier
[0]) {
2864 case DRM_FORMAT_MOD_NONE
:
2866 case I915_FORMAT_MOD_X_TILED
:
2867 plane_ctl
|= PLANE_CTL_TILED_X
;
2869 case I915_FORMAT_MOD_Y_TILED
:
2870 plane_ctl
|= PLANE_CTL_TILED_Y
;
2872 case I915_FORMAT_MOD_Yf_TILED
:
2873 plane_ctl
|= PLANE_CTL_TILED_YF
;
2876 MISSING_CASE(fb
->modifier
[0]);
2879 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2880 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
))
2881 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2883 obj
= intel_fb_obj(fb
);
2884 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
2887 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2889 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2890 i915_gem_obj_ggtt_offset(obj
),
2891 x
, y
, fb
->width
, fb
->height
,
2894 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2895 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2896 I915_WRITE(PLANE_SIZE(pipe
, 0),
2897 (intel_crtc
->config
->pipe_src_h
- 1) << 16 |
2898 (intel_crtc
->config
->pipe_src_w
- 1));
2899 I915_WRITE(PLANE_STRIDE(pipe
, 0), fb
->pitches
[0] / stride_div
);
2900 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2902 POSTING_READ(PLANE_SURF(pipe
, 0));
2905 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2907 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2908 int x
, int y
, enum mode_set_atomic state
)
2910 struct drm_device
*dev
= crtc
->dev
;
2911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2913 if (dev_priv
->display
.disable_fbc
)
2914 dev_priv
->display
.disable_fbc(dev
);
2916 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2921 static void intel_complete_page_flips(struct drm_device
*dev
)
2923 struct drm_crtc
*crtc
;
2925 for_each_crtc(dev
, crtc
) {
2926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2927 enum plane plane
= intel_crtc
->plane
;
2929 intel_prepare_page_flip(dev
, plane
);
2930 intel_finish_page_flip_plane(dev
, plane
);
2934 static void intel_update_primary_planes(struct drm_device
*dev
)
2936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2937 struct drm_crtc
*crtc
;
2939 for_each_crtc(dev
, crtc
) {
2940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2942 drm_modeset_lock(&crtc
->mutex
, NULL
);
2944 * FIXME: Once we have proper support for primary planes (and
2945 * disabling them without disabling the entire crtc) allow again
2946 * a NULL crtc->primary->fb.
2948 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2949 dev_priv
->display
.update_primary_plane(crtc
,
2953 drm_modeset_unlock(&crtc
->mutex
);
2957 void intel_prepare_reset(struct drm_device
*dev
)
2959 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2960 struct intel_crtc
*crtc
;
2962 /* no reset support for gen2 */
2966 /* reset doesn't touch the display */
2967 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
2970 drm_modeset_lock_all(dev
);
2973 * Disabling the crtcs gracefully seems nicer. Also the
2974 * g33 docs say we should at least disable all the planes.
2976 for_each_intel_crtc(dev
, crtc
) {
2978 dev_priv
->display
.crtc_disable(&crtc
->base
);
2982 void intel_finish_reset(struct drm_device
*dev
)
2984 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2987 * Flips in the rings will be nuked by the reset,
2988 * so complete all pending flips so that user space
2989 * will get its events and not get stuck.
2991 intel_complete_page_flips(dev
);
2993 /* no reset support for gen2 */
2997 /* reset doesn't touch the display */
2998 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3000 * Flips in the rings have been nuked by the reset,
3001 * so update the base address of all primary
3002 * planes to the the last fb to make sure we're
3003 * showing the correct fb after a reset.
3005 intel_update_primary_planes(dev
);
3010 * The display has been reset as well,
3011 * so need a full re-initialization.
3013 intel_runtime_pm_disable_interrupts(dev_priv
);
3014 intel_runtime_pm_enable_interrupts(dev_priv
);
3016 intel_modeset_init_hw(dev
);
3018 spin_lock_irq(&dev_priv
->irq_lock
);
3019 if (dev_priv
->display
.hpd_irq_setup
)
3020 dev_priv
->display
.hpd_irq_setup(dev
);
3021 spin_unlock_irq(&dev_priv
->irq_lock
);
3023 intel_modeset_setup_hw_state(dev
, true);
3025 intel_hpd_init(dev_priv
);
3027 drm_modeset_unlock_all(dev
);
3031 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3033 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3034 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3035 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3038 /* Big Hammer, we also need to ensure that any pending
3039 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3040 * current scanout is retired before unpinning the old
3043 * This should only fail upon a hung GPU, in which case we
3044 * can safely continue.
3046 dev_priv
->mm
.interruptible
= false;
3047 ret
= i915_gem_object_finish_gpu(obj
);
3048 dev_priv
->mm
.interruptible
= was_interruptible
;
3053 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3055 struct drm_device
*dev
= crtc
->dev
;
3056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3057 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3060 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3061 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3064 spin_lock_irq(&dev
->event_lock
);
3065 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3066 spin_unlock_irq(&dev
->event_lock
);
3071 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3073 struct drm_device
*dev
= crtc
->base
.dev
;
3074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3075 const struct drm_display_mode
*adjusted_mode
;
3081 * Update pipe size and adjust fitter if needed: the reason for this is
3082 * that in compute_mode_changes we check the native mode (not the pfit
3083 * mode) to see if we can flip rather than do a full mode set. In the
3084 * fastboot case, we'll flip, but if we don't update the pipesrc and
3085 * pfit state, we'll end up with a big fb scanned out into the wrong
3088 * To fix this properly, we need to hoist the checks up into
3089 * compute_mode_changes (or above), check the actual pfit state and
3090 * whether the platform allows pfit disable with pipe active, and only
3091 * then update the pipesrc and pfit state, even on the flip path.
3094 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3096 I915_WRITE(PIPESRC(crtc
->pipe
),
3097 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3098 (adjusted_mode
->crtc_vdisplay
- 1));
3099 if (!crtc
->config
->pch_pfit
.enabled
&&
3100 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3101 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3102 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3103 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3104 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3106 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3107 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3110 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3112 struct drm_device
*dev
= crtc
->dev
;
3113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3114 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3115 int pipe
= intel_crtc
->pipe
;
3118 /* enable normal train */
3119 reg
= FDI_TX_CTL(pipe
);
3120 temp
= I915_READ(reg
);
3121 if (IS_IVYBRIDGE(dev
)) {
3122 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3123 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3125 temp
&= ~FDI_LINK_TRAIN_NONE
;
3126 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3128 I915_WRITE(reg
, temp
);
3130 reg
= FDI_RX_CTL(pipe
);
3131 temp
= I915_READ(reg
);
3132 if (HAS_PCH_CPT(dev
)) {
3133 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3134 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3136 temp
&= ~FDI_LINK_TRAIN_NONE
;
3137 temp
|= FDI_LINK_TRAIN_NONE
;
3139 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3141 /* wait one idle pattern time */
3145 /* IVB wants error correction enabled */
3146 if (IS_IVYBRIDGE(dev
))
3147 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3148 FDI_FE_ERRC_ENABLE
);
3151 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3153 return crtc
->base
.state
->enable
&& crtc
->active
&&
3154 crtc
->config
->has_pch_encoder
;
3157 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3160 struct intel_crtc
*pipe_B_crtc
=
3161 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3162 struct intel_crtc
*pipe_C_crtc
=
3163 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3167 * When everything is off disable fdi C so that we could enable fdi B
3168 * with all lanes. Note that we don't care about enabled pipes without
3169 * an enabled pch encoder.
3171 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3172 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3173 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3174 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3176 temp
= I915_READ(SOUTH_CHICKEN1
);
3177 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3178 DRM_DEBUG_KMS("disabling fdi C rx\n");
3179 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3183 /* The FDI link training functions for ILK/Ibexpeak. */
3184 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3186 struct drm_device
*dev
= crtc
->dev
;
3187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3188 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3189 int pipe
= intel_crtc
->pipe
;
3190 u32 reg
, temp
, tries
;
3192 /* FDI needs bits from pipe first */
3193 assert_pipe_enabled(dev_priv
, pipe
);
3195 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3197 reg
= FDI_RX_IMR(pipe
);
3198 temp
= I915_READ(reg
);
3199 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3200 temp
&= ~FDI_RX_BIT_LOCK
;
3201 I915_WRITE(reg
, temp
);
3205 /* enable CPU FDI TX and PCH FDI RX */
3206 reg
= FDI_TX_CTL(pipe
);
3207 temp
= I915_READ(reg
);
3208 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3209 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3210 temp
&= ~FDI_LINK_TRAIN_NONE
;
3211 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3212 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3214 reg
= FDI_RX_CTL(pipe
);
3215 temp
= I915_READ(reg
);
3216 temp
&= ~FDI_LINK_TRAIN_NONE
;
3217 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3218 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3223 /* Ironlake workaround, enable clock pointer after FDI enable*/
3224 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3225 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3226 FDI_RX_PHASE_SYNC_POINTER_EN
);
3228 reg
= FDI_RX_IIR(pipe
);
3229 for (tries
= 0; tries
< 5; tries
++) {
3230 temp
= I915_READ(reg
);
3231 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3233 if ((temp
& FDI_RX_BIT_LOCK
)) {
3234 DRM_DEBUG_KMS("FDI train 1 done.\n");
3235 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3240 DRM_ERROR("FDI train 1 fail!\n");
3243 reg
= FDI_TX_CTL(pipe
);
3244 temp
= I915_READ(reg
);
3245 temp
&= ~FDI_LINK_TRAIN_NONE
;
3246 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3247 I915_WRITE(reg
, temp
);
3249 reg
= FDI_RX_CTL(pipe
);
3250 temp
= I915_READ(reg
);
3251 temp
&= ~FDI_LINK_TRAIN_NONE
;
3252 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3253 I915_WRITE(reg
, temp
);
3258 reg
= FDI_RX_IIR(pipe
);
3259 for (tries
= 0; tries
< 5; tries
++) {
3260 temp
= I915_READ(reg
);
3261 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3263 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3264 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3265 DRM_DEBUG_KMS("FDI train 2 done.\n");
3270 DRM_ERROR("FDI train 2 fail!\n");
3272 DRM_DEBUG_KMS("FDI train done\n");
3276 static const int snb_b_fdi_train_param
[] = {
3277 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3278 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3279 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3280 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3283 /* The FDI link training functions for SNB/Cougarpoint. */
3284 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3286 struct drm_device
*dev
= crtc
->dev
;
3287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3289 int pipe
= intel_crtc
->pipe
;
3290 u32 reg
, temp
, i
, retry
;
3292 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3294 reg
= FDI_RX_IMR(pipe
);
3295 temp
= I915_READ(reg
);
3296 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3297 temp
&= ~FDI_RX_BIT_LOCK
;
3298 I915_WRITE(reg
, temp
);
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg
= FDI_TX_CTL(pipe
);
3305 temp
= I915_READ(reg
);
3306 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3307 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3308 temp
&= ~FDI_LINK_TRAIN_NONE
;
3309 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3310 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3312 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3313 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3315 I915_WRITE(FDI_RX_MISC(pipe
),
3316 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3318 reg
= FDI_RX_CTL(pipe
);
3319 temp
= I915_READ(reg
);
3320 if (HAS_PCH_CPT(dev
)) {
3321 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3322 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3324 temp
&= ~FDI_LINK_TRAIN_NONE
;
3325 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3327 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3332 for (i
= 0; i
< 4; i
++) {
3333 reg
= FDI_TX_CTL(pipe
);
3334 temp
= I915_READ(reg
);
3335 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3336 temp
|= snb_b_fdi_train_param
[i
];
3337 I915_WRITE(reg
, temp
);
3342 for (retry
= 0; retry
< 5; retry
++) {
3343 reg
= FDI_RX_IIR(pipe
);
3344 temp
= I915_READ(reg
);
3345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3346 if (temp
& FDI_RX_BIT_LOCK
) {
3347 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3348 DRM_DEBUG_KMS("FDI train 1 done.\n");
3357 DRM_ERROR("FDI train 1 fail!\n");
3360 reg
= FDI_TX_CTL(pipe
);
3361 temp
= I915_READ(reg
);
3362 temp
&= ~FDI_LINK_TRAIN_NONE
;
3363 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3365 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3367 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3369 I915_WRITE(reg
, temp
);
3371 reg
= FDI_RX_CTL(pipe
);
3372 temp
= I915_READ(reg
);
3373 if (HAS_PCH_CPT(dev
)) {
3374 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3375 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3377 temp
&= ~FDI_LINK_TRAIN_NONE
;
3378 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3380 I915_WRITE(reg
, temp
);
3385 for (i
= 0; i
< 4; i
++) {
3386 reg
= FDI_TX_CTL(pipe
);
3387 temp
= I915_READ(reg
);
3388 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3389 temp
|= snb_b_fdi_train_param
[i
];
3390 I915_WRITE(reg
, temp
);
3395 for (retry
= 0; retry
< 5; retry
++) {
3396 reg
= FDI_RX_IIR(pipe
);
3397 temp
= I915_READ(reg
);
3398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3399 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3400 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3401 DRM_DEBUG_KMS("FDI train 2 done.\n");
3410 DRM_ERROR("FDI train 2 fail!\n");
3412 DRM_DEBUG_KMS("FDI train done.\n");
3415 /* Manual link training for Ivy Bridge A0 parts */
3416 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3418 struct drm_device
*dev
= crtc
->dev
;
3419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3421 int pipe
= intel_crtc
->pipe
;
3422 u32 reg
, temp
, i
, j
;
3424 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426 reg
= FDI_RX_IMR(pipe
);
3427 temp
= I915_READ(reg
);
3428 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3429 temp
&= ~FDI_RX_BIT_LOCK
;
3430 I915_WRITE(reg
, temp
);
3435 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3436 I915_READ(FDI_RX_IIR(pipe
)));
3438 /* Try each vswing and preemphasis setting twice before moving on */
3439 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3440 /* disable first in case we need to retry */
3441 reg
= FDI_TX_CTL(pipe
);
3442 temp
= I915_READ(reg
);
3443 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3444 temp
&= ~FDI_TX_ENABLE
;
3445 I915_WRITE(reg
, temp
);
3447 reg
= FDI_RX_CTL(pipe
);
3448 temp
= I915_READ(reg
);
3449 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3450 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3451 temp
&= ~FDI_RX_ENABLE
;
3452 I915_WRITE(reg
, temp
);
3454 /* enable CPU FDI TX and PCH FDI RX */
3455 reg
= FDI_TX_CTL(pipe
);
3456 temp
= I915_READ(reg
);
3457 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3458 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3459 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3460 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3461 temp
|= snb_b_fdi_train_param
[j
/2];
3462 temp
|= FDI_COMPOSITE_SYNC
;
3463 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3465 I915_WRITE(FDI_RX_MISC(pipe
),
3466 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3468 reg
= FDI_RX_CTL(pipe
);
3469 temp
= I915_READ(reg
);
3470 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3471 temp
|= FDI_COMPOSITE_SYNC
;
3472 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3475 udelay(1); /* should be 0.5us */
3477 for (i
= 0; i
< 4; i
++) {
3478 reg
= FDI_RX_IIR(pipe
);
3479 temp
= I915_READ(reg
);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3482 if (temp
& FDI_RX_BIT_LOCK
||
3483 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3484 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3485 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3489 udelay(1); /* should be 0.5us */
3492 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3497 reg
= FDI_TX_CTL(pipe
);
3498 temp
= I915_READ(reg
);
3499 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3500 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3501 I915_WRITE(reg
, temp
);
3503 reg
= FDI_RX_CTL(pipe
);
3504 temp
= I915_READ(reg
);
3505 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3506 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3507 I915_WRITE(reg
, temp
);
3510 udelay(2); /* should be 1.5us */
3512 for (i
= 0; i
< 4; i
++) {
3513 reg
= FDI_RX_IIR(pipe
);
3514 temp
= I915_READ(reg
);
3515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3517 if (temp
& FDI_RX_SYMBOL_LOCK
||
3518 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3519 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3520 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3524 udelay(2); /* should be 1.5us */
3527 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3531 DRM_DEBUG_KMS("FDI train done.\n");
3534 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3536 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3538 int pipe
= intel_crtc
->pipe
;
3542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3543 reg
= FDI_RX_CTL(pipe
);
3544 temp
= I915_READ(reg
);
3545 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3546 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3547 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3548 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3553 /* Switch from Rawclk to PCDclk */
3554 temp
= I915_READ(reg
);
3555 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3560 /* Enable CPU FDI TX PLL, always on for Ironlake */
3561 reg
= FDI_TX_CTL(pipe
);
3562 temp
= I915_READ(reg
);
3563 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3564 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3571 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3573 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3575 int pipe
= intel_crtc
->pipe
;
3578 /* Switch from PCDclk to Rawclk */
3579 reg
= FDI_RX_CTL(pipe
);
3580 temp
= I915_READ(reg
);
3581 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3583 /* Disable CPU FDI TX PLL */
3584 reg
= FDI_TX_CTL(pipe
);
3585 temp
= I915_READ(reg
);
3586 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3591 reg
= FDI_RX_CTL(pipe
);
3592 temp
= I915_READ(reg
);
3593 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3595 /* Wait for the clocks to turn off. */
3600 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3602 struct drm_device
*dev
= crtc
->dev
;
3603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3604 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3605 int pipe
= intel_crtc
->pipe
;
3608 /* disable CPU FDI tx and PCH FDI rx */
3609 reg
= FDI_TX_CTL(pipe
);
3610 temp
= I915_READ(reg
);
3611 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3614 reg
= FDI_RX_CTL(pipe
);
3615 temp
= I915_READ(reg
);
3616 temp
&= ~(0x7 << 16);
3617 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3618 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3623 /* Ironlake workaround, disable clock pointer after downing FDI */
3624 if (HAS_PCH_IBX(dev
))
3625 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3627 /* still set train pattern 1 */
3628 reg
= FDI_TX_CTL(pipe
);
3629 temp
= I915_READ(reg
);
3630 temp
&= ~FDI_LINK_TRAIN_NONE
;
3631 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3632 I915_WRITE(reg
, temp
);
3634 reg
= FDI_RX_CTL(pipe
);
3635 temp
= I915_READ(reg
);
3636 if (HAS_PCH_CPT(dev
)) {
3637 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3638 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3640 temp
&= ~FDI_LINK_TRAIN_NONE
;
3641 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3643 /* BPC in FDI rx is consistent with that in PIPECONF */
3644 temp
&= ~(0x07 << 16);
3645 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3646 I915_WRITE(reg
, temp
);
3652 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3654 struct intel_crtc
*crtc
;
3656 /* Note that we don't need to be called with mode_config.lock here
3657 * as our list of CRTC objects is static for the lifetime of the
3658 * device and so cannot disappear as we iterate. Similarly, we can
3659 * happily treat the predicates as racy, atomic checks as userspace
3660 * cannot claim and pin a new fb without at least acquring the
3661 * struct_mutex and so serialising with us.
3663 for_each_intel_crtc(dev
, crtc
) {
3664 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3667 if (crtc
->unpin_work
)
3668 intel_wait_for_vblank(dev
, crtc
->pipe
);
3676 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3678 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3679 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3681 /* ensure that the unpin work is consistent wrt ->pending. */
3683 intel_crtc
->unpin_work
= NULL
;
3686 drm_send_vblank_event(intel_crtc
->base
.dev
,
3690 drm_crtc_vblank_put(&intel_crtc
->base
);
3692 wake_up_all(&dev_priv
->pending_flip_queue
);
3693 queue_work(dev_priv
->wq
, &work
->work
);
3695 trace_i915_flip_complete(intel_crtc
->plane
,
3696 work
->pending_flip_obj
);
3699 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3701 struct drm_device
*dev
= crtc
->dev
;
3702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3704 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3705 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3706 !intel_crtc_has_pending_flip(crtc
),
3708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3710 spin_lock_irq(&dev
->event_lock
);
3711 if (intel_crtc
->unpin_work
) {
3712 WARN_ONCE(1, "Removing stuck page flip\n");
3713 page_flip_completed(intel_crtc
);
3715 spin_unlock_irq(&dev
->event_lock
);
3718 if (crtc
->primary
->fb
) {
3719 mutex_lock(&dev
->struct_mutex
);
3720 intel_finish_fb(crtc
->primary
->fb
);
3721 mutex_unlock(&dev
->struct_mutex
);
3725 /* Program iCLKIP clock to the desired frequency */
3726 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3728 struct drm_device
*dev
= crtc
->dev
;
3729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3730 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3731 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3734 mutex_lock(&dev_priv
->dpio_lock
);
3736 /* It is necessary to ungate the pixclk gate prior to programming
3737 * the divisors, and gate it back when it is done.
3739 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3741 /* Disable SSCCTL */
3742 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3743 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3747 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3748 if (clock
== 20000) {
3753 /* The iCLK virtual clock root frequency is in MHz,
3754 * but the adjusted_mode->crtc_clock in in KHz. To get the
3755 * divisors, it is necessary to divide one by another, so we
3756 * convert the virtual clock precision to KHz here for higher
3759 u32 iclk_virtual_root_freq
= 172800 * 1000;
3760 u32 iclk_pi_range
= 64;
3761 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3763 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3764 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3765 pi_value
= desired_divisor
% iclk_pi_range
;
3768 divsel
= msb_divisor_value
- 2;
3769 phaseinc
= pi_value
;
3772 /* This should not happen with any sane values */
3773 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3774 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3775 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3776 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3778 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3785 /* Program SSCDIVINTPHASE6 */
3786 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3787 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3788 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3789 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3790 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3791 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3792 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3793 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3795 /* Program SSCAUXDIV */
3796 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3797 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3798 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3799 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3801 /* Enable modulator and associated divider */
3802 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3803 temp
&= ~SBI_SSCCTL_DISABLE
;
3804 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3806 /* Wait for initialization time */
3809 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3811 mutex_unlock(&dev_priv
->dpio_lock
);
3814 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3815 enum pipe pch_transcoder
)
3817 struct drm_device
*dev
= crtc
->base
.dev
;
3818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3819 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3821 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3822 I915_READ(HTOTAL(cpu_transcoder
)));
3823 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3824 I915_READ(HBLANK(cpu_transcoder
)));
3825 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3826 I915_READ(HSYNC(cpu_transcoder
)));
3828 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3829 I915_READ(VTOTAL(cpu_transcoder
)));
3830 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3831 I915_READ(VBLANK(cpu_transcoder
)));
3832 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3833 I915_READ(VSYNC(cpu_transcoder
)));
3834 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3835 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3838 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3843 temp
= I915_READ(SOUTH_CHICKEN1
);
3844 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3848 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3850 temp
|= FDI_BC_BIFURCATION_SELECT
;
3851 DRM_DEBUG_KMS("enabling fdi C rx\n");
3852 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3853 POSTING_READ(SOUTH_CHICKEN1
);
3856 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3858 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3861 switch (intel_crtc
->pipe
) {
3865 if (intel_crtc
->config
->fdi_lanes
> 2)
3866 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3868 cpt_enable_fdi_bc_bifurcation(dev
);
3872 cpt_enable_fdi_bc_bifurcation(dev
);
3881 * Enable PCH resources required for PCH ports:
3883 * - FDI training & RX/TX
3884 * - update transcoder timings
3885 * - DP transcoding bits
3888 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3890 struct drm_device
*dev
= crtc
->dev
;
3891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3892 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3893 int pipe
= intel_crtc
->pipe
;
3896 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3898 if (IS_IVYBRIDGE(dev
))
3899 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3901 /* Write the TU size bits before fdi link training, so that error
3902 * detection works. */
3903 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3904 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3906 /* For PCH output, training FDI link */
3907 dev_priv
->display
.fdi_link_train(crtc
);
3909 /* We need to program the right clock selection before writing the pixel
3910 * mutliplier into the DPLL. */
3911 if (HAS_PCH_CPT(dev
)) {
3914 temp
= I915_READ(PCH_DPLL_SEL
);
3915 temp
|= TRANS_DPLL_ENABLE(pipe
);
3916 sel
= TRANS_DPLLB_SEL(pipe
);
3917 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
3921 I915_WRITE(PCH_DPLL_SEL
, temp
);
3924 /* XXX: pch pll's can be enabled any time before we enable the PCH
3925 * transcoder, and we actually should do this to not upset any PCH
3926 * transcoder that already use the clock when we share it.
3928 * Note that enable_shared_dpll tries to do the right thing, but
3929 * get_shared_dpll unconditionally resets the pll - we need that to have
3930 * the right LVDS enable sequence. */
3931 intel_enable_shared_dpll(intel_crtc
);
3933 /* set transcoder timing, panel must allow it */
3934 assert_panel_unlocked(dev_priv
, pipe
);
3935 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3937 intel_fdi_normal_train(crtc
);
3939 /* For PCH DP, enable TRANS_DP_CTL */
3940 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
3941 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3942 reg
= TRANS_DP_CTL(pipe
);
3943 temp
= I915_READ(reg
);
3944 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3945 TRANS_DP_SYNC_MASK
|
3947 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3948 TRANS_DP_ENH_FRAMING
);
3949 temp
|= bpc
<< 9; /* same format but at 11:9 */
3951 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3952 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3953 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3954 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3956 switch (intel_trans_dp_port_sel(crtc
)) {
3958 temp
|= TRANS_DP_PORT_SEL_B
;
3961 temp
|= TRANS_DP_PORT_SEL_C
;
3964 temp
|= TRANS_DP_PORT_SEL_D
;
3970 I915_WRITE(reg
, temp
);
3973 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3976 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3978 struct drm_device
*dev
= crtc
->dev
;
3979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3980 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3981 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
3983 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3985 lpt_program_iclkip(crtc
);
3987 /* Set transcoder timing. */
3988 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3990 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3993 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3995 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4000 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4001 WARN(1, "bad %s crtc mask\n", pll
->name
);
4005 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4006 if (pll
->config
.crtc_mask
== 0) {
4008 WARN_ON(pll
->active
);
4011 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4014 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4015 struct intel_crtc_state
*crtc_state
)
4017 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4018 struct intel_shared_dpll
*pll
;
4019 enum intel_dpll_id i
;
4021 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4022 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4023 i
= (enum intel_dpll_id
) crtc
->pipe
;
4024 pll
= &dev_priv
->shared_dplls
[i
];
4026 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4027 crtc
->base
.base
.id
, pll
->name
);
4029 WARN_ON(pll
->new_config
->crtc_mask
);
4034 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4035 pll
= &dev_priv
->shared_dplls
[i
];
4037 /* Only want to check enabled timings first */
4038 if (pll
->new_config
->crtc_mask
== 0)
4041 if (memcmp(&crtc_state
->dpll_hw_state
,
4042 &pll
->new_config
->hw_state
,
4043 sizeof(pll
->new_config
->hw_state
)) == 0) {
4044 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4045 crtc
->base
.base
.id
, pll
->name
,
4046 pll
->new_config
->crtc_mask
,
4052 /* Ok no matching timings, maybe there's a free one? */
4053 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4054 pll
= &dev_priv
->shared_dplls
[i
];
4055 if (pll
->new_config
->crtc_mask
== 0) {
4056 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4057 crtc
->base
.base
.id
, pll
->name
);
4065 if (pll
->new_config
->crtc_mask
== 0)
4066 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4068 crtc_state
->shared_dpll
= i
;
4069 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4070 pipe_name(crtc
->pipe
));
4072 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4078 * intel_shared_dpll_start_config - start a new PLL staged config
4079 * @dev_priv: DRM device
4080 * @clear_pipes: mask of pipes that will have their PLLs freed
4082 * Starts a new PLL staged config, copying the current config but
4083 * releasing the references of pipes specified in clear_pipes.
4085 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4086 unsigned clear_pipes
)
4088 struct intel_shared_dpll
*pll
;
4089 enum intel_dpll_id i
;
4091 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4092 pll
= &dev_priv
->shared_dplls
[i
];
4094 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4096 if (!pll
->new_config
)
4099 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4106 pll
= &dev_priv
->shared_dplls
[i
];
4107 kfree(pll
->new_config
);
4108 pll
->new_config
= NULL
;
4114 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4116 struct intel_shared_dpll
*pll
;
4117 enum intel_dpll_id i
;
4119 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4120 pll
= &dev_priv
->shared_dplls
[i
];
4122 WARN_ON(pll
->new_config
== &pll
->config
);
4124 pll
->config
= *pll
->new_config
;
4125 kfree(pll
->new_config
);
4126 pll
->new_config
= NULL
;
4130 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4132 struct intel_shared_dpll
*pll
;
4133 enum intel_dpll_id i
;
4135 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4136 pll
= &dev_priv
->shared_dplls
[i
];
4138 WARN_ON(pll
->new_config
== &pll
->config
);
4140 kfree(pll
->new_config
);
4141 pll
->new_config
= NULL
;
4145 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4148 int dslreg
= PIPEDSL(pipe
);
4151 temp
= I915_READ(dslreg
);
4153 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4154 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4155 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4159 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4161 struct drm_device
*dev
= crtc
->base
.dev
;
4162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4163 int pipe
= crtc
->pipe
;
4165 if (crtc
->config
->pch_pfit
.enabled
) {
4166 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4167 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4168 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4172 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4174 struct drm_device
*dev
= crtc
->base
.dev
;
4175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4176 int pipe
= crtc
->pipe
;
4178 if (crtc
->config
->pch_pfit
.enabled
) {
4179 /* Force use of hard-coded filter coefficients
4180 * as some pre-programmed values are broken,
4183 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4184 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4185 PF_PIPE_SEL_IVB(pipe
));
4187 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4188 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4189 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4193 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4195 struct drm_device
*dev
= crtc
->dev
;
4196 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4197 struct drm_plane
*plane
;
4198 struct intel_plane
*intel_plane
;
4200 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4201 intel_plane
= to_intel_plane(plane
);
4202 if (intel_plane
->pipe
== pipe
)
4203 intel_plane_restore(&intel_plane
->base
);
4207 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4209 struct drm_device
*dev
= crtc
->dev
;
4210 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4211 struct drm_plane
*plane
;
4212 struct intel_plane
*intel_plane
;
4214 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4215 intel_plane
= to_intel_plane(plane
);
4216 if (intel_plane
->pipe
== pipe
)
4217 plane
->funcs
->disable_plane(plane
);
4221 void hsw_enable_ips(struct intel_crtc
*crtc
)
4223 struct drm_device
*dev
= crtc
->base
.dev
;
4224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4226 if (!crtc
->config
->ips_enabled
)
4229 /* We can only enable IPS after we enable a plane and wait for a vblank */
4230 intel_wait_for_vblank(dev
, crtc
->pipe
);
4232 assert_plane_enabled(dev_priv
, crtc
->plane
);
4233 if (IS_BROADWELL(dev
)) {
4234 mutex_lock(&dev_priv
->rps
.hw_lock
);
4235 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4236 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4237 /* Quoting Art Runyan: "its not safe to expect any particular
4238 * value in IPS_CTL bit 31 after enabling IPS through the
4239 * mailbox." Moreover, the mailbox may return a bogus state,
4240 * so we need to just enable it and continue on.
4243 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4244 /* The bit only becomes 1 in the next vblank, so this wait here
4245 * is essentially intel_wait_for_vblank. If we don't have this
4246 * and don't wait for vblanks until the end of crtc_enable, then
4247 * the HW state readout code will complain that the expected
4248 * IPS_CTL value is not the one we read. */
4249 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4250 DRM_ERROR("Timed out waiting for IPS enable\n");
4254 void hsw_disable_ips(struct intel_crtc
*crtc
)
4256 struct drm_device
*dev
= crtc
->base
.dev
;
4257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4259 if (!crtc
->config
->ips_enabled
)
4262 assert_plane_enabled(dev_priv
, crtc
->plane
);
4263 if (IS_BROADWELL(dev
)) {
4264 mutex_lock(&dev_priv
->rps
.hw_lock
);
4265 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4266 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4267 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4268 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4269 DRM_ERROR("Timed out waiting for IPS disable\n");
4271 I915_WRITE(IPS_CTL
, 0);
4272 POSTING_READ(IPS_CTL
);
4275 /* We need to wait for a vblank before we can disable the plane. */
4276 intel_wait_for_vblank(dev
, crtc
->pipe
);
4279 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4280 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4282 struct drm_device
*dev
= crtc
->dev
;
4283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4285 enum pipe pipe
= intel_crtc
->pipe
;
4286 int palreg
= PALETTE(pipe
);
4288 bool reenable_ips
= false;
4290 /* The clocks have to be on to load the palette. */
4291 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4294 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4295 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4296 assert_dsi_pll_enabled(dev_priv
);
4298 assert_pll_enabled(dev_priv
, pipe
);
4301 /* use legacy palette for Ironlake */
4302 if (!HAS_GMCH_DISPLAY(dev
))
4303 palreg
= LGC_PALETTE(pipe
);
4305 /* Workaround : Do not read or write the pipe palette/gamma data while
4306 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4308 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4309 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4310 GAMMA_MODE_MODE_SPLIT
)) {
4311 hsw_disable_ips(intel_crtc
);
4312 reenable_ips
= true;
4315 for (i
= 0; i
< 256; i
++) {
4316 I915_WRITE(palreg
+ 4 * i
,
4317 (intel_crtc
->lut_r
[i
] << 16) |
4318 (intel_crtc
->lut_g
[i
] << 8) |
4319 intel_crtc
->lut_b
[i
]);
4323 hsw_enable_ips(intel_crtc
);
4326 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4328 if (!enable
&& intel_crtc
->overlay
) {
4329 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4332 mutex_lock(&dev
->struct_mutex
);
4333 dev_priv
->mm
.interruptible
= false;
4334 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4335 dev_priv
->mm
.interruptible
= true;
4336 mutex_unlock(&dev
->struct_mutex
);
4339 /* Let userspace switch the overlay on again. In most cases userspace
4340 * has to recompute where to put it anyway.
4344 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4346 struct drm_device
*dev
= crtc
->dev
;
4347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4348 int pipe
= intel_crtc
->pipe
;
4350 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4351 intel_enable_sprite_planes(crtc
);
4352 intel_crtc_update_cursor(crtc
, true);
4353 intel_crtc_dpms_overlay(intel_crtc
, true);
4355 hsw_enable_ips(intel_crtc
);
4357 mutex_lock(&dev
->struct_mutex
);
4358 intel_fbc_update(dev
);
4359 mutex_unlock(&dev
->struct_mutex
);
4362 * FIXME: Once we grow proper nuclear flip support out of this we need
4363 * to compute the mask of flip planes precisely. For the time being
4364 * consider this a flip from a NULL plane.
4366 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4369 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4371 struct drm_device
*dev
= crtc
->dev
;
4372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4373 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4374 int pipe
= intel_crtc
->pipe
;
4376 intel_crtc_wait_for_pending_flips(crtc
);
4378 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4379 intel_fbc_disable(dev
);
4381 hsw_disable_ips(intel_crtc
);
4383 intel_crtc_dpms_overlay(intel_crtc
, false);
4384 intel_crtc_update_cursor(crtc
, false);
4385 intel_disable_sprite_planes(crtc
);
4386 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4389 * FIXME: Once we grow proper nuclear flip support out of this we need
4390 * to compute the mask of flip planes precisely. For the time being
4391 * consider this a flip to a NULL plane.
4393 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4396 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4398 struct drm_device
*dev
= crtc
->dev
;
4399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4401 struct intel_encoder
*encoder
;
4402 int pipe
= intel_crtc
->pipe
;
4404 WARN_ON(!crtc
->state
->enable
);
4406 if (intel_crtc
->active
)
4409 if (intel_crtc
->config
->has_pch_encoder
)
4410 intel_prepare_shared_dpll(intel_crtc
);
4412 if (intel_crtc
->config
->has_dp_encoder
)
4413 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4415 intel_set_pipe_timings(intel_crtc
);
4417 if (intel_crtc
->config
->has_pch_encoder
) {
4418 intel_cpu_transcoder_set_m_n(intel_crtc
,
4419 &intel_crtc
->config
->fdi_m_n
, NULL
);
4422 ironlake_set_pipeconf(crtc
);
4424 intel_crtc
->active
= true;
4426 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4427 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4429 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4430 if (encoder
->pre_enable
)
4431 encoder
->pre_enable(encoder
);
4433 if (intel_crtc
->config
->has_pch_encoder
) {
4434 /* Note: FDI PLL enabling _must_ be done before we enable the
4435 * cpu pipes, hence this is separate from all the other fdi/pch
4437 ironlake_fdi_pll_enable(intel_crtc
);
4439 assert_fdi_tx_disabled(dev_priv
, pipe
);
4440 assert_fdi_rx_disabled(dev_priv
, pipe
);
4443 ironlake_pfit_enable(intel_crtc
);
4446 * On ILK+ LUT must be loaded before the pipe is running but with
4449 intel_crtc_load_lut(crtc
);
4451 intel_update_watermarks(crtc
);
4452 intel_enable_pipe(intel_crtc
);
4454 if (intel_crtc
->config
->has_pch_encoder
)
4455 ironlake_pch_enable(crtc
);
4457 assert_vblank_disabled(crtc
);
4458 drm_crtc_vblank_on(crtc
);
4460 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4461 encoder
->enable(encoder
);
4463 if (HAS_PCH_CPT(dev
))
4464 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4466 intel_crtc_enable_planes(crtc
);
4469 /* IPS only exists on ULT machines and is tied to pipe A. */
4470 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4472 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4476 * This implements the workaround described in the "notes" section of the mode
4477 * set sequence documentation. When going from no pipes or single pipe to
4478 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4479 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4481 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4483 struct drm_device
*dev
= crtc
->base
.dev
;
4484 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4486 /* We want to get the other_active_crtc only if there's only 1 other
4488 for_each_intel_crtc(dev
, crtc_it
) {
4489 if (!crtc_it
->active
|| crtc_it
== crtc
)
4492 if (other_active_crtc
)
4495 other_active_crtc
= crtc_it
;
4497 if (!other_active_crtc
)
4500 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4501 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4504 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4506 struct drm_device
*dev
= crtc
->dev
;
4507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4508 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4509 struct intel_encoder
*encoder
;
4510 int pipe
= intel_crtc
->pipe
;
4512 WARN_ON(!crtc
->state
->enable
);
4514 if (intel_crtc
->active
)
4517 if (intel_crtc_to_shared_dpll(intel_crtc
))
4518 intel_enable_shared_dpll(intel_crtc
);
4520 if (intel_crtc
->config
->has_dp_encoder
)
4521 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4523 intel_set_pipe_timings(intel_crtc
);
4525 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4526 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4527 intel_crtc
->config
->pixel_multiplier
- 1);
4530 if (intel_crtc
->config
->has_pch_encoder
) {
4531 intel_cpu_transcoder_set_m_n(intel_crtc
,
4532 &intel_crtc
->config
->fdi_m_n
, NULL
);
4535 haswell_set_pipeconf(crtc
);
4537 intel_set_pipe_csc(crtc
);
4539 intel_crtc
->active
= true;
4541 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4542 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4543 if (encoder
->pre_enable
)
4544 encoder
->pre_enable(encoder
);
4546 if (intel_crtc
->config
->has_pch_encoder
) {
4547 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4549 dev_priv
->display
.fdi_link_train(crtc
);
4552 intel_ddi_enable_pipe_clock(intel_crtc
);
4554 if (IS_SKYLAKE(dev
))
4555 skylake_pfit_enable(intel_crtc
);
4557 ironlake_pfit_enable(intel_crtc
);
4560 * On ILK+ LUT must be loaded before the pipe is running but with
4563 intel_crtc_load_lut(crtc
);
4565 intel_ddi_set_pipe_settings(crtc
);
4566 intel_ddi_enable_transcoder_func(crtc
);
4568 intel_update_watermarks(crtc
);
4569 intel_enable_pipe(intel_crtc
);
4571 if (intel_crtc
->config
->has_pch_encoder
)
4572 lpt_pch_enable(crtc
);
4574 if (intel_crtc
->config
->dp_encoder_is_mst
)
4575 intel_ddi_set_vc_payload_alloc(crtc
, true);
4577 assert_vblank_disabled(crtc
);
4578 drm_crtc_vblank_on(crtc
);
4580 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4581 encoder
->enable(encoder
);
4582 intel_opregion_notify_encoder(encoder
, true);
4585 /* If we change the relative order between pipe/planes enabling, we need
4586 * to change the workaround. */
4587 haswell_mode_set_planes_workaround(intel_crtc
);
4588 intel_crtc_enable_planes(crtc
);
4591 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4593 struct drm_device
*dev
= crtc
->base
.dev
;
4594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4595 int pipe
= crtc
->pipe
;
4597 /* To avoid upsetting the power well on haswell only disable the pfit if
4598 * it's in use. The hw state code will make sure we get this right. */
4599 if (crtc
->config
->pch_pfit
.enabled
) {
4600 I915_WRITE(PS_CTL(pipe
), 0);
4601 I915_WRITE(PS_WIN_POS(pipe
), 0);
4602 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4606 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4608 struct drm_device
*dev
= crtc
->base
.dev
;
4609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4610 int pipe
= crtc
->pipe
;
4612 /* To avoid upsetting the power well on haswell only disable the pfit if
4613 * it's in use. The hw state code will make sure we get this right. */
4614 if (crtc
->config
->pch_pfit
.enabled
) {
4615 I915_WRITE(PF_CTL(pipe
), 0);
4616 I915_WRITE(PF_WIN_POS(pipe
), 0);
4617 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4621 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4623 struct drm_device
*dev
= crtc
->dev
;
4624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4625 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4626 struct intel_encoder
*encoder
;
4627 int pipe
= intel_crtc
->pipe
;
4630 if (!intel_crtc
->active
)
4633 intel_crtc_disable_planes(crtc
);
4635 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4636 encoder
->disable(encoder
);
4638 drm_crtc_vblank_off(crtc
);
4639 assert_vblank_disabled(crtc
);
4641 if (intel_crtc
->config
->has_pch_encoder
)
4642 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4644 intel_disable_pipe(intel_crtc
);
4646 ironlake_pfit_disable(intel_crtc
);
4648 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4649 if (encoder
->post_disable
)
4650 encoder
->post_disable(encoder
);
4652 if (intel_crtc
->config
->has_pch_encoder
) {
4653 ironlake_fdi_disable(crtc
);
4655 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4657 if (HAS_PCH_CPT(dev
)) {
4658 /* disable TRANS_DP_CTL */
4659 reg
= TRANS_DP_CTL(pipe
);
4660 temp
= I915_READ(reg
);
4661 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4662 TRANS_DP_PORT_SEL_MASK
);
4663 temp
|= TRANS_DP_PORT_SEL_NONE
;
4664 I915_WRITE(reg
, temp
);
4666 /* disable DPLL_SEL */
4667 temp
= I915_READ(PCH_DPLL_SEL
);
4668 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4669 I915_WRITE(PCH_DPLL_SEL
, temp
);
4672 /* disable PCH DPLL */
4673 intel_disable_shared_dpll(intel_crtc
);
4675 ironlake_fdi_pll_disable(intel_crtc
);
4678 intel_crtc
->active
= false;
4679 intel_update_watermarks(crtc
);
4681 mutex_lock(&dev
->struct_mutex
);
4682 intel_fbc_update(dev
);
4683 mutex_unlock(&dev
->struct_mutex
);
4686 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4688 struct drm_device
*dev
= crtc
->dev
;
4689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4691 struct intel_encoder
*encoder
;
4692 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4694 if (!intel_crtc
->active
)
4697 intel_crtc_disable_planes(crtc
);
4699 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4700 intel_opregion_notify_encoder(encoder
, false);
4701 encoder
->disable(encoder
);
4704 drm_crtc_vblank_off(crtc
);
4705 assert_vblank_disabled(crtc
);
4707 if (intel_crtc
->config
->has_pch_encoder
)
4708 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4710 intel_disable_pipe(intel_crtc
);
4712 if (intel_crtc
->config
->dp_encoder_is_mst
)
4713 intel_ddi_set_vc_payload_alloc(crtc
, false);
4715 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4717 if (IS_SKYLAKE(dev
))
4718 skylake_pfit_disable(intel_crtc
);
4720 ironlake_pfit_disable(intel_crtc
);
4722 intel_ddi_disable_pipe_clock(intel_crtc
);
4724 if (intel_crtc
->config
->has_pch_encoder
) {
4725 lpt_disable_pch_transcoder(dev_priv
);
4726 intel_ddi_fdi_disable(crtc
);
4729 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4730 if (encoder
->post_disable
)
4731 encoder
->post_disable(encoder
);
4733 intel_crtc
->active
= false;
4734 intel_update_watermarks(crtc
);
4736 mutex_lock(&dev
->struct_mutex
);
4737 intel_fbc_update(dev
);
4738 mutex_unlock(&dev
->struct_mutex
);
4740 if (intel_crtc_to_shared_dpll(intel_crtc
))
4741 intel_disable_shared_dpll(intel_crtc
);
4744 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4747 intel_put_shared_dpll(intel_crtc
);
4751 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4753 struct drm_device
*dev
= crtc
->base
.dev
;
4754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4755 struct intel_crtc_state
*pipe_config
= crtc
->config
;
4757 if (!pipe_config
->gmch_pfit
.control
)
4761 * The panel fitter should only be adjusted whilst the pipe is disabled,
4762 * according to register description and PRM.
4764 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4765 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4767 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4768 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4770 /* Border color in case we don't scale up to the full screen. Black by
4771 * default, change to something else for debugging. */
4772 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4775 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4779 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4781 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4783 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4785 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4788 return POWER_DOMAIN_PORT_OTHER
;
4792 #define for_each_power_domain(domain, mask) \
4793 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4794 if ((1 << (domain)) & (mask))
4796 enum intel_display_power_domain
4797 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4799 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4800 struct intel_digital_port
*intel_dig_port
;
4802 switch (intel_encoder
->type
) {
4803 case INTEL_OUTPUT_UNKNOWN
:
4804 /* Only DDI platforms should ever use this output type */
4805 WARN_ON_ONCE(!HAS_DDI(dev
));
4806 case INTEL_OUTPUT_DISPLAYPORT
:
4807 case INTEL_OUTPUT_HDMI
:
4808 case INTEL_OUTPUT_EDP
:
4809 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4810 return port_to_power_domain(intel_dig_port
->port
);
4811 case INTEL_OUTPUT_DP_MST
:
4812 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4813 return port_to_power_domain(intel_dig_port
->port
);
4814 case INTEL_OUTPUT_ANALOG
:
4815 return POWER_DOMAIN_PORT_CRT
;
4816 case INTEL_OUTPUT_DSI
:
4817 return POWER_DOMAIN_PORT_DSI
;
4819 return POWER_DOMAIN_PORT_OTHER
;
4823 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4825 struct drm_device
*dev
= crtc
->dev
;
4826 struct intel_encoder
*intel_encoder
;
4827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4828 enum pipe pipe
= intel_crtc
->pipe
;
4830 enum transcoder transcoder
;
4832 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4834 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4835 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4836 if (intel_crtc
->config
->pch_pfit
.enabled
||
4837 intel_crtc
->config
->pch_pfit
.force_thru
)
4838 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4840 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4841 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4846 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4849 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4850 struct intel_crtc
*crtc
;
4853 * First get all needed power domains, then put all unneeded, to avoid
4854 * any unnecessary toggling of the power wells.
4856 for_each_intel_crtc(dev
, crtc
) {
4857 enum intel_display_power_domain domain
;
4859 if (!crtc
->base
.state
->enable
)
4862 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4864 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4865 intel_display_power_get(dev_priv
, domain
);
4868 if (dev_priv
->display
.modeset_global_resources
)
4869 dev_priv
->display
.modeset_global_resources(dev
);
4871 for_each_intel_crtc(dev
, crtc
) {
4872 enum intel_display_power_domain domain
;
4874 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4875 intel_display_power_put(dev_priv
, domain
);
4877 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4880 intel_display_set_init_power(dev_priv
, false);
4883 /* returns HPLL frequency in kHz */
4884 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4886 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4888 /* Obtain SKU information */
4889 mutex_lock(&dev_priv
->dpio_lock
);
4890 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4891 CCK_FUSE_HPLL_FREQ_MASK
;
4892 mutex_unlock(&dev_priv
->dpio_lock
);
4894 return vco_freq
[hpll_freq
] * 1000;
4897 static void vlv_update_cdclk(struct drm_device
*dev
)
4899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4901 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4902 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4903 dev_priv
->vlv_cdclk_freq
);
4906 * Program the gmbus_freq based on the cdclk frequency.
4907 * BSpec erroneously claims we should aim for 4MHz, but
4908 * in fact 1MHz is the correct frequency.
4910 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
4913 /* Adjust CDclk dividers to allow high res or save power if possible */
4914 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4919 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4921 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4923 else if (cdclk
== 266667)
4928 mutex_lock(&dev_priv
->rps
.hw_lock
);
4929 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4930 val
&= ~DSPFREQGUAR_MASK
;
4931 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4932 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4933 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4934 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4936 DRM_ERROR("timed out waiting for CDclk change\n");
4938 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4940 if (cdclk
== 400000) {
4943 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
4945 mutex_lock(&dev_priv
->dpio_lock
);
4946 /* adjust cdclk divider */
4947 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4948 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4950 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4952 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4953 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4955 DRM_ERROR("timed out waiting for CDclk change\n");
4956 mutex_unlock(&dev_priv
->dpio_lock
);
4959 mutex_lock(&dev_priv
->dpio_lock
);
4960 /* adjust self-refresh exit latency value */
4961 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4965 * For high bandwidth configs, we set a higher latency in the bunit
4966 * so that the core display fetch happens in time to avoid underruns.
4968 if (cdclk
== 400000)
4969 val
|= 4500 / 250; /* 4.5 usec */
4971 val
|= 3000 / 250; /* 3.0 usec */
4972 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4973 mutex_unlock(&dev_priv
->dpio_lock
);
4975 vlv_update_cdclk(dev
);
4978 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4983 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
5000 MISSING_CASE(cdclk
);
5004 mutex_lock(&dev_priv
->rps
.hw_lock
);
5005 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5006 val
&= ~DSPFREQGUAR_MASK_CHV
;
5007 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5008 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5009 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5010 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5012 DRM_ERROR("timed out waiting for CDclk change\n");
5014 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5016 vlv_update_cdclk(dev
);
5019 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5022 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5024 /* FIXME: Punit isn't quite ready yet */
5025 if (IS_CHERRYVIEW(dev_priv
->dev
))
5029 * Really only a few cases to deal with, as only 4 CDclks are supported:
5032 * 320/333MHz (depends on HPLL freq)
5034 * So we check to see whether we're above 90% of the lower bin and
5037 * We seem to get an unstable or solid color picture at 200MHz.
5038 * Not sure what's wrong. For now use 200MHz only when all pipes
5041 if (max_pixclk
> freq_320
*9/10)
5043 else if (max_pixclk
> 266667*9/10)
5045 else if (max_pixclk
> 0)
5051 /* compute the max pixel clock for new configuration */
5052 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
5054 struct drm_device
*dev
= dev_priv
->dev
;
5055 struct intel_crtc
*intel_crtc
;
5058 for_each_intel_crtc(dev
, intel_crtc
) {
5059 if (intel_crtc
->new_enabled
)
5060 max_pixclk
= max(max_pixclk
,
5061 intel_crtc
->new_config
->base
.adjusted_mode
.crtc_clock
);
5067 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
5068 unsigned *prepare_pipes
)
5070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5071 struct intel_crtc
*intel_crtc
;
5072 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
5074 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
5075 dev_priv
->vlv_cdclk_freq
)
5078 /* disable/enable all currently active pipes while we change cdclk */
5079 for_each_intel_crtc(dev
, intel_crtc
)
5080 if (intel_crtc
->base
.state
->enable
)
5081 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
5084 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
5086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5087 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
5088 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5090 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
5092 * FIXME: We can end up here with all power domains off, yet
5093 * with a CDCLK frequency other than the minimum. To account
5094 * for this take the PIPE-A power domain, which covers the HW
5095 * blocks needed for the following programming. This can be
5096 * removed once it's guaranteed that we get here either with
5097 * the minimum CDCLK set, or the required power domains
5100 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5102 if (IS_CHERRYVIEW(dev
))
5103 cherryview_set_cdclk(dev
, req_cdclk
);
5105 valleyview_set_cdclk(dev
, req_cdclk
);
5107 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5111 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5113 struct drm_device
*dev
= crtc
->dev
;
5114 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5115 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5116 struct intel_encoder
*encoder
;
5117 int pipe
= intel_crtc
->pipe
;
5120 WARN_ON(!crtc
->state
->enable
);
5122 if (intel_crtc
->active
)
5125 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5128 if (IS_CHERRYVIEW(dev
))
5129 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5131 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5134 if (intel_crtc
->config
->has_dp_encoder
)
5135 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5137 intel_set_pipe_timings(intel_crtc
);
5139 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5142 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5143 I915_WRITE(CHV_CANVAS(pipe
), 0);
5146 i9xx_set_pipeconf(intel_crtc
);
5148 intel_crtc
->active
= true;
5150 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5152 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5153 if (encoder
->pre_pll_enable
)
5154 encoder
->pre_pll_enable(encoder
);
5157 if (IS_CHERRYVIEW(dev
))
5158 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5160 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5163 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5164 if (encoder
->pre_enable
)
5165 encoder
->pre_enable(encoder
);
5167 i9xx_pfit_enable(intel_crtc
);
5169 intel_crtc_load_lut(crtc
);
5171 intel_update_watermarks(crtc
);
5172 intel_enable_pipe(intel_crtc
);
5174 assert_vblank_disabled(crtc
);
5175 drm_crtc_vblank_on(crtc
);
5177 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5178 encoder
->enable(encoder
);
5180 intel_crtc_enable_planes(crtc
);
5182 /* Underruns don't raise interrupts, so check manually. */
5183 i9xx_check_fifo_underruns(dev_priv
);
5186 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5188 struct drm_device
*dev
= crtc
->base
.dev
;
5189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5191 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5192 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5195 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5197 struct drm_device
*dev
= crtc
->dev
;
5198 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5199 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5200 struct intel_encoder
*encoder
;
5201 int pipe
= intel_crtc
->pipe
;
5203 WARN_ON(!crtc
->state
->enable
);
5205 if (intel_crtc
->active
)
5208 i9xx_set_pll_dividers(intel_crtc
);
5210 if (intel_crtc
->config
->has_dp_encoder
)
5211 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5213 intel_set_pipe_timings(intel_crtc
);
5215 i9xx_set_pipeconf(intel_crtc
);
5217 intel_crtc
->active
= true;
5220 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5222 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5223 if (encoder
->pre_enable
)
5224 encoder
->pre_enable(encoder
);
5226 i9xx_enable_pll(intel_crtc
);
5228 i9xx_pfit_enable(intel_crtc
);
5230 intel_crtc_load_lut(crtc
);
5232 intel_update_watermarks(crtc
);
5233 intel_enable_pipe(intel_crtc
);
5235 assert_vblank_disabled(crtc
);
5236 drm_crtc_vblank_on(crtc
);
5238 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5239 encoder
->enable(encoder
);
5241 intel_crtc_enable_planes(crtc
);
5244 * Gen2 reports pipe underruns whenever all planes are disabled.
5245 * So don't enable underrun reporting before at least some planes
5247 * FIXME: Need to fix the logic to work when we turn off all planes
5248 * but leave the pipe running.
5251 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5253 /* Underruns don't raise interrupts, so check manually. */
5254 i9xx_check_fifo_underruns(dev_priv
);
5257 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5259 struct drm_device
*dev
= crtc
->base
.dev
;
5260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5262 if (!crtc
->config
->gmch_pfit
.control
)
5265 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5267 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5268 I915_READ(PFIT_CONTROL
));
5269 I915_WRITE(PFIT_CONTROL
, 0);
5272 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5274 struct drm_device
*dev
= crtc
->dev
;
5275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5276 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5277 struct intel_encoder
*encoder
;
5278 int pipe
= intel_crtc
->pipe
;
5280 if (!intel_crtc
->active
)
5284 * Gen2 reports pipe underruns whenever all planes are disabled.
5285 * So diasble underrun reporting before all the planes get disabled.
5286 * FIXME: Need to fix the logic to work when we turn off all planes
5287 * but leave the pipe running.
5290 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5293 * Vblank time updates from the shadow to live plane control register
5294 * are blocked if the memory self-refresh mode is active at that
5295 * moment. So to make sure the plane gets truly disabled, disable
5296 * first the self-refresh mode. The self-refresh enable bit in turn
5297 * will be checked/applied by the HW only at the next frame start
5298 * event which is after the vblank start event, so we need to have a
5299 * wait-for-vblank between disabling the plane and the pipe.
5301 intel_set_memory_cxsr(dev_priv
, false);
5302 intel_crtc_disable_planes(crtc
);
5305 * On gen2 planes are double buffered but the pipe isn't, so we must
5306 * wait for planes to fully turn off before disabling the pipe.
5307 * We also need to wait on all gmch platforms because of the
5308 * self-refresh mode constraint explained above.
5310 intel_wait_for_vblank(dev
, pipe
);
5312 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5313 encoder
->disable(encoder
);
5315 drm_crtc_vblank_off(crtc
);
5316 assert_vblank_disabled(crtc
);
5318 intel_disable_pipe(intel_crtc
);
5320 i9xx_pfit_disable(intel_crtc
);
5322 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5323 if (encoder
->post_disable
)
5324 encoder
->post_disable(encoder
);
5326 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5327 if (IS_CHERRYVIEW(dev
))
5328 chv_disable_pll(dev_priv
, pipe
);
5329 else if (IS_VALLEYVIEW(dev
))
5330 vlv_disable_pll(dev_priv
, pipe
);
5332 i9xx_disable_pll(intel_crtc
);
5336 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5338 intel_crtc
->active
= false;
5339 intel_update_watermarks(crtc
);
5341 mutex_lock(&dev
->struct_mutex
);
5342 intel_fbc_update(dev
);
5343 mutex_unlock(&dev
->struct_mutex
);
5346 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5350 /* Master function to enable/disable CRTC and corresponding power wells */
5351 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5353 struct drm_device
*dev
= crtc
->dev
;
5354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5355 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5356 enum intel_display_power_domain domain
;
5357 unsigned long domains
;
5360 if (!intel_crtc
->active
) {
5361 domains
= get_crtc_power_domains(crtc
);
5362 for_each_power_domain(domain
, domains
)
5363 intel_display_power_get(dev_priv
, domain
);
5364 intel_crtc
->enabled_power_domains
= domains
;
5366 dev_priv
->display
.crtc_enable(crtc
);
5369 if (intel_crtc
->active
) {
5370 dev_priv
->display
.crtc_disable(crtc
);
5372 domains
= intel_crtc
->enabled_power_domains
;
5373 for_each_power_domain(domain
, domains
)
5374 intel_display_power_put(dev_priv
, domain
);
5375 intel_crtc
->enabled_power_domains
= 0;
5381 * Sets the power management mode of the pipe and plane.
5383 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5385 struct drm_device
*dev
= crtc
->dev
;
5386 struct intel_encoder
*intel_encoder
;
5387 bool enable
= false;
5389 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5390 enable
|= intel_encoder
->connectors_active
;
5392 intel_crtc_control(crtc
, enable
);
5395 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5397 struct drm_device
*dev
= crtc
->dev
;
5398 struct drm_connector
*connector
;
5399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5401 /* crtc should still be enabled when we disable it. */
5402 WARN_ON(!crtc
->state
->enable
);
5404 dev_priv
->display
.crtc_disable(crtc
);
5405 dev_priv
->display
.off(crtc
);
5407 crtc
->primary
->funcs
->disable_plane(crtc
->primary
);
5409 /* Update computed state. */
5410 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5411 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5414 if (connector
->encoder
->crtc
!= crtc
)
5417 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5418 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5422 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5424 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5426 drm_encoder_cleanup(encoder
);
5427 kfree(intel_encoder
);
5430 /* Simple dpms helper for encoders with just one connector, no cloning and only
5431 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5432 * state of the entire output pipe. */
5433 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5435 if (mode
== DRM_MODE_DPMS_ON
) {
5436 encoder
->connectors_active
= true;
5438 intel_crtc_update_dpms(encoder
->base
.crtc
);
5440 encoder
->connectors_active
= false;
5442 intel_crtc_update_dpms(encoder
->base
.crtc
);
5446 /* Cross check the actual hw state with our own modeset state tracking (and it's
5447 * internal consistency). */
5448 static void intel_connector_check_state(struct intel_connector
*connector
)
5450 if (connector
->get_hw_state(connector
)) {
5451 struct intel_encoder
*encoder
= connector
->encoder
;
5452 struct drm_crtc
*crtc
;
5453 bool encoder_enabled
;
5456 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5457 connector
->base
.base
.id
,
5458 connector
->base
.name
);
5460 /* there is no real hw state for MST connectors */
5461 if (connector
->mst_port
)
5464 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5465 "wrong connector dpms state\n");
5466 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
5467 "active connector not linked to encoder\n");
5470 I915_STATE_WARN(!encoder
->connectors_active
,
5471 "encoder->connectors_active not set\n");
5473 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5474 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
5475 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
5478 crtc
= encoder
->base
.crtc
;
5480 I915_STATE_WARN(!crtc
->state
->enable
,
5481 "crtc not enabled\n");
5482 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5483 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5484 "encoder active on the wrong pipe\n");
5489 /* Even simpler default implementation, if there's really no special case to
5491 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5493 /* All the simple cases only support two dpms states. */
5494 if (mode
!= DRM_MODE_DPMS_ON
)
5495 mode
= DRM_MODE_DPMS_OFF
;
5497 if (mode
== connector
->dpms
)
5500 connector
->dpms
= mode
;
5502 /* Only need to change hw state when actually enabled */
5503 if (connector
->encoder
)
5504 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5506 intel_modeset_check_state(connector
->dev
);
5509 /* Simple connector->get_hw_state implementation for encoders that support only
5510 * one connector and no cloning and hence the encoder state determines the state
5511 * of the connector. */
5512 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5515 struct intel_encoder
*encoder
= connector
->encoder
;
5517 return encoder
->get_hw_state(encoder
, &pipe
);
5520 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5521 struct intel_crtc_state
*pipe_config
)
5523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5524 struct intel_crtc
*pipe_B_crtc
=
5525 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5527 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5528 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5529 if (pipe_config
->fdi_lanes
> 4) {
5530 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5531 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5535 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5536 if (pipe_config
->fdi_lanes
> 2) {
5537 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5538 pipe_config
->fdi_lanes
);
5545 if (INTEL_INFO(dev
)->num_pipes
== 2)
5548 /* Ivybridge 3 pipe is really complicated */
5553 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5554 pipe_config
->fdi_lanes
> 2) {
5555 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5556 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5561 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5562 pipe_B_crtc
->config
->fdi_lanes
<= 2) {
5563 if (pipe_config
->fdi_lanes
> 2) {
5564 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5565 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5569 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5579 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5580 struct intel_crtc_state
*pipe_config
)
5582 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5583 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5584 int lane
, link_bw
, fdi_dotclock
;
5585 bool setup_ok
, needs_recompute
= false;
5588 /* FDI is a binary signal running at ~2.7GHz, encoding
5589 * each output octet as 10 bits. The actual frequency
5590 * is stored as a divider into a 100MHz clock, and the
5591 * mode pixel clock is stored in units of 1KHz.
5592 * Hence the bw of each lane in terms of the mode signal
5595 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5597 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5599 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5600 pipe_config
->pipe_bpp
);
5602 pipe_config
->fdi_lanes
= lane
;
5604 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5605 link_bw
, &pipe_config
->fdi_m_n
);
5607 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5608 intel_crtc
->pipe
, pipe_config
);
5609 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5610 pipe_config
->pipe_bpp
-= 2*3;
5611 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5612 pipe_config
->pipe_bpp
);
5613 needs_recompute
= true;
5614 pipe_config
->bw_constrained
= true;
5619 if (needs_recompute
)
5622 return setup_ok
? 0 : -EINVAL
;
5625 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5626 struct intel_crtc_state
*pipe_config
)
5628 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5629 hsw_crtc_supports_ips(crtc
) &&
5630 pipe_config
->pipe_bpp
<= 24;
5633 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5634 struct intel_crtc_state
*pipe_config
)
5636 struct drm_device
*dev
= crtc
->base
.dev
;
5637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5638 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5640 /* FIXME should check pixel clock limits on all platforms */
5641 if (INTEL_INFO(dev
)->gen
< 4) {
5643 dev_priv
->display
.get_display_clock_speed(dev
);
5646 * Enable pixel doubling when the dot clock
5647 * is > 90% of the (display) core speed.
5649 * GDG double wide on either pipe,
5650 * otherwise pipe A only.
5652 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5653 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5655 pipe_config
->double_wide
= true;
5658 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5663 * Pipe horizontal size must be even in:
5665 * - LVDS dual channel mode
5666 * - Double wide pipe
5668 if ((intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5669 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5670 pipe_config
->pipe_src_w
&= ~1;
5672 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5673 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5675 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5676 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5679 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5680 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5681 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5682 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5684 pipe_config
->pipe_bpp
= 8*3;
5688 hsw_compute_ips_config(crtc
, pipe_config
);
5690 if (pipe_config
->has_pch_encoder
)
5691 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5696 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5702 /* FIXME: Punit isn't quite ready yet */
5703 if (IS_CHERRYVIEW(dev
))
5706 if (dev_priv
->hpll_freq
== 0)
5707 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5709 mutex_lock(&dev_priv
->dpio_lock
);
5710 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5711 mutex_unlock(&dev_priv
->dpio_lock
);
5713 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5715 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5716 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5717 "cdclk change in progress\n");
5719 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5722 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5727 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5732 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5737 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5741 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5743 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5744 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5746 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5748 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5750 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5753 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5754 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5756 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5761 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5765 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5767 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5770 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5771 case GC_DISPLAY_CLOCK_333_MHZ
:
5774 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5780 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5785 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5788 /* Assume that the hardware is in the high speed state. This
5789 * should be the default.
5791 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5792 case GC_CLOCK_133_200
:
5793 case GC_CLOCK_100_200
:
5795 case GC_CLOCK_166_250
:
5797 case GC_CLOCK_100_133
:
5801 /* Shouldn't happen */
5805 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5811 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5813 while (*num
> DATA_LINK_M_N_MASK
||
5814 *den
> DATA_LINK_M_N_MASK
) {
5820 static void compute_m_n(unsigned int m
, unsigned int n
,
5821 uint32_t *ret_m
, uint32_t *ret_n
)
5823 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5824 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5825 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5829 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5830 int pixel_clock
, int link_clock
,
5831 struct intel_link_m_n
*m_n
)
5835 compute_m_n(bits_per_pixel
* pixel_clock
,
5836 link_clock
* nlanes
* 8,
5837 &m_n
->gmch_m
, &m_n
->gmch_n
);
5839 compute_m_n(pixel_clock
, link_clock
,
5840 &m_n
->link_m
, &m_n
->link_n
);
5843 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5845 if (i915
.panel_use_ssc
>= 0)
5846 return i915
.panel_use_ssc
!= 0;
5847 return dev_priv
->vbt
.lvds_use_ssc
5848 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5851 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5853 struct drm_device
*dev
= crtc
->base
.dev
;
5854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5857 if (IS_VALLEYVIEW(dev
)) {
5859 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5860 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5861 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5862 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5863 } else if (!IS_GEN2(dev
)) {
5872 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5874 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5877 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5879 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5882 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5883 struct intel_crtc_state
*crtc_state
,
5884 intel_clock_t
*reduced_clock
)
5886 struct drm_device
*dev
= crtc
->base
.dev
;
5889 if (IS_PINEVIEW(dev
)) {
5890 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
5892 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5894 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
5896 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5899 crtc_state
->dpll_hw_state
.fp0
= fp
;
5901 crtc
->lowfreq_avail
= false;
5902 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5903 reduced_clock
&& i915
.powersave
) {
5904 crtc_state
->dpll_hw_state
.fp1
= fp2
;
5905 crtc
->lowfreq_avail
= true;
5907 crtc_state
->dpll_hw_state
.fp1
= fp
;
5911 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5917 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5918 * and set it to a reasonable value instead.
5920 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5921 reg_val
&= 0xffffff00;
5922 reg_val
|= 0x00000030;
5923 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5925 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5926 reg_val
&= 0x8cffffff;
5927 reg_val
= 0x8c000000;
5928 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5930 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5931 reg_val
&= 0xffffff00;
5932 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5934 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5935 reg_val
&= 0x00ffffff;
5936 reg_val
|= 0xb0000000;
5937 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5940 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5941 struct intel_link_m_n
*m_n
)
5943 struct drm_device
*dev
= crtc
->base
.dev
;
5944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5945 int pipe
= crtc
->pipe
;
5947 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5948 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5949 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5950 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5953 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5954 struct intel_link_m_n
*m_n
,
5955 struct intel_link_m_n
*m2_n2
)
5957 struct drm_device
*dev
= crtc
->base
.dev
;
5958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5959 int pipe
= crtc
->pipe
;
5960 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
5962 if (INTEL_INFO(dev
)->gen
>= 5) {
5963 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5964 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5965 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5966 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5967 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5968 * for gen < 8) and if DRRS is supported (to make sure the
5969 * registers are not unnecessarily accessed).
5971 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
5972 crtc
->config
->has_drrs
) {
5973 I915_WRITE(PIPE_DATA_M2(transcoder
),
5974 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5975 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5976 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5977 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5980 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5981 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5982 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5983 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5987 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
5989 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
5992 dp_m_n
= &crtc
->config
->dp_m_n
;
5993 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
5994 } else if (m_n
== M2_N2
) {
5997 * M2_N2 registers are not supported. Hence m2_n2 divider value
5998 * needs to be programmed into M1_N1.
6000 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6002 DRM_ERROR("Unsupported divider value\n");
6006 if (crtc
->config
->has_pch_encoder
)
6007 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6009 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6012 static void vlv_update_pll(struct intel_crtc
*crtc
,
6013 struct intel_crtc_state
*pipe_config
)
6018 * Enable DPIO clock input. We should never disable the reference
6019 * clock for pipe B, since VGA hotplug / manual detection depends
6022 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6023 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6024 /* We should never disable this, set it here for state tracking */
6025 if (crtc
->pipe
== PIPE_B
)
6026 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6027 dpll
|= DPLL_VCO_ENABLE
;
6028 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6030 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6031 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6032 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6035 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6036 const struct intel_crtc_state
*pipe_config
)
6038 struct drm_device
*dev
= crtc
->base
.dev
;
6039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6040 int pipe
= crtc
->pipe
;
6042 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6043 u32 coreclk
, reg_val
;
6045 mutex_lock(&dev_priv
->dpio_lock
);
6047 bestn
= pipe_config
->dpll
.n
;
6048 bestm1
= pipe_config
->dpll
.m1
;
6049 bestm2
= pipe_config
->dpll
.m2
;
6050 bestp1
= pipe_config
->dpll
.p1
;
6051 bestp2
= pipe_config
->dpll
.p2
;
6053 /* See eDP HDMI DPIO driver vbios notes doc */
6055 /* PLL B needs special handling */
6057 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6059 /* Set up Tx target for periodic Rcomp update */
6060 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6062 /* Disable target IRef on PLL */
6063 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6064 reg_val
&= 0x00ffffff;
6065 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6067 /* Disable fast lock */
6068 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6070 /* Set idtafcrecal before PLL is enabled */
6071 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6072 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6073 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6074 mdiv
|= (1 << DPIO_K_SHIFT
);
6077 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6078 * but we don't support that).
6079 * Note: don't use the DAC post divider as it seems unstable.
6081 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6082 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6084 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6085 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6087 /* Set HBR and RBR LPF coefficients */
6088 if (pipe_config
->port_clock
== 162000 ||
6089 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6090 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6091 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6094 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6097 if (pipe_config
->has_dp_encoder
) {
6098 /* Use SSC source */
6100 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6103 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6105 } else { /* HDMI or VGA */
6106 /* Use bend source */
6108 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6111 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6115 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6116 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6117 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6118 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6119 coreclk
|= 0x01000000;
6120 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6122 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6123 mutex_unlock(&dev_priv
->dpio_lock
);
6126 static void chv_update_pll(struct intel_crtc
*crtc
,
6127 struct intel_crtc_state
*pipe_config
)
6129 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6130 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6132 if (crtc
->pipe
!= PIPE_A
)
6133 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6135 pipe_config
->dpll_hw_state
.dpll_md
=
6136 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6139 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6140 const struct intel_crtc_state
*pipe_config
)
6142 struct drm_device
*dev
= crtc
->base
.dev
;
6143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6144 int pipe
= crtc
->pipe
;
6145 int dpll_reg
= DPLL(crtc
->pipe
);
6146 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6147 u32 loopfilter
, intcoeff
;
6148 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6151 bestn
= pipe_config
->dpll
.n
;
6152 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6153 bestm1
= pipe_config
->dpll
.m1
;
6154 bestm2
= pipe_config
->dpll
.m2
>> 22;
6155 bestp1
= pipe_config
->dpll
.p1
;
6156 bestp2
= pipe_config
->dpll
.p2
;
6159 * Enable Refclk and SSC
6161 I915_WRITE(dpll_reg
,
6162 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6164 mutex_lock(&dev_priv
->dpio_lock
);
6166 /* p1 and p2 divider */
6167 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6168 5 << DPIO_CHV_S1_DIV_SHIFT
|
6169 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6170 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6171 1 << DPIO_CHV_K_DIV_SHIFT
);
6173 /* Feedback post-divider - m2 */
6174 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6176 /* Feedback refclk divider - n and m1 */
6177 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6178 DPIO_CHV_M1_DIV_BY_2
|
6179 1 << DPIO_CHV_N_DIV_SHIFT
);
6181 /* M2 fraction division */
6182 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6184 /* M2 fraction division enable */
6185 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6186 DPIO_CHV_FRAC_DIV_EN
|
6187 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6190 refclk
= i9xx_get_refclk(crtc
, 0);
6191 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6192 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6193 if (refclk
== 100000)
6195 else if (refclk
== 38400)
6199 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6200 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6203 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6204 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6207 mutex_unlock(&dev_priv
->dpio_lock
);
6211 * vlv_force_pll_on - forcibly enable just the PLL
6212 * @dev_priv: i915 private structure
6213 * @pipe: pipe PLL to enable
6214 * @dpll: PLL configuration
6216 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6217 * in cases where we need the PLL enabled even when @pipe is not going to
6220 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6221 const struct dpll
*dpll
)
6223 struct intel_crtc
*crtc
=
6224 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6225 struct intel_crtc_state pipe_config
= {
6226 .pixel_multiplier
= 1,
6230 if (IS_CHERRYVIEW(dev
)) {
6231 chv_update_pll(crtc
, &pipe_config
);
6232 chv_prepare_pll(crtc
, &pipe_config
);
6233 chv_enable_pll(crtc
, &pipe_config
);
6235 vlv_update_pll(crtc
, &pipe_config
);
6236 vlv_prepare_pll(crtc
, &pipe_config
);
6237 vlv_enable_pll(crtc
, &pipe_config
);
6242 * vlv_force_pll_off - forcibly disable just the PLL
6243 * @dev_priv: i915 private structure
6244 * @pipe: pipe PLL to disable
6246 * Disable the PLL for @pipe. To be used in cases where we need
6247 * the PLL enabled even when @pipe is not going to be enabled.
6249 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6251 if (IS_CHERRYVIEW(dev
))
6252 chv_disable_pll(to_i915(dev
), pipe
);
6254 vlv_disable_pll(to_i915(dev
), pipe
);
6257 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6258 struct intel_crtc_state
*crtc_state
,
6259 intel_clock_t
*reduced_clock
,
6262 struct drm_device
*dev
= crtc
->base
.dev
;
6263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6266 struct dpll
*clock
= &crtc_state
->dpll
;
6268 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6270 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6271 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6273 dpll
= DPLL_VGA_MODE_DIS
;
6275 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6276 dpll
|= DPLLB_MODE_LVDS
;
6278 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6280 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6281 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6282 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6286 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6288 if (crtc_state
->has_dp_encoder
)
6289 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6291 /* compute bitmask from p1 value */
6292 if (IS_PINEVIEW(dev
))
6293 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6295 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6296 if (IS_G4X(dev
) && reduced_clock
)
6297 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6299 switch (clock
->p2
) {
6301 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6304 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6307 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6310 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6313 if (INTEL_INFO(dev
)->gen
>= 4)
6314 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6316 if (crtc_state
->sdvo_tv_clock
)
6317 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6318 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6319 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6320 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6322 dpll
|= PLL_REF_INPUT_DREFCLK
;
6324 dpll
|= DPLL_VCO_ENABLE
;
6325 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6327 if (INTEL_INFO(dev
)->gen
>= 4) {
6328 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6329 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6330 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6334 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6335 struct intel_crtc_state
*crtc_state
,
6336 intel_clock_t
*reduced_clock
,
6339 struct drm_device
*dev
= crtc
->base
.dev
;
6340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6342 struct dpll
*clock
= &crtc_state
->dpll
;
6344 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6346 dpll
= DPLL_VGA_MODE_DIS
;
6348 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6349 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6352 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6354 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6356 dpll
|= PLL_P2_DIVIDE_BY_4
;
6359 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6360 dpll
|= DPLL_DVO_2X_MODE
;
6362 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6363 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6364 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6366 dpll
|= PLL_REF_INPUT_DREFCLK
;
6368 dpll
|= DPLL_VCO_ENABLE
;
6369 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6372 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6374 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6376 enum pipe pipe
= intel_crtc
->pipe
;
6377 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6378 struct drm_display_mode
*adjusted_mode
=
6379 &intel_crtc
->config
->base
.adjusted_mode
;
6380 uint32_t crtc_vtotal
, crtc_vblank_end
;
6383 /* We need to be careful not to changed the adjusted mode, for otherwise
6384 * the hw state checker will get angry at the mismatch. */
6385 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6386 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6388 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6389 /* the chip adds 2 halflines automatically */
6391 crtc_vblank_end
-= 1;
6393 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6394 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6396 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6397 adjusted_mode
->crtc_htotal
/ 2;
6399 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6402 if (INTEL_INFO(dev
)->gen
> 3)
6403 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6405 I915_WRITE(HTOTAL(cpu_transcoder
),
6406 (adjusted_mode
->crtc_hdisplay
- 1) |
6407 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6408 I915_WRITE(HBLANK(cpu_transcoder
),
6409 (adjusted_mode
->crtc_hblank_start
- 1) |
6410 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6411 I915_WRITE(HSYNC(cpu_transcoder
),
6412 (adjusted_mode
->crtc_hsync_start
- 1) |
6413 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6415 I915_WRITE(VTOTAL(cpu_transcoder
),
6416 (adjusted_mode
->crtc_vdisplay
- 1) |
6417 ((crtc_vtotal
- 1) << 16));
6418 I915_WRITE(VBLANK(cpu_transcoder
),
6419 (adjusted_mode
->crtc_vblank_start
- 1) |
6420 ((crtc_vblank_end
- 1) << 16));
6421 I915_WRITE(VSYNC(cpu_transcoder
),
6422 (adjusted_mode
->crtc_vsync_start
- 1) |
6423 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6425 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6426 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6427 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6429 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6430 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6431 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6433 /* pipesrc controls the size that is scaled from, which should
6434 * always be the user's requested size.
6436 I915_WRITE(PIPESRC(pipe
),
6437 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
6438 (intel_crtc
->config
->pipe_src_h
- 1));
6441 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6442 struct intel_crtc_state
*pipe_config
)
6444 struct drm_device
*dev
= crtc
->base
.dev
;
6445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6446 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6449 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6450 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6451 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6452 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6453 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6454 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6455 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6456 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6457 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6459 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6460 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6461 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6462 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6463 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6464 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6465 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6466 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6467 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6469 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6470 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6471 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
6472 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
6475 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6476 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6477 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6479 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
6480 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
6483 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6484 struct intel_crtc_state
*pipe_config
)
6486 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
6487 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
6488 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
6489 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
6491 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
6492 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
6493 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
6494 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
6496 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
6498 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6499 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
6502 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6504 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6510 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6511 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6512 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6514 if (intel_crtc
->config
->double_wide
)
6515 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6517 /* only g4x and later have fancy bpc/dither controls */
6518 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6519 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6520 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
6521 pipeconf
|= PIPECONF_DITHER_EN
|
6522 PIPECONF_DITHER_TYPE_SP
;
6524 switch (intel_crtc
->config
->pipe_bpp
) {
6526 pipeconf
|= PIPECONF_6BPC
;
6529 pipeconf
|= PIPECONF_8BPC
;
6532 pipeconf
|= PIPECONF_10BPC
;
6535 /* Case prevented by intel_choose_pipe_bpp_dither. */
6540 if (HAS_PIPE_CXSR(dev
)) {
6541 if (intel_crtc
->lowfreq_avail
) {
6542 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6543 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6545 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6549 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6550 if (INTEL_INFO(dev
)->gen
< 4 ||
6551 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6552 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6554 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6556 pipeconf
|= PIPECONF_PROGRESSIVE
;
6558 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
6559 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6561 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6562 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6565 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
6566 struct intel_crtc_state
*crtc_state
)
6568 struct drm_device
*dev
= crtc
->base
.dev
;
6569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6570 int refclk
, num_connectors
= 0;
6571 intel_clock_t clock
, reduced_clock
;
6572 bool ok
, has_reduced_clock
= false;
6573 bool is_lvds
= false, is_dsi
= false;
6574 struct intel_encoder
*encoder
;
6575 const intel_limit_t
*limit
;
6577 for_each_intel_encoder(dev
, encoder
) {
6578 if (encoder
->new_crtc
!= crtc
)
6581 switch (encoder
->type
) {
6582 case INTEL_OUTPUT_LVDS
:
6585 case INTEL_OUTPUT_DSI
:
6598 if (!crtc_state
->clock_set
) {
6599 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6602 * Returns a set of divisors for the desired target clock with
6603 * the given refclk, or FALSE. The returned values represent
6604 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6607 limit
= intel_limit(crtc
, refclk
);
6608 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6609 crtc_state
->port_clock
,
6610 refclk
, NULL
, &clock
);
6612 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6616 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6618 * Ensure we match the reduced clock's P to the target
6619 * clock. If the clocks don't match, we can't switch
6620 * the display clock by using the FP0/FP1. In such case
6621 * we will disable the LVDS downclock feature.
6624 dev_priv
->display
.find_dpll(limit
, crtc
,
6625 dev_priv
->lvds_downclock
,
6629 /* Compat-code for transition, will disappear. */
6630 crtc_state
->dpll
.n
= clock
.n
;
6631 crtc_state
->dpll
.m1
= clock
.m1
;
6632 crtc_state
->dpll
.m2
= clock
.m2
;
6633 crtc_state
->dpll
.p1
= clock
.p1
;
6634 crtc_state
->dpll
.p2
= clock
.p2
;
6638 i8xx_update_pll(crtc
, crtc_state
,
6639 has_reduced_clock
? &reduced_clock
: NULL
,
6641 } else if (IS_CHERRYVIEW(dev
)) {
6642 chv_update_pll(crtc
, crtc_state
);
6643 } else if (IS_VALLEYVIEW(dev
)) {
6644 vlv_update_pll(crtc
, crtc_state
);
6646 i9xx_update_pll(crtc
, crtc_state
,
6647 has_reduced_clock
? &reduced_clock
: NULL
,
6654 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6655 struct intel_crtc_state
*pipe_config
)
6657 struct drm_device
*dev
= crtc
->base
.dev
;
6658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6661 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6664 tmp
= I915_READ(PFIT_CONTROL
);
6665 if (!(tmp
& PFIT_ENABLE
))
6668 /* Check whether the pfit is attached to our pipe. */
6669 if (INTEL_INFO(dev
)->gen
< 4) {
6670 if (crtc
->pipe
!= PIPE_B
)
6673 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6677 pipe_config
->gmch_pfit
.control
= tmp
;
6678 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6679 if (INTEL_INFO(dev
)->gen
< 5)
6680 pipe_config
->gmch_pfit
.lvds_border_bits
=
6681 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6684 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6685 struct intel_crtc_state
*pipe_config
)
6687 struct drm_device
*dev
= crtc
->base
.dev
;
6688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6689 int pipe
= pipe_config
->cpu_transcoder
;
6690 intel_clock_t clock
;
6692 int refclk
= 100000;
6694 /* In case of MIPI DPLL will not even be used */
6695 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6698 mutex_lock(&dev_priv
->dpio_lock
);
6699 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6700 mutex_unlock(&dev_priv
->dpio_lock
);
6702 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6703 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6704 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6705 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6706 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6708 vlv_clock(refclk
, &clock
);
6710 /* clock.dot is the fast clock */
6711 pipe_config
->port_clock
= clock
.dot
/ 5;
6715 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
6716 struct intel_initial_plane_config
*plane_config
)
6718 struct drm_device
*dev
= crtc
->base
.dev
;
6719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6720 u32 val
, base
, offset
;
6721 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6722 int fourcc
, pixel_format
;
6724 struct drm_framebuffer
*fb
;
6725 struct intel_framebuffer
*intel_fb
;
6727 val
= I915_READ(DSPCNTR(plane
));
6728 if (!(val
& DISPLAY_PLANE_ENABLE
))
6731 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6733 DRM_DEBUG_KMS("failed to alloc fb\n");
6737 fb
= &intel_fb
->base
;
6739 if (INTEL_INFO(dev
)->gen
>= 4) {
6740 if (val
& DISPPLANE_TILED
) {
6741 plane_config
->tiling
= I915_TILING_X
;
6742 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
6746 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6747 fourcc
= i9xx_format_to_fourcc(pixel_format
);
6748 fb
->pixel_format
= fourcc
;
6749 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
6751 if (INTEL_INFO(dev
)->gen
>= 4) {
6752 if (plane_config
->tiling
)
6753 offset
= I915_READ(DSPTILEOFF(plane
));
6755 offset
= I915_READ(DSPLINOFF(plane
));
6756 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6758 base
= I915_READ(DSPADDR(plane
));
6760 plane_config
->base
= base
;
6762 val
= I915_READ(PIPESRC(pipe
));
6763 fb
->width
= ((val
>> 16) & 0xfff) + 1;
6764 fb
->height
= ((val
>> 0) & 0xfff) + 1;
6766 val
= I915_READ(DSPSTRIDE(pipe
));
6767 fb
->pitches
[0] = val
& 0xffffffc0;
6769 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
6773 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
6775 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6776 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
6777 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
6778 plane_config
->size
);
6780 plane_config
->fb
= intel_fb
;
6783 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6784 struct intel_crtc_state
*pipe_config
)
6786 struct drm_device
*dev
= crtc
->base
.dev
;
6787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6788 int pipe
= pipe_config
->cpu_transcoder
;
6789 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6790 intel_clock_t clock
;
6791 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6792 int refclk
= 100000;
6794 mutex_lock(&dev_priv
->dpio_lock
);
6795 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6796 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6797 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6798 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6799 mutex_unlock(&dev_priv
->dpio_lock
);
6801 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6802 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6803 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6804 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6805 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6807 chv_clock(refclk
, &clock
);
6809 /* clock.dot is the fast clock */
6810 pipe_config
->port_clock
= clock
.dot
/ 5;
6813 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6814 struct intel_crtc_state
*pipe_config
)
6816 struct drm_device
*dev
= crtc
->base
.dev
;
6817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6820 if (!intel_display_power_is_enabled(dev_priv
,
6821 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6824 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6825 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6827 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6828 if (!(tmp
& PIPECONF_ENABLE
))
6831 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6832 switch (tmp
& PIPECONF_BPC_MASK
) {
6834 pipe_config
->pipe_bpp
= 18;
6837 pipe_config
->pipe_bpp
= 24;
6839 case PIPECONF_10BPC
:
6840 pipe_config
->pipe_bpp
= 30;
6847 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6848 pipe_config
->limited_color_range
= true;
6850 if (INTEL_INFO(dev
)->gen
< 4)
6851 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6853 intel_get_pipe_timings(crtc
, pipe_config
);
6855 i9xx_get_pfit_config(crtc
, pipe_config
);
6857 if (INTEL_INFO(dev
)->gen
>= 4) {
6858 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6859 pipe_config
->pixel_multiplier
=
6860 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6861 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6862 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6863 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6864 tmp
= I915_READ(DPLL(crtc
->pipe
));
6865 pipe_config
->pixel_multiplier
=
6866 ((tmp
& SDVO_MULTIPLIER_MASK
)
6867 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6869 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6870 * port and will be fixed up in the encoder->get_config
6872 pipe_config
->pixel_multiplier
= 1;
6874 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6875 if (!IS_VALLEYVIEW(dev
)) {
6877 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6878 * on 830. Filter it out here so that we don't
6879 * report errors due to that.
6882 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6884 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6885 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6887 /* Mask out read-only status bits. */
6888 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6889 DPLL_PORTC_READY_MASK
|
6890 DPLL_PORTB_READY_MASK
);
6893 if (IS_CHERRYVIEW(dev
))
6894 chv_crtc_clock_get(crtc
, pipe_config
);
6895 else if (IS_VALLEYVIEW(dev
))
6896 vlv_crtc_clock_get(crtc
, pipe_config
);
6898 i9xx_crtc_clock_get(crtc
, pipe_config
);
6903 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6906 struct intel_encoder
*encoder
;
6908 bool has_lvds
= false;
6909 bool has_cpu_edp
= false;
6910 bool has_panel
= false;
6911 bool has_ck505
= false;
6912 bool can_ssc
= false;
6914 /* We need to take the global config into account */
6915 for_each_intel_encoder(dev
, encoder
) {
6916 switch (encoder
->type
) {
6917 case INTEL_OUTPUT_LVDS
:
6921 case INTEL_OUTPUT_EDP
:
6923 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6931 if (HAS_PCH_IBX(dev
)) {
6932 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6933 can_ssc
= has_ck505
;
6939 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6940 has_panel
, has_lvds
, has_ck505
);
6942 /* Ironlake: try to setup display ref clock before DPLL
6943 * enabling. This is only under driver's control after
6944 * PCH B stepping, previous chipset stepping should be
6945 * ignoring this setting.
6947 val
= I915_READ(PCH_DREF_CONTROL
);
6949 /* As we must carefully and slowly disable/enable each source in turn,
6950 * compute the final state we want first and check if we need to
6951 * make any changes at all.
6954 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6956 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6958 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6960 final
&= ~DREF_SSC_SOURCE_MASK
;
6961 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6962 final
&= ~DREF_SSC1_ENABLE
;
6965 final
|= DREF_SSC_SOURCE_ENABLE
;
6967 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6968 final
|= DREF_SSC1_ENABLE
;
6971 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6972 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6974 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6976 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6978 final
|= DREF_SSC_SOURCE_DISABLE
;
6979 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6985 /* Always enable nonspread source */
6986 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6989 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6991 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6994 val
&= ~DREF_SSC_SOURCE_MASK
;
6995 val
|= DREF_SSC_SOURCE_ENABLE
;
6997 /* SSC must be turned on before enabling the CPU output */
6998 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6999 DRM_DEBUG_KMS("Using SSC on panel\n");
7000 val
|= DREF_SSC1_ENABLE
;
7002 val
&= ~DREF_SSC1_ENABLE
;
7004 /* Get SSC going before enabling the outputs */
7005 I915_WRITE(PCH_DREF_CONTROL
, val
);
7006 POSTING_READ(PCH_DREF_CONTROL
);
7009 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7011 /* Enable CPU source on CPU attached eDP */
7013 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7014 DRM_DEBUG_KMS("Using SSC on eDP\n");
7015 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7017 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7019 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7021 I915_WRITE(PCH_DREF_CONTROL
, val
);
7022 POSTING_READ(PCH_DREF_CONTROL
);
7025 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7027 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7029 /* Turn off CPU output */
7030 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7032 I915_WRITE(PCH_DREF_CONTROL
, val
);
7033 POSTING_READ(PCH_DREF_CONTROL
);
7036 /* Turn off the SSC source */
7037 val
&= ~DREF_SSC_SOURCE_MASK
;
7038 val
|= DREF_SSC_SOURCE_DISABLE
;
7041 val
&= ~DREF_SSC1_ENABLE
;
7043 I915_WRITE(PCH_DREF_CONTROL
, val
);
7044 POSTING_READ(PCH_DREF_CONTROL
);
7048 BUG_ON(val
!= final
);
7051 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7055 tmp
= I915_READ(SOUTH_CHICKEN2
);
7056 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7057 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7059 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7060 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7061 DRM_ERROR("FDI mPHY reset assert timeout\n");
7063 tmp
= I915_READ(SOUTH_CHICKEN2
);
7064 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7065 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7067 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7068 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7069 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7072 /* WaMPhyProgramming:hsw */
7073 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7077 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7078 tmp
&= ~(0xFF << 24);
7079 tmp
|= (0x12 << 24);
7080 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7082 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7084 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7086 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7088 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7090 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7091 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7092 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7094 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7095 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7096 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7098 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7101 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
7103 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
7106 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7108 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7111 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7113 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7116 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7118 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7119 tmp
&= ~(0xFF << 16);
7120 tmp
|= (0x1C << 16);
7121 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7123 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7124 tmp
&= ~(0xFF << 16);
7125 tmp
|= (0x1C << 16);
7126 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7128 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7130 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7132 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7134 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7136 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7137 tmp
&= ~(0xF << 28);
7139 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7141 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7142 tmp
&= ~(0xF << 28);
7144 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7147 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7148 * Programming" based on the parameters passed:
7149 * - Sequence to enable CLKOUT_DP
7150 * - Sequence to enable CLKOUT_DP without spread
7151 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7153 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
7156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7159 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7161 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
7162 with_fdi
, "LP PCH doesn't have FDI\n"))
7165 mutex_lock(&dev_priv
->dpio_lock
);
7167 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7168 tmp
&= ~SBI_SSCCTL_DISABLE
;
7169 tmp
|= SBI_SSCCTL_PATHALT
;
7170 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7175 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7176 tmp
&= ~SBI_SSCCTL_PATHALT
;
7177 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7180 lpt_reset_fdi_mphy(dev_priv
);
7181 lpt_program_fdi_mphy(dev_priv
);
7185 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7186 SBI_GEN0
: SBI_DBUFF0
;
7187 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7188 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7189 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7191 mutex_unlock(&dev_priv
->dpio_lock
);
7194 /* Sequence to disable CLKOUT_DP */
7195 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7200 mutex_lock(&dev_priv
->dpio_lock
);
7202 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7203 SBI_GEN0
: SBI_DBUFF0
;
7204 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7205 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7206 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7208 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7209 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7210 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7211 tmp
|= SBI_SSCCTL_PATHALT
;
7212 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7215 tmp
|= SBI_SSCCTL_DISABLE
;
7216 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7219 mutex_unlock(&dev_priv
->dpio_lock
);
7222 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7224 struct intel_encoder
*encoder
;
7225 bool has_vga
= false;
7227 for_each_intel_encoder(dev
, encoder
) {
7228 switch (encoder
->type
) {
7229 case INTEL_OUTPUT_ANALOG
:
7238 lpt_enable_clkout_dp(dev
, true, true);
7240 lpt_disable_clkout_dp(dev
);
7244 * Initialize reference clocks when the driver loads
7246 void intel_init_pch_refclk(struct drm_device
*dev
)
7248 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7249 ironlake_init_pch_refclk(dev
);
7250 else if (HAS_PCH_LPT(dev
))
7251 lpt_init_pch_refclk(dev
);
7254 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7256 struct drm_device
*dev
= crtc
->dev
;
7257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7258 struct intel_encoder
*encoder
;
7259 int num_connectors
= 0;
7260 bool is_lvds
= false;
7262 for_each_intel_encoder(dev
, encoder
) {
7263 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7266 switch (encoder
->type
) {
7267 case INTEL_OUTPUT_LVDS
:
7276 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7277 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7278 dev_priv
->vbt
.lvds_ssc_freq
);
7279 return dev_priv
->vbt
.lvds_ssc_freq
;
7285 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7287 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7289 int pipe
= intel_crtc
->pipe
;
7294 switch (intel_crtc
->config
->pipe_bpp
) {
7296 val
|= PIPECONF_6BPC
;
7299 val
|= PIPECONF_8BPC
;
7302 val
|= PIPECONF_10BPC
;
7305 val
|= PIPECONF_12BPC
;
7308 /* Case prevented by intel_choose_pipe_bpp_dither. */
7312 if (intel_crtc
->config
->dither
)
7313 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7315 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7316 val
|= PIPECONF_INTERLACED_ILK
;
7318 val
|= PIPECONF_PROGRESSIVE
;
7320 if (intel_crtc
->config
->limited_color_range
)
7321 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7323 I915_WRITE(PIPECONF(pipe
), val
);
7324 POSTING_READ(PIPECONF(pipe
));
7328 * Set up the pipe CSC unit.
7330 * Currently only full range RGB to limited range RGB conversion
7331 * is supported, but eventually this should handle various
7332 * RGB<->YCbCr scenarios as well.
7334 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7336 struct drm_device
*dev
= crtc
->dev
;
7337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7338 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7339 int pipe
= intel_crtc
->pipe
;
7340 uint16_t coeff
= 0x7800; /* 1.0 */
7343 * TODO: Check what kind of values actually come out of the pipe
7344 * with these coeff/postoff values and adjust to get the best
7345 * accuracy. Perhaps we even need to take the bpc value into
7349 if (intel_crtc
->config
->limited_color_range
)
7350 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7353 * GY/GU and RY/RU should be the other way around according
7354 * to BSpec, but reality doesn't agree. Just set them up in
7355 * a way that results in the correct picture.
7357 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7358 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7360 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7361 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7363 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7364 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7366 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7367 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7368 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7370 if (INTEL_INFO(dev
)->gen
> 6) {
7371 uint16_t postoff
= 0;
7373 if (intel_crtc
->config
->limited_color_range
)
7374 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7376 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7377 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7378 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7380 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7382 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7384 if (intel_crtc
->config
->limited_color_range
)
7385 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7387 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7391 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7393 struct drm_device
*dev
= crtc
->dev
;
7394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7395 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7396 enum pipe pipe
= intel_crtc
->pipe
;
7397 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7402 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
7403 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7405 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7406 val
|= PIPECONF_INTERLACED_ILK
;
7408 val
|= PIPECONF_PROGRESSIVE
;
7410 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7411 POSTING_READ(PIPECONF(cpu_transcoder
));
7413 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7414 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7416 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7419 switch (intel_crtc
->config
->pipe_bpp
) {
7421 val
|= PIPEMISC_DITHER_6_BPC
;
7424 val
|= PIPEMISC_DITHER_8_BPC
;
7427 val
|= PIPEMISC_DITHER_10_BPC
;
7430 val
|= PIPEMISC_DITHER_12_BPC
;
7433 /* Case prevented by pipe_config_set_bpp. */
7437 if (intel_crtc
->config
->dither
)
7438 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7440 I915_WRITE(PIPEMISC(pipe
), val
);
7444 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7445 struct intel_crtc_state
*crtc_state
,
7446 intel_clock_t
*clock
,
7447 bool *has_reduced_clock
,
7448 intel_clock_t
*reduced_clock
)
7450 struct drm_device
*dev
= crtc
->dev
;
7451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7452 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7454 const intel_limit_t
*limit
;
7455 bool ret
, is_lvds
= false;
7457 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7459 refclk
= ironlake_get_refclk(crtc
);
7462 * Returns a set of divisors for the desired target clock with the given
7463 * refclk, or FALSE. The returned values represent the clock equation:
7464 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7466 limit
= intel_limit(intel_crtc
, refclk
);
7467 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7468 crtc_state
->port_clock
,
7469 refclk
, NULL
, clock
);
7473 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7475 * Ensure we match the reduced clock's P to the target clock.
7476 * If the clocks don't match, we can't switch the display clock
7477 * by using the FP0/FP1. In such case we will disable the LVDS
7478 * downclock feature.
7480 *has_reduced_clock
=
7481 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7482 dev_priv
->lvds_downclock
,
7490 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7493 * Account for spread spectrum to avoid
7494 * oversubscribing the link. Max center spread
7495 * is 2.5%; use 5% for safety's sake.
7497 u32 bps
= target_clock
* bpp
* 21 / 20;
7498 return DIV_ROUND_UP(bps
, link_bw
* 8);
7501 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7503 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7506 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7507 struct intel_crtc_state
*crtc_state
,
7509 intel_clock_t
*reduced_clock
, u32
*fp2
)
7511 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7512 struct drm_device
*dev
= crtc
->dev
;
7513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7514 struct intel_encoder
*intel_encoder
;
7516 int factor
, num_connectors
= 0;
7517 bool is_lvds
= false, is_sdvo
= false;
7519 for_each_intel_encoder(dev
, intel_encoder
) {
7520 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7523 switch (intel_encoder
->type
) {
7524 case INTEL_OUTPUT_LVDS
:
7527 case INTEL_OUTPUT_SDVO
:
7528 case INTEL_OUTPUT_HDMI
:
7538 /* Enable autotuning of the PLL clock (if permissible) */
7541 if ((intel_panel_use_ssc(dev_priv
) &&
7542 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7543 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7545 } else if (crtc_state
->sdvo_tv_clock
)
7548 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
7551 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7557 dpll
|= DPLLB_MODE_LVDS
;
7559 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7561 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7562 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7565 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7566 if (crtc_state
->has_dp_encoder
)
7567 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7569 /* compute bitmask from p1 value */
7570 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7572 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7574 switch (crtc_state
->dpll
.p2
) {
7576 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7579 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7582 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7585 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7589 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7590 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7592 dpll
|= PLL_REF_INPUT_DREFCLK
;
7594 return dpll
| DPLL_VCO_ENABLE
;
7597 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
7598 struct intel_crtc_state
*crtc_state
)
7600 struct drm_device
*dev
= crtc
->base
.dev
;
7601 intel_clock_t clock
, reduced_clock
;
7602 u32 dpll
= 0, fp
= 0, fp2
= 0;
7603 bool ok
, has_reduced_clock
= false;
7604 bool is_lvds
= false;
7605 struct intel_shared_dpll
*pll
;
7607 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7609 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7610 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7612 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
7613 &has_reduced_clock
, &reduced_clock
);
7614 if (!ok
&& !crtc_state
->clock_set
) {
7615 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7618 /* Compat-code for transition, will disappear. */
7619 if (!crtc_state
->clock_set
) {
7620 crtc_state
->dpll
.n
= clock
.n
;
7621 crtc_state
->dpll
.m1
= clock
.m1
;
7622 crtc_state
->dpll
.m2
= clock
.m2
;
7623 crtc_state
->dpll
.p1
= clock
.p1
;
7624 crtc_state
->dpll
.p2
= clock
.p2
;
7627 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7628 if (crtc_state
->has_pch_encoder
) {
7629 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7630 if (has_reduced_clock
)
7631 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7633 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
7634 &fp
, &reduced_clock
,
7635 has_reduced_clock
? &fp2
: NULL
);
7637 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7638 crtc_state
->dpll_hw_state
.fp0
= fp
;
7639 if (has_reduced_clock
)
7640 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7642 crtc_state
->dpll_hw_state
.fp1
= fp
;
7644 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
7646 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7647 pipe_name(crtc
->pipe
));
7652 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7653 crtc
->lowfreq_avail
= true;
7655 crtc
->lowfreq_avail
= false;
7660 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7661 struct intel_link_m_n
*m_n
)
7663 struct drm_device
*dev
= crtc
->base
.dev
;
7664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7665 enum pipe pipe
= crtc
->pipe
;
7667 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7668 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7669 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7671 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7672 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7673 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7676 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7677 enum transcoder transcoder
,
7678 struct intel_link_m_n
*m_n
,
7679 struct intel_link_m_n
*m2_n2
)
7681 struct drm_device
*dev
= crtc
->base
.dev
;
7682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7683 enum pipe pipe
= crtc
->pipe
;
7685 if (INTEL_INFO(dev
)->gen
>= 5) {
7686 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7687 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7688 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7690 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7691 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7692 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7693 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7694 * gen < 8) and if DRRS is supported (to make sure the
7695 * registers are not unnecessarily read).
7697 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7698 crtc
->config
->has_drrs
) {
7699 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7700 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7701 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7703 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7704 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7705 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7708 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7709 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7710 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7712 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7713 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7714 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7718 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7719 struct intel_crtc_state
*pipe_config
)
7721 if (pipe_config
->has_pch_encoder
)
7722 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7724 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7725 &pipe_config
->dp_m_n
,
7726 &pipe_config
->dp_m2_n2
);
7729 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7730 struct intel_crtc_state
*pipe_config
)
7732 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7733 &pipe_config
->fdi_m_n
, NULL
);
7736 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
7737 struct intel_crtc_state
*pipe_config
)
7739 struct drm_device
*dev
= crtc
->base
.dev
;
7740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7743 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
7745 if (tmp
& PS_ENABLE
) {
7746 pipe_config
->pch_pfit
.enabled
= true;
7747 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
7748 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
7753 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
7754 struct intel_initial_plane_config
*plane_config
)
7756 struct drm_device
*dev
= crtc
->base
.dev
;
7757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7758 u32 val
, base
, offset
, stride_mult
, tiling
;
7759 int pipe
= crtc
->pipe
;
7760 int fourcc
, pixel_format
;
7762 struct drm_framebuffer
*fb
;
7763 struct intel_framebuffer
*intel_fb
;
7765 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7767 DRM_DEBUG_KMS("failed to alloc fb\n");
7771 fb
= &intel_fb
->base
;
7773 val
= I915_READ(PLANE_CTL(pipe
, 0));
7774 if (!(val
& PLANE_CTL_ENABLE
))
7777 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
7778 fourcc
= skl_format_to_fourcc(pixel_format
,
7779 val
& PLANE_CTL_ORDER_RGBX
,
7780 val
& PLANE_CTL_ALPHA_MASK
);
7781 fb
->pixel_format
= fourcc
;
7782 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7784 tiling
= val
& PLANE_CTL_TILED_MASK
;
7786 case PLANE_CTL_TILED_LINEAR
:
7787 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
7789 case PLANE_CTL_TILED_X
:
7790 plane_config
->tiling
= I915_TILING_X
;
7791 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7793 case PLANE_CTL_TILED_Y
:
7794 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
7796 case PLANE_CTL_TILED_YF
:
7797 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
7800 MISSING_CASE(tiling
);
7804 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
7805 plane_config
->base
= base
;
7807 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
7809 val
= I915_READ(PLANE_SIZE(pipe
, 0));
7810 fb
->height
= ((val
>> 16) & 0xfff) + 1;
7811 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
7813 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
7814 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
7816 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
7818 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7822 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7824 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7825 pipe_name(pipe
), fb
->width
, fb
->height
,
7826 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7827 plane_config
->size
);
7829 plane_config
->fb
= intel_fb
;
7836 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7837 struct intel_crtc_state
*pipe_config
)
7839 struct drm_device
*dev
= crtc
->base
.dev
;
7840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7843 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7845 if (tmp
& PF_ENABLE
) {
7846 pipe_config
->pch_pfit
.enabled
= true;
7847 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7848 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7850 /* We currently do not free assignements of panel fitters on
7851 * ivb/hsw (since we don't use the higher upscaling modes which
7852 * differentiates them) so just WARN about this case for now. */
7854 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7855 PF_PIPE_SEL_IVB(crtc
->pipe
));
7861 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
7862 struct intel_initial_plane_config
*plane_config
)
7864 struct drm_device
*dev
= crtc
->base
.dev
;
7865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7866 u32 val
, base
, offset
;
7867 int pipe
= crtc
->pipe
;
7868 int fourcc
, pixel_format
;
7870 struct drm_framebuffer
*fb
;
7871 struct intel_framebuffer
*intel_fb
;
7873 val
= I915_READ(DSPCNTR(pipe
));
7874 if (!(val
& DISPLAY_PLANE_ENABLE
))
7877 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7879 DRM_DEBUG_KMS("failed to alloc fb\n");
7883 fb
= &intel_fb
->base
;
7885 if (INTEL_INFO(dev
)->gen
>= 4) {
7886 if (val
& DISPPLANE_TILED
) {
7887 plane_config
->tiling
= I915_TILING_X
;
7888 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7892 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7893 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7894 fb
->pixel_format
= fourcc
;
7895 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7897 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
7898 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7899 offset
= I915_READ(DSPOFFSET(pipe
));
7901 if (plane_config
->tiling
)
7902 offset
= I915_READ(DSPTILEOFF(pipe
));
7904 offset
= I915_READ(DSPLINOFF(pipe
));
7906 plane_config
->base
= base
;
7908 val
= I915_READ(PIPESRC(pipe
));
7909 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7910 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7912 val
= I915_READ(DSPSTRIDE(pipe
));
7913 fb
->pitches
[0] = val
& 0xffffffc0;
7915 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7919 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7921 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7922 pipe_name(pipe
), fb
->width
, fb
->height
,
7923 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7924 plane_config
->size
);
7926 plane_config
->fb
= intel_fb
;
7929 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7930 struct intel_crtc_state
*pipe_config
)
7932 struct drm_device
*dev
= crtc
->base
.dev
;
7933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7936 if (!intel_display_power_is_enabled(dev_priv
,
7937 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7940 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7941 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7943 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7944 if (!(tmp
& PIPECONF_ENABLE
))
7947 switch (tmp
& PIPECONF_BPC_MASK
) {
7949 pipe_config
->pipe_bpp
= 18;
7952 pipe_config
->pipe_bpp
= 24;
7954 case PIPECONF_10BPC
:
7955 pipe_config
->pipe_bpp
= 30;
7957 case PIPECONF_12BPC
:
7958 pipe_config
->pipe_bpp
= 36;
7964 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7965 pipe_config
->limited_color_range
= true;
7967 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7968 struct intel_shared_dpll
*pll
;
7970 pipe_config
->has_pch_encoder
= true;
7972 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7973 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7974 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7976 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7978 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7979 pipe_config
->shared_dpll
=
7980 (enum intel_dpll_id
) crtc
->pipe
;
7982 tmp
= I915_READ(PCH_DPLL_SEL
);
7983 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7984 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7986 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7989 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7991 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7992 &pipe_config
->dpll_hw_state
));
7994 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7995 pipe_config
->pixel_multiplier
=
7996 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7997 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7999 ironlake_pch_clock_get(crtc
, pipe_config
);
8001 pipe_config
->pixel_multiplier
= 1;
8004 intel_get_pipe_timings(crtc
, pipe_config
);
8006 ironlake_get_pfit_config(crtc
, pipe_config
);
8011 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8013 struct drm_device
*dev
= dev_priv
->dev
;
8014 struct intel_crtc
*crtc
;
8016 for_each_intel_crtc(dev
, crtc
)
8017 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8018 pipe_name(crtc
->pipe
));
8020 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8021 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8022 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8023 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8024 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8025 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8026 "CPU PWM1 enabled\n");
8027 if (IS_HASWELL(dev
))
8028 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8029 "CPU PWM2 enabled\n");
8030 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8031 "PCH PWM1 enabled\n");
8032 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8033 "Utility pin enabled\n");
8034 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8037 * In theory we can still leave IRQs enabled, as long as only the HPD
8038 * interrupts remain enabled. We used to check for that, but since it's
8039 * gen-specific and since we only disable LCPLL after we fully disable
8040 * the interrupts, the check below should be enough.
8042 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8045 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8047 struct drm_device
*dev
= dev_priv
->dev
;
8049 if (IS_HASWELL(dev
))
8050 return I915_READ(D_COMP_HSW
);
8052 return I915_READ(D_COMP_BDW
);
8055 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8057 struct drm_device
*dev
= dev_priv
->dev
;
8059 if (IS_HASWELL(dev
)) {
8060 mutex_lock(&dev_priv
->rps
.hw_lock
);
8061 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8063 DRM_ERROR("Failed to write to D_COMP\n");
8064 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8066 I915_WRITE(D_COMP_BDW
, val
);
8067 POSTING_READ(D_COMP_BDW
);
8072 * This function implements pieces of two sequences from BSpec:
8073 * - Sequence for display software to disable LCPLL
8074 * - Sequence for display software to allow package C8+
8075 * The steps implemented here are just the steps that actually touch the LCPLL
8076 * register. Callers should take care of disabling all the display engine
8077 * functions, doing the mode unset, fixing interrupts, etc.
8079 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
8080 bool switch_to_fclk
, bool allow_power_down
)
8084 assert_can_disable_lcpll(dev_priv
);
8086 val
= I915_READ(LCPLL_CTL
);
8088 if (switch_to_fclk
) {
8089 val
|= LCPLL_CD_SOURCE_FCLK
;
8090 I915_WRITE(LCPLL_CTL
, val
);
8092 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
8093 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
8094 DRM_ERROR("Switching to FCLK failed\n");
8096 val
= I915_READ(LCPLL_CTL
);
8099 val
|= LCPLL_PLL_DISABLE
;
8100 I915_WRITE(LCPLL_CTL
, val
);
8101 POSTING_READ(LCPLL_CTL
);
8103 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
8104 DRM_ERROR("LCPLL still locked\n");
8106 val
= hsw_read_dcomp(dev_priv
);
8107 val
|= D_COMP_COMP_DISABLE
;
8108 hsw_write_dcomp(dev_priv
, val
);
8111 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
8113 DRM_ERROR("D_COMP RCOMP still in progress\n");
8115 if (allow_power_down
) {
8116 val
= I915_READ(LCPLL_CTL
);
8117 val
|= LCPLL_POWER_DOWN_ALLOW
;
8118 I915_WRITE(LCPLL_CTL
, val
);
8119 POSTING_READ(LCPLL_CTL
);
8124 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8127 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
8131 val
= I915_READ(LCPLL_CTL
);
8133 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
8134 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
8138 * Make sure we're not on PC8 state before disabling PC8, otherwise
8139 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8141 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
8143 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
8144 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
8145 I915_WRITE(LCPLL_CTL
, val
);
8146 POSTING_READ(LCPLL_CTL
);
8149 val
= hsw_read_dcomp(dev_priv
);
8150 val
|= D_COMP_COMP_FORCE
;
8151 val
&= ~D_COMP_COMP_DISABLE
;
8152 hsw_write_dcomp(dev_priv
, val
);
8154 val
= I915_READ(LCPLL_CTL
);
8155 val
&= ~LCPLL_PLL_DISABLE
;
8156 I915_WRITE(LCPLL_CTL
, val
);
8158 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
8159 DRM_ERROR("LCPLL not locked yet\n");
8161 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8162 val
= I915_READ(LCPLL_CTL
);
8163 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8164 I915_WRITE(LCPLL_CTL
, val
);
8166 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
8167 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8168 DRM_ERROR("Switching back to LCPLL failed\n");
8171 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8175 * Package states C8 and deeper are really deep PC states that can only be
8176 * reached when all the devices on the system allow it, so even if the graphics
8177 * device allows PC8+, it doesn't mean the system will actually get to these
8178 * states. Our driver only allows PC8+ when going into runtime PM.
8180 * The requirements for PC8+ are that all the outputs are disabled, the power
8181 * well is disabled and most interrupts are disabled, and these are also
8182 * requirements for runtime PM. When these conditions are met, we manually do
8183 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8184 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8187 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8188 * the state of some registers, so when we come back from PC8+ we need to
8189 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8190 * need to take care of the registers kept by RC6. Notice that this happens even
8191 * if we don't put the device in PCI D3 state (which is what currently happens
8192 * because of the runtime PM support).
8194 * For more, read "Display Sequences for Package C8" on the hardware
8197 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8199 struct drm_device
*dev
= dev_priv
->dev
;
8202 DRM_DEBUG_KMS("Enabling package C8+\n");
8204 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8205 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8206 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8207 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8210 lpt_disable_clkout_dp(dev
);
8211 hsw_disable_lcpll(dev_priv
, true, true);
8214 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8216 struct drm_device
*dev
= dev_priv
->dev
;
8219 DRM_DEBUG_KMS("Disabling package C8+\n");
8221 hsw_restore_lcpll(dev_priv
);
8222 lpt_init_pch_refclk(dev
);
8224 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8225 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8226 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8227 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8230 intel_prepare_ddi(dev
);
8233 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
8234 struct intel_crtc_state
*crtc_state
)
8236 if (!intel_ddi_pll_select(crtc
, crtc_state
))
8239 crtc
->lowfreq_avail
= false;
8244 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8246 struct intel_crtc_state
*pipe_config
)
8248 u32 temp
, dpll_ctl1
;
8250 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
8251 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
8253 switch (pipe_config
->ddi_pll_sel
) {
8256 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8257 * of the shared DPLL framework and thus needs to be read out
8260 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
8261 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
8264 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
8267 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8270 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8275 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8277 struct intel_crtc_state
*pipe_config
)
8279 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8281 switch (pipe_config
->ddi_pll_sel
) {
8282 case PORT_CLK_SEL_WRPLL1
:
8283 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8285 case PORT_CLK_SEL_WRPLL2
:
8286 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8291 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8292 struct intel_crtc_state
*pipe_config
)
8294 struct drm_device
*dev
= crtc
->base
.dev
;
8295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8296 struct intel_shared_dpll
*pll
;
8300 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8302 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8304 if (IS_SKYLAKE(dev
))
8305 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8307 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8309 if (pipe_config
->shared_dpll
>= 0) {
8310 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8312 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8313 &pipe_config
->dpll_hw_state
));
8317 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8318 * DDI E. So just check whether this pipe is wired to DDI E and whether
8319 * the PCH transcoder is on.
8321 if (INTEL_INFO(dev
)->gen
< 9 &&
8322 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8323 pipe_config
->has_pch_encoder
= true;
8325 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8326 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8327 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8329 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8333 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8334 struct intel_crtc_state
*pipe_config
)
8336 struct drm_device
*dev
= crtc
->base
.dev
;
8337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8338 enum intel_display_power_domain pfit_domain
;
8341 if (!intel_display_power_is_enabled(dev_priv
,
8342 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8345 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8346 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8348 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8349 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8350 enum pipe trans_edp_pipe
;
8351 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8353 WARN(1, "unknown pipe linked to edp transcoder\n");
8354 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8355 case TRANS_DDI_EDP_INPUT_A_ON
:
8356 trans_edp_pipe
= PIPE_A
;
8358 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8359 trans_edp_pipe
= PIPE_B
;
8361 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8362 trans_edp_pipe
= PIPE_C
;
8366 if (trans_edp_pipe
== crtc
->pipe
)
8367 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8370 if (!intel_display_power_is_enabled(dev_priv
,
8371 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8374 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8375 if (!(tmp
& PIPECONF_ENABLE
))
8378 haswell_get_ddi_port_state(crtc
, pipe_config
);
8380 intel_get_pipe_timings(crtc
, pipe_config
);
8382 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8383 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8384 if (IS_SKYLAKE(dev
))
8385 skylake_get_pfit_config(crtc
, pipe_config
);
8387 ironlake_get_pfit_config(crtc
, pipe_config
);
8390 if (IS_HASWELL(dev
))
8391 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8392 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8394 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8395 pipe_config
->pixel_multiplier
=
8396 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8398 pipe_config
->pixel_multiplier
= 1;
8404 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8406 struct drm_device
*dev
= crtc
->dev
;
8407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8409 uint32_t cntl
= 0, size
= 0;
8412 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
8413 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
8414 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8418 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8429 cntl
|= CURSOR_ENABLE
|
8430 CURSOR_GAMMA_ENABLE
|
8431 CURSOR_FORMAT_ARGB
|
8432 CURSOR_STRIDE(stride
);
8434 size
= (height
<< 12) | width
;
8437 if (intel_crtc
->cursor_cntl
!= 0 &&
8438 (intel_crtc
->cursor_base
!= base
||
8439 intel_crtc
->cursor_size
!= size
||
8440 intel_crtc
->cursor_cntl
!= cntl
)) {
8441 /* On these chipsets we can only modify the base/size/stride
8442 * whilst the cursor is disabled.
8444 I915_WRITE(_CURACNTR
, 0);
8445 POSTING_READ(_CURACNTR
);
8446 intel_crtc
->cursor_cntl
= 0;
8449 if (intel_crtc
->cursor_base
!= base
) {
8450 I915_WRITE(_CURABASE
, base
);
8451 intel_crtc
->cursor_base
= base
;
8454 if (intel_crtc
->cursor_size
!= size
) {
8455 I915_WRITE(CURSIZE
, size
);
8456 intel_crtc
->cursor_size
= size
;
8459 if (intel_crtc
->cursor_cntl
!= cntl
) {
8460 I915_WRITE(_CURACNTR
, cntl
);
8461 POSTING_READ(_CURACNTR
);
8462 intel_crtc
->cursor_cntl
= cntl
;
8466 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8468 struct drm_device
*dev
= crtc
->dev
;
8469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8470 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8471 int pipe
= intel_crtc
->pipe
;
8476 cntl
= MCURSOR_GAMMA_ENABLE
;
8477 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
8479 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8482 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8485 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8488 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
8491 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8493 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8494 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8497 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
8498 cntl
|= CURSOR_ROTATE_180
;
8500 if (intel_crtc
->cursor_cntl
!= cntl
) {
8501 I915_WRITE(CURCNTR(pipe
), cntl
);
8502 POSTING_READ(CURCNTR(pipe
));
8503 intel_crtc
->cursor_cntl
= cntl
;
8506 /* and commit changes on next vblank */
8507 I915_WRITE(CURBASE(pipe
), base
);
8508 POSTING_READ(CURBASE(pipe
));
8510 intel_crtc
->cursor_base
= base
;
8513 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8514 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8517 struct drm_device
*dev
= crtc
->dev
;
8518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8519 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8520 int pipe
= intel_crtc
->pipe
;
8521 int x
= crtc
->cursor_x
;
8522 int y
= crtc
->cursor_y
;
8523 u32 base
= 0, pos
= 0;
8526 base
= intel_crtc
->cursor_addr
;
8528 if (x
>= intel_crtc
->config
->pipe_src_w
)
8531 if (y
>= intel_crtc
->config
->pipe_src_h
)
8535 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
8538 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8541 pos
|= x
<< CURSOR_X_SHIFT
;
8544 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
8547 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8550 pos
|= y
<< CURSOR_Y_SHIFT
;
8552 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8555 I915_WRITE(CURPOS(pipe
), pos
);
8557 /* ILK+ do this automagically */
8558 if (HAS_GMCH_DISPLAY(dev
) &&
8559 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
8560 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
8561 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
8564 if (IS_845G(dev
) || IS_I865G(dev
))
8565 i845_update_cursor(crtc
, base
);
8567 i9xx_update_cursor(crtc
, base
);
8570 static bool cursor_size_ok(struct drm_device
*dev
,
8571 uint32_t width
, uint32_t height
)
8573 if (width
== 0 || height
== 0)
8577 * 845g/865g are special in that they are only limited by
8578 * the width of their cursors, the height is arbitrary up to
8579 * the precision of the register. Everything else requires
8580 * square cursors, limited to a few power-of-two sizes.
8582 if (IS_845G(dev
) || IS_I865G(dev
)) {
8583 if ((width
& 63) != 0)
8586 if (width
> (IS_845G(dev
) ? 64 : 512))
8592 switch (width
| height
) {
8607 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8608 u16
*blue
, uint32_t start
, uint32_t size
)
8610 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8611 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8613 for (i
= start
; i
< end
; i
++) {
8614 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8615 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8616 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8619 intel_crtc_load_lut(crtc
);
8622 /* VESA 640x480x72Hz mode to set on the pipe */
8623 static struct drm_display_mode load_detect_mode
= {
8624 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8625 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8628 struct drm_framebuffer
*
8629 __intel_framebuffer_create(struct drm_device
*dev
,
8630 struct drm_mode_fb_cmd2
*mode_cmd
,
8631 struct drm_i915_gem_object
*obj
)
8633 struct intel_framebuffer
*intel_fb
;
8636 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8638 drm_gem_object_unreference(&obj
->base
);
8639 return ERR_PTR(-ENOMEM
);
8642 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8646 return &intel_fb
->base
;
8648 drm_gem_object_unreference(&obj
->base
);
8651 return ERR_PTR(ret
);
8654 static struct drm_framebuffer
*
8655 intel_framebuffer_create(struct drm_device
*dev
,
8656 struct drm_mode_fb_cmd2
*mode_cmd
,
8657 struct drm_i915_gem_object
*obj
)
8659 struct drm_framebuffer
*fb
;
8662 ret
= i915_mutex_lock_interruptible(dev
);
8664 return ERR_PTR(ret
);
8665 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8666 mutex_unlock(&dev
->struct_mutex
);
8672 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8674 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8675 return ALIGN(pitch
, 64);
8679 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8681 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8682 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8685 static struct drm_framebuffer
*
8686 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8687 struct drm_display_mode
*mode
,
8690 struct drm_i915_gem_object
*obj
;
8691 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8693 obj
= i915_gem_alloc_object(dev
,
8694 intel_framebuffer_size_for_mode(mode
, bpp
));
8696 return ERR_PTR(-ENOMEM
);
8698 mode_cmd
.width
= mode
->hdisplay
;
8699 mode_cmd
.height
= mode
->vdisplay
;
8700 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8702 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8704 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8707 static struct drm_framebuffer
*
8708 mode_fits_in_fbdev(struct drm_device
*dev
,
8709 struct drm_display_mode
*mode
)
8711 #ifdef CONFIG_DRM_I915_FBDEV
8712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8713 struct drm_i915_gem_object
*obj
;
8714 struct drm_framebuffer
*fb
;
8716 if (!dev_priv
->fbdev
)
8719 if (!dev_priv
->fbdev
->fb
)
8722 obj
= dev_priv
->fbdev
->fb
->obj
;
8725 fb
= &dev_priv
->fbdev
->fb
->base
;
8726 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8727 fb
->bits_per_pixel
))
8730 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8739 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8740 struct drm_display_mode
*mode
,
8741 struct intel_load_detect_pipe
*old
,
8742 struct drm_modeset_acquire_ctx
*ctx
)
8744 struct intel_crtc
*intel_crtc
;
8745 struct intel_encoder
*intel_encoder
=
8746 intel_attached_encoder(connector
);
8747 struct drm_crtc
*possible_crtc
;
8748 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8749 struct drm_crtc
*crtc
= NULL
;
8750 struct drm_device
*dev
= encoder
->dev
;
8751 struct drm_framebuffer
*fb
;
8752 struct drm_mode_config
*config
= &dev
->mode_config
;
8755 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8756 connector
->base
.id
, connector
->name
,
8757 encoder
->base
.id
, encoder
->name
);
8760 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8765 * Algorithm gets a little messy:
8767 * - if the connector already has an assigned crtc, use it (but make
8768 * sure it's on first)
8770 * - try to find the first unused crtc that can drive this connector,
8771 * and use that if we find one
8774 /* See if we already have a CRTC for this connector */
8775 if (encoder
->crtc
) {
8776 crtc
= encoder
->crtc
;
8778 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8781 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8785 old
->dpms_mode
= connector
->dpms
;
8786 old
->load_detect_temp
= false;
8788 /* Make sure the crtc and connector are running */
8789 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8790 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8795 /* Find an unused one (if possible) */
8796 for_each_crtc(dev
, possible_crtc
) {
8798 if (!(encoder
->possible_crtcs
& (1 << i
)))
8800 if (possible_crtc
->state
->enable
)
8802 /* This can occur when applying the pipe A quirk on resume. */
8803 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8806 crtc
= possible_crtc
;
8811 * If we didn't find an unused CRTC, don't use any.
8814 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8818 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8821 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8824 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8825 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8827 intel_crtc
= to_intel_crtc(crtc
);
8828 intel_crtc
->new_enabled
= true;
8829 intel_crtc
->new_config
= intel_crtc
->config
;
8830 old
->dpms_mode
= connector
->dpms
;
8831 old
->load_detect_temp
= true;
8832 old
->release_fb
= NULL
;
8835 mode
= &load_detect_mode
;
8837 /* We need a framebuffer large enough to accommodate all accesses
8838 * that the plane may generate whilst we perform load detection.
8839 * We can not rely on the fbcon either being present (we get called
8840 * during its initialisation to detect all boot displays, or it may
8841 * not even exist) or that it is large enough to satisfy the
8844 fb
= mode_fits_in_fbdev(dev
, mode
);
8846 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8847 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8848 old
->release_fb
= fb
;
8850 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8852 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8856 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8857 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8858 if (old
->release_fb
)
8859 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8862 crtc
->primary
->crtc
= crtc
;
8864 /* let the connector get through one full cycle before testing */
8865 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8869 intel_crtc
->new_enabled
= crtc
->state
->enable
;
8870 if (intel_crtc
->new_enabled
)
8871 intel_crtc
->new_config
= intel_crtc
->config
;
8873 intel_crtc
->new_config
= NULL
;
8875 if (ret
== -EDEADLK
) {
8876 drm_modeset_backoff(ctx
);
8883 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8884 struct intel_load_detect_pipe
*old
)
8886 struct intel_encoder
*intel_encoder
=
8887 intel_attached_encoder(connector
);
8888 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8889 struct drm_crtc
*crtc
= encoder
->crtc
;
8890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8893 connector
->base
.id
, connector
->name
,
8894 encoder
->base
.id
, encoder
->name
);
8896 if (old
->load_detect_temp
) {
8897 to_intel_connector(connector
)->new_encoder
= NULL
;
8898 intel_encoder
->new_crtc
= NULL
;
8899 intel_crtc
->new_enabled
= false;
8900 intel_crtc
->new_config
= NULL
;
8901 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8903 if (old
->release_fb
) {
8904 drm_framebuffer_unregister_private(old
->release_fb
);
8905 drm_framebuffer_unreference(old
->release_fb
);
8911 /* Switch crtc and encoder back off if necessary */
8912 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8913 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8916 static int i9xx_pll_refclk(struct drm_device
*dev
,
8917 const struct intel_crtc_state
*pipe_config
)
8919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8920 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8922 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8923 return dev_priv
->vbt
.lvds_ssc_freq
;
8924 else if (HAS_PCH_SPLIT(dev
))
8926 else if (!IS_GEN2(dev
))
8932 /* Returns the clock of the currently programmed mode of the given pipe. */
8933 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8934 struct intel_crtc_state
*pipe_config
)
8936 struct drm_device
*dev
= crtc
->base
.dev
;
8937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8938 int pipe
= pipe_config
->cpu_transcoder
;
8939 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8941 intel_clock_t clock
;
8942 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8944 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8945 fp
= pipe_config
->dpll_hw_state
.fp0
;
8947 fp
= pipe_config
->dpll_hw_state
.fp1
;
8949 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8950 if (IS_PINEVIEW(dev
)) {
8951 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8952 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8954 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8955 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8958 if (!IS_GEN2(dev
)) {
8959 if (IS_PINEVIEW(dev
))
8960 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8961 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8963 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8964 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8966 switch (dpll
& DPLL_MODE_MASK
) {
8967 case DPLLB_MODE_DAC_SERIAL
:
8968 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8971 case DPLLB_MODE_LVDS
:
8972 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8976 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8977 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8981 if (IS_PINEVIEW(dev
))
8982 pineview_clock(refclk
, &clock
);
8984 i9xx_clock(refclk
, &clock
);
8986 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8987 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8990 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8991 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8993 if (lvds
& LVDS_CLKB_POWER_UP
)
8998 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
9001 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
9002 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
9004 if (dpll
& PLL_P2_DIVIDE_BY_4
)
9010 i9xx_clock(refclk
, &clock
);
9014 * This value includes pixel_multiplier. We will use
9015 * port_clock to compute adjusted_mode.crtc_clock in the
9016 * encoder's get_config() function.
9018 pipe_config
->port_clock
= clock
.dot
;
9021 int intel_dotclock_calculate(int link_freq
,
9022 const struct intel_link_m_n
*m_n
)
9025 * The calculation for the data clock is:
9026 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9027 * But we want to avoid losing precison if possible, so:
9028 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9030 * and the link clock is simpler:
9031 * link_clock = (m * link_clock) / n
9037 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
9040 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
9041 struct intel_crtc_state
*pipe_config
)
9043 struct drm_device
*dev
= crtc
->base
.dev
;
9045 /* read out port_clock from the DPLL */
9046 i9xx_crtc_clock_get(crtc
, pipe_config
);
9049 * This value does not include pixel_multiplier.
9050 * We will check that port_clock and adjusted_mode.crtc_clock
9051 * agree once we know their relationship in the encoder's
9052 * get_config() function.
9054 pipe_config
->base
.adjusted_mode
.crtc_clock
=
9055 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
9056 &pipe_config
->fdi_m_n
);
9059 /** Returns the currently programmed mode of the given pipe. */
9060 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
9061 struct drm_crtc
*crtc
)
9063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9064 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9065 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
9066 struct drm_display_mode
*mode
;
9067 struct intel_crtc_state pipe_config
;
9068 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
9069 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
9070 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
9071 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
9072 enum pipe pipe
= intel_crtc
->pipe
;
9074 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
9079 * Construct a pipe_config sufficient for getting the clock info
9080 * back out of crtc_clock_get.
9082 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9083 * to use a real value here instead.
9085 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
9086 pipe_config
.pixel_multiplier
= 1;
9087 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
9088 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
9089 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
9090 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
9092 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
9093 mode
->hdisplay
= (htot
& 0xffff) + 1;
9094 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
9095 mode
->hsync_start
= (hsync
& 0xffff) + 1;
9096 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
9097 mode
->vdisplay
= (vtot
& 0xffff) + 1;
9098 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
9099 mode
->vsync_start
= (vsync
& 0xffff) + 1;
9100 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
9102 drm_mode_set_name(mode
);
9107 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9109 struct drm_device
*dev
= crtc
->dev
;
9110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9111 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9113 if (!HAS_GMCH_DISPLAY(dev
))
9116 if (!dev_priv
->lvds_downclock_avail
)
9120 * Since this is called by a timer, we should never get here in
9123 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9124 int pipe
= intel_crtc
->pipe
;
9125 int dpll_reg
= DPLL(pipe
);
9128 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9130 assert_panel_unlocked(dev_priv
, pipe
);
9132 dpll
= I915_READ(dpll_reg
);
9133 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9134 I915_WRITE(dpll_reg
, dpll
);
9135 intel_wait_for_vblank(dev
, pipe
);
9136 dpll
= I915_READ(dpll_reg
);
9137 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9138 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9143 void intel_mark_busy(struct drm_device
*dev
)
9145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9147 if (dev_priv
->mm
.busy
)
9150 intel_runtime_pm_get(dev_priv
);
9151 i915_update_gfx_val(dev_priv
);
9152 dev_priv
->mm
.busy
= true;
9155 void intel_mark_idle(struct drm_device
*dev
)
9157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9158 struct drm_crtc
*crtc
;
9160 if (!dev_priv
->mm
.busy
)
9163 dev_priv
->mm
.busy
= false;
9165 if (!i915
.powersave
)
9168 for_each_crtc(dev
, crtc
) {
9169 if (!crtc
->primary
->fb
)
9172 intel_decrease_pllclock(crtc
);
9175 if (INTEL_INFO(dev
)->gen
>= 6)
9176 gen6_rps_idle(dev
->dev_private
);
9179 intel_runtime_pm_put(dev_priv
);
9182 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
9183 struct intel_crtc_state
*crtc_state
)
9185 kfree(crtc
->config
);
9186 crtc
->config
= crtc_state
;
9187 crtc
->base
.state
= &crtc_state
->base
;
9190 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9193 struct drm_device
*dev
= crtc
->dev
;
9194 struct intel_unpin_work
*work
;
9196 spin_lock_irq(&dev
->event_lock
);
9197 work
= intel_crtc
->unpin_work
;
9198 intel_crtc
->unpin_work
= NULL
;
9199 spin_unlock_irq(&dev
->event_lock
);
9202 cancel_work_sync(&work
->work
);
9206 intel_crtc_set_state(intel_crtc
, NULL
);
9207 drm_crtc_cleanup(crtc
);
9212 static void intel_unpin_work_fn(struct work_struct
*__work
)
9214 struct intel_unpin_work
*work
=
9215 container_of(__work
, struct intel_unpin_work
, work
);
9216 struct drm_device
*dev
= work
->crtc
->dev
;
9217 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9219 mutex_lock(&dev
->struct_mutex
);
9220 intel_unpin_fb_obj(intel_fb_obj(work
->old_fb
));
9221 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9222 drm_framebuffer_unreference(work
->old_fb
);
9224 intel_fbc_update(dev
);
9226 if (work
->flip_queued_req
)
9227 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
9228 mutex_unlock(&dev
->struct_mutex
);
9230 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9232 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9233 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9238 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9239 struct drm_crtc
*crtc
)
9241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9242 struct intel_unpin_work
*work
;
9243 unsigned long flags
;
9245 /* Ignore early vblank irqs */
9246 if (intel_crtc
== NULL
)
9250 * This is called both by irq handlers and the reset code (to complete
9251 * lost pageflips) so needs the full irqsave spinlocks.
9253 spin_lock_irqsave(&dev
->event_lock
, flags
);
9254 work
= intel_crtc
->unpin_work
;
9256 /* Ensure we don't miss a work->pending update ... */
9259 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9260 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9264 page_flip_completed(intel_crtc
);
9266 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9269 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9272 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9274 do_intel_finish_page_flip(dev
, crtc
);
9277 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9280 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9282 do_intel_finish_page_flip(dev
, crtc
);
9285 /* Is 'a' after or equal to 'b'? */
9286 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9288 return !((a
- b
) & 0x80000000);
9291 static bool page_flip_finished(struct intel_crtc
*crtc
)
9293 struct drm_device
*dev
= crtc
->base
.dev
;
9294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9296 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9297 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9301 * The relevant registers doen't exist on pre-ctg.
9302 * As the flip done interrupt doesn't trigger for mmio
9303 * flips on gmch platforms, a flip count check isn't
9304 * really needed there. But since ctg has the registers,
9305 * include it in the check anyway.
9307 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9311 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9312 * used the same base address. In that case the mmio flip might
9313 * have completed, but the CS hasn't even executed the flip yet.
9315 * A flip count check isn't enough as the CS might have updated
9316 * the base address just after start of vblank, but before we
9317 * managed to process the interrupt. This means we'd complete the
9320 * Combining both checks should get us a good enough result. It may
9321 * still happen that the CS flip has been executed, but has not
9322 * yet actually completed. But in case the base address is the same
9323 * anyway, we don't really care.
9325 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9326 crtc
->unpin_work
->gtt_offset
&&
9327 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9328 crtc
->unpin_work
->flip_count
);
9331 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9334 struct intel_crtc
*intel_crtc
=
9335 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9336 unsigned long flags
;
9340 * This is called both by irq handlers and the reset code (to complete
9341 * lost pageflips) so needs the full irqsave spinlocks.
9343 * NB: An MMIO update of the plane base pointer will also
9344 * generate a page-flip completion irq, i.e. every modeset
9345 * is also accompanied by a spurious intel_prepare_page_flip().
9347 spin_lock_irqsave(&dev
->event_lock
, flags
);
9348 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9349 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9350 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9353 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9355 /* Ensure that the work item is consistent when activating it ... */
9357 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9358 /* and that it is marked active as soon as the irq could fire. */
9362 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9363 struct drm_crtc
*crtc
,
9364 struct drm_framebuffer
*fb
,
9365 struct drm_i915_gem_object
*obj
,
9366 struct intel_engine_cs
*ring
,
9369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9373 ret
= intel_ring_begin(ring
, 6);
9377 /* Can't queue multiple flips, so wait for the previous
9378 * one to finish before executing the next.
9380 if (intel_crtc
->plane
)
9381 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9383 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9384 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9385 intel_ring_emit(ring
, MI_NOOP
);
9386 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9387 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9388 intel_ring_emit(ring
, fb
->pitches
[0]);
9389 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9390 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9392 intel_mark_page_flip_active(intel_crtc
);
9393 __intel_ring_advance(ring
);
9397 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9398 struct drm_crtc
*crtc
,
9399 struct drm_framebuffer
*fb
,
9400 struct drm_i915_gem_object
*obj
,
9401 struct intel_engine_cs
*ring
,
9404 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9408 ret
= intel_ring_begin(ring
, 6);
9412 if (intel_crtc
->plane
)
9413 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9415 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9416 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9417 intel_ring_emit(ring
, MI_NOOP
);
9418 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9419 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9420 intel_ring_emit(ring
, fb
->pitches
[0]);
9421 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9422 intel_ring_emit(ring
, MI_NOOP
);
9424 intel_mark_page_flip_active(intel_crtc
);
9425 __intel_ring_advance(ring
);
9429 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9430 struct drm_crtc
*crtc
,
9431 struct drm_framebuffer
*fb
,
9432 struct drm_i915_gem_object
*obj
,
9433 struct intel_engine_cs
*ring
,
9436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9437 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9438 uint32_t pf
, pipesrc
;
9441 ret
= intel_ring_begin(ring
, 4);
9445 /* i965+ uses the linear or tiled offsets from the
9446 * Display Registers (which do not change across a page-flip)
9447 * so we need only reprogram the base address.
9449 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9450 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9451 intel_ring_emit(ring
, fb
->pitches
[0]);
9452 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9455 /* XXX Enabling the panel-fitter across page-flip is so far
9456 * untested on non-native modes, so ignore it for now.
9457 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9460 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9461 intel_ring_emit(ring
, pf
| pipesrc
);
9463 intel_mark_page_flip_active(intel_crtc
);
9464 __intel_ring_advance(ring
);
9468 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9469 struct drm_crtc
*crtc
,
9470 struct drm_framebuffer
*fb
,
9471 struct drm_i915_gem_object
*obj
,
9472 struct intel_engine_cs
*ring
,
9475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9476 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9477 uint32_t pf
, pipesrc
;
9480 ret
= intel_ring_begin(ring
, 4);
9484 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9485 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9486 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9487 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9489 /* Contrary to the suggestions in the documentation,
9490 * "Enable Panel Fitter" does not seem to be required when page
9491 * flipping with a non-native mode, and worse causes a normal
9493 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9496 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9497 intel_ring_emit(ring
, pf
| pipesrc
);
9499 intel_mark_page_flip_active(intel_crtc
);
9500 __intel_ring_advance(ring
);
9504 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9505 struct drm_crtc
*crtc
,
9506 struct drm_framebuffer
*fb
,
9507 struct drm_i915_gem_object
*obj
,
9508 struct intel_engine_cs
*ring
,
9511 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9512 uint32_t plane_bit
= 0;
9515 switch (intel_crtc
->plane
) {
9517 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9520 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9523 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9526 WARN_ONCE(1, "unknown plane in flip command\n");
9531 if (ring
->id
== RCS
) {
9534 * On Gen 8, SRM is now taking an extra dword to accommodate
9535 * 48bits addresses, and we need a NOOP for the batch size to
9543 * BSpec MI_DISPLAY_FLIP for IVB:
9544 * "The full packet must be contained within the same cache line."
9546 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9547 * cacheline, if we ever start emitting more commands before
9548 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9549 * then do the cacheline alignment, and finally emit the
9552 ret
= intel_ring_cacheline_align(ring
);
9556 ret
= intel_ring_begin(ring
, len
);
9560 /* Unmask the flip-done completion message. Note that the bspec says that
9561 * we should do this for both the BCS and RCS, and that we must not unmask
9562 * more than one flip event at any time (or ensure that one flip message
9563 * can be sent by waiting for flip-done prior to queueing new flips).
9564 * Experimentation says that BCS works despite DERRMR masking all
9565 * flip-done completion events and that unmasking all planes at once
9566 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9567 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9569 if (ring
->id
== RCS
) {
9570 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9571 intel_ring_emit(ring
, DERRMR
);
9572 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9573 DERRMR_PIPEB_PRI_FLIP_DONE
|
9574 DERRMR_PIPEC_PRI_FLIP_DONE
));
9576 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9577 MI_SRM_LRM_GLOBAL_GTT
);
9579 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9580 MI_SRM_LRM_GLOBAL_GTT
);
9581 intel_ring_emit(ring
, DERRMR
);
9582 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9584 intel_ring_emit(ring
, 0);
9585 intel_ring_emit(ring
, MI_NOOP
);
9589 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9590 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9591 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9592 intel_ring_emit(ring
, (MI_NOOP
));
9594 intel_mark_page_flip_active(intel_crtc
);
9595 __intel_ring_advance(ring
);
9599 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9600 struct drm_i915_gem_object
*obj
)
9603 * This is not being used for older platforms, because
9604 * non-availability of flip done interrupt forces us to use
9605 * CS flips. Older platforms derive flip done using some clever
9606 * tricks involving the flip_pending status bits and vblank irqs.
9607 * So using MMIO flips there would disrupt this mechanism.
9613 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9616 if (i915
.use_mmio_flip
< 0)
9618 else if (i915
.use_mmio_flip
> 0)
9620 else if (i915
.enable_execlists
)
9623 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
9626 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9628 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9630 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
9631 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9632 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9633 const enum pipe pipe
= intel_crtc
->pipe
;
9636 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
9637 ctl
&= ~PLANE_CTL_TILED_MASK
;
9638 if (obj
->tiling_mode
== I915_TILING_X
)
9639 ctl
|= PLANE_CTL_TILED_X
;
9642 * The stride is either expressed as a multiple of 64 bytes chunks for
9643 * linear buffers or in number of tiles for tiled buffers.
9645 stride
= fb
->pitches
[0] >> 6;
9646 if (obj
->tiling_mode
== I915_TILING_X
)
9647 stride
= fb
->pitches
[0] >> 9; /* X tiles are 512 bytes wide */
9650 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9651 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9653 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
9654 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
9656 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
9657 POSTING_READ(PLANE_SURF(pipe
, 0));
9660 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9662 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9664 struct intel_framebuffer
*intel_fb
=
9665 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9666 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9670 reg
= DSPCNTR(intel_crtc
->plane
);
9671 dspcntr
= I915_READ(reg
);
9673 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9674 dspcntr
|= DISPPLANE_TILED
;
9676 dspcntr
&= ~DISPPLANE_TILED
;
9678 I915_WRITE(reg
, dspcntr
);
9680 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9681 intel_crtc
->unpin_work
->gtt_offset
);
9682 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9687 * XXX: This is the temporary way to update the plane registers until we get
9688 * around to using the usual plane update functions for MMIO flips
9690 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9692 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9694 u32 start_vbl_count
;
9696 intel_mark_page_flip_active(intel_crtc
);
9698 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9700 if (INTEL_INFO(dev
)->gen
>= 9)
9701 skl_do_mmio_flip(intel_crtc
);
9703 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9704 ilk_do_mmio_flip(intel_crtc
);
9707 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9710 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9712 struct intel_crtc
*crtc
=
9713 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9714 struct intel_mmio_flip
*mmio_flip
;
9716 mmio_flip
= &crtc
->mmio_flip
;
9718 WARN_ON(__i915_wait_request(mmio_flip
->req
,
9719 crtc
->reset_counter
,
9720 false, NULL
, NULL
) != 0);
9722 intel_do_mmio_flip(crtc
);
9723 if (mmio_flip
->req
) {
9724 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
9725 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
9726 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
9730 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9731 struct drm_crtc
*crtc
,
9732 struct drm_framebuffer
*fb
,
9733 struct drm_i915_gem_object
*obj
,
9734 struct intel_engine_cs
*ring
,
9737 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9739 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
9740 obj
->last_write_req
);
9742 schedule_work(&intel_crtc
->mmio_flip
.work
);
9747 static int intel_default_queue_flip(struct drm_device
*dev
,
9748 struct drm_crtc
*crtc
,
9749 struct drm_framebuffer
*fb
,
9750 struct drm_i915_gem_object
*obj
,
9751 struct intel_engine_cs
*ring
,
9757 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9758 struct drm_crtc
*crtc
)
9760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9761 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9762 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9765 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9768 if (!work
->enable_stall_check
)
9771 if (work
->flip_ready_vblank
== 0) {
9772 if (work
->flip_queued_req
&&
9773 !i915_gem_request_completed(work
->flip_queued_req
, true))
9776 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
9779 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
9782 /* Potential stall - if we see that the flip has happened,
9783 * assume a missed interrupt. */
9784 if (INTEL_INFO(dev
)->gen
>= 4)
9785 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9787 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9789 /* There is a potential issue here with a false positive after a flip
9790 * to the same address. We could address this by checking for a
9791 * non-incrementing frame counter.
9793 return addr
== work
->gtt_offset
;
9796 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9799 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9800 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9807 spin_lock(&dev
->event_lock
);
9808 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9809 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9810 intel_crtc
->unpin_work
->flip_queued_vblank
,
9811 drm_vblank_count(dev
, pipe
));
9812 page_flip_completed(intel_crtc
);
9814 spin_unlock(&dev
->event_lock
);
9817 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9818 struct drm_framebuffer
*fb
,
9819 struct drm_pending_vblank_event
*event
,
9820 uint32_t page_flip_flags
)
9822 struct drm_device
*dev
= crtc
->dev
;
9823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9824 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9825 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9827 struct drm_plane
*primary
= crtc
->primary
;
9828 enum pipe pipe
= intel_crtc
->pipe
;
9829 struct intel_unpin_work
*work
;
9830 struct intel_engine_cs
*ring
;
9834 * drm_mode_page_flip_ioctl() should already catch this, but double
9835 * check to be safe. In the future we may enable pageflipping from
9836 * a disabled primary plane.
9838 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9841 /* Can't change pixel format via MI display flips. */
9842 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9846 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9847 * Note that pitch changes could also affect these register.
9849 if (INTEL_INFO(dev
)->gen
> 3 &&
9850 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9851 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9854 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9857 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9861 work
->event
= event
;
9863 work
->old_fb
= old_fb
;
9864 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9866 ret
= drm_crtc_vblank_get(crtc
);
9870 /* We borrow the event spin lock for protecting unpin_work */
9871 spin_lock_irq(&dev
->event_lock
);
9872 if (intel_crtc
->unpin_work
) {
9873 /* Before declaring the flip queue wedged, check if
9874 * the hardware completed the operation behind our backs.
9876 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9877 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9878 page_flip_completed(intel_crtc
);
9880 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9881 spin_unlock_irq(&dev
->event_lock
);
9883 drm_crtc_vblank_put(crtc
);
9888 intel_crtc
->unpin_work
= work
;
9889 spin_unlock_irq(&dev
->event_lock
);
9891 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9892 flush_workqueue(dev_priv
->wq
);
9894 ret
= i915_mutex_lock_interruptible(dev
);
9898 /* Reference the objects for the scheduled work. */
9899 drm_framebuffer_reference(work
->old_fb
);
9900 drm_gem_object_reference(&obj
->base
);
9902 crtc
->primary
->fb
= fb
;
9903 update_state_fb(crtc
->primary
);
9905 work
->pending_flip_obj
= obj
;
9907 atomic_inc(&intel_crtc
->unpin_work_count
);
9908 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9910 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9911 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9913 if (IS_VALLEYVIEW(dev
)) {
9914 ring
= &dev_priv
->ring
[BCS
];
9915 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
9916 /* vlv: DISPLAY_FLIP fails to change tiling */
9918 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
9919 ring
= &dev_priv
->ring
[BCS
];
9920 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9921 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
9922 if (ring
== NULL
|| ring
->id
!= RCS
)
9923 ring
= &dev_priv
->ring
[BCS
];
9925 ring
= &dev_priv
->ring
[RCS
];
9928 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9930 goto cleanup_pending
;
9933 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9935 if (use_mmio_flip(ring
, obj
)) {
9936 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9941 i915_gem_request_assign(&work
->flip_queued_req
,
9942 obj
->last_write_req
);
9944 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9949 i915_gem_request_assign(&work
->flip_queued_req
,
9950 intel_ring_get_request(ring
));
9953 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
9954 work
->enable_stall_check
= true;
9956 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
9957 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9959 intel_fbc_disable(dev
);
9960 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9961 mutex_unlock(&dev
->struct_mutex
);
9963 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9968 intel_unpin_fb_obj(obj
);
9970 atomic_dec(&intel_crtc
->unpin_work_count
);
9971 crtc
->primary
->fb
= old_fb
;
9972 update_state_fb(crtc
->primary
);
9973 drm_framebuffer_unreference(work
->old_fb
);
9974 drm_gem_object_unreference(&obj
->base
);
9975 mutex_unlock(&dev
->struct_mutex
);
9978 spin_lock_irq(&dev
->event_lock
);
9979 intel_crtc
->unpin_work
= NULL
;
9980 spin_unlock_irq(&dev
->event_lock
);
9982 drm_crtc_vblank_put(crtc
);
9988 ret
= intel_plane_restore(primary
);
9989 if (ret
== 0 && event
) {
9990 spin_lock_irq(&dev
->event_lock
);
9991 drm_send_vblank_event(dev
, pipe
, event
);
9992 spin_unlock_irq(&dev
->event_lock
);
9998 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9999 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10000 .load_lut
= intel_crtc_load_lut
,
10001 .atomic_begin
= intel_begin_crtc_commit
,
10002 .atomic_flush
= intel_finish_crtc_commit
,
10006 * intel_modeset_update_staged_output_state
10008 * Updates the staged output configuration state, e.g. after we've read out the
10009 * current hw state.
10011 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10013 struct intel_crtc
*crtc
;
10014 struct intel_encoder
*encoder
;
10015 struct intel_connector
*connector
;
10017 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10019 connector
->new_encoder
=
10020 to_intel_encoder(connector
->base
.encoder
);
10023 for_each_intel_encoder(dev
, encoder
) {
10024 encoder
->new_crtc
=
10025 to_intel_crtc(encoder
->base
.crtc
);
10028 for_each_intel_crtc(dev
, crtc
) {
10029 crtc
->new_enabled
= crtc
->base
.state
->enable
;
10031 if (crtc
->new_enabled
)
10032 crtc
->new_config
= crtc
->config
;
10034 crtc
->new_config
= NULL
;
10039 * intel_modeset_commit_output_state
10041 * This function copies the stage display pipe configuration to the real one.
10043 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10045 struct intel_crtc
*crtc
;
10046 struct intel_encoder
*encoder
;
10047 struct intel_connector
*connector
;
10049 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10051 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10054 for_each_intel_encoder(dev
, encoder
) {
10055 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10058 for_each_intel_crtc(dev
, crtc
) {
10059 crtc
->base
.state
->enable
= crtc
->new_enabled
;
10060 crtc
->base
.enabled
= crtc
->new_enabled
;
10065 connected_sink_compute_bpp(struct intel_connector
*connector
,
10066 struct intel_crtc_state
*pipe_config
)
10068 int bpp
= pipe_config
->pipe_bpp
;
10070 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10071 connector
->base
.base
.id
,
10072 connector
->base
.name
);
10074 /* Don't use an invalid EDID bpc value */
10075 if (connector
->base
.display_info
.bpc
&&
10076 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10077 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10078 bpp
, connector
->base
.display_info
.bpc
*3);
10079 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10082 /* Clamp bpp to 8 on screens without EDID 1.4 */
10083 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10084 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10086 pipe_config
->pipe_bpp
= 24;
10091 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10092 struct drm_framebuffer
*fb
,
10093 struct intel_crtc_state
*pipe_config
)
10095 struct drm_device
*dev
= crtc
->base
.dev
;
10096 struct intel_connector
*connector
;
10099 switch (fb
->pixel_format
) {
10100 case DRM_FORMAT_C8
:
10101 bpp
= 8*3; /* since we go through a colormap */
10103 case DRM_FORMAT_XRGB1555
:
10104 case DRM_FORMAT_ARGB1555
:
10105 /* checked in intel_framebuffer_init already */
10106 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10108 case DRM_FORMAT_RGB565
:
10109 bpp
= 6*3; /* min is 18bpp */
10111 case DRM_FORMAT_XBGR8888
:
10112 case DRM_FORMAT_ABGR8888
:
10113 /* checked in intel_framebuffer_init already */
10114 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10116 case DRM_FORMAT_XRGB8888
:
10117 case DRM_FORMAT_ARGB8888
:
10120 case DRM_FORMAT_XRGB2101010
:
10121 case DRM_FORMAT_ARGB2101010
:
10122 case DRM_FORMAT_XBGR2101010
:
10123 case DRM_FORMAT_ABGR2101010
:
10124 /* checked in intel_framebuffer_init already */
10125 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10129 /* TODO: gen4+ supports 16 bpc floating point, too. */
10131 DRM_DEBUG_KMS("unsupported depth\n");
10135 pipe_config
->pipe_bpp
= bpp
;
10137 /* Clamp display bpp to EDID value */
10138 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10140 if (!connector
->new_encoder
||
10141 connector
->new_encoder
->new_crtc
!= crtc
)
10144 connected_sink_compute_bpp(connector
, pipe_config
);
10150 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10152 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10153 "type: 0x%x flags: 0x%x\n",
10155 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10156 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10157 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10158 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10161 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10162 struct intel_crtc_state
*pipe_config
,
10163 const char *context
)
10165 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10166 context
, pipe_name(crtc
->pipe
));
10168 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10169 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10170 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10171 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10172 pipe_config
->has_pch_encoder
,
10173 pipe_config
->fdi_lanes
,
10174 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10175 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10176 pipe_config
->fdi_m_n
.tu
);
10177 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10178 pipe_config
->has_dp_encoder
,
10179 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10180 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10181 pipe_config
->dp_m_n
.tu
);
10183 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10184 pipe_config
->has_dp_encoder
,
10185 pipe_config
->dp_m2_n2
.gmch_m
,
10186 pipe_config
->dp_m2_n2
.gmch_n
,
10187 pipe_config
->dp_m2_n2
.link_m
,
10188 pipe_config
->dp_m2_n2
.link_n
,
10189 pipe_config
->dp_m2_n2
.tu
);
10191 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10192 pipe_config
->has_audio
,
10193 pipe_config
->has_infoframe
);
10195 DRM_DEBUG_KMS("requested mode:\n");
10196 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10197 DRM_DEBUG_KMS("adjusted mode:\n");
10198 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10199 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10200 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10201 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10202 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10203 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10204 pipe_config
->gmch_pfit
.control
,
10205 pipe_config
->gmch_pfit
.pgm_ratios
,
10206 pipe_config
->gmch_pfit
.lvds_border_bits
);
10207 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10208 pipe_config
->pch_pfit
.pos
,
10209 pipe_config
->pch_pfit
.size
,
10210 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10211 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10212 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10215 static bool encoders_cloneable(const struct intel_encoder
*a
,
10216 const struct intel_encoder
*b
)
10218 /* masks could be asymmetric, so check both ways */
10219 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10220 b
->cloneable
& (1 << a
->type
));
10223 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10224 struct intel_encoder
*encoder
)
10226 struct drm_device
*dev
= crtc
->base
.dev
;
10227 struct intel_encoder
*source_encoder
;
10229 for_each_intel_encoder(dev
, source_encoder
) {
10230 if (source_encoder
->new_crtc
!= crtc
)
10233 if (!encoders_cloneable(encoder
, source_encoder
))
10240 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10242 struct drm_device
*dev
= crtc
->base
.dev
;
10243 struct intel_encoder
*encoder
;
10245 for_each_intel_encoder(dev
, encoder
) {
10246 if (encoder
->new_crtc
!= crtc
)
10249 if (!check_single_encoder_cloning(crtc
, encoder
))
10256 static bool check_digital_port_conflicts(struct drm_device
*dev
)
10258 struct intel_connector
*connector
;
10259 unsigned int used_ports
= 0;
10262 * Walk the connector list instead of the encoder
10263 * list to detect the problem on ddi platforms
10264 * where there's just one encoder per digital port.
10266 list_for_each_entry(connector
,
10267 &dev
->mode_config
.connector_list
, base
.head
) {
10268 struct intel_encoder
*encoder
= connector
->new_encoder
;
10273 WARN_ON(!encoder
->new_crtc
);
10275 switch (encoder
->type
) {
10276 unsigned int port_mask
;
10277 case INTEL_OUTPUT_UNKNOWN
:
10278 if (WARN_ON(!HAS_DDI(dev
)))
10280 case INTEL_OUTPUT_DISPLAYPORT
:
10281 case INTEL_OUTPUT_HDMI
:
10282 case INTEL_OUTPUT_EDP
:
10283 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10285 /* the same port mustn't appear more than once */
10286 if (used_ports
& port_mask
)
10289 used_ports
|= port_mask
;
10298 static struct intel_crtc_state
*
10299 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10300 struct drm_framebuffer
*fb
,
10301 struct drm_display_mode
*mode
)
10303 struct drm_device
*dev
= crtc
->dev
;
10304 struct intel_encoder
*encoder
;
10305 struct intel_crtc_state
*pipe_config
;
10306 int plane_bpp
, ret
= -EINVAL
;
10309 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10310 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10311 return ERR_PTR(-EINVAL
);
10314 if (!check_digital_port_conflicts(dev
)) {
10315 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10316 return ERR_PTR(-EINVAL
);
10319 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10321 return ERR_PTR(-ENOMEM
);
10323 pipe_config
->base
.crtc
= crtc
;
10324 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
10325 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
10327 pipe_config
->cpu_transcoder
=
10328 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10329 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10332 * Sanitize sync polarity flags based on requested ones. If neither
10333 * positive or negative polarity is requested, treat this as meaning
10334 * negative polarity.
10336 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10337 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10338 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10340 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10341 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10342 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10344 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10345 * plane pixel format and any sink constraints into account. Returns the
10346 * source plane bpp so that dithering can be selected on mismatches
10347 * after encoders and crtc also have had their say. */
10348 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10354 * Determine the real pipe dimensions. Note that stereo modes can
10355 * increase the actual pipe size due to the frame doubling and
10356 * insertion of additional space for blanks between the frame. This
10357 * is stored in the crtc timings. We use the requested mode to do this
10358 * computation to clearly distinguish it from the adjusted mode, which
10359 * can be changed by the connectors in the below retry loop.
10361 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
10362 &pipe_config
->pipe_src_w
,
10363 &pipe_config
->pipe_src_h
);
10366 /* Ensure the port clock defaults are reset when retrying. */
10367 pipe_config
->port_clock
= 0;
10368 pipe_config
->pixel_multiplier
= 1;
10370 /* Fill in default crtc timings, allow encoders to overwrite them. */
10371 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10372 CRTC_STEREO_DOUBLE
);
10374 /* Pass our mode to the connectors and the CRTC to give them a chance to
10375 * adjust it according to limitations or connector properties, and also
10376 * a chance to reject the mode entirely.
10378 for_each_intel_encoder(dev
, encoder
) {
10380 if (&encoder
->new_crtc
->base
!= crtc
)
10383 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10384 DRM_DEBUG_KMS("Encoder config failure\n");
10389 /* Set default port clock if not overwritten by the encoder. Needs to be
10390 * done afterwards in case the encoder adjusts the mode. */
10391 if (!pipe_config
->port_clock
)
10392 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10393 * pipe_config
->pixel_multiplier
;
10395 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10397 DRM_DEBUG_KMS("CRTC fixup failed\n");
10401 if (ret
== RETRY
) {
10402 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10407 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10409 goto encoder_retry
;
10412 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10413 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10414 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10416 return pipe_config
;
10418 kfree(pipe_config
);
10419 return ERR_PTR(ret
);
10422 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10423 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10425 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10426 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10428 struct intel_crtc
*intel_crtc
;
10429 struct drm_device
*dev
= crtc
->dev
;
10430 struct intel_encoder
*encoder
;
10431 struct intel_connector
*connector
;
10432 struct drm_crtc
*tmp_crtc
;
10434 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10436 /* Check which crtcs have changed outputs connected to them, these need
10437 * to be part of the prepare_pipes mask. We don't (yet) support global
10438 * modeset across multiple crtcs, so modeset_pipes will only have one
10439 * bit set at most. */
10440 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10442 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10445 if (connector
->base
.encoder
) {
10446 tmp_crtc
= connector
->base
.encoder
->crtc
;
10448 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10451 if (connector
->new_encoder
)
10453 1 << connector
->new_encoder
->new_crtc
->pipe
;
10456 for_each_intel_encoder(dev
, encoder
) {
10457 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10460 if (encoder
->base
.crtc
) {
10461 tmp_crtc
= encoder
->base
.crtc
;
10463 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10466 if (encoder
->new_crtc
)
10467 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10470 /* Check for pipes that will be enabled/disabled ... */
10471 for_each_intel_crtc(dev
, intel_crtc
) {
10472 if (intel_crtc
->base
.state
->enable
== intel_crtc
->new_enabled
)
10475 if (!intel_crtc
->new_enabled
)
10476 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10478 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10482 /* set_mode is also used to update properties on life display pipes. */
10483 intel_crtc
= to_intel_crtc(crtc
);
10484 if (intel_crtc
->new_enabled
)
10485 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10488 * For simplicity do a full modeset on any pipe where the output routing
10489 * changed. We could be more clever, but that would require us to be
10490 * more careful with calling the relevant encoder->mode_set functions.
10492 if (*prepare_pipes
)
10493 *modeset_pipes
= *prepare_pipes
;
10495 /* ... and mask these out. */
10496 *modeset_pipes
&= ~(*disable_pipes
);
10497 *prepare_pipes
&= ~(*disable_pipes
);
10500 * HACK: We don't (yet) fully support global modesets. intel_set_config
10501 * obies this rule, but the modeset restore mode of
10502 * intel_modeset_setup_hw_state does not.
10504 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10505 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10507 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10508 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10511 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10513 struct drm_encoder
*encoder
;
10514 struct drm_device
*dev
= crtc
->dev
;
10516 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10517 if (encoder
->crtc
== crtc
)
10524 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10527 struct intel_encoder
*intel_encoder
;
10528 struct intel_crtc
*intel_crtc
;
10529 struct drm_connector
*connector
;
10531 intel_shared_dpll_commit(dev_priv
);
10533 for_each_intel_encoder(dev
, intel_encoder
) {
10534 if (!intel_encoder
->base
.crtc
)
10537 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10539 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10540 intel_encoder
->connectors_active
= false;
10543 intel_modeset_commit_output_state(dev
);
10545 /* Double check state. */
10546 for_each_intel_crtc(dev
, intel_crtc
) {
10547 WARN_ON(intel_crtc
->base
.state
->enable
!= intel_crtc_in_use(&intel_crtc
->base
));
10548 WARN_ON(intel_crtc
->new_config
&&
10549 intel_crtc
->new_config
!= intel_crtc
->config
);
10550 WARN_ON(intel_crtc
->base
.state
->enable
!= !!intel_crtc
->new_config
);
10553 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10554 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10557 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10559 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10560 struct drm_property
*dpms_property
=
10561 dev
->mode_config
.dpms_property
;
10563 connector
->dpms
= DRM_MODE_DPMS_ON
;
10564 drm_object_property_set_value(&connector
->base
,
10568 intel_encoder
= to_intel_encoder(connector
->encoder
);
10569 intel_encoder
->connectors_active
= true;
10575 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10579 if (clock1
== clock2
)
10582 if (!clock1
|| !clock2
)
10585 diff
= abs(clock1
- clock2
);
10587 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10593 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10594 list_for_each_entry((intel_crtc), \
10595 &(dev)->mode_config.crtc_list, \
10597 if (mask & (1 <<(intel_crtc)->pipe))
10600 intel_pipe_config_compare(struct drm_device
*dev
,
10601 struct intel_crtc_state
*current_config
,
10602 struct intel_crtc_state
*pipe_config
)
10604 #define PIPE_CONF_CHECK_X(name) \
10605 if (current_config->name != pipe_config->name) { \
10606 DRM_ERROR("mismatch in " #name " " \
10607 "(expected 0x%08x, found 0x%08x)\n", \
10608 current_config->name, \
10609 pipe_config->name); \
10613 #define PIPE_CONF_CHECK_I(name) \
10614 if (current_config->name != pipe_config->name) { \
10615 DRM_ERROR("mismatch in " #name " " \
10616 "(expected %i, found %i)\n", \
10617 current_config->name, \
10618 pipe_config->name); \
10622 /* This is required for BDW+ where there is only one set of registers for
10623 * switching between high and low RR.
10624 * This macro can be used whenever a comparison has to be made between one
10625 * hw state and multiple sw state variables.
10627 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10628 if ((current_config->name != pipe_config->name) && \
10629 (current_config->alt_name != pipe_config->name)) { \
10630 DRM_ERROR("mismatch in " #name " " \
10631 "(expected %i or %i, found %i)\n", \
10632 current_config->name, \
10633 current_config->alt_name, \
10634 pipe_config->name); \
10638 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10639 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10640 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10641 "(expected %i, found %i)\n", \
10642 current_config->name & (mask), \
10643 pipe_config->name & (mask)); \
10647 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10648 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10649 DRM_ERROR("mismatch in " #name " " \
10650 "(expected %i, found %i)\n", \
10651 current_config->name, \
10652 pipe_config->name); \
10656 #define PIPE_CONF_QUIRK(quirk) \
10657 ((current_config->quirks | pipe_config->quirks) & (quirk))
10659 PIPE_CONF_CHECK_I(cpu_transcoder
);
10661 PIPE_CONF_CHECK_I(has_pch_encoder
);
10662 PIPE_CONF_CHECK_I(fdi_lanes
);
10663 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10664 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10665 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10666 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10667 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10669 PIPE_CONF_CHECK_I(has_dp_encoder
);
10671 if (INTEL_INFO(dev
)->gen
< 8) {
10672 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10673 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10674 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10675 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10676 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10678 if (current_config
->has_drrs
) {
10679 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10680 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10681 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10682 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10683 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10686 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10687 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10688 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10689 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10690 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10693 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
10694 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
10695 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
10696 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
10697 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
10698 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
10700 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
10701 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
10702 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
10703 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
10704 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
10705 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
10707 PIPE_CONF_CHECK_I(pixel_multiplier
);
10708 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10709 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10710 IS_VALLEYVIEW(dev
))
10711 PIPE_CONF_CHECK_I(limited_color_range
);
10712 PIPE_CONF_CHECK_I(has_infoframe
);
10714 PIPE_CONF_CHECK_I(has_audio
);
10716 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10717 DRM_MODE_FLAG_INTERLACE
);
10719 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10720 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10721 DRM_MODE_FLAG_PHSYNC
);
10722 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10723 DRM_MODE_FLAG_NHSYNC
);
10724 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10725 DRM_MODE_FLAG_PVSYNC
);
10726 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10727 DRM_MODE_FLAG_NVSYNC
);
10730 PIPE_CONF_CHECK_I(pipe_src_w
);
10731 PIPE_CONF_CHECK_I(pipe_src_h
);
10734 * FIXME: BIOS likes to set up a cloned config with lvds+external
10735 * screen. Since we don't yet re-compute the pipe config when moving
10736 * just the lvds port away to another pipe the sw tracking won't match.
10738 * Proper atomic modesets with recomputed global state will fix this.
10739 * Until then just don't check gmch state for inherited modes.
10741 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10742 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10743 /* pfit ratios are autocomputed by the hw on gen4+ */
10744 if (INTEL_INFO(dev
)->gen
< 4)
10745 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10746 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10749 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10750 if (current_config
->pch_pfit
.enabled
) {
10751 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10752 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10755 /* BDW+ don't expose a synchronous way to read the state */
10756 if (IS_HASWELL(dev
))
10757 PIPE_CONF_CHECK_I(ips_enabled
);
10759 PIPE_CONF_CHECK_I(double_wide
);
10761 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10763 PIPE_CONF_CHECK_I(shared_dpll
);
10764 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10765 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10766 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10767 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10768 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10769 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
10770 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
10771 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
10773 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10774 PIPE_CONF_CHECK_I(pipe_bpp
);
10776 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
10777 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10779 #undef PIPE_CONF_CHECK_X
10780 #undef PIPE_CONF_CHECK_I
10781 #undef PIPE_CONF_CHECK_I_ALT
10782 #undef PIPE_CONF_CHECK_FLAGS
10783 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10784 #undef PIPE_CONF_QUIRK
10789 static void check_wm_state(struct drm_device
*dev
)
10791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10792 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
10793 struct intel_crtc
*intel_crtc
;
10796 if (INTEL_INFO(dev
)->gen
< 9)
10799 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
10800 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
10802 for_each_intel_crtc(dev
, intel_crtc
) {
10803 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
10804 const enum pipe pipe
= intel_crtc
->pipe
;
10806 if (!intel_crtc
->active
)
10810 for_each_plane(dev_priv
, pipe
, plane
) {
10811 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
10812 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
10814 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10817 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10818 "(expected (%u,%u), found (%u,%u))\n",
10819 pipe_name(pipe
), plane
+ 1,
10820 sw_entry
->start
, sw_entry
->end
,
10821 hw_entry
->start
, hw_entry
->end
);
10825 hw_entry
= &hw_ddb
.cursor
[pipe
];
10826 sw_entry
= &sw_ddb
->cursor
[pipe
];
10828 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10831 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10832 "(expected (%u,%u), found (%u,%u))\n",
10834 sw_entry
->start
, sw_entry
->end
,
10835 hw_entry
->start
, hw_entry
->end
);
10840 check_connector_state(struct drm_device
*dev
)
10842 struct intel_connector
*connector
;
10844 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10846 /* This also checks the encoder/connector hw state with the
10847 * ->get_hw_state callbacks. */
10848 intel_connector_check_state(connector
);
10850 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10851 "connector's staged encoder doesn't match current encoder\n");
10856 check_encoder_state(struct drm_device
*dev
)
10858 struct intel_encoder
*encoder
;
10859 struct intel_connector
*connector
;
10861 for_each_intel_encoder(dev
, encoder
) {
10862 bool enabled
= false;
10863 bool active
= false;
10864 enum pipe pipe
, tracked_pipe
;
10866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10867 encoder
->base
.base
.id
,
10868 encoder
->base
.name
);
10870 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10871 "encoder's stage crtc doesn't match current crtc\n");
10872 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10873 "encoder's active_connectors set, but no crtc\n");
10875 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10877 if (connector
->base
.encoder
!= &encoder
->base
)
10880 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10884 * for MST connectors if we unplug the connector is gone
10885 * away but the encoder is still connected to a crtc
10886 * until a modeset happens in response to the hotplug.
10888 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10891 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
10892 "encoder's enabled state mismatch "
10893 "(expected %i, found %i)\n",
10894 !!encoder
->base
.crtc
, enabled
);
10895 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
10896 "active encoder with no crtc\n");
10898 I915_STATE_WARN(encoder
->connectors_active
!= active
,
10899 "encoder's computed active state doesn't match tracked active state "
10900 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10902 active
= encoder
->get_hw_state(encoder
, &pipe
);
10903 I915_STATE_WARN(active
!= encoder
->connectors_active
,
10904 "encoder's hw state doesn't match sw tracking "
10905 "(expected %i, found %i)\n",
10906 encoder
->connectors_active
, active
);
10908 if (!encoder
->base
.crtc
)
10911 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10912 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
10913 "active encoder's pipe doesn't match"
10914 "(expected %i, found %i)\n",
10915 tracked_pipe
, pipe
);
10921 check_crtc_state(struct drm_device
*dev
)
10923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10924 struct intel_crtc
*crtc
;
10925 struct intel_encoder
*encoder
;
10926 struct intel_crtc_state pipe_config
;
10928 for_each_intel_crtc(dev
, crtc
) {
10929 bool enabled
= false;
10930 bool active
= false;
10932 memset(&pipe_config
, 0, sizeof(pipe_config
));
10934 DRM_DEBUG_KMS("[CRTC:%d]\n",
10935 crtc
->base
.base
.id
);
10937 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
10938 "active crtc, but not enabled in sw tracking\n");
10940 for_each_intel_encoder(dev
, encoder
) {
10941 if (encoder
->base
.crtc
!= &crtc
->base
)
10944 if (encoder
->connectors_active
)
10948 I915_STATE_WARN(active
!= crtc
->active
,
10949 "crtc's computed active state doesn't match tracked active state "
10950 "(expected %i, found %i)\n", active
, crtc
->active
);
10951 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
10952 "crtc's computed enabled state doesn't match tracked enabled state "
10953 "(expected %i, found %i)\n", enabled
,
10954 crtc
->base
.state
->enable
);
10956 active
= dev_priv
->display
.get_pipe_config(crtc
,
10959 /* hw state is inconsistent with the pipe quirk */
10960 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10961 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10962 active
= crtc
->active
;
10964 for_each_intel_encoder(dev
, encoder
) {
10966 if (encoder
->base
.crtc
!= &crtc
->base
)
10968 if (encoder
->get_hw_state(encoder
, &pipe
))
10969 encoder
->get_config(encoder
, &pipe_config
);
10972 I915_STATE_WARN(crtc
->active
!= active
,
10973 "crtc active state doesn't match with hw state "
10974 "(expected %i, found %i)\n", crtc
->active
, active
);
10977 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
10978 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10979 intel_dump_pipe_config(crtc
, &pipe_config
,
10981 intel_dump_pipe_config(crtc
, crtc
->config
,
10988 check_shared_dpll_state(struct drm_device
*dev
)
10990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10991 struct intel_crtc
*crtc
;
10992 struct intel_dpll_hw_state dpll_hw_state
;
10995 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10996 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10997 int enabled_crtcs
= 0, active_crtcs
= 0;
11000 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
11002 DRM_DEBUG_KMS("%s\n", pll
->name
);
11004 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11006 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
11007 "more active pll users than references: %i vs %i\n",
11008 pll
->active
, hweight32(pll
->config
.crtc_mask
));
11009 I915_STATE_WARN(pll
->active
&& !pll
->on
,
11010 "pll in active use but not on in sw tracking\n");
11011 I915_STATE_WARN(pll
->on
&& !pll
->active
,
11012 "pll in on but not on in use in sw tracking\n");
11013 I915_STATE_WARN(pll
->on
!= active
,
11014 "pll on state mismatch (expected %i, found %i)\n",
11017 for_each_intel_crtc(dev
, crtc
) {
11018 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11020 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11023 I915_STATE_WARN(pll
->active
!= active_crtcs
,
11024 "pll active crtcs mismatch (expected %i, found %i)\n",
11025 pll
->active
, active_crtcs
);
11026 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
11027 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11028 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
11030 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
11031 sizeof(dpll_hw_state
)),
11032 "pll hw state mismatch\n");
11037 intel_modeset_check_state(struct drm_device
*dev
)
11039 check_wm_state(dev
);
11040 check_connector_state(dev
);
11041 check_encoder_state(dev
);
11042 check_crtc_state(dev
);
11043 check_shared_dpll_state(dev
);
11046 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
11050 * FDI already provided one idea for the dotclock.
11051 * Yell if the encoder disagrees.
11053 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
11054 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11055 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
11058 static void update_scanline_offset(struct intel_crtc
*crtc
)
11060 struct drm_device
*dev
= crtc
->base
.dev
;
11063 * The scanline counter increments at the leading edge of hsync.
11065 * On most platforms it starts counting from vtotal-1 on the
11066 * first active line. That means the scanline counter value is
11067 * always one less than what we would expect. Ie. just after
11068 * start of vblank, which also occurs at start of hsync (on the
11069 * last active line), the scanline counter will read vblank_start-1.
11071 * On gen2 the scanline counter starts counting from 1 instead
11072 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11073 * to keep the value positive), instead of adding one.
11075 * On HSW+ the behaviour of the scanline counter depends on the output
11076 * type. For DP ports it behaves like most other platforms, but on HDMI
11077 * there's an extra 1 line difference. So we need to add two instead of
11078 * one to the value.
11080 if (IS_GEN2(dev
)) {
11081 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
11084 vtotal
= mode
->crtc_vtotal
;
11085 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11088 crtc
->scanline_offset
= vtotal
- 1;
11089 } else if (HAS_DDI(dev
) &&
11090 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
11091 crtc
->scanline_offset
= 2;
11093 crtc
->scanline_offset
= 1;
11096 static struct intel_crtc_state
*
11097 intel_modeset_compute_config(struct drm_crtc
*crtc
,
11098 struct drm_display_mode
*mode
,
11099 struct drm_framebuffer
*fb
,
11100 unsigned *modeset_pipes
,
11101 unsigned *prepare_pipes
,
11102 unsigned *disable_pipes
)
11104 struct intel_crtc_state
*pipe_config
= NULL
;
11106 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
11107 prepare_pipes
, disable_pipes
);
11109 if ((*modeset_pipes
) == 0)
11113 * Note this needs changes when we start tracking multiple modes
11114 * and crtcs. At that point we'll need to compute the whole config
11115 * (i.e. one pipe_config for each crtc) rather than just the one
11118 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11119 if (IS_ERR(pipe_config
)) {
11122 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11126 return pipe_config
;
11129 static int __intel_set_mode_setup_plls(struct drm_device
*dev
,
11130 unsigned modeset_pipes
,
11131 unsigned disable_pipes
)
11133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11134 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
11135 struct intel_crtc
*intel_crtc
;
11138 if (!dev_priv
->display
.crtc_compute_clock
)
11141 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
11145 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11146 struct intel_crtc_state
*state
= intel_crtc
->new_config
;
11147 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11150 intel_shared_dpll_abort_config(dev_priv
);
11159 static int __intel_set_mode(struct drm_crtc
*crtc
,
11160 struct drm_display_mode
*mode
,
11161 int x
, int y
, struct drm_framebuffer
*fb
,
11162 struct intel_crtc_state
*pipe_config
,
11163 unsigned modeset_pipes
,
11164 unsigned prepare_pipes
,
11165 unsigned disable_pipes
)
11167 struct drm_device
*dev
= crtc
->dev
;
11168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11169 struct drm_display_mode
*saved_mode
;
11170 struct intel_crtc
*intel_crtc
;
11173 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11177 *saved_mode
= crtc
->mode
;
11180 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11183 * See if the config requires any additional preparation, e.g.
11184 * to adjust global state with pipes off. We need to do this
11185 * here so we can get the modeset_pipe updated config for the new
11186 * mode set on this crtc. For other crtcs we need to use the
11187 * adjusted_mode bits in the crtc directly.
11189 if (IS_VALLEYVIEW(dev
)) {
11190 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11192 /* may have added more to prepare_pipes than we should */
11193 prepare_pipes
&= ~disable_pipes
;
11196 ret
= __intel_set_mode_setup_plls(dev
, modeset_pipes
, disable_pipes
);
11200 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11201 intel_crtc_disable(&intel_crtc
->base
);
11203 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11204 if (intel_crtc
->base
.state
->enable
)
11205 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11208 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11209 * to set it here already despite that we pass it down the callchain.
11211 * Note we'll need to fix this up when we start tracking multiple
11212 * pipes; here we assume a single modeset_pipe and only track the
11213 * single crtc and mode.
11215 if (modeset_pipes
) {
11216 crtc
->mode
= *mode
;
11217 /* mode_set/enable/disable functions rely on a correct pipe
11219 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
11222 * Calculate and store various constants which
11223 * are later needed by vblank and swap-completion
11224 * timestamping. They are derived from true hwmode.
11226 drm_calc_timestamping_constants(crtc
,
11227 &pipe_config
->base
.adjusted_mode
);
11230 /* Only after disabling all output pipelines that will be changed can we
11231 * update the the output configuration. */
11232 intel_modeset_update_state(dev
, prepare_pipes
);
11234 modeset_update_crtc_power_domains(dev
);
11236 /* Set up the DPLL and any encoders state that needs to adjust or depend
11239 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11240 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
11241 int vdisplay
, hdisplay
;
11243 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11244 ret
= primary
->funcs
->update_plane(primary
, &intel_crtc
->base
,
11246 hdisplay
, vdisplay
,
11248 hdisplay
<< 16, vdisplay
<< 16);
11251 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11252 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11253 update_scanline_offset(intel_crtc
);
11255 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11258 /* FIXME: add subpixel order */
11260 if (ret
&& crtc
->state
->enable
)
11261 crtc
->mode
= *saved_mode
;
11267 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11268 struct drm_display_mode
*mode
,
11269 int x
, int y
, struct drm_framebuffer
*fb
,
11270 struct intel_crtc_state
*pipe_config
,
11271 unsigned modeset_pipes
,
11272 unsigned prepare_pipes
,
11273 unsigned disable_pipes
)
11277 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11278 prepare_pipes
, disable_pipes
);
11281 intel_modeset_check_state(crtc
->dev
);
11286 static int intel_set_mode(struct drm_crtc
*crtc
,
11287 struct drm_display_mode
*mode
,
11288 int x
, int y
, struct drm_framebuffer
*fb
)
11290 struct intel_crtc_state
*pipe_config
;
11291 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11293 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
,
11298 if (IS_ERR(pipe_config
))
11299 return PTR_ERR(pipe_config
);
11301 return intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11302 modeset_pipes
, prepare_pipes
,
11306 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11308 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11311 #undef for_each_intel_crtc_masked
11313 static void intel_set_config_free(struct intel_set_config
*config
)
11318 kfree(config
->save_connector_encoders
);
11319 kfree(config
->save_encoder_crtcs
);
11320 kfree(config
->save_crtc_enabled
);
11324 static int intel_set_config_save_state(struct drm_device
*dev
,
11325 struct intel_set_config
*config
)
11327 struct drm_crtc
*crtc
;
11328 struct drm_encoder
*encoder
;
11329 struct drm_connector
*connector
;
11332 config
->save_crtc_enabled
=
11333 kcalloc(dev
->mode_config
.num_crtc
,
11334 sizeof(bool), GFP_KERNEL
);
11335 if (!config
->save_crtc_enabled
)
11338 config
->save_encoder_crtcs
=
11339 kcalloc(dev
->mode_config
.num_encoder
,
11340 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11341 if (!config
->save_encoder_crtcs
)
11344 config
->save_connector_encoders
=
11345 kcalloc(dev
->mode_config
.num_connector
,
11346 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11347 if (!config
->save_connector_encoders
)
11350 /* Copy data. Note that driver private data is not affected.
11351 * Should anything bad happen only the expected state is
11352 * restored, not the drivers personal bookkeeping.
11355 for_each_crtc(dev
, crtc
) {
11356 config
->save_crtc_enabled
[count
++] = crtc
->state
->enable
;
11360 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11361 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11365 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11366 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11372 static void intel_set_config_restore_state(struct drm_device
*dev
,
11373 struct intel_set_config
*config
)
11375 struct intel_crtc
*crtc
;
11376 struct intel_encoder
*encoder
;
11377 struct intel_connector
*connector
;
11381 for_each_intel_crtc(dev
, crtc
) {
11382 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11384 if (crtc
->new_enabled
)
11385 crtc
->new_config
= crtc
->config
;
11387 crtc
->new_config
= NULL
;
11391 for_each_intel_encoder(dev
, encoder
) {
11392 encoder
->new_crtc
=
11393 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11397 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11398 connector
->new_encoder
=
11399 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11404 is_crtc_connector_off(struct drm_mode_set
*set
)
11408 if (set
->num_connectors
== 0)
11411 if (WARN_ON(set
->connectors
== NULL
))
11414 for (i
= 0; i
< set
->num_connectors
; i
++)
11415 if (set
->connectors
[i
]->encoder
&&
11416 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11417 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11424 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11425 struct intel_set_config
*config
)
11428 /* We should be able to check here if the fb has the same properties
11429 * and then just flip_or_move it */
11430 if (is_crtc_connector_off(set
)) {
11431 config
->mode_changed
= true;
11432 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11434 * If we have no fb, we can only flip as long as the crtc is
11435 * active, otherwise we need a full mode set. The crtc may
11436 * be active if we've only disabled the primary plane, or
11437 * in fastboot situations.
11439 if (set
->crtc
->primary
->fb
== NULL
) {
11440 struct intel_crtc
*intel_crtc
=
11441 to_intel_crtc(set
->crtc
);
11443 if (intel_crtc
->active
) {
11444 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11445 config
->fb_changed
= true;
11447 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11448 config
->mode_changed
= true;
11450 } else if (set
->fb
== NULL
) {
11451 config
->mode_changed
= true;
11452 } else if (set
->fb
->pixel_format
!=
11453 set
->crtc
->primary
->fb
->pixel_format
) {
11454 config
->mode_changed
= true;
11456 config
->fb_changed
= true;
11460 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11461 config
->fb_changed
= true;
11463 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11464 DRM_DEBUG_KMS("modes are different, full mode set\n");
11465 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11466 drm_mode_debug_printmodeline(set
->mode
);
11467 config
->mode_changed
= true;
11470 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11471 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11475 intel_modeset_stage_output_state(struct drm_device
*dev
,
11476 struct drm_mode_set
*set
,
11477 struct intel_set_config
*config
)
11479 struct intel_connector
*connector
;
11480 struct intel_encoder
*encoder
;
11481 struct intel_crtc
*crtc
;
11484 /* The upper layers ensure that we either disable a crtc or have a list
11485 * of connectors. For paranoia, double-check this. */
11486 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11487 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11489 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11491 /* Otherwise traverse passed in connector list and get encoders
11493 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11494 if (set
->connectors
[ro
] == &connector
->base
) {
11495 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11500 /* If we disable the crtc, disable all its connectors. Also, if
11501 * the connector is on the changing crtc but not on the new
11502 * connector list, disable it. */
11503 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11504 connector
->base
.encoder
&&
11505 connector
->base
.encoder
->crtc
== set
->crtc
) {
11506 connector
->new_encoder
= NULL
;
11508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11509 connector
->base
.base
.id
,
11510 connector
->base
.name
);
11514 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11515 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11516 config
->mode_changed
= true;
11519 /* connector->new_encoder is now updated for all connectors. */
11521 /* Update crtc of enabled connectors. */
11522 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11524 struct drm_crtc
*new_crtc
;
11526 if (!connector
->new_encoder
)
11529 new_crtc
= connector
->new_encoder
->base
.crtc
;
11531 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11532 if (set
->connectors
[ro
] == &connector
->base
)
11533 new_crtc
= set
->crtc
;
11536 /* Make sure the new CRTC will work with the encoder */
11537 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11541 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11543 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11544 connector
->base
.base
.id
,
11545 connector
->base
.name
,
11546 new_crtc
->base
.id
);
11549 /* Check for any encoders that needs to be disabled. */
11550 for_each_intel_encoder(dev
, encoder
) {
11551 int num_connectors
= 0;
11552 list_for_each_entry(connector
,
11553 &dev
->mode_config
.connector_list
,
11555 if (connector
->new_encoder
== encoder
) {
11556 WARN_ON(!connector
->new_encoder
->new_crtc
);
11561 if (num_connectors
== 0)
11562 encoder
->new_crtc
= NULL
;
11563 else if (num_connectors
> 1)
11566 /* Only now check for crtc changes so we don't miss encoders
11567 * that will be disabled. */
11568 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11569 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11570 config
->mode_changed
= true;
11573 /* Now we've also updated encoder->new_crtc for all encoders. */
11574 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11576 if (connector
->new_encoder
)
11577 if (connector
->new_encoder
!= connector
->encoder
)
11578 connector
->encoder
= connector
->new_encoder
;
11580 for_each_intel_crtc(dev
, crtc
) {
11581 crtc
->new_enabled
= false;
11583 for_each_intel_encoder(dev
, encoder
) {
11584 if (encoder
->new_crtc
== crtc
) {
11585 crtc
->new_enabled
= true;
11590 if (crtc
->new_enabled
!= crtc
->base
.state
->enable
) {
11591 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11592 crtc
->new_enabled
? "en" : "dis");
11593 config
->mode_changed
= true;
11596 if (crtc
->new_enabled
)
11597 crtc
->new_config
= crtc
->config
;
11599 crtc
->new_config
= NULL
;
11605 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11607 struct drm_device
*dev
= crtc
->base
.dev
;
11608 struct intel_encoder
*encoder
;
11609 struct intel_connector
*connector
;
11611 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11612 pipe_name(crtc
->pipe
));
11614 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11615 if (connector
->new_encoder
&&
11616 connector
->new_encoder
->new_crtc
== crtc
)
11617 connector
->new_encoder
= NULL
;
11620 for_each_intel_encoder(dev
, encoder
) {
11621 if (encoder
->new_crtc
== crtc
)
11622 encoder
->new_crtc
= NULL
;
11625 crtc
->new_enabled
= false;
11626 crtc
->new_config
= NULL
;
11629 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11631 struct drm_device
*dev
;
11632 struct drm_mode_set save_set
;
11633 struct intel_set_config
*config
;
11634 struct intel_crtc_state
*pipe_config
;
11635 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11639 BUG_ON(!set
->crtc
);
11640 BUG_ON(!set
->crtc
->helper_private
);
11642 /* Enforce sane interface api - has been abused by the fb helper. */
11643 BUG_ON(!set
->mode
&& set
->fb
);
11644 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11647 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11648 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11649 (int)set
->num_connectors
, set
->x
, set
->y
);
11651 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11654 dev
= set
->crtc
->dev
;
11657 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11661 ret
= intel_set_config_save_state(dev
, config
);
11665 save_set
.crtc
= set
->crtc
;
11666 save_set
.mode
= &set
->crtc
->mode
;
11667 save_set
.x
= set
->crtc
->x
;
11668 save_set
.y
= set
->crtc
->y
;
11669 save_set
.fb
= set
->crtc
->primary
->fb
;
11671 /* Compute whether we need a full modeset, only an fb base update or no
11672 * change at all. In the future we might also check whether only the
11673 * mode changed, e.g. for LVDS where we only change the panel fitter in
11675 intel_set_config_compute_mode_changes(set
, config
);
11677 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11681 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
11686 if (IS_ERR(pipe_config
)) {
11687 ret
= PTR_ERR(pipe_config
);
11689 } else if (pipe_config
) {
11690 if (pipe_config
->has_audio
!=
11691 to_intel_crtc(set
->crtc
)->config
->has_audio
)
11692 config
->mode_changed
= true;
11695 * Note we have an issue here with infoframes: current code
11696 * only updates them on the full mode set path per hw
11697 * requirements. So here we should be checking for any
11698 * required changes and forcing a mode set.
11702 /* set_mode will free it in the mode_changed case */
11703 if (!config
->mode_changed
)
11704 kfree(pipe_config
);
11706 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
11708 if (config
->mode_changed
) {
11709 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
11710 set
->x
, set
->y
, set
->fb
, pipe_config
,
11711 modeset_pipes
, prepare_pipes
,
11713 } else if (config
->fb_changed
) {
11714 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11715 struct drm_plane
*primary
= set
->crtc
->primary
;
11716 int vdisplay
, hdisplay
;
11718 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
11719 ret
= primary
->funcs
->update_plane(primary
, set
->crtc
, set
->fb
,
11720 0, 0, hdisplay
, vdisplay
,
11721 set
->x
<< 16, set
->y
<< 16,
11722 hdisplay
<< 16, vdisplay
<< 16);
11725 * We need to make sure the primary plane is re-enabled if it
11726 * has previously been turned off.
11728 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11729 WARN_ON(!intel_crtc
->active
);
11730 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11734 * In the fastboot case this may be our only check of the
11735 * state after boot. It would be better to only do it on
11736 * the first update, but we don't have a nice way of doing that
11737 * (and really, set_config isn't used much for high freq page
11738 * flipping, so increasing its cost here shouldn't be a big
11741 if (i915
.fastboot
&& ret
== 0)
11742 intel_modeset_check_state(set
->crtc
->dev
);
11746 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11747 set
->crtc
->base
.id
, ret
);
11749 intel_set_config_restore_state(dev
, config
);
11752 * HACK: if the pipe was on, but we didn't have a framebuffer,
11753 * force the pipe off to avoid oopsing in the modeset code
11754 * due to fb==NULL. This should only happen during boot since
11755 * we don't yet reconstruct the FB from the hardware state.
11757 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11758 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11760 /* Try to restore the config */
11761 if (config
->mode_changed
&&
11762 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11763 save_set
.x
, save_set
.y
, save_set
.fb
))
11764 DRM_ERROR("failed to restore config after modeset failure\n");
11768 intel_set_config_free(config
);
11772 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11773 .gamma_set
= intel_crtc_gamma_set
,
11774 .set_config
= intel_crtc_set_config
,
11775 .destroy
= intel_crtc_destroy
,
11776 .page_flip
= intel_crtc_page_flip
,
11777 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
11778 .atomic_destroy_state
= intel_crtc_destroy_state
,
11781 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11782 struct intel_shared_dpll
*pll
,
11783 struct intel_dpll_hw_state
*hw_state
)
11787 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11790 val
= I915_READ(PCH_DPLL(pll
->id
));
11791 hw_state
->dpll
= val
;
11792 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11793 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11795 return val
& DPLL_VCO_ENABLE
;
11798 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11799 struct intel_shared_dpll
*pll
)
11801 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11802 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11805 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11806 struct intel_shared_dpll
*pll
)
11808 /* PCH refclock must be enabled first */
11809 ibx_assert_pch_refclk_enabled(dev_priv
);
11811 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11813 /* Wait for the clocks to stabilize. */
11814 POSTING_READ(PCH_DPLL(pll
->id
));
11817 /* The pixel multiplier can only be updated once the
11818 * DPLL is enabled and the clocks are stable.
11820 * So write it again.
11822 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11823 POSTING_READ(PCH_DPLL(pll
->id
));
11827 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11828 struct intel_shared_dpll
*pll
)
11830 struct drm_device
*dev
= dev_priv
->dev
;
11831 struct intel_crtc
*crtc
;
11833 /* Make sure no transcoder isn't still depending on us. */
11834 for_each_intel_crtc(dev
, crtc
) {
11835 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11836 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11839 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11840 POSTING_READ(PCH_DPLL(pll
->id
));
11844 static char *ibx_pch_dpll_names
[] = {
11849 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11854 dev_priv
->num_shared_dpll
= 2;
11856 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11857 dev_priv
->shared_dplls
[i
].id
= i
;
11858 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11859 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11860 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11861 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11862 dev_priv
->shared_dplls
[i
].get_hw_state
=
11863 ibx_pch_dpll_get_hw_state
;
11867 static void intel_shared_dpll_init(struct drm_device
*dev
)
11869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11872 intel_ddi_pll_init(dev
);
11873 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11874 ibx_pch_dpll_init(dev
);
11876 dev_priv
->num_shared_dpll
= 0;
11878 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11882 * intel_prepare_plane_fb - Prepare fb for usage on plane
11883 * @plane: drm plane to prepare for
11884 * @fb: framebuffer to prepare for presentation
11886 * Prepares a framebuffer for usage on a display plane. Generally this
11887 * involves pinning the underlying object and updating the frontbuffer tracking
11888 * bits. Some older platforms need special physical address handling for
11891 * Returns 0 on success, negative error code on failure.
11894 intel_prepare_plane_fb(struct drm_plane
*plane
,
11895 struct drm_framebuffer
*fb
,
11896 const struct drm_plane_state
*new_state
)
11898 struct drm_device
*dev
= plane
->dev
;
11899 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11900 enum pipe pipe
= intel_plane
->pipe
;
11901 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11902 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11903 unsigned frontbuffer_bits
= 0;
11909 switch (plane
->type
) {
11910 case DRM_PLANE_TYPE_PRIMARY
:
11911 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
11913 case DRM_PLANE_TYPE_CURSOR
:
11914 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
11916 case DRM_PLANE_TYPE_OVERLAY
:
11917 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
11921 mutex_lock(&dev
->struct_mutex
);
11923 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
11924 INTEL_INFO(dev
)->cursor_needs_physical
) {
11925 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
11926 ret
= i915_gem_object_attach_phys(obj
, align
);
11928 DRM_DEBUG_KMS("failed to attach phys object\n");
11930 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11934 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
11936 mutex_unlock(&dev
->struct_mutex
);
11942 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11943 * @plane: drm plane to clean up for
11944 * @fb: old framebuffer that was on plane
11946 * Cleans up a framebuffer that has just been removed from a plane.
11949 intel_cleanup_plane_fb(struct drm_plane
*plane
,
11950 struct drm_framebuffer
*fb
,
11951 const struct drm_plane_state
*old_state
)
11953 struct drm_device
*dev
= plane
->dev
;
11954 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11959 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
11960 !INTEL_INFO(dev
)->cursor_needs_physical
) {
11961 mutex_lock(&dev
->struct_mutex
);
11962 intel_unpin_fb_obj(obj
);
11963 mutex_unlock(&dev
->struct_mutex
);
11968 intel_check_primary_plane(struct drm_plane
*plane
,
11969 struct intel_plane_state
*state
)
11971 struct drm_device
*dev
= plane
->dev
;
11972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11973 struct drm_crtc
*crtc
= state
->base
.crtc
;
11974 struct intel_crtc
*intel_crtc
;
11975 struct drm_framebuffer
*fb
= state
->base
.fb
;
11976 struct drm_rect
*dest
= &state
->dst
;
11977 struct drm_rect
*src
= &state
->src
;
11978 const struct drm_rect
*clip
= &state
->clip
;
11981 crtc
= crtc
? crtc
: plane
->crtc
;
11982 intel_crtc
= to_intel_crtc(crtc
);
11984 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11986 DRM_PLANE_HELPER_NO_SCALING
,
11987 DRM_PLANE_HELPER_NO_SCALING
,
11988 false, true, &state
->visible
);
11992 if (intel_crtc
->active
) {
11993 intel_crtc
->atomic
.wait_for_flips
= true;
11996 * FBC does not work on some platforms for rotated
11997 * planes, so disable it when rotation is not 0 and
11998 * update it when rotation is set back to 0.
12000 * FIXME: This is redundant with the fbc update done in
12001 * the primary plane enable function except that that
12002 * one is done too late. We eventually need to unify
12005 if (intel_crtc
->primary_enabled
&&
12006 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
12007 dev_priv
->fbc
.crtc
== intel_crtc
&&
12008 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
12009 intel_crtc
->atomic
.disable_fbc
= true;
12012 if (state
->visible
) {
12014 * BDW signals flip done immediately if the plane
12015 * is disabled, even if the plane enable is already
12016 * armed to occur at the next vblank :(
12018 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
12019 intel_crtc
->atomic
.wait_vblank
= true;
12022 intel_crtc
->atomic
.fb_bits
|=
12023 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
12025 intel_crtc
->atomic
.update_fbc
= true;
12027 /* Update watermarks on tiling changes. */
12028 if (!plane
->state
->fb
|| !state
->base
.fb
||
12029 plane
->state
->fb
->modifier
[0] !=
12030 state
->base
.fb
->modifier
[0])
12031 intel_crtc
->atomic
.update_wm
= true;
12038 intel_commit_primary_plane(struct drm_plane
*plane
,
12039 struct intel_plane_state
*state
)
12041 struct drm_crtc
*crtc
= state
->base
.crtc
;
12042 struct drm_framebuffer
*fb
= state
->base
.fb
;
12043 struct drm_device
*dev
= plane
->dev
;
12044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12045 struct intel_crtc
*intel_crtc
;
12046 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12047 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12048 struct drm_rect
*src
= &state
->src
;
12050 crtc
= crtc
? crtc
: plane
->crtc
;
12051 intel_crtc
= to_intel_crtc(crtc
);
12054 crtc
->x
= src
->x1
>> 16;
12055 crtc
->y
= src
->y1
>> 16;
12057 intel_plane
->obj
= obj
;
12059 if (intel_crtc
->active
) {
12060 if (state
->visible
) {
12061 /* FIXME: kill this fastboot hack */
12062 intel_update_pipe_size(intel_crtc
);
12064 intel_crtc
->primary_enabled
= true;
12066 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
12070 * If clipping results in a non-visible primary plane,
12071 * we'll disable the primary plane. Note that this is
12072 * a bit different than what happens if userspace
12073 * explicitly disables the plane by passing fb=0
12074 * because plane->fb still gets set and pinned.
12076 intel_disable_primary_hw_plane(plane
, crtc
);
12081 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
12083 struct drm_device
*dev
= crtc
->dev
;
12084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12085 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12086 struct intel_plane
*intel_plane
;
12087 struct drm_plane
*p
;
12088 unsigned fb_bits
= 0;
12090 /* Track fb's for any planes being disabled */
12091 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
12092 intel_plane
= to_intel_plane(p
);
12094 if (intel_crtc
->atomic
.disabled_planes
&
12095 (1 << drm_plane_index(p
))) {
12097 case DRM_PLANE_TYPE_PRIMARY
:
12098 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
12100 case DRM_PLANE_TYPE_CURSOR
:
12101 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
12103 case DRM_PLANE_TYPE_OVERLAY
:
12104 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
12108 mutex_lock(&dev
->struct_mutex
);
12109 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
12110 mutex_unlock(&dev
->struct_mutex
);
12114 if (intel_crtc
->atomic
.wait_for_flips
)
12115 intel_crtc_wait_for_pending_flips(crtc
);
12117 if (intel_crtc
->atomic
.disable_fbc
)
12118 intel_fbc_disable(dev
);
12120 if (intel_crtc
->atomic
.pre_disable_primary
)
12121 intel_pre_disable_primary(crtc
);
12123 if (intel_crtc
->atomic
.update_wm
)
12124 intel_update_watermarks(crtc
);
12126 intel_runtime_pm_get(dev_priv
);
12128 /* Perform vblank evasion around commit operation */
12129 if (intel_crtc
->active
)
12130 intel_crtc
->atomic
.evade
=
12131 intel_pipe_update_start(intel_crtc
,
12132 &intel_crtc
->atomic
.start_vbl_count
);
12135 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
12137 struct drm_device
*dev
= crtc
->dev
;
12138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12139 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12140 struct drm_plane
*p
;
12142 if (intel_crtc
->atomic
.evade
)
12143 intel_pipe_update_end(intel_crtc
,
12144 intel_crtc
->atomic
.start_vbl_count
);
12146 intel_runtime_pm_put(dev_priv
);
12148 if (intel_crtc
->atomic
.wait_vblank
)
12149 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
12151 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
12153 if (intel_crtc
->atomic
.update_fbc
) {
12154 mutex_lock(&dev
->struct_mutex
);
12155 intel_fbc_update(dev
);
12156 mutex_unlock(&dev
->struct_mutex
);
12159 if (intel_crtc
->atomic
.post_enable_primary
)
12160 intel_post_enable_primary(crtc
);
12162 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
12163 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
12164 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
12167 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
12171 * intel_plane_destroy - destroy a plane
12172 * @plane: plane to destroy
12174 * Common destruction function for all types of planes (primary, cursor,
12177 void intel_plane_destroy(struct drm_plane
*plane
)
12179 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12180 drm_plane_cleanup(plane
);
12181 kfree(intel_plane
);
12184 const struct drm_plane_funcs intel_plane_funcs
= {
12185 .update_plane
= drm_plane_helper_update
,
12186 .disable_plane
= drm_plane_helper_disable
,
12187 .destroy
= intel_plane_destroy
,
12188 .set_property
= drm_atomic_helper_plane_set_property
,
12189 .atomic_get_property
= intel_plane_atomic_get_property
,
12190 .atomic_set_property
= intel_plane_atomic_set_property
,
12191 .atomic_duplicate_state
= intel_plane_duplicate_state
,
12192 .atomic_destroy_state
= intel_plane_destroy_state
,
12196 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12199 struct intel_plane
*primary
;
12200 struct intel_plane_state
*state
;
12201 const uint32_t *intel_primary_formats
;
12204 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12205 if (primary
== NULL
)
12208 state
= intel_create_plane_state(&primary
->base
);
12213 primary
->base
.state
= &state
->base
;
12215 primary
->can_scale
= false;
12216 primary
->max_downscale
= 1;
12217 primary
->pipe
= pipe
;
12218 primary
->plane
= pipe
;
12219 primary
->check_plane
= intel_check_primary_plane
;
12220 primary
->commit_plane
= intel_commit_primary_plane
;
12221 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12222 primary
->plane
= !pipe
;
12224 if (INTEL_INFO(dev
)->gen
<= 3) {
12225 intel_primary_formats
= intel_primary_formats_gen2
;
12226 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12228 intel_primary_formats
= intel_primary_formats_gen4
;
12229 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12232 drm_universal_plane_init(dev
, &primary
->base
, 0,
12233 &intel_plane_funcs
,
12234 intel_primary_formats
, num_formats
,
12235 DRM_PLANE_TYPE_PRIMARY
);
12237 if (INTEL_INFO(dev
)->gen
>= 4) {
12238 if (!dev
->mode_config
.rotation_property
)
12239 dev
->mode_config
.rotation_property
=
12240 drm_mode_create_rotation_property(dev
,
12241 BIT(DRM_ROTATE_0
) |
12242 BIT(DRM_ROTATE_180
));
12243 if (dev
->mode_config
.rotation_property
)
12244 drm_object_attach_property(&primary
->base
.base
,
12245 dev
->mode_config
.rotation_property
,
12246 state
->base
.rotation
);
12249 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
12251 return &primary
->base
;
12255 intel_check_cursor_plane(struct drm_plane
*plane
,
12256 struct intel_plane_state
*state
)
12258 struct drm_crtc
*crtc
= state
->base
.crtc
;
12259 struct drm_device
*dev
= plane
->dev
;
12260 struct drm_framebuffer
*fb
= state
->base
.fb
;
12261 struct drm_rect
*dest
= &state
->dst
;
12262 struct drm_rect
*src
= &state
->src
;
12263 const struct drm_rect
*clip
= &state
->clip
;
12264 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12265 struct intel_crtc
*intel_crtc
;
12269 crtc
= crtc
? crtc
: plane
->crtc
;
12270 intel_crtc
= to_intel_crtc(crtc
);
12272 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12274 DRM_PLANE_HELPER_NO_SCALING
,
12275 DRM_PLANE_HELPER_NO_SCALING
,
12276 true, true, &state
->visible
);
12281 /* if we want to turn off the cursor ignore width and height */
12285 /* Check for which cursor types we support */
12286 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
12287 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12288 state
->base
.crtc_w
, state
->base
.crtc_h
);
12292 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
12293 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
12294 DRM_DEBUG_KMS("buffer is too small\n");
12298 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
12299 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12304 if (intel_crtc
->active
) {
12305 if (intel_crtc
->base
.cursor
->state
->crtc_w
!= state
->base
.crtc_w
)
12306 intel_crtc
->atomic
.update_wm
= true;
12308 intel_crtc
->atomic
.fb_bits
|=
12309 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
12316 intel_commit_cursor_plane(struct drm_plane
*plane
,
12317 struct intel_plane_state
*state
)
12319 struct drm_crtc
*crtc
= state
->base
.crtc
;
12320 struct drm_device
*dev
= plane
->dev
;
12321 struct intel_crtc
*intel_crtc
;
12322 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12323 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
12326 crtc
= crtc
? crtc
: plane
->crtc
;
12327 intel_crtc
= to_intel_crtc(crtc
);
12329 plane
->fb
= state
->base
.fb
;
12330 crtc
->cursor_x
= state
->base
.crtc_x
;
12331 crtc
->cursor_y
= state
->base
.crtc_y
;
12333 intel_plane
->obj
= obj
;
12335 if (intel_crtc
->cursor_bo
== obj
)
12340 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
12341 addr
= i915_gem_obj_ggtt_offset(obj
);
12343 addr
= obj
->phys_handle
->busaddr
;
12345 intel_crtc
->cursor_addr
= addr
;
12346 intel_crtc
->cursor_bo
= obj
;
12349 if (intel_crtc
->active
)
12350 intel_crtc_update_cursor(crtc
, state
->visible
);
12353 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12356 struct intel_plane
*cursor
;
12357 struct intel_plane_state
*state
;
12359 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12360 if (cursor
== NULL
)
12363 state
= intel_create_plane_state(&cursor
->base
);
12368 cursor
->base
.state
= &state
->base
;
12370 cursor
->can_scale
= false;
12371 cursor
->max_downscale
= 1;
12372 cursor
->pipe
= pipe
;
12373 cursor
->plane
= pipe
;
12374 cursor
->check_plane
= intel_check_cursor_plane
;
12375 cursor
->commit_plane
= intel_commit_cursor_plane
;
12377 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12378 &intel_plane_funcs
,
12379 intel_cursor_formats
,
12380 ARRAY_SIZE(intel_cursor_formats
),
12381 DRM_PLANE_TYPE_CURSOR
);
12383 if (INTEL_INFO(dev
)->gen
>= 4) {
12384 if (!dev
->mode_config
.rotation_property
)
12385 dev
->mode_config
.rotation_property
=
12386 drm_mode_create_rotation_property(dev
,
12387 BIT(DRM_ROTATE_0
) |
12388 BIT(DRM_ROTATE_180
));
12389 if (dev
->mode_config
.rotation_property
)
12390 drm_object_attach_property(&cursor
->base
.base
,
12391 dev
->mode_config
.rotation_property
,
12392 state
->base
.rotation
);
12395 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
12397 return &cursor
->base
;
12400 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12403 struct intel_crtc
*intel_crtc
;
12404 struct intel_crtc_state
*crtc_state
= NULL
;
12405 struct drm_plane
*primary
= NULL
;
12406 struct drm_plane
*cursor
= NULL
;
12409 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12410 if (intel_crtc
== NULL
)
12413 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
12416 intel_crtc_set_state(intel_crtc
, crtc_state
);
12417 crtc_state
->base
.crtc
= &intel_crtc
->base
;
12419 primary
= intel_primary_plane_create(dev
, pipe
);
12423 cursor
= intel_cursor_plane_create(dev
, pipe
);
12427 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12428 cursor
, &intel_crtc_funcs
);
12432 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12433 for (i
= 0; i
< 256; i
++) {
12434 intel_crtc
->lut_r
[i
] = i
;
12435 intel_crtc
->lut_g
[i
] = i
;
12436 intel_crtc
->lut_b
[i
] = i
;
12440 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12441 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12443 intel_crtc
->pipe
= pipe
;
12444 intel_crtc
->plane
= pipe
;
12445 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12446 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12447 intel_crtc
->plane
= !pipe
;
12450 intel_crtc
->cursor_base
= ~0;
12451 intel_crtc
->cursor_cntl
= ~0;
12452 intel_crtc
->cursor_size
= ~0;
12454 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12455 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12456 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12457 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12459 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
12461 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12463 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12468 drm_plane_cleanup(primary
);
12470 drm_plane_cleanup(cursor
);
12475 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12477 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12478 struct drm_device
*dev
= connector
->base
.dev
;
12480 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12482 if (!encoder
|| WARN_ON(!encoder
->crtc
))
12483 return INVALID_PIPE
;
12485 return to_intel_crtc(encoder
->crtc
)->pipe
;
12488 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12489 struct drm_file
*file
)
12491 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12492 struct drm_crtc
*drmmode_crtc
;
12493 struct intel_crtc
*crtc
;
12495 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12497 if (!drmmode_crtc
) {
12498 DRM_ERROR("no such CRTC id\n");
12502 crtc
= to_intel_crtc(drmmode_crtc
);
12503 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12508 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12510 struct drm_device
*dev
= encoder
->base
.dev
;
12511 struct intel_encoder
*source_encoder
;
12512 int index_mask
= 0;
12515 for_each_intel_encoder(dev
, source_encoder
) {
12516 if (encoders_cloneable(encoder
, source_encoder
))
12517 index_mask
|= (1 << entry
);
12525 static bool has_edp_a(struct drm_device
*dev
)
12527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12529 if (!IS_MOBILE(dev
))
12532 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12535 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12541 static bool intel_crt_present(struct drm_device
*dev
)
12543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12545 if (INTEL_INFO(dev
)->gen
>= 9)
12548 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12551 if (IS_CHERRYVIEW(dev
))
12554 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12560 static void intel_setup_outputs(struct drm_device
*dev
)
12562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12563 struct intel_encoder
*encoder
;
12564 struct drm_connector
*connector
;
12565 bool dpd_is_edp
= false;
12567 intel_lvds_init(dev
);
12569 if (intel_crt_present(dev
))
12570 intel_crt_init(dev
);
12572 if (HAS_DDI(dev
)) {
12575 /* Haswell uses DDI functions to detect digital outputs */
12576 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12577 /* DDI A only supports eDP */
12579 intel_ddi_init(dev
, PORT_A
);
12581 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12583 found
= I915_READ(SFUSE_STRAP
);
12585 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12586 intel_ddi_init(dev
, PORT_B
);
12587 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12588 intel_ddi_init(dev
, PORT_C
);
12589 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12590 intel_ddi_init(dev
, PORT_D
);
12591 } else if (HAS_PCH_SPLIT(dev
)) {
12593 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12595 if (has_edp_a(dev
))
12596 intel_dp_init(dev
, DP_A
, PORT_A
);
12598 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12599 /* PCH SDVOB multiplex with HDMIB */
12600 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12602 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12603 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12604 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12607 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12608 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12610 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12611 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12613 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12614 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12616 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12617 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12618 } else if (IS_VALLEYVIEW(dev
)) {
12620 * The DP_DETECTED bit is the latched state of the DDC
12621 * SDA pin at boot. However since eDP doesn't require DDC
12622 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12623 * eDP ports may have been muxed to an alternate function.
12624 * Thus we can't rely on the DP_DETECTED bit alone to detect
12625 * eDP ports. Consult the VBT as well as DP_DETECTED to
12626 * detect eDP ports.
12628 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
12629 !intel_dp_is_edp(dev
, PORT_B
))
12630 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12632 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12633 intel_dp_is_edp(dev
, PORT_B
))
12634 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12636 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
12637 !intel_dp_is_edp(dev
, PORT_C
))
12638 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12640 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12641 intel_dp_is_edp(dev
, PORT_C
))
12642 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12644 if (IS_CHERRYVIEW(dev
)) {
12645 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12646 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12648 /* eDP not supported on port D, so don't check VBT */
12649 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12650 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12653 intel_dsi_init(dev
);
12654 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12655 bool found
= false;
12657 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12658 DRM_DEBUG_KMS("probing SDVOB\n");
12659 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12660 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12661 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12662 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12665 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12666 intel_dp_init(dev
, DP_B
, PORT_B
);
12669 /* Before G4X SDVOC doesn't have its own detect register */
12671 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12672 DRM_DEBUG_KMS("probing SDVOC\n");
12673 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12676 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12678 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12679 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12680 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12682 if (SUPPORTS_INTEGRATED_DP(dev
))
12683 intel_dp_init(dev
, DP_C
, PORT_C
);
12686 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12687 (I915_READ(DP_D
) & DP_DETECTED
))
12688 intel_dp_init(dev
, DP_D
, PORT_D
);
12689 } else if (IS_GEN2(dev
))
12690 intel_dvo_init(dev
);
12692 if (SUPPORTS_TV(dev
))
12693 intel_tv_init(dev
);
12696 * FIXME: We don't have full atomic support yet, but we want to be
12697 * able to enable/test plane updates via the atomic interface in the
12698 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12699 * will take some atomic codepaths to lookup properties during
12700 * drmModeGetConnector() that unconditionally dereference
12701 * connector->state.
12703 * We create a dummy connector state here for each connector to ensure
12704 * the DRM core doesn't try to dereference a NULL connector->state.
12705 * The actual connector properties will never be updated or contain
12706 * useful information, but since we're doing this specifically for
12707 * testing/debug of the plane operations (and only when a specific
12708 * kernel module option is given), that shouldn't really matter.
12710 * Once atomic support for crtc's + connectors lands, this loop should
12711 * be removed since we'll be setting up real connector state, which
12712 * will contain Intel-specific properties.
12714 if (drm_core_check_feature(dev
, DRIVER_ATOMIC
)) {
12715 list_for_each_entry(connector
,
12716 &dev
->mode_config
.connector_list
,
12718 if (!WARN_ON(connector
->state
)) {
12720 kzalloc(sizeof(*connector
->state
),
12726 intel_psr_init(dev
);
12728 for_each_intel_encoder(dev
, encoder
) {
12729 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12730 encoder
->base
.possible_clones
=
12731 intel_encoder_clones(encoder
);
12734 intel_init_pch_refclk(dev
);
12736 drm_helper_move_panel_connectors_to_head(dev
);
12739 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12741 struct drm_device
*dev
= fb
->dev
;
12742 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12744 drm_framebuffer_cleanup(fb
);
12745 mutex_lock(&dev
->struct_mutex
);
12746 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12747 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12748 mutex_unlock(&dev
->struct_mutex
);
12752 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12753 struct drm_file
*file
,
12754 unsigned int *handle
)
12756 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12757 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12759 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12762 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12763 .destroy
= intel_user_framebuffer_destroy
,
12764 .create_handle
= intel_user_framebuffer_create_handle
,
12768 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
12769 uint32_t pixel_format
)
12771 u32 gen
= INTEL_INFO(dev
)->gen
;
12774 /* "The stride in bytes must not exceed the of the size of 8K
12775 * pixels and 32K bytes."
12777 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
12778 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12780 } else if (gen
>= 4) {
12781 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
12785 } else if (gen
>= 3) {
12786 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
12791 /* XXX DSPC is limited to 4k tiled */
12796 static int intel_framebuffer_init(struct drm_device
*dev
,
12797 struct intel_framebuffer
*intel_fb
,
12798 struct drm_mode_fb_cmd2
*mode_cmd
,
12799 struct drm_i915_gem_object
*obj
)
12801 int aligned_height
;
12803 u32 pitch_limit
, stride_alignment
;
12805 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12807 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
12808 /* Enforce that fb modifier and tiling mode match, but only for
12809 * X-tiled. This is needed for FBC. */
12810 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
12811 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
12812 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12816 if (obj
->tiling_mode
== I915_TILING_X
)
12817 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
12818 else if (obj
->tiling_mode
== I915_TILING_Y
) {
12819 DRM_DEBUG("No Y tiling for legacy addfb\n");
12824 /* Passed in modifier sanity checking. */
12825 switch (mode_cmd
->modifier
[0]) {
12826 case I915_FORMAT_MOD_Y_TILED
:
12827 case I915_FORMAT_MOD_Yf_TILED
:
12828 if (INTEL_INFO(dev
)->gen
< 9) {
12829 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12830 mode_cmd
->modifier
[0]);
12833 case DRM_FORMAT_MOD_NONE
:
12834 case I915_FORMAT_MOD_X_TILED
:
12837 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12838 mode_cmd
->modifier
[0]);
12842 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
12843 mode_cmd
->pixel_format
);
12844 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
12845 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12846 mode_cmd
->pitches
[0], stride_alignment
);
12850 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
12851 mode_cmd
->pixel_format
);
12852 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12853 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12854 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
12855 "tiled" : "linear",
12856 mode_cmd
->pitches
[0], pitch_limit
);
12860 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
12861 mode_cmd
->pitches
[0] != obj
->stride
) {
12862 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12863 mode_cmd
->pitches
[0], obj
->stride
);
12867 /* Reject formats not supported by any plane early. */
12868 switch (mode_cmd
->pixel_format
) {
12869 case DRM_FORMAT_C8
:
12870 case DRM_FORMAT_RGB565
:
12871 case DRM_FORMAT_XRGB8888
:
12872 case DRM_FORMAT_ARGB8888
:
12874 case DRM_FORMAT_XRGB1555
:
12875 case DRM_FORMAT_ARGB1555
:
12876 if (INTEL_INFO(dev
)->gen
> 3) {
12877 DRM_DEBUG("unsupported pixel format: %s\n",
12878 drm_get_format_name(mode_cmd
->pixel_format
));
12882 case DRM_FORMAT_XBGR8888
:
12883 case DRM_FORMAT_ABGR8888
:
12884 case DRM_FORMAT_XRGB2101010
:
12885 case DRM_FORMAT_ARGB2101010
:
12886 case DRM_FORMAT_XBGR2101010
:
12887 case DRM_FORMAT_ABGR2101010
:
12888 if (INTEL_INFO(dev
)->gen
< 4) {
12889 DRM_DEBUG("unsupported pixel format: %s\n",
12890 drm_get_format_name(mode_cmd
->pixel_format
));
12894 case DRM_FORMAT_YUYV
:
12895 case DRM_FORMAT_UYVY
:
12896 case DRM_FORMAT_YVYU
:
12897 case DRM_FORMAT_VYUY
:
12898 if (INTEL_INFO(dev
)->gen
< 5) {
12899 DRM_DEBUG("unsupported pixel format: %s\n",
12900 drm_get_format_name(mode_cmd
->pixel_format
));
12905 DRM_DEBUG("unsupported pixel format: %s\n",
12906 drm_get_format_name(mode_cmd
->pixel_format
));
12910 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12911 if (mode_cmd
->offsets
[0] != 0)
12914 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
12915 mode_cmd
->pixel_format
,
12916 mode_cmd
->modifier
[0]);
12917 /* FIXME drm helper for size checks (especially planar formats)? */
12918 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12921 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12922 intel_fb
->obj
= obj
;
12923 intel_fb
->obj
->framebuffer_references
++;
12925 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12927 DRM_ERROR("framebuffer init failed %d\n", ret
);
12934 static struct drm_framebuffer
*
12935 intel_user_framebuffer_create(struct drm_device
*dev
,
12936 struct drm_file
*filp
,
12937 struct drm_mode_fb_cmd2
*mode_cmd
)
12939 struct drm_i915_gem_object
*obj
;
12941 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12942 mode_cmd
->handles
[0]));
12943 if (&obj
->base
== NULL
)
12944 return ERR_PTR(-ENOENT
);
12946 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12949 #ifndef CONFIG_DRM_I915_FBDEV
12950 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12955 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12956 .fb_create
= intel_user_framebuffer_create
,
12957 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12958 .atomic_check
= intel_atomic_check
,
12959 .atomic_commit
= intel_atomic_commit
,
12962 /* Set up chip specific display functions */
12963 static void intel_init_display(struct drm_device
*dev
)
12965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12967 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12968 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12969 else if (IS_CHERRYVIEW(dev
))
12970 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12971 else if (IS_VALLEYVIEW(dev
))
12972 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12973 else if (IS_PINEVIEW(dev
))
12974 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12976 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12978 if (INTEL_INFO(dev
)->gen
>= 9) {
12979 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12980 dev_priv
->display
.get_initial_plane_config
=
12981 skylake_get_initial_plane_config
;
12982 dev_priv
->display
.crtc_compute_clock
=
12983 haswell_crtc_compute_clock
;
12984 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12985 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12986 dev_priv
->display
.off
= ironlake_crtc_off
;
12987 dev_priv
->display
.update_primary_plane
=
12988 skylake_update_primary_plane
;
12989 } else if (HAS_DDI(dev
)) {
12990 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12991 dev_priv
->display
.get_initial_plane_config
=
12992 ironlake_get_initial_plane_config
;
12993 dev_priv
->display
.crtc_compute_clock
=
12994 haswell_crtc_compute_clock
;
12995 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12996 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12997 dev_priv
->display
.off
= ironlake_crtc_off
;
12998 dev_priv
->display
.update_primary_plane
=
12999 ironlake_update_primary_plane
;
13000 } else if (HAS_PCH_SPLIT(dev
)) {
13001 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
13002 dev_priv
->display
.get_initial_plane_config
=
13003 ironlake_get_initial_plane_config
;
13004 dev_priv
->display
.crtc_compute_clock
=
13005 ironlake_crtc_compute_clock
;
13006 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
13007 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
13008 dev_priv
->display
.off
= ironlake_crtc_off
;
13009 dev_priv
->display
.update_primary_plane
=
13010 ironlake_update_primary_plane
;
13011 } else if (IS_VALLEYVIEW(dev
)) {
13012 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
13013 dev_priv
->display
.get_initial_plane_config
=
13014 i9xx_get_initial_plane_config
;
13015 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
13016 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
13017 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
13018 dev_priv
->display
.off
= i9xx_crtc_off
;
13019 dev_priv
->display
.update_primary_plane
=
13020 i9xx_update_primary_plane
;
13022 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
13023 dev_priv
->display
.get_initial_plane_config
=
13024 i9xx_get_initial_plane_config
;
13025 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
13026 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
13027 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
13028 dev_priv
->display
.off
= i9xx_crtc_off
;
13029 dev_priv
->display
.update_primary_plane
=
13030 i9xx_update_primary_plane
;
13033 /* Returns the core display clock speed */
13034 if (IS_VALLEYVIEW(dev
))
13035 dev_priv
->display
.get_display_clock_speed
=
13036 valleyview_get_display_clock_speed
;
13037 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
13038 dev_priv
->display
.get_display_clock_speed
=
13039 i945_get_display_clock_speed
;
13040 else if (IS_I915G(dev
))
13041 dev_priv
->display
.get_display_clock_speed
=
13042 i915_get_display_clock_speed
;
13043 else if (IS_I945GM(dev
) || IS_845G(dev
))
13044 dev_priv
->display
.get_display_clock_speed
=
13045 i9xx_misc_get_display_clock_speed
;
13046 else if (IS_PINEVIEW(dev
))
13047 dev_priv
->display
.get_display_clock_speed
=
13048 pnv_get_display_clock_speed
;
13049 else if (IS_I915GM(dev
))
13050 dev_priv
->display
.get_display_clock_speed
=
13051 i915gm_get_display_clock_speed
;
13052 else if (IS_I865G(dev
))
13053 dev_priv
->display
.get_display_clock_speed
=
13054 i865_get_display_clock_speed
;
13055 else if (IS_I85X(dev
))
13056 dev_priv
->display
.get_display_clock_speed
=
13057 i855_get_display_clock_speed
;
13058 else /* 852, 830 */
13059 dev_priv
->display
.get_display_clock_speed
=
13060 i830_get_display_clock_speed
;
13062 if (IS_GEN5(dev
)) {
13063 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
13064 } else if (IS_GEN6(dev
)) {
13065 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
13066 } else if (IS_IVYBRIDGE(dev
)) {
13067 /* FIXME: detect B0+ stepping and use auto training */
13068 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
13069 dev_priv
->display
.modeset_global_resources
=
13070 ivb_modeset_global_resources
;
13071 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
13072 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
13073 } else if (IS_VALLEYVIEW(dev
)) {
13074 dev_priv
->display
.modeset_global_resources
=
13075 valleyview_modeset_global_resources
;
13078 switch (INTEL_INFO(dev
)->gen
) {
13080 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
13084 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
13089 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
13093 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
13096 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13097 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
13100 /* Drop through - unsupported since execlist only. */
13102 /* Default just returns -ENODEV to indicate unsupported */
13103 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
13106 intel_panel_init_backlight_funcs(dev
);
13108 mutex_init(&dev_priv
->pps_mutex
);
13112 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13113 * resume, or other times. This quirk makes sure that's the case for
13114 * affected systems.
13116 static void quirk_pipea_force(struct drm_device
*dev
)
13118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13120 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
13121 DRM_INFO("applying pipe a force quirk\n");
13124 static void quirk_pipeb_force(struct drm_device
*dev
)
13126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13128 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
13129 DRM_INFO("applying pipe b force quirk\n");
13133 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13135 static void quirk_ssc_force_disable(struct drm_device
*dev
)
13137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13138 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
13139 DRM_INFO("applying lvds SSC disable quirk\n");
13143 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13146 static void quirk_invert_brightness(struct drm_device
*dev
)
13148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13149 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
13150 DRM_INFO("applying inverted panel brightness quirk\n");
13153 /* Some VBT's incorrectly indicate no backlight is present */
13154 static void quirk_backlight_present(struct drm_device
*dev
)
13156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13157 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
13158 DRM_INFO("applying backlight present quirk\n");
13161 struct intel_quirk
{
13163 int subsystem_vendor
;
13164 int subsystem_device
;
13165 void (*hook
)(struct drm_device
*dev
);
13168 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13169 struct intel_dmi_quirk
{
13170 void (*hook
)(struct drm_device
*dev
);
13171 const struct dmi_system_id (*dmi_id_list
)[];
13174 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
13176 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
13180 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
13182 .dmi_id_list
= &(const struct dmi_system_id
[]) {
13184 .callback
= intel_dmi_reverse_brightness
,
13185 .ident
= "NCR Corporation",
13186 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
13187 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
13190 { } /* terminating entry */
13192 .hook
= quirk_invert_brightness
,
13196 static struct intel_quirk intel_quirks
[] = {
13197 /* HP Mini needs pipe A force quirk (LP: #322104) */
13198 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
13200 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13201 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
13203 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13204 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
13206 /* 830 needs to leave pipe A & dpll A up */
13207 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
13209 /* 830 needs to leave pipe B & dpll B up */
13210 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
13212 /* Lenovo U160 cannot use SSC on LVDS */
13213 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
13215 /* Sony Vaio Y cannot use SSC on LVDS */
13216 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
13218 /* Acer Aspire 5734Z must invert backlight brightness */
13219 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
13221 /* Acer/eMachines G725 */
13222 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
13224 /* Acer/eMachines e725 */
13225 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
13227 /* Acer/Packard Bell NCL20 */
13228 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
13230 /* Acer Aspire 4736Z */
13231 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
13233 /* Acer Aspire 5336 */
13234 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
13236 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13237 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
13239 /* Acer C720 Chromebook (Core i3 4005U) */
13240 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
13242 /* Apple Macbook 2,1 (Core 2 T7400) */
13243 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
13245 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13246 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
13248 /* HP Chromebook 14 (Celeron 2955U) */
13249 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
13251 /* Dell Chromebook 11 */
13252 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
13255 static void intel_init_quirks(struct drm_device
*dev
)
13257 struct pci_dev
*d
= dev
->pdev
;
13260 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
13261 struct intel_quirk
*q
= &intel_quirks
[i
];
13263 if (d
->device
== q
->device
&&
13264 (d
->subsystem_vendor
== q
->subsystem_vendor
||
13265 q
->subsystem_vendor
== PCI_ANY_ID
) &&
13266 (d
->subsystem_device
== q
->subsystem_device
||
13267 q
->subsystem_device
== PCI_ANY_ID
))
13270 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
13271 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
13272 intel_dmi_quirks
[i
].hook(dev
);
13276 /* Disable the VGA plane that we never use */
13277 static void i915_disable_vga(struct drm_device
*dev
)
13279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13281 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13283 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13284 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13285 outb(SR01
, VGA_SR_INDEX
);
13286 sr1
= inb(VGA_SR_DATA
);
13287 outb(sr1
| 1<<5, VGA_SR_DATA
);
13288 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13291 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
13292 POSTING_READ(vga_reg
);
13295 void intel_modeset_init_hw(struct drm_device
*dev
)
13297 intel_prepare_ddi(dev
);
13299 if (IS_VALLEYVIEW(dev
))
13300 vlv_update_cdclk(dev
);
13302 intel_init_clock_gating(dev
);
13304 intel_enable_gt_powersave(dev
);
13307 void intel_modeset_init(struct drm_device
*dev
)
13309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13312 struct intel_crtc
*crtc
;
13314 drm_mode_config_init(dev
);
13316 dev
->mode_config
.min_width
= 0;
13317 dev
->mode_config
.min_height
= 0;
13319 dev
->mode_config
.preferred_depth
= 24;
13320 dev
->mode_config
.prefer_shadow
= 1;
13322 dev
->mode_config
.allow_fb_modifiers
= true;
13324 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13326 intel_init_quirks(dev
);
13328 intel_init_pm(dev
);
13330 if (INTEL_INFO(dev
)->num_pipes
== 0)
13333 intel_init_display(dev
);
13334 intel_init_audio(dev
);
13336 if (IS_GEN2(dev
)) {
13337 dev
->mode_config
.max_width
= 2048;
13338 dev
->mode_config
.max_height
= 2048;
13339 } else if (IS_GEN3(dev
)) {
13340 dev
->mode_config
.max_width
= 4096;
13341 dev
->mode_config
.max_height
= 4096;
13343 dev
->mode_config
.max_width
= 8192;
13344 dev
->mode_config
.max_height
= 8192;
13347 if (IS_845G(dev
) || IS_I865G(dev
)) {
13348 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13349 dev
->mode_config
.cursor_height
= 1023;
13350 } else if (IS_GEN2(dev
)) {
13351 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13352 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13354 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13355 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13358 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13360 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13361 INTEL_INFO(dev
)->num_pipes
,
13362 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13364 for_each_pipe(dev_priv
, pipe
) {
13365 intel_crtc_init(dev
, pipe
);
13366 for_each_sprite(dev_priv
, pipe
, sprite
) {
13367 ret
= intel_plane_init(dev
, pipe
, sprite
);
13369 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13370 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13374 intel_init_dpio(dev
);
13376 intel_shared_dpll_init(dev
);
13378 /* Just disable it once at startup */
13379 i915_disable_vga(dev
);
13380 intel_setup_outputs(dev
);
13382 /* Just in case the BIOS is doing something questionable. */
13383 intel_fbc_disable(dev
);
13385 drm_modeset_lock_all(dev
);
13386 intel_modeset_setup_hw_state(dev
, false);
13387 drm_modeset_unlock_all(dev
);
13389 for_each_intel_crtc(dev
, crtc
) {
13394 * Note that reserving the BIOS fb up front prevents us
13395 * from stuffing other stolen allocations like the ring
13396 * on top. This prevents some ugliness at boot time, and
13397 * can even allow for smooth boot transitions if the BIOS
13398 * fb is large enough for the active pipe configuration.
13400 if (dev_priv
->display
.get_initial_plane_config
) {
13401 dev_priv
->display
.get_initial_plane_config(crtc
,
13402 &crtc
->plane_config
);
13404 * If the fb is shared between multiple heads, we'll
13405 * just get the first one.
13407 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13412 static void intel_enable_pipe_a(struct drm_device
*dev
)
13414 struct intel_connector
*connector
;
13415 struct drm_connector
*crt
= NULL
;
13416 struct intel_load_detect_pipe load_detect_temp
;
13417 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13419 /* We can't just switch on the pipe A, we need to set things up with a
13420 * proper mode and output configuration. As a gross hack, enable pipe A
13421 * by enabling the load detect pipe once. */
13422 list_for_each_entry(connector
,
13423 &dev
->mode_config
.connector_list
,
13425 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13426 crt
= &connector
->base
;
13434 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13435 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13439 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13441 struct drm_device
*dev
= crtc
->base
.dev
;
13442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13445 if (INTEL_INFO(dev
)->num_pipes
== 1)
13448 reg
= DSPCNTR(!crtc
->plane
);
13449 val
= I915_READ(reg
);
13451 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13452 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13458 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13460 struct drm_device
*dev
= crtc
->base
.dev
;
13461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13464 /* Clear any frame start delays used for debugging left by the BIOS */
13465 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
13466 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13468 /* restore vblank interrupts to correct state */
13469 drm_crtc_vblank_reset(&crtc
->base
);
13470 if (crtc
->active
) {
13471 update_scanline_offset(crtc
);
13472 drm_crtc_vblank_on(&crtc
->base
);
13475 /* We need to sanitize the plane -> pipe mapping first because this will
13476 * disable the crtc (and hence change the state) if it is wrong. Note
13477 * that gen4+ has a fixed plane -> pipe mapping. */
13478 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13479 struct intel_connector
*connector
;
13482 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13483 crtc
->base
.base
.id
);
13485 /* Pipe has the wrong plane attached and the plane is active.
13486 * Temporarily change the plane mapping and disable everything
13488 plane
= crtc
->plane
;
13489 crtc
->plane
= !plane
;
13490 crtc
->primary_enabled
= true;
13491 dev_priv
->display
.crtc_disable(&crtc
->base
);
13492 crtc
->plane
= plane
;
13494 /* ... and break all links. */
13495 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13497 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13500 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13501 connector
->base
.encoder
= NULL
;
13503 /* multiple connectors may have the same encoder:
13504 * handle them and break crtc link separately */
13505 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13507 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13508 connector
->encoder
->base
.crtc
= NULL
;
13509 connector
->encoder
->connectors_active
= false;
13512 WARN_ON(crtc
->active
);
13513 crtc
->base
.state
->enable
= false;
13514 crtc
->base
.enabled
= false;
13517 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13518 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13519 /* BIOS forgot to enable pipe A, this mostly happens after
13520 * resume. Force-enable the pipe to fix this, the update_dpms
13521 * call below we restore the pipe to the right state, but leave
13522 * the required bits on. */
13523 intel_enable_pipe_a(dev
);
13526 /* Adjust the state of the output pipe according to whether we
13527 * have active connectors/encoders. */
13528 intel_crtc_update_dpms(&crtc
->base
);
13530 if (crtc
->active
!= crtc
->base
.state
->enable
) {
13531 struct intel_encoder
*encoder
;
13533 /* This can happen either due to bugs in the get_hw_state
13534 * functions or because the pipe is force-enabled due to the
13536 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13537 crtc
->base
.base
.id
,
13538 crtc
->base
.state
->enable
? "enabled" : "disabled",
13539 crtc
->active
? "enabled" : "disabled");
13541 crtc
->base
.state
->enable
= crtc
->active
;
13542 crtc
->base
.enabled
= crtc
->active
;
13544 /* Because we only establish the connector -> encoder ->
13545 * crtc links if something is active, this means the
13546 * crtc is now deactivated. Break the links. connector
13547 * -> encoder links are only establish when things are
13548 * actually up, hence no need to break them. */
13549 WARN_ON(crtc
->active
);
13551 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13552 WARN_ON(encoder
->connectors_active
);
13553 encoder
->base
.crtc
= NULL
;
13557 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13559 * We start out with underrun reporting disabled to avoid races.
13560 * For correct bookkeeping mark this on active crtcs.
13562 * Also on gmch platforms we dont have any hardware bits to
13563 * disable the underrun reporting. Which means we need to start
13564 * out with underrun reporting disabled also on inactive pipes,
13565 * since otherwise we'll complain about the garbage we read when
13566 * e.g. coming up after runtime pm.
13568 * No protection against concurrent access is required - at
13569 * worst a fifo underrun happens which also sets this to false.
13571 crtc
->cpu_fifo_underrun_disabled
= true;
13572 crtc
->pch_fifo_underrun_disabled
= true;
13576 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13578 struct intel_connector
*connector
;
13579 struct drm_device
*dev
= encoder
->base
.dev
;
13581 /* We need to check both for a crtc link (meaning that the
13582 * encoder is active and trying to read from a pipe) and the
13583 * pipe itself being active. */
13584 bool has_active_crtc
= encoder
->base
.crtc
&&
13585 to_intel_crtc(encoder
->base
.crtc
)->active
;
13587 if (encoder
->connectors_active
&& !has_active_crtc
) {
13588 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13589 encoder
->base
.base
.id
,
13590 encoder
->base
.name
);
13592 /* Connector is active, but has no active pipe. This is
13593 * fallout from our resume register restoring. Disable
13594 * the encoder manually again. */
13595 if (encoder
->base
.crtc
) {
13596 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13597 encoder
->base
.base
.id
,
13598 encoder
->base
.name
);
13599 encoder
->disable(encoder
);
13600 if (encoder
->post_disable
)
13601 encoder
->post_disable(encoder
);
13603 encoder
->base
.crtc
= NULL
;
13604 encoder
->connectors_active
= false;
13606 /* Inconsistent output/port/pipe state happens presumably due to
13607 * a bug in one of the get_hw_state functions. Or someplace else
13608 * in our code, like the register restore mess on resume. Clamp
13609 * things to off as a safer default. */
13610 list_for_each_entry(connector
,
13611 &dev
->mode_config
.connector_list
,
13613 if (connector
->encoder
!= encoder
)
13615 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13616 connector
->base
.encoder
= NULL
;
13619 /* Enabled encoders without active connectors will be fixed in
13620 * the crtc fixup. */
13623 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13626 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13628 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13629 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13630 i915_disable_vga(dev
);
13634 void i915_redisable_vga(struct drm_device
*dev
)
13636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13638 /* This function can be called both from intel_modeset_setup_hw_state or
13639 * at a very early point in our resume sequence, where the power well
13640 * structures are not yet restored. Since this function is at a very
13641 * paranoid "someone might have enabled VGA while we were not looking"
13642 * level, just check if the power well is enabled instead of trying to
13643 * follow the "don't touch the power well if we don't need it" policy
13644 * the rest of the driver uses. */
13645 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13648 i915_redisable_vga_power_on(dev
);
13651 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13653 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13658 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13661 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13665 struct intel_crtc
*crtc
;
13666 struct intel_encoder
*encoder
;
13667 struct intel_connector
*connector
;
13670 for_each_intel_crtc(dev
, crtc
) {
13671 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
13673 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13675 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13678 crtc
->base
.state
->enable
= crtc
->active
;
13679 crtc
->base
.enabled
= crtc
->active
;
13680 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13682 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13683 crtc
->base
.base
.id
,
13684 crtc
->active
? "enabled" : "disabled");
13687 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13688 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13690 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13691 &pll
->config
.hw_state
);
13693 pll
->config
.crtc_mask
= 0;
13694 for_each_intel_crtc(dev
, crtc
) {
13695 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13697 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13701 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13702 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13704 if (pll
->config
.crtc_mask
)
13705 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13708 for_each_intel_encoder(dev
, encoder
) {
13711 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13712 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13713 encoder
->base
.crtc
= &crtc
->base
;
13714 encoder
->get_config(encoder
, crtc
->config
);
13716 encoder
->base
.crtc
= NULL
;
13719 encoder
->connectors_active
= false;
13720 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13721 encoder
->base
.base
.id
,
13722 encoder
->base
.name
,
13723 encoder
->base
.crtc
? "enabled" : "disabled",
13727 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13729 if (connector
->get_hw_state(connector
)) {
13730 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13731 connector
->encoder
->connectors_active
= true;
13732 connector
->base
.encoder
= &connector
->encoder
->base
;
13734 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13735 connector
->base
.encoder
= NULL
;
13737 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13738 connector
->base
.base
.id
,
13739 connector
->base
.name
,
13740 connector
->base
.encoder
? "enabled" : "disabled");
13744 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13745 * and i915 state tracking structures. */
13746 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13747 bool force_restore
)
13749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13751 struct intel_crtc
*crtc
;
13752 struct intel_encoder
*encoder
;
13755 intel_modeset_readout_hw_state(dev
);
13758 * Now that we have the config, copy it to each CRTC struct
13759 * Note that this could go away if we move to using crtc_config
13760 * checking everywhere.
13762 for_each_intel_crtc(dev
, crtc
) {
13763 if (crtc
->active
&& i915
.fastboot
) {
13764 intel_mode_from_pipe_config(&crtc
->base
.mode
,
13766 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13767 crtc
->base
.base
.id
);
13768 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13772 /* HW state is read out, now we need to sanitize this mess. */
13773 for_each_intel_encoder(dev
, encoder
) {
13774 intel_sanitize_encoder(encoder
);
13777 for_each_pipe(dev_priv
, pipe
) {
13778 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13779 intel_sanitize_crtc(crtc
);
13780 intel_dump_pipe_config(crtc
, crtc
->config
,
13781 "[setup_hw_state]");
13784 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13785 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13787 if (!pll
->on
|| pll
->active
)
13790 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13792 pll
->disable(dev_priv
, pll
);
13797 skl_wm_get_hw_state(dev
);
13798 else if (HAS_PCH_SPLIT(dev
))
13799 ilk_wm_get_hw_state(dev
);
13801 if (force_restore
) {
13802 i915_redisable_vga(dev
);
13805 * We need to use raw interfaces for restoring state to avoid
13806 * checking (bogus) intermediate states.
13808 for_each_pipe(dev_priv
, pipe
) {
13809 struct drm_crtc
*crtc
=
13810 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13812 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13813 crtc
->primary
->fb
);
13816 intel_modeset_update_staged_output_state(dev
);
13819 intel_modeset_check_state(dev
);
13822 void intel_modeset_gem_init(struct drm_device
*dev
)
13824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13825 struct drm_crtc
*c
;
13826 struct drm_i915_gem_object
*obj
;
13828 mutex_lock(&dev
->struct_mutex
);
13829 intel_init_gt_powersave(dev
);
13830 mutex_unlock(&dev
->struct_mutex
);
13833 * There may be no VBT; and if the BIOS enabled SSC we can
13834 * just keep using it to avoid unnecessary flicker. Whereas if the
13835 * BIOS isn't using it, don't assume it will work even if the VBT
13836 * indicates as much.
13838 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13839 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
13842 intel_modeset_init_hw(dev
);
13844 intel_setup_overlay(dev
);
13847 * Make sure any fbs we allocated at startup are properly
13848 * pinned & fenced. When we do the allocation it's too early
13851 mutex_lock(&dev
->struct_mutex
);
13852 for_each_crtc(dev
, c
) {
13853 obj
= intel_fb_obj(c
->primary
->fb
);
13857 if (intel_pin_and_fence_fb_obj(c
->primary
,
13860 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13861 to_intel_crtc(c
)->pipe
);
13862 drm_framebuffer_unreference(c
->primary
->fb
);
13863 c
->primary
->fb
= NULL
;
13864 update_state_fb(c
->primary
);
13867 mutex_unlock(&dev
->struct_mutex
);
13869 intel_backlight_register(dev
);
13872 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13874 struct drm_connector
*connector
= &intel_connector
->base
;
13876 intel_panel_destroy_backlight(connector
);
13877 drm_connector_unregister(connector
);
13880 void intel_modeset_cleanup(struct drm_device
*dev
)
13882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13883 struct drm_connector
*connector
;
13885 intel_disable_gt_powersave(dev
);
13887 intel_backlight_unregister(dev
);
13890 * Interrupts and polling as the first thing to avoid creating havoc.
13891 * Too much stuff here (turning of connectors, ...) would
13892 * experience fancy races otherwise.
13894 intel_irq_uninstall(dev_priv
);
13897 * Due to the hpd irq storm handling the hotplug work can re-arm the
13898 * poll handlers. Hence disable polling after hpd handling is shut down.
13900 drm_kms_helper_poll_fini(dev
);
13902 mutex_lock(&dev
->struct_mutex
);
13904 intel_unregister_dsm_handler();
13906 intel_fbc_disable(dev
);
13908 ironlake_teardown_rc6(dev
);
13910 mutex_unlock(&dev
->struct_mutex
);
13912 /* flush any delayed tasks or pending work */
13913 flush_scheduled_work();
13915 /* destroy the backlight and sysfs files before encoders/connectors */
13916 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13917 struct intel_connector
*intel_connector
;
13919 intel_connector
= to_intel_connector(connector
);
13920 intel_connector
->unregister(intel_connector
);
13923 drm_mode_config_cleanup(dev
);
13925 intel_cleanup_overlay(dev
);
13927 mutex_lock(&dev
->struct_mutex
);
13928 intel_cleanup_gt_powersave(dev
);
13929 mutex_unlock(&dev
->struct_mutex
);
13933 * Return which encoder is currently attached for connector.
13935 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13937 return &intel_attached_encoder(connector
)->base
;
13940 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13941 struct intel_encoder
*encoder
)
13943 connector
->encoder
= encoder
;
13944 drm_mode_connector_attach_encoder(&connector
->base
,
13949 * set vga decode state - true == enable VGA decode
13951 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13954 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13957 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13958 DRM_ERROR("failed to read control word\n");
13962 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13966 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13968 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13970 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13971 DRM_ERROR("failed to write control word\n");
13978 struct intel_display_error_state
{
13980 u32 power_well_driver
;
13982 int num_transcoders
;
13984 struct intel_cursor_error_state
{
13989 } cursor
[I915_MAX_PIPES
];
13991 struct intel_pipe_error_state
{
13992 bool power_domain_on
;
13995 } pipe
[I915_MAX_PIPES
];
13997 struct intel_plane_error_state
{
14005 } plane
[I915_MAX_PIPES
];
14007 struct intel_transcoder_error_state
{
14008 bool power_domain_on
;
14009 enum transcoder cpu_transcoder
;
14022 struct intel_display_error_state
*
14023 intel_display_capture_error_state(struct drm_device
*dev
)
14025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14026 struct intel_display_error_state
*error
;
14027 int transcoders
[] = {
14035 if (INTEL_INFO(dev
)->num_pipes
== 0)
14038 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
14042 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14043 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
14045 for_each_pipe(dev_priv
, i
) {
14046 error
->pipe
[i
].power_domain_on
=
14047 __intel_display_power_is_enabled(dev_priv
,
14048 POWER_DOMAIN_PIPE(i
));
14049 if (!error
->pipe
[i
].power_domain_on
)
14052 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
14053 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
14054 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
14056 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
14057 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
14058 if (INTEL_INFO(dev
)->gen
<= 3) {
14059 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
14060 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
14062 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14063 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
14064 if (INTEL_INFO(dev
)->gen
>= 4) {
14065 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
14066 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
14069 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
14071 if (HAS_GMCH_DISPLAY(dev
))
14072 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
14075 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
14076 if (HAS_DDI(dev_priv
->dev
))
14077 error
->num_transcoders
++; /* Account for eDP. */
14079 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14080 enum transcoder cpu_transcoder
= transcoders
[i
];
14082 error
->transcoder
[i
].power_domain_on
=
14083 __intel_display_power_is_enabled(dev_priv
,
14084 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
14085 if (!error
->transcoder
[i
].power_domain_on
)
14088 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
14090 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
14091 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
14092 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
14093 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
14094 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
14095 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
14096 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
14102 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14105 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
14106 struct drm_device
*dev
,
14107 struct intel_display_error_state
*error
)
14109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14115 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
14116 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14117 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
14118 error
->power_well_driver
);
14119 for_each_pipe(dev_priv
, i
) {
14120 err_printf(m
, "Pipe [%d]:\n", i
);
14121 err_printf(m
, " Power: %s\n",
14122 error
->pipe
[i
].power_domain_on
? "on" : "off");
14123 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
14124 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
14126 err_printf(m
, "Plane [%d]:\n", i
);
14127 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
14128 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
14129 if (INTEL_INFO(dev
)->gen
<= 3) {
14130 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
14131 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
14133 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14134 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
14135 if (INTEL_INFO(dev
)->gen
>= 4) {
14136 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
14137 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
14140 err_printf(m
, "Cursor [%d]:\n", i
);
14141 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
14142 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
14143 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
14146 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14147 err_printf(m
, "CPU transcoder: %c\n",
14148 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
14149 err_printf(m
, " Power: %s\n",
14150 error
->transcoder
[i
].power_domain_on
? "on" : "off");
14151 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
14152 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
14153 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
14154 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
14155 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
14156 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
14157 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
14161 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
14163 struct intel_crtc
*crtc
;
14165 for_each_intel_crtc(dev
, crtc
) {
14166 struct intel_unpin_work
*work
;
14168 spin_lock_irq(&dev
->event_lock
);
14170 work
= crtc
->unpin_work
;
14172 if (work
&& work
->event
&&
14173 work
->event
->base
.file_priv
== file
) {
14174 kfree(work
->event
);
14175 work
->event
= NULL
;
14178 spin_unlock_irq(&dev
->event_lock
);